Semiconductor manufacturing device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor manufacturing device that can suppress chipping of a semiconductor wafer in a dicing process, and a method for manufacturing the same.SOLUTION: A semiconductor manufacturing device cuts a semiconductor wafer into a plurality of semiconductor chips (CH). A storage unit stores position information of a plurality of first lines (DLa to DLg, DL1 to DL5) to be cut and position information of second lines (SL1 to SL5) not to be cut among the plurality of first lines on a first surface of the semiconductor wafer. A cutting unit cuts the semiconductor wafer along a plurality of first lines other than the second lines.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device. [Background technology]

[0002] Voids may occur at the bonding interface of a bonded wafer in which multiple semiconductor wafers are bonded together. In such cases, the semiconductor wafer may be chipped at the location of the void during the dicing process of the bonded wafer. The chipping of the semiconductor wafer may contaminate the dicing device and make it difficult to process the bonded wafer and semiconductor chips in the subsequent processes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-088093 A [Patent Document 2] Patent Publication No. 2022-062622 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device capable of suppressing chipping of a semiconductor wafer in a dicing process are provided. [Means for solving the problem]

[0005] The semiconductor manufacturing apparatus according to the present embodiment cuts a semiconductor wafer into a plurality of semiconductor chips. The storage unit stores position information of a plurality of first lines to be cut on a first surface of the semiconductor wafer, and position information of a second line among the plurality of first lines that is not to be cut. The cutting unit cuts the semiconductor wafer at the plurality of first lines other than the second lines. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a dicing device according to a first embodiment. [Diagram 2] FIG. 1 is a cross-sectional view showing an example of a defect in a semiconductor wafer. [Diagram 3] FIG. 4 is a flow diagram showing an example of a dicing method using the dicing device according to the first embodiment. [Figure 4] 1A and 1B are conceptual plan views of a semiconductor wafer illustrating an example of a dicing method. [Diagram 5] FIG. 5 is a plan view showing an example of a dicing method following FIG. 4. [Figure 6] FIG. 6 is a plan view showing an example of a dicing method following FIG. 5. [Figure 7] FIG. 7 is a plan view showing an example of a dicing method following FIG. 6. [Figure 8] 1 is a table showing position information of dicing areas. [Figure 9] 1 is a table showing position information of dicing areas. [Figure 10] FIG. 11 is a plan view showing a semiconductor chip that has not been separated into individual chips. [Figure 11] 11 is a table showing an example of position information of dicing lines surrounding semiconductor chips that have not been singulated. [Figure 12] 11 is a table showing an example of position information of dicing lines surrounding semiconductor chips that have not been singulated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are given the same reference numerals.

[0008] (First embodiment) FIG. 1 is a block diagram showing an example of the configuration of a dicing apparatus according to a first embodiment. The dicing apparatus 1 is a semiconductor manufacturing apparatus that cuts a semiconductor wafer into a plurality of semiconductor chips. The semiconductor wafer may be, for example, composed of a single semiconductor substrate, or may be composed of a bonded wafer in which a plurality of semiconductor substrates S1 and S2 are bonded together as shown in FIG. 2. Semiconductor elements have already been formed on the surface of the semiconductor wafer in a pre-process of the semiconductor manufacturing process. After the pre-process, the semiconductor wafer is subjected to a surface inspection, an electrical property inspection, and the like, and is then singulated into semiconductor chips in the dicing apparatus 1.

[0009] The dicing device 1 includes a receiving section 10, a calculation section 20, a control section 30, a dicing section 40, a transmitting section 50, a GUI (Graphical User Interface) 60, and a storage section .

[0010] The receiving unit 10 receives the inspection results obtained in the surface inspection from outside. The inspection results are received from an inspection device (not shown). The inspection results are, for example, position information of defects on the surface of the semiconductor wafer. The defect of the semiconductor wafer is, for example, a void BD generated on the bonding surface FB of the bonded wafer as shown in FIG. 2. The position information may be a planar coordinate system with the center of the semiconductor wafer as the origin.

[0011] If the voids BD are cut in the dicing process, they may cause chipping of the semiconductor chip and may cause contamination in the subsequent back grinding process, etc. Therefore, the dicing device 1 according to this embodiment is set so as not to cut the voids BD based on the position information of the defects, etc.

[0012] The calculation unit 20 sets skip lines that are not to be cut among the dicing lines of the semiconductor wafer based on the product information of the semiconductor wafer and the position information of the defects. The dicing lines are an example of first lines that are to be cut on the surface of the semiconductor wafer. The dicing lines are between a plurality of adjacent semiconductor chips. On the other hand, the skip lines are dicing lines that are not to be cut in the dicing process among the dicing lines, and are set, for example, in line portions of dicing lines that have defects such as voids BD and should not be cut. The skip lines are an example of second lines. The calculation unit 20 sets whether or not to set each line segment of the dicing lines corresponding to the sides of the adjacent semiconductor chips as a skip line. That is, the skip lines are set partially for each side of the semiconductor chip. The calculation unit 20 may be, for example, a CPU (Central Processing Unit) or the like. The setting of the skip lines will be described in detail later.

[0013] The control unit 30 controls the dicing unit 40. At this time, the control unit 30 controls the dicing unit 40 so as to cut the dicing lines that are not set as skip lines, and not to cut the dicing lines that are set as skip lines. The control unit 30 may be, for example, a CPU, a PLC (Programmable Logic Controller), or the like.

[0014] The dicing unit 40 cuts the semiconductor wafer under the control of the control unit 30. The dicing unit 40 cuts the dicing lines other than the skip lines. The dicing unit 40 includes, for example, a dicing blade that cuts the semiconductor wafer with a rotating blade or a laser generator that cuts the semiconductor wafer with laser light. Although not shown, the dicing unit 40 further includes a stage on which the semiconductor wafer is placed, a transport mechanism that transports the semiconductor wafer to the stage and removes the semiconductor wafer from the stage, and the like.

[0015] The transmitting unit 50 transmits the position information of the semiconductor chip adjacent to the skip line to the outside. The receiving unit 10 and the transmitting unit 50 may be configured as a single input / output circuit.

[0016] The GUI 60 displays inspection information of the semiconductor wafer, product information of the semiconductor wafer, dicing lines, dicing areas, and skip lines on the surface of the semiconductor wafer. The GUI 60 is also configured to allow a user to input information. For example, the user selects a product to be diced in the GUI 60. The GUI 60 transfers the selected product information to the calculation unit 20. The calculation unit 20 extracts the product information selected by the user from a plurality of pieces of product information stored in the storage unit 70. The GUI 60 displays the product information of the semiconductor wafer to be diced. The GUI 60 may be, for example, a touch panel display, a keyboard, or the like.

[0017] The storage unit 70 prestores product information of semiconductor wafers related to various products and the inspection results of each semiconductor wafer received by the receiving unit 10. The product information of the semiconductor wafer is information specified by the product formed on the semiconductor wafer, and includes, for example, size information of the semiconductor chip, position information of a unique pattern provided on the semiconductor chip, information on the interval between adjacent dicing lines, length information of the dicing line, etc. The unique pattern may be, for example, an alignment mark provided on each semiconductor chip. The storage unit 70 prestores product information of a plurality of products. When the user selects a certain product using the GUI 60, the calculation unit 20 receives product information corresponding to the product from the storage unit 70.

[0018] Furthermore, the storage unit 70 stores the inspection information of the semiconductor wafer received by the receiving unit 10 during the dicing process. The inspection information is information specific to each semiconductor wafer, and is stored in the storage unit 70 for each semiconductor wafer. Note that the position information of the defect may be expressed in position coordinates with the center of the surface of the semiconductor wafer as the origin.

[0019] Furthermore, the storage unit 70 stores position information of skip lines set based on position information of defects in the dicing lines, which enables the dicing unit 40 to cut the dicing lines other than the line portions of the dicing lines set as skip lines.

[0020] Furthermore, the storage unit 70 stores, as a dicing area, an area to be removed when the dicing unit 40 cuts the dicing line. The dicing area is an area on the surface of the semiconductor wafer, centered on the dicing line, having a width to be removed by dicing. In other words, the dicing area is an area other than the semiconductor chips cut out from the semiconductor wafer. The storage unit 70 may be, for example, a memory or storage such as an SSD (Solid State Drive) or an HDD (Hard Disc Drive).

[0021] 2 is a cross-sectional view showing an example of a defect in a semiconductor wafer. The semiconductor wafer W is, for example, a bonded wafer in which a plurality of semiconductor substrates S1, S2 are bonded at a bonding surface FB. In such a semiconductor wafer W, a void BD may remain as a defect on the bonding surface FB. As described above, cutting the void BD may cause chipping of the semiconductor chip. Therefore, when a defect such as a void BD is included in a dicing line, the calculation unit 20 sets the line portion of the dicing line as a skip line so as not to cut the defect.

[0022] Fig. 3 is a flow diagram showing an example of a dicing method using the dicing apparatus according to the first embodiment. Figs. 4 to 7 are conceptual plan views of a semiconductor wafer showing an example of the dicing method. The storage unit 70 stores in advance product information of semiconductor wafers related to various products.

[0023] First, the receiving unit 10 receives inspection results of the semiconductor wafer W from an external inspection device (not shown) (S10). The inspection results include position information of defects (e.g., voids BD) on the surface of the semiconductor wafer W. The inspection results are stored in the memory unit 70. In addition, the user inputs or selects product information of the semiconductor wafer W to be diced using the GUI 60 (S11). The product information of the semiconductor wafer W to be diced is stored in the memory unit 70. Furthermore, the dicing apparatus 1 loads the semiconductor wafer W to be diced into the chamber of the dicing unit 40, and places the semiconductor wafer W on a stage (not shown) (S12).

[0024] Next, as shown in FIG. 4, the calculation unit 20 detects unique patterns (e.g., alignment marks) UP1 to UP3 of multiple semiconductor chips in the semiconductor wafer W from the product information (S20). The control unit 30 aligns the semiconductor wafer W using position information of the unique patterns UP1 to UP3 (S30). The alignment of the semiconductor wafer W is performed in the X direction, the Y direction intersecting the X direction, and the rotation direction in the XY plane. At this time, position information of the unique patterns of two or more semiconductor chips is used to suppress deviation in the rotation direction in a plan view seen from above the surface of the semiconductor wafer W. For example, as shown in FIG. 4, the alignment of the semiconductor wafer W may be performed using three unique patterns UP1 to UP3.

[0025] Next, as shown in Fig. 5, the calculation unit 20 sets dicing lines DLa-DLg, DL1-DL5 on the surface of the semiconductor wafer W based on the information on the spacing between the dicing lines and the information on the length of the dicing lines (S40). The information on the spacing between the dicing lines indicates, for example, the spacing between multiple dicing lines DLa-DLg adjacent to each other in the X direction and the spacing between multiple dicing lines DL1-DL5 adjacent to each other in the Y direction. In the same semiconductor wafer W, the spacing between the dicing lines DLa-DLg in the X direction may be equal and at an equal pitch. In addition, in the same semiconductor wafer W, the spacing between the dicing lines DL1-DL5 in the Y direction may be equal and at an equal pitch.

[0026] The length information of the dicing lines DLa-DLg, DL1-DL5 may be set individually for each of the multiple dicing lines DLa-DLg, DL1-DL5. Alternatively, the lengths of the multiple dicing lines DLa-DLg, DL1-DL5 may be equal, as shown in Fig. 5. In this case, the lengths of the dicing lines DLa-DLg, DL1-DL5 are set longer than the diameter of the semiconductor wafer W so that the dicing section 40 can dices up to the edge of the semiconductor wafer W.

[0027] 5, the calculation unit 20 sets a plurality of dicing lines DL1-DL5 extending in the X direction and a plurality of dicing lines DLa-DLg extending in the Y direction. The dicing lines DL1-DL5 and the dicing lines DLa-DLg are, for example, substantially perpendicular to each other. The numbers of the dicing lines DL1-DL5 and the dicing lines DLa-DLg are not particularly limited, but depend on the chip size of the semiconductor chip.

[0028] The position information of the dicing lines DLa-DLg, DL1-DL5 can be set by the coordinates of one end and the coordinates of the other end. The position information of the dicing lines DLa-DLg, DL1-DL5 is stored in the storage unit 70. The intersection coordinates of the dicing lines DLa-DLg, DL1-DL5 are also stored in the storage unit 70. This allows the calculation unit 20 to identify a portion between the intersections of the dicing lines DLa-DLg, DL1-DL5.

[0029] Next, as shown in Fig. 6 and Fig. 7, the calculation unit 20 sets dicing regions DRa-DRg, DR1-DR5 on the surface of the semiconductor wafer W based on the position information of the dicing lines DLa-DLg, DL1-DL5, the interval information between the dicing lines DLa-DLg, DL1-DL5, the length information of the dicing lines DLa-DLg, DL1-DL5, and the size information of the semiconductor chip CH (S50). The dicing regions DRa-DRg, DR1-DR5 are regions to be removed when the dicing unit 40 cuts the dicing lines DLa-DLg, DL1-DL5. Therefore, the region of the semiconductor wafer W other than the dicing regions DRa-DRg, DR1-DR5 becomes the region of the semiconductor chip CH. The size information of the semiconductor chip CH is the size in the XY plane of the semiconductor chip CH cut out from the semiconductor wafer W.

[0030] 7, the width of the semiconductor chip CH in the X direction is denoted by cX, and the width of the semiconductor chip CH in the Y direction is denoted by cY. The interval between dicing lines (second lines to cut) DLa-DLg adjacent in the X direction is denoted by pX, and the interval between dicing lines (first lines to cut) DL1-DL5 adjacent in the Y direction is denoted by pY.

[0031] At this time, the calculation unit 20 sets regions having a width of ±(pY-cY) / 2 in the Y direction from each of the dicing lines DL1-DL5 as dicing regions DR1-DR5. The calculation unit 20 also sets regions having a width of ±(pX-cX) / 2 in the X direction from each of the dicing lines DLa-DLg as dicing regions DRa-DRg.

[0032] FIG. 8 is a table showing position information of the dicing regions DR1 to DR5. The X column of the table in FIG. 8 shows the lengths (for example, −150 mm to 150 mm) of the dicing regions DR1 to DR5 in the X direction. The Y column of the table in FIG. 8 shows the widths (for example, −150 mm to 150 mm) of the dicing regions DR1 to DR5 in the Y direction. Y_DL1 to Y_DL5 show the Y coordinates of the dicing lines DL1 to DL5, respectively. Therefore, it can be seen that the dicing regions DR1 to DR5 are regions on the surface of the semiconductor wafer W that have a width of ±(pY-cY) / 2 in the Y direction centered on the dicing lines DL1 to DL5, respectively. In addition, the lengths (for example, −150 mm to 150 mm) of the dicing regions DR1 to DR5 in the X direction may be the same as the lengths (for example, −150 mm to 150 mm) of the dicing lines DL1 to DL5 in the X direction, and are equal to or greater than the diameter of the semiconductor wafer W.

[0033] FIG. 9 is a table showing position information of the dicing regions DRa to DRg. The Y column of the table in FIG. 9 shows the lengths (-150 mm to 150 mm) of the dicing regions DRa to DRg in the Y direction. The X column of the table in FIG. 9 shows the widths of the dicing regions DRa to DRg in the X direction. X_DLa to X_DLg show the X coordinates of the dicing lines DLa to DLg, respectively. Therefore, it can be seen that the dicing regions DRa to DRg are regions on the surface of the semiconductor wafer W that have a width of ±(pX-cX) / 2 in the X direction centered on the dicing lines DLa to DLg, respectively. In addition, the lengths (for example, -150 mm to 150 mm) of the dicing regions DRa to DRg in the Y direction may be the same as the lengths of the dicing lines DLa to DLg in the X direction, and are equal to or greater than the diameter of the semiconductor wafer W.

[0034] The calculation unit 20 stores in the storage unit 70 the position information of the dicing regions DR1 to DR5 and DRa to DRg set as described above.

[0035] Next, the calculation unit 20 sets a skip line based on the position information of the defect and the position information of the dicing area (S60). The position information of the defect indicates the coordinates of the defect in the surface of the semiconductor wafer W. For example, as shown in FIG. 7, it is assumed that there are defects BD1 and BD2. The defect BD1 exists in the dicing area DR2. Therefore, the calculation unit 20 sets a skip line SL in the dicing line DL2 corresponding to the dicing area DR2. More specifically, the calculation unit 20 sets the line segment between the adjacent semiconductor chips CHsk1 and CHsk2 in the dicing area DR2 in which the defect BD1 exists as the skip line SL1. The skip line SL1 corresponds to the side of the adjacent semiconductor chips CHsk1 and CHsk2, and is indicated by a dashed line in FIG. 7.

[0036] Moreover, the defect BD2 is in an overlapping region between the dicing region DR4 and the dicing region DRd. In this case, the calculation unit 20 sets a skip line SL in the dicing lines DL4 and DLd corresponding to the dicing regions DR4 and DRd. The overlapping region in which the defect BD2 exists corresponds to the corners of the semiconductor chips CHsk3 to CHsk6. Therefore, the calculation unit 20 sets, as skip lines, a line segment SL2 between the semiconductor chips CHsk3 and CHsk4, a line segment SL3 between the semiconductor chips CHsk3 and CHsk5, a line segment SL4 between the semiconductor chips CHsk5 and CHsk6, and a line segment SL5 between the semiconductor chips CHsk6 and CHsk4 in the overlapping region in which the defect BD2 exists. The skip line SL2 corresponds to one side between the semiconductor chips CHsk3 and CHsk4. The skip line SL3 corresponds to one side between the semiconductor chips CHsk3 and CHsk5. The skip line SL4 corresponds to one side between the semiconductor chips CHsk5 and CHsk6. The skip line SL5 corresponds to one side between the semiconductor chips CHsk6 and CHsk5. The skip lines SL2 to SL5 are indicated by dashed lines in FIG.

[0037] Thus, in this embodiment, the calculation unit 20 sets the portions within the dicing lines DL2, DL4, DLd corresponding to the dicing regions DR2, DR4, DRd in which defects BD1, BD2 are located as skip lines SL1 to SL5 for each line segment corresponding to the sides of multiple adjacent semiconductor chips CHsk1 to CHsk5.

[0038] The position information of the skip lines SL1 to SL5 is stored in the storage unit 70. The position information of the skip lines SL1 to SL5 may be the position coordinates (intersection coordinates of both ends) of the corresponding dicing lines. For example, the position information of the skip line SL1 may be indicated by the intersection coordinates of the dicing lines DL2 and DLd and the intersection coordinates of the dicing lines DL2 and DLe. The position information of the skip line SL2 may be indicated by the intersection coordinates of the dicing lines DL3 and DLd and the intersection coordinates of the dicing lines DL4 and DLd. The position information of the skip line SL3 may be indicated by the intersection coordinates of the dicing lines DL4 and DLc and the intersection coordinates of the dicing lines DL4 and DLd. The position information of the skip line SL4 may be indicated by the intersection coordinates of the dicing lines DL4 and DLd and the intersection coordinates of the dicing lines DL5 and DLd. The position information of the skip line SL5 may be indicated by the intersection coordinates of the dicing lines DL4 and DLd and the intersection coordinates of the dicing lines DL4 and DLe.

[0039] Next, the control unit 30 controls the dicing unit 40 to skip the skip lines SL1 to SL5 among the dicing lines DL1 to DL5 and DLa to DLg, and cut the other dicing lines. The dicing unit 40 cuts the dicing lines other than the skip lines SL1 to SL5 (S70), and the individualized semiconductor chips CH are cut out from the semiconductor wafer W. Here, the skip lines SL1 to SL5 are not cut, so the adjacent semiconductor chips CHsk1 and CHsk2 remain connected, and the semiconductor chips CHsk3 to CHsk6 also remain connected. The semiconductor chips CHsk1, CHsk2, and CHsk3 to CHsk6 are not diced and become defective chips.

[0040] Next, the transmitting unit 50 transmits to the outside the position information of the semiconductor chips CHsk1, CHsk2 and the semiconductor chips CHsk3 to CHsk6 that were not singulated (S80). Fig. 10 is a plan view showing the semiconductor chips CHsk1 to CHsk6 that were not singulated. The position information of the semiconductor chips CHsk1, CHsk2 and the semiconductor chips CHsk3 to CHsk6 that were not singulated is position information of the dicing lines surrounding the semiconductor chips CHsk1 and CHsk2 adjacent to the skip line SL1, and position information of the dicing lines surrounding the semiconductor chips CHsk3 to CHsk6 adjacent to the skip lines SL2 to SL5.

[0041] 11 is a table showing an example of position information of dicing lines surrounding the semiconductor chips CHsk1 and CHsk2 that have not been singulated. The storage unit 70 stores position information of the dicing lines DL1 to DL5 and DLa to DLg and their intersection coordinates. Therefore, the position information of the dicing lines surrounding the semiconductor chips CHsk1 and CHsk2 may be the coordinates of the corners of the dicing lines surrounding the semiconductor chips CHsk1 and CHsk2. For example, the semiconductor chips CHsk1 and CHsk2 are represented by the intersection coordinate 1d between the dicing lines DL1 and DLd, the intersection coordinate 1e between the dicing lines DL1 and DLe, the intersection coordinate 3d between the dicing lines DL3 and DLd, and the intersection coordinate 3e between the dicing lines DL3 and DLe.

[0042] 12 is a table showing an example of position information of dicing lines surrounding the semiconductor chips CHsk3 to CHsk6 that have not been singulated. The position information of the dicing lines surrounding the semiconductor chips CHsk3 to CHsk6 may be coordinates of corners of the dicing lines surrounding the semiconductor chips CHsk3 to CHsk6. For example, the semiconductor chips CHsk3 to CHsk6 are represented by the intersection coordinates 3c of the dicing lines DL3 and DLc, the intersection coordinates 3e of the dicing lines DL3 and DLe, the intersection coordinates 5c of the dicing lines DL5 and DLc, and the intersection coordinates 5e of the dicing lines DL5 and DLe.

[0043] The transmitting unit 50 may output the intersection coordinates shown in FIG. 11 and FIG. 12 to the outside. This can prevent the semiconductor chips CHsk1 to CHsk6 in FIG. 10 from being picked up in the subsequent assembly process. Here, the information output by the transmitting unit 50 to the outside may be position information corresponding to one semiconductor chip CH, not position information corresponding to multiple semiconductor chips CH. For example, if the skip line is set not between multiple adjacent semiconductor chips CH but on a line segment of a dicing line corresponding to the edge of the semiconductor wafer W on the outer periphery side of the semiconductor wafer W of the semiconductor chip CH arranged on the outermost periphery of the semiconductor wafer W, the one semiconductor chip CH that is not singulated and becomes a defective chip is the one semiconductor chip CH adjacent to the center side of the semiconductor wafer W with respect to the skip line. Therefore, the position information of the dicing line surrounding this one semiconductor chip CH is output to the outside as position information of the semiconductor chip CH that was not singulated. That is, the transmitting unit 50 transmits position information of one or more semiconductor chips CH adjacent to the skip line to the outside as position information of the semiconductor chip CH that was not singulated.

[0044] According to this embodiment, the calculation unit 20 automatically sets the dicing regions DR1-DR5, DRa-DRg based on the position information of the dicing lines DL1-DL5, DLa-DLg, the size information cX, cY of the semiconductor chip CH, and the interval information pX, pY of the dicing lines DL1-DL5, DLa-DLg. Then, the calculation unit 20 sets the line segment between the semiconductor chips CHsk1 and CHsk2 adjacent to the defect BD1 in the dicing line DL2 corresponding to the dicing region DR2 having the defect BD1 as the skip line SL1. Furthermore, the calculation unit 20 automatically sets the line segment between the semiconductor chips CHsk3-CHsk6 adjacent to the defect BD2 in the dicing lines DL4, DLd corresponding to the dicing regions DR4, DRd having the defect BD2 as the skip lines SL2-SL5. This allows the dicing unit 40 to cut other line portions within the dicing lines DL1-DL5 and DLa-DLg without cutting the skip lines SL1 and SL2-SL5 portions where the defects BD1, BD2 exist, thereby making it possible to suppress chipping of the semiconductor wafer W in the dicing process.

[0045] Moreover, the skip lines are set for each line segment of the dicing line corresponding to the side of the adjacent semiconductor chips CH. This makes it possible to reduce the number of semiconductor chips CHsk1 to CHsk6 that are not used as products.

[0046] Second embodiment A second embodiment will be described with reference to FIGS.

[0047] In the second embodiment, the GUI 60 displays defects BD1, BD2, dicing lines DL1-DL5, DLa-DLg, and dicing regions DR1-DR5, DRa-DRg in the semiconductor wafer W, as shown in Fig. 7. Note that the GUI 60 may display an enlarged view of the portion of the semiconductor wafer W where the defects BD1, BD2 exist, as shown in Fig. 7, or may display the entire semiconductor wafer W, as shown in Fig. 6.

[0048] The user refers to the GUI 60 and selects skip lines based on the positions of the defects BD1, BD2 and the dicing regions DR1-DR5, DRa-DRg. For example, the user selects and sets skip lines SL1 and SL2-SL5 for each line segment corresponding to the sides of the adjacent semiconductor chips CHsk1-CHsk6 among the dicing lines DL2, DL4, DLd corresponding to the dicing regions DR2, DR4, DRd having the defects BD1, BD2 in the dicing lines DL1-DL5, DLa-DLg. In this way, the user can arbitrarily select skip lines by referring to the defects BD1, BD2 and the dicing regions DR1-DR5, DRa-DRg through the GUI 60. Therefore, for example, the user can exclude the line segments (skip lines SL2 and SL5) in the dicing lines DL4, DLd corresponding to the two sides of the semiconductor chip CHsk4 that are relatively far from the defect BD2 from the skip lines. The selection or deselection of a skip line may be performed by the user using an input function to the GUI 60 (for example, input via a touch panel or keyboard).

[0049] Other configurations and operations of the second embodiment may be the same as those of the first embodiment. As a result, although the second embodiment cannot automatically set a skip line, it can suppress chipping of the semiconductor wafer W in the dicing process, similar to the first embodiment.

[0050] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0051] 1 Dicing equipment 10 Receiving section 20 Arithmetic section 30 Control section 40 Dicing Department 50 Transmitter 60 GUI 70 Storage section DLa~DLg, ​​DL1~DL5 Dicing Lines DRa~DRg, DR1~DR5 dicing area SL1~SL5 Skip Line

Claims

1. A semiconductor manufacturing apparatus for cutting a semiconductor wafer into a plurality of semiconductor chips, a storage unit that stores position information of a plurality of first lines to be cut on a first surface of the semiconductor wafer and position information of a second line among the plurality of first lines that is not to be cut; a cutting unit that cuts the semiconductor wafer in each of the first lines other than the second line.

2. 2 . The semiconductor manufacturing apparatus according to claim 1 , wherein the second lines are set for each line segment of the first lines corresponding to sides of the semiconductor chips adjacent to the first lines.

3. a receiving unit for receiving position information of the defect on the semiconductor wafer, 3. The semiconductor manufacturing apparatus of claim 2, wherein the memory unit further stores position information of the defect and position information of a first region to be removed by cutting between adjacent ones of the plurality of semiconductor chips, and stores a line portion within the plurality of first lines corresponding to the first region in which the defect is located as the second line.

4. the storage unit further stores product information including size information of the semiconductor chips and interval information between adjacent first lines for a plurality of products; The semiconductor manufacturing apparatus according to claim 3 , further comprising a calculation unit that sets the first area based on position information of the plurality of first lines, the size information, and the interval information.

5. A method for manufacturing a semiconductor device using a semiconductor manufacturing apparatus having a cutting unit that cuts a semiconductor wafer into a plurality of semiconductor chips, comprising: A method for manufacturing a semiconductor device, comprising: cutting the semiconductor wafer at the multiple first lines other than the second lines based on position information of multiple first lines to be cut on a first surface of the semiconductor wafer and position information of second lines which are a portion of the multiple first lines.

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