Manufacturing method of semiconductor device and semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device, in which method a deep p-type region can be easily formed.SOLUTION: A manufacturing method of a semiconductor device comprises: forming a mask material that has an opening on a surface of a silicon carbide layer; performing first processing to implant at least one material selected from a group composed of hydrogen (H), helium (He) and an electron into a first region of the silicon carbide layer using the mask material as a mask; performing first ion implantation to implant a p-type impurity into a second region being shallower than the first region using the mask material as a mask before the first processing or after the first processing; peeling the mask material after the first processing and the first ion implantation; and performing first heat treatment at 1600°C or higher after peeling the mask material.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is one of the materials for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap about three times larger, a breakdown electric field strength about ten times larger, and a thermal conductivity about three times larger. By utilizing these physical properties, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] In vertical Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), the superjunction structure (hereinafter also referred to as the "SJ structure") is a structure that achieves both high breakdown voltage and low on-resistance. In the SJ structure, p-type regions and n-type regions are arranged alternately in the horizontal direction. The depletion layers that extend horizontally in the p-type and n-type regions reduce the electric field strength in the semiconductor, achieving a high breakdown voltage for the MOSFET. At the same time, a low on-resistance for the MOSFET can be achieved by increasing the concentration of the impurity regions.

[0004] In a MOSFET with an SJ structure, it is necessary to form a deep p-type region in a silicon carbide layer, and therefore a method for easily forming the deep p-type region is required. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2015-216182 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily form a deep p-type region. [Means for solving the problem]

[0007] A method for manufacturing a semiconductor device according to an embodiment includes forming a mask material having an opening on a surface of a silicon carbide layer, performing a first process of implanting at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons into a first region of the silicon carbide layer using the mask material as a mask, performing a first ion implantation before or after the first process of implanting a p-type impurity into a second region shallower than the first region using the mask material as a mask, removing the mask material after the first process and the first ion implantation, and performing a first heat treatment at 1600°C or more after removing the mask material. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Diagram 3] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Diagram 5] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 10]3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 12] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 13] FIG. 11 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 14] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 15] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 16] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 17] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 18] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 19] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 20] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 21] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 22] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 23] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 24] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Diagram 25] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the second embodiment. [Figure 26] 13 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a third embodiment. [Figure 27] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Figure 28]10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Figure 29] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Diagram 30] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Diagram 31] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Diagram 32] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Diagram 33] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Diagram 34] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. [Diagram 35] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.

[0010] In the following description, n + , n, n - And, p + , p, p - When the notation "n" is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p -The type may be simply referred to as p-type. The impurity concentration of each region is represented by, for example, the impurity concentration value at the center of each region, unless otherwise specified.

[0011] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). Distances such as the width and depth of the impurity region can be obtained by, for example, SIMS. Distances such as the width and depth of the impurity region can also be obtained from, for example, an SCM image.

[0012] (First embodiment) A semiconductor device according to a first embodiment includes a silicon carbide layer having a first electrode, a second electrode, a first surface located between the first electrode and the second electrode and parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first direction and the second direction and facing the first surface, the silicon carbide layer including a p-type first silicon carbide region and an n-type second silicon carbide region alternately arranged in the first direction, a p-type third silicon carbide region located between the second silicon carbide region and the first surface, and an n-type fourth silicon carbide region located between the third silicon carbide region and the first surface; a gate electrode provided on the first surface side of the silicon carbide layer, facing the third silicon carbide region, and extending in the second direction; and a gate insulating layer located between the gate electrode and the silicon carbide layer. Z measured by DLTS 1 / 2 The level density is measured by DLTS of the second silicon carbide region. 1 / 2 is smaller than the level density.

[0013] A method for manufacturing a semiconductor device according to a first embodiment includes forming a mask material having an opening on a surface of a silicon carbide layer, performing a first process of implanting at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons into a first region of the silicon carbide layer using the mask material as a mask, performing a first ion implantation process before or after the first process of implanting a p-type impurity into a second region shallower than the first region using the mask material as a mask, removing the mask material after the first process and the first ion implantation, and performing a first heat treatment at 1600°C or higher after removing the mask material.

[0014] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a planar-gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 is an n-channel MOSFET in which electrons serve as carriers. The MOSFET 100 has a superjunction structure (SJ structure).

[0015] Fig. 2 is a schematic plan view of the semiconductor device of the first embodiment. Fig. 2 is a plan view of the first surface (P1 in Fig. 1) of Fig. 1. Fig. 1 is a cross-sectional view taken along line AA' of Fig. 2.

[0016] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0017] The silicon carbide layer 10 is + Drain region 24, n - A drift region 26 of the p-type, a p-pillar region 28 of the p-type (first silicon carbide region), an n-pillar region 30 of the n-type (second silicon carbide region), a body region 32 of the p-type (third silicon carbide region), + A source region 34 (fourth silicon carbide region), + The contact area 38 is of the same type.

[0018] The silicon carbide layer 10 is located between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 has a first surface ("P1" in FIG. 1) and a second surface ("P2" in FIG. 1). Hereinafter, the first surface P1 will also be referred to as the front surface, and the second surface P2 will also be referred to as the back surface. The second surface P2 faces the first surface P1.

[0019] The first direction and the second direction are parallel to the first plane P1. The second direction is a direction intersecting the first direction. The second direction is, for example, a direction perpendicular to the first direction. The third direction is a direction perpendicular to the first plane. The third direction is a direction perpendicular to the first direction and the second direction.

[0020] Hereinafter, the term "depth" refers to the depth based on the first plane P1, and the term "thickness" refers to the length in the third direction.

[0021] The silicon carbide layer 10 is made of single crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC. The silicon carbide layer 10 has a thickness of, for example, 5 μm or more and 500 μm or less.

[0022] The first plane P1 is, for example, a plane inclined at 0 to 8 degrees with respect to the (0001) plane. That is, the normal is a plane inclined at 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off angle with respect to the (0001) plane is 0 to 8 degrees. The second plane P2 is, for example, a plane inclined at 0 to 8 degrees with respect to the (000-1) plane.

[0023] The (0001) plane is called a silicon plane. The (000-1) plane is called a carbon plane. The tilt direction of the first plane P1 and the second plane P2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 1, for example, the first direction shown in the figure is the a-axis direction.

[0024] The gate electrode 16 is provided on the first face P1 side of the silicon carbide layer 10. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14. The gate electrode 16 extends in the second direction.

[0025] The gate electrode 16 is a conductive layer, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0026] The gate insulating layer 18 is located between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is provided between the gate electrode 16 and the source regions 34, the body regions 32, and the n-pillar regions 30.

[0027] The gate insulating layer 18 is, for example, a silicon oxide film. For example, a high dielectric constant insulating film having a higher dielectric constant than a silicon oxide film can be used for the gate insulating layer 18. Also, for example, a stacked film of a silicon oxide film and a high dielectric constant insulating film can be used for the gate insulating layer 18.

[0028] The interlayer insulating layer 20 is provided on the gate electrode 16. The interlayer insulating layer 20 is, for example, a silicon oxide film. The interlayer insulating layer 20 electrically separates the gate electrode 16 and the source electrode 12.

[0029] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 is provided on the first face P1 of the silicon carbide layer 10. The source electrode 12 contacts the source region and the contact region .

[0030] The source electrode 12 includes a metal. The metal forming the source electrode 12 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 12 may include a metal silicide or a metal carbide in contact with the silicon carbide layer 10.

[0031] The drain electrode 14 is provided on the second face P2 side of the silicon carbide layer 10. The drain electrode 14 is provided on the second face P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 24.

[0032] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound, and includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0033] n + The n-type drain region 24 is provided on the second face P2 side of the silicon carbide layer 10. The drain region 24 is located between the second face P2 and the p-pillar region 28 and the n-pillar region 30.

[0034] The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 24 is higher than the n-type impurity concentration of the n-pillar region 30. The n-type impurity concentration of the drain region 24 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0035] n - The n-type drift region 26 is provided on the drain region 24. The drift region 26 is located between the second plane P2 and the p-pillar region 28 and the n-pillar region 30. The n-type impurity concentration of the drift region 26 is, for example, equal to or lower than the n-type impurity concentration of the n-pillar region 30. For example, the n-type impurity concentration of the drift region 26 is lower than the n-type impurity concentration of the n-pillar region 30.

[0036] The drift region 26 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurity in the drift region 26 is, for example, 4×10 14 cm -3 More than 1×10 18 cm -3 The following is the result.

[0037] The p-type p-pillar region 28 and the n-type n-pillar region 30 are provided between the drain region 24 and the first plane P1. The p-pillar region 28 and the n-pillar region 30 are provided between the drift region 26 and the first plane P1.

[0038] The p-pillar regions 28 and the n-pillar regions 30 are arranged alternately in a first direction. The p-pillar regions 28 and the n-pillar regions 30 form a so-called superjunction structure (SJ structure).

[0039] In the MOSFET 100 having the SJ structure, during off operation, a depletion layer extends laterally (in a first direction) in the p-pillar region 28 and the n-pillar region 30. The extension of the depletion layer in the lateral direction reduces the electric field strength in the silicon carbide layer 10, thereby achieving a high breakdown voltage.

[0040] The p-pillar region 28 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-pillar region 28 is, for example, 5×10 15 cm -3 5×10 or more 17 cm -3 The following is the result.

[0041] The n-pillar region 30 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-pillar region 30 is, for example, 5×10 15 cm -3 5×10 or more 17 cm -3 The following is the result.

[0042] For example, when the width of the p-pillar region 28 in the second direction is W1, the p-type impurity concentration of the p-pillar region 28 is N1, the width of the n-pillar region 30 in the second direction is W2, and the n-type impurity concentration of the n-pillar region 30 is N2, the relationship in the following equation is satisfied. 0.8≦(W1×N1) / (W2×N2)≦1.2

[0043] The aspect ratio (d1 / W1) between the depth d1 of the p-pillar region 28 in the third direction and the width (W1 in FIG. 1) of the p-pillar region 28 in the second direction is, for example, greater than or equal to 3. The depth d1 of the p-pillar region 28 in the third direction perpendicular to the first surface is, for example, greater than or equal to 5 μm and less than or equal to 10 μm.

[0044] Z measured by Deep Level Transient Spectroscopy (DLTS) in p-pillar region 281 / 2 The level density is measured by DLTS in the n-pillar region 30. 1 / 2 The density of the states in the p-pillar region 28 is smaller than the 1 / 2 The level density is, for example, Z 1 / 2 This is less than 50% of the level density.

[0045] Z measured by DLTS 1 / 2 The level density corresponds to the density of carbon vacancies. Therefore, the density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30.

[0046] The p-type body region 32 is located between the n-pillar region 30 and the first face P1. The p-type body region 32 is located between the p-pillar region 28 and the first face P1.

[0047] The body region 32 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-operation state, a channel through which electrons flow is formed in a region of the body region 32 in contact with the gate insulating layer 18. The region of the body region 32 in contact with the gate insulating layer 18 serves as a channel formation region.

[0048] The body region 32 contains, for example, aluminum (Al) as a p-type impurity. The impurity concentration of the p-type impurity in the body region 32 is, for example, 5×10 16 cm -3 5×10 or more 17 cm -3 The following is the result.

[0049] The depth of the body region 32 is, for example, not less than 0.2 μm and not more than 1.0 μm.

[0050] n + The source region 34 is located between the body region 32 and the first face P1. The source region 34 contacts the source electrode 12. The source region 34 contacts the gate insulating layer 18.

[0051] The source region 34 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 34 is higher than the n-type impurity concentrations of the drift region 26 and the n-pillar region 30. The n-type impurity concentration of the source region 34 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0052] The depth of the source region 34 is shallower than the depth of the body region 32. The depth of the source region 34 is, for example, not less than 0.1 μm and not more than 0.3 μm.

[0053] p + The contact region 38 is located between the body region 32 and the first face P1. The contact region 38 contacts the source electrode 12.

[0054] As shown in FIG. 2, the contact regions 38 are, for example, striped and extend in the second direction.

[0055] The contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 38 is higher than the p-type impurity concentration of the body region 32. The p-type impurity concentration of the contact region 38 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0056] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0057] Figures 3, 4, 5, 6, 7, 8, 9, 10, and 11 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device of the first embodiment. Figures 3 to 11 show cross sections corresponding to Figure 1. Below, an example will be described in which the p-type impurity is aluminum (Al).

[0058] First, n + A drain region 24 and an n -A silicon carbide layer 10 having n-type and n-type epitaxial layers 11 is prepared (FIG. 3). The epitaxial layer 11 is a layer formed by epitaxial growth on the drain region 24. Parts of the epitaxial layer 11 will eventually become the drift region 26 and the n-pillar region 30.

[0059] Next, a mask material 50 having an opening is formed on the silicon carbide layer 10 (FIG. 4). The mask material 50 is, for example, a laminated film of a silicon oxide film 50a and a metal film 50b. The metal film 50b is, for example, tungsten.

[0060] Next, using the mask material 50 as a mask, hydrogen (H) is ion-implanted into the silicon carbide layer 10 (FIG. 5). Hydrogen (H) is an example of a substance. The ion-implantation of hydrogen (H) is an example of a first process.

[0061] By the ion implantation of hydrogen (H), hydrogen (H) is implanted into the first region 51 of the silicon carbide layer 10. The ion implantation of hydrogen (H) includes multiple ion implantations. For example, the ion implantation of hydrogen (H) includes five ion implantations.

[0062] The five ion implantations are performed with different acceleration energies. Hydrogen (H) is implanted into the first portion 51a, the second portion 51b, the third portion 51c, the fourth portion 51d, and the fifth portion 51e at different depths by each of the five ion implantations. For example, the five ion implantations are performed so that the distribution of hydrogen (H) is continuous among the first portion 51a, the second portion 51b, the third portion 51c, the fourth portion 51d, and the fifth portion 51e.

[0063] The concentration of hydrogen (H) in the first region 51 is, for example, 1×10 15 cm -3 More than 1×10 21 cm -3 Hydrogen (H) ion implantation is performed as follows:

[0064] By the ion implantation of hydrogen (H), carbon vacancies are formed in the first region 51. By each of the five ion implantations, carbon vacancies are formed in a first portion 51a, a second portion 51b, a third portion 51c, a fourth portion 51d, and a fifth portion 51e at different depths.

[0065] The ion implantation of hydrogen (H) is performed, for example, at a temperature of 300° C. or higher. The ion implantation of hydrogen (H) is performed, for example, in a state where a holder on which the silicon carbide layer 10 is placed is maintained at a temperature of 300° C. or higher. By performing the ion implantation of hydrogen (H) at a temperature of 300° C. or higher, for example, deterioration in the crystallinity of the silicon carbide layer 10 is suppressed.

[0066] Next, using the mask material 50 as a mask, aluminum (Al) is ion-implanted into the silicon carbide layer 10 (FIG. 6). The ion-implantation of aluminum (Al) is an example of a first ion implantation.

[0067] By the ion implantation of aluminum (Al), aluminum (Al) is implanted into the second region 52 of the silicon carbide layer 10. The second region 52 is shallower than the first region 51.

[0068] The second region 52 overlaps, for example, a part of the first region 51. The second region 52 overlaps, for example, a part of the fifth portion 51e. The depth of the first region 51 is, for example, three times or more the depth of the second region 52.

[0069] The ion implantation of aluminum (Al) is carried out at a temperature of, for example, 300° C. or higher.

[0070] The aluminum (Al) ion implantation can also be performed, for example, before the hydrogen (H) ion implantation.

[0071] Next, a second heat treatment is performed at 300° C. or higher (FIG. 7). The second heat treatment is performed in a non-oxidizing atmosphere. For example, the second heat treatment is performed in an inert gas atmosphere. For example, the second heat treatment is performed in an argon gas atmosphere.

[0072] The second heat treatment causes aluminum (Al) to diffuse into the first regions 51, forming the p-pillar regions 28. The regions between the p-pillar regions 28 become the n-pillar regions 30.

[0073] When the ion implantation of aluminum (Al) is performed at a temperature of 300° C. or higher, aluminum (Al) diffuses into first region 51 even during the ion implantation of aluminum (Al). For example, if aluminum (Al) can be sufficiently diffused into first region 51 during the ion implantation of aluminum (Al), it is possible to omit the second heat treatment.

[0074] Next, a second ion implantation is performed to ion-implant carbon (C) into silicon carbide layer 10 using mask material 50 as a mask (FIG. 8). By the ion implantation of carbon (C), carbon (C) is implanted into third region 53. Third region 53 is shallower than first region 51.

[0075] The carbon (C) ion implantation is carried out at a temperature of, for example, 300° C. or higher.

[0076] Next, a third heat treatment is performed at 300° C. or higher (FIG. 9). The third heat treatment is performed in a non-oxidizing atmosphere. For example, the third heat treatment is performed in an inert gas atmosphere. For example, the third heat treatment is performed in an argon gas atmosphere.

[0077] The third heat treatment causes carbon (C) to diffuse into the p-pillar region .

[0078] When the carbon (C) ion implantation is performed at a temperature of 300° C. or higher, the carbon (C) diffuses into the p-pillar region 28 during the carbon (C) ion implantation. For example, if the carbon (C) can be sufficiently diffused into the p-pillar region 28 during the carbon (C) ion implantation, it is possible to omit the third heat treatment.

[0079] Next, the mask material 50 is removed. The mask material 50 is removed by using, for example, a wet etching method.

[0080] Next, a p-type body region 32 and an n-type body region 33 are formed in the epitaxial layer 11 by using a known photolithography method and an ion implantation method. + A source region 34 of the p + A mold contact area 38 is formed (FIG. 10).

[0081] Next, a carbon film 55 is formed on the surface of the silicon carbide layer 10 (FIG. 11).

[0082] Next, a first heat treatment is performed. The first heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The first heat treatment is performed in a non-oxidizing atmosphere. For example, the first heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0083] The first heat treatment activates the implanted aluminum (Al) and causes the implanted carbon (C) to fill the carbon vacancies formed by the implantation of hydrogen (H).

[0084] Next, using a known process technology, the gate insulating layer 18, the gate electrode 16, the interlayer insulating layer 20, the source electrode 12, and the drain electrode 14 are formed. By the above manufacturing method, the MOSFET 100 shown in FIG.

[0085] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0086] The MOSFET 100 has an SJ structure formed by the p-pillar region 28 and the n-pillar region 30. The SJ structure alleviates the electric field strength in the semiconductor by a depletion layer extending laterally in the p-pillar region 28 and the n-pillar region 30, thereby realizing a high breakdown voltage for the MOSFET 100. Furthermore, by providing the SJ structure, it is possible to increase the n-type impurity concentration in the n-pillar region 30. Therefore, the on-resistance of the MOSFET 100 is reduced.

[0087] The MOSFE100 has a Z measured by Deep Level Transient Spectroscopy (DLTS) in the p-pillar region 28. 1 / 2 The level density is measured by DLTS in the n-pillar region 30. 1 / 2 The density of states is smaller than the Z measured by DLTS. 1 / 2 The level density corresponds to the density of carbon vacancies. The density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30.

[0088] As described above, the SJ structure alleviates the electric field strength in the semiconductor due to the depletion layers extending laterally in the p-pillar region 28 and the n-pillar region 30, thereby realizing a high breakdown voltage for the MOSFET 100. The presence of carbon vacancies shortens the lifetime of carriers in silicon carbide. For example, the presence of carbon vacancies shortens the lifetime of holes in the p-pillar region 28 and the lifetime of electrons in the n-pillar region 30. In particular, the presence of carbon vacancies shortens the lifetime of holes compared to the lifetime of electrons.

[0089] Since the lifetime of holes is shorter than that of electrons, if the density of carbon vacancies in the p-pillar region 28 is the same as that in the n-pillar region 30, the balance between the change in depletion layer width over time in the p-pillar region 28 and the depletion layer width in the n-pillar region 30 is lost, which may result in a decrease in the breakdown voltage of the MOSFET.

[0090] In the MOSFET 100, the density of carbon vacancies in the p-pillar region 28 is lower than the density of carbon vacancies in the n-pillar region 30, thereby maintaining a balance between the time change of the depletion layer width in the p-pillar region 28 and the depletion layer width in the n-pillar region 30. Therefore, the MOSFET 100 can achieve a high breakdown voltage.

[0091] In a MOSFET with an SJ structure, it is required to form a deep p-type region in the silicon carbide layer. For example, it is required to form a deep p-type region of 5 μm or more. With normal ion implantation methods, it is difficult to implant p-type impurities such as aluminum (Al) and boron (B) into a deep region of 5 μm or more.

[0092] For this reason, for example, when forming an SJ structure, there is a method in which epitaxial growth of a silicon carbide film, ion implantation of p-type impurities, and activation annealing of the p-type impurities are repeated to form a deep p-type region in a silicon carbide layer. This method has the problem that the manufacturing cost increases due to the increased number of steps. In addition, this method has the problem that it is not suitable for miniaturizing MOSFETs because it requires alignment of the ion implantation of p-type impurities.

[0093] In addition, for example, when forming an SJ structure, there is a method of performing channeling ion implantation, in which ions of p-type impurities are implanted along a specific crystal axis, to form a deep p-type region in a silicon carbide layer. In this method, it is necessary to match the crystal orientation of the surface of the silicon carbide layer with the ion implantation direction with high precision. Therefore, there is a problem in that the variation in the crystal orientation of the surface of the silicon carbide layer causes a large variation in the depth of the p-type region.

[0094] In the method for manufacturing a semiconductor device according to the first embodiment, hydrogen (H) ion implantation is performed before ion implantation of p-type impurities to form a deep first region 51 with a high carbon vacancy density. Hydrogen (H) has a smaller ionic radius than aluminum (Al) or boron (B). Therefore, it is easy to implant hydrogen (H) to a deep region of, for example, 5 μm or more. In the first region 51, the density of carbon vacancies in silicon carbide increases due to damage caused by the ion implantation of hydrogen (H).

[0095] For example, after forming a deep first region 51 with a high carbon vacancy density, p-type impurities are ion-implanted. Then, the p-type impurities are diffused by, for example, a second heat treatment. The presence of carbon vacancies in silicon carbide promotes the diffusion of the p-type impurities. Therefore, the p-type impurities can diffuse, for example, throughout the entire first region 51, forming a deep p-type region in the silicon carbide layer. Therefore, it is possible to form a deep p-pillar region 28 in the silicon carbide layer 10.

[0096] The p-type impurities diffuse along the first region 51 having a high carbon vacancy density, and thus the lateral diffusion of the p-type impurities is suppressed, making it possible to form a p-type region that is deep and narrow in width, in other words, a p-type region with a large aspect ratio.

[0097] According to the method for manufacturing a semiconductor device of the first embodiment, it is possible to form a deep p-type region in a silicon carbide layer using a simple manufacturing method with a small number of steps.

[0098] In addition, in the method for manufacturing the semiconductor device according to the first embodiment, the ion implantation of hydrogen (H) and the multiple ion implantations of p-type impurities are performed using the same mask material, which eliminates the need for alignment of ion implantations and allows for miniaturization of MOSFETs.

[0099] Furthermore, since the method for manufacturing a semiconductor device according to the first embodiment does not depend on channeling ion implantation, it is possible to form a p-type region of the same depth regardless of the crystal orientation of the surface of the silicon carbide layer 10. Therefore, according to the method for manufacturing a semiconductor device according to the first embodiment, it is possible to suppress variations in the depth of the p-type region. Since the substrate has an off-angle, when ions are implanted into the substrate from directly above, the ions are implanted under conditions that do not cause channeling. Therefore, there is almost no variation in the depth of the ion implantation.

[0100] From the viewpoint of increasing the uniformity of the carbon vacancy density from deep to shallow portions of the first region 51, it is preferable that the ion implantation of hydrogen (H) is performed a plurality of times with different acceleration energies.

[0101] From the viewpoint of increasing the carbon vacancy density and promoting the diffusion of p-type impurities, the concentration of hydrogen (H) in the first region 51 is set to 1×10 15 cm -3 It is preferable to perform hydrogen (H) ion implantation so that the concentration is 1×10 16 cm -3 It is more preferable to implant hydrogen (H) ions so that the concentration is 1×10 17 cm -3It is more preferable to perform hydrogen (H) ion implantation so as to achieve the above.

[0102] From the viewpoint of suppressing deterioration in the crystallinity of the silicon carbide layer 10, the concentration of hydrogen (H) in the first region 51 is set to 1×10 21 cm -3 It is preferable to perform hydrogen (H) ion implantation so that the concentration is 1×10 20 cm -3 It is more preferable to implant hydrogen (H) ions so that the concentration is less than 1×10 19 cm -3 It is more preferable to perform hydrogen (H) ion implantation so that the following is satisfied:

[0103] From the viewpoint of suppressing deterioration in the crystallinity of the silicon carbide layer 10, the ion implantation of hydrogen (H) is preferably performed at a temperature of 300° C. or higher, more preferably at a temperature of 500° C. or higher, and even more preferably at a temperature of 900° C. or higher.

[0104] From the viewpoint of diffusing aluminum (Al) into the first region 51 during the first ion implantation of aluminum (Al), the first ion implantation is preferably performed at a temperature of 300° C. or higher, more preferably at a temperature of 500° C. or higher, and even more preferably at a temperature of 900° C. or higher.

[0105] From the viewpoint of promoting diffusion of aluminum (Al) into the first region 51, the temperature of the second heat treatment performed after the first ion implantation is preferably 300°C or higher, more preferably 500°C or higher, and even more preferably 900°C or higher.

[0106] From the viewpoint of eliminating carbon vacancies generated in the first region 51 by the ion implantation of hydrogen (H), it is preferable to perform a second ion implantation in which carbon (C) ions are implanted into the silicon carbide layer 10 after the diffusion of aluminum (Al).

[0107] By performing the second ion implantation, it is possible to make the density of carbon vacancies in the p-pillar region 28 smaller than the density of carbon vacancies in the n-pillar region 30.

[0108] From the viewpoint of promoting the diffusion of carbon (C) into the p-pillar region 28, the second ion implantation is preferably performed at a temperature of 300°C or higher, more preferably at a temperature of 500°C or higher, and even more preferably at a temperature of 900°C or higher. In the series of ion implantations, since the mask material 50 is composed of a laminated film of a silicon oxide film 50a and a metal film 50b, ion implantation can be performed at a high temperature range that is difficult to achieve with a resist. Since a hard mask such as a silicon oxide film 50a is used, the upper limit is about 1200°C.

[0109] From the viewpoint of promoting the diffusion of carbon (C) into the p-pillar region 28, the temperature of the third heat treatment performed after the ion implantation of carbon (C) is preferably 300°C or higher, more preferably 500°C or higher, and even more preferably 900°C or higher.

[0110] (First Modification) The manufacturing method of a semiconductor device of the first variant of the first embodiment differs from the manufacturing method of a semiconductor device of the first embodiment in that the substance is helium (He) and the first process is ion implantation of helium (He) into a first region.

[0111] Like hydrogen (H), helium (He) has a smaller ionic radius than aluminum (Al) or boron (B). For this reason, it is easy to implant it to a depth of, for example, 5 μm or more.

[0112] According to the method for manufacturing a semiconductor device of the first modified example of the first embodiment, it is possible to obtain the same functions and effects as those of the method for manufacturing a semiconductor device of the first embodiment.

[0113] (Second Modification) The manufacturing method of a semiconductor device of the second variant of the first embodiment differs from the manufacturing method of a semiconductor device of the first embodiment in that the substance is electrons and the first process is injection of electrons into a first region by irradiation with an electron beam.

[0114] Since electrons have a smaller diameter than aluminum (Al) or boron (B), they can be easily injected into a deep region, for example, 5 μm or deeper, by electron beam irradiation.

[0115] According to the method for manufacturing a semiconductor device of the second modified example of the first embodiment, it is possible to obtain the same functions and effects as those of the method for manufacturing a semiconductor device of the first embodiment.

[0116] As described above, according to the first embodiment and its modifications, a semiconductor device with high breakdown voltage can be realized. Also, according to the first embodiment and its modifications, a manufacturing method for a semiconductor device that can easily form a deep p-type region can be realized.

[0117] Second Embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer further includes a trench located on the first surface side and extending in the second direction in the first surface, and the gate electrode is provided in the trench. Also, the manufacturing method of the semiconductor device of the second embodiment differs from the manufacturing method of the semiconductor device of the first embodiment in that a trench is formed in the silicon carbide layer using a mask material as a mask before the first process and the first ion implantation. Hereinafter, some description of contents that overlap with the first embodiment may be omitted.

[0118] 12 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment is a trench-gate vertical MOSFET 200 using silicon carbide. The MOSFET 200 is an n-channel MOSFET in which electrons serve as carriers. The MOSFET 200 has a superjunction structure (SJ structure).

[0119] Fig. 13 is a schematic plan view of the semiconductor device of the second embodiment. Fig. 13 is a plan view of the first surface (P1 in Fig. 12) of Fig. 12. Fig. 12 is a cross-sectional view taken along line AA' of Fig. 13.

[0120] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0121] The silicon carbide layer 10 includes a gate trench 22 (trench), + Drain region 24, n - A drift region 26 of the p-type, a p-pillar region 28 of the p-type (first silicon carbide region), an n-pillar region 30 of the n-type (second silicon carbide region), a body region 32 of the p-type (third silicon carbide region), + A source region 34 (fourth silicon carbide region), + 36, p-type electric field relaxation region + The contact area 38 is of the same type.

[0122] The gate trench 22 is present in the silicon carbide layer 10. The gate trench 22 is located on the side of the first face P1 of the silicon carbide layer 10. The gate trench 22 is a groove formed in the silicon carbide layer 10.

[0123] The gate trenches 22 extend in a second direction as shown in Fig. 13. The gate trenches 22 are repeatedly arranged in a first direction as shown in Fig. 13. The repeat pitch of the gate trenches 22 in the first direction is, for example, 1 µm or more and 5 µm or less. The depth of the gate trenches 22 is, for example, 1 µm or more and 2 µm or less. The width of the gate trenches 22 in the first direction is, for example, 0.5 µm or more and 1 µm or less.

[0124] The gate electrode 16 is located in the gate trench 22. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14. The gate electrode 16 extends in a second direction.

[0125] The gate insulating layer 18 is located between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is provided between the gate electrode 16 and the source region 34, the body region 32, the electric field relief region 36, and the n-pillar region 30.

[0126] The p-type p-pillar region 28 and the n-type n-pillar region 30 are provided between the drain region 24 and the first plane P1. The p-pillar region 28 and the n-pillar region 30 are provided between the drift region 26 and the first plane P1.

[0127] The p-pillar region 28 is provided between the gate trench 22 and the second face P2.

[0128] The p-pillar regions 28 and the n-pillar regions 30 are arranged alternately in a first direction. The p-pillar regions 28 and the n-pillar regions 30 form a so-called superjunction structure (SJ structure).

[0129] The p-pillar region 28 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-pillar region 28 is, for example, 5×10 15 cm -3 5×10 or more 17 cm -3 The following is the result.

[0130] The n-pillar region 30 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-pillar region 30 is, for example, 5×10 15 cm -3 5×10 or more 17 cm -3 The following is the result.

[0131] For example, when the width of the p-pillar region 28 in the second direction is W1, the p-type impurity concentration of the p-pillar region 28 is N1, the width of the n-pillar region 30 in the second direction is W2, and the n-type impurity concentration of the n-pillar region 30 is N2, the relationship in the following equation is satisfied. 0.8≦(W1×N1) / (W2×N2)≦1.2

[0132] The aspect ratio (d1 / W1) between the depth d1 of the p-pillar region 28 in the third direction and the width (W1 in FIG. 12) of the p-pillar region 28 in the second direction is, for example, greater than or equal to 3. The depth d1 of the p-pillar region 28 in the third direction perpendicular to the first surface is, for example, greater than or equal to 5 μm and less than or equal to 10 μm.

[0133] Z measured by Deep Level Transient Spectroscopy (DLTS) in p-pillar region 28 1 / 2 The level density is measured by DLTS in the n-pillar region 30. 1 / 2 The density of the states in the p-pillar region 28 is smaller than the 1 / 2 The level density is, for example, Z 1 / 2 This is less than 50% of the level density.

[0134] Z measured by DLTS 1 / 2 The level density corresponds to the density of carbon vacancies. The density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30.

[0135] p + The electric field relief region 36 is located between the p-pillar region 28 and the gate trench 22. The electric field relief region 36 contacts the bottom surface of the gate trench 22. The electric field relief region 36 contacts the gate insulating layer 18. The electric field relief region 36 contacts the p-pillar region 28.

[0136] The electric field relaxation region 36 has a function of relaxing the electric field applied to the gate insulating layer 18 during the off operation of the MOSFET 200. The electric field relaxation region 36 is fixed to the same potential as the source electrode 12, for example.

[0137] The electric field buffer region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field buffer region 36 is higher than the p-type impurity concentration of the p-pillar region 28. The p-type impurity concentration of the electric field buffer region 36 is, for example, 10 times or more the p-type impurity concentration of the p-pillar region 28. The p-type impurity concentration of the electric field buffer region 36 is, for example, 5×10 17 cm -35×10 or more 19 cm -3 The following is the result.

[0138] Next, an example of a method for manufacturing the semiconductor device according to the second embodiment will be described.

[0139] Figures 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, and 25 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device of the second embodiment. Figures 14 to 25 show a cross section corresponding to Figure 12.

[0140] First, n + A drain region 24 and an n - A silicon carbide layer 10 having n-type and n-type epitaxial layers 11 is prepared (FIG. 14). Parts of the epitaxial layer 11 will eventually become the drift region 26 and the n-pillar region 30.

[0141] Next, a p-type body region 32 and an n-type body region 33 are formed in the epitaxial layer 11 by using a known photolithography method and an ion implantation method. + A source region 34 of the p + A mold contact area 38 is formed (FIG. 15).

[0142] Next, a mask material 50 having an opening is formed on the silicon carbide layer 10 (FIG. 16). The mask material 50 is, for example, a laminated film of a silicon oxide film 50a and a metal film 50b. The metal film 50b is, for example, tungsten.

[0143] Next, the gate trench 22 is formed using the mask material 50 as a mask by using a known reactive ion etching method (FIG. 17). The gate trench 22 is formed so as to penetrate the source region 34 and the body region 32.

[0144] Next, using the mask material 50 as a mask, hydrogen (H) is ion-implanted into the silicon carbide layer 10 from the opening (FIG. 18). Hydrogen (H) is implanted into the silicon carbide layer 10 from the bottom of the gate trench 22. Hydrogen (H) is an example of a substance. The ion implantation of hydrogen (H) is an example of a first process.

[0145] By the ion implantation of hydrogen (H), hydrogen (H) is implanted into the first region 51. The ion implantation of hydrogen (H) includes multiple ion implantations. For example, the ion implantation of hydrogen (H) includes four ion implantations.

[0146] The four ion implantations are performed with different acceleration energies, and hydrogen (H) is implanted into the first portion 51a, the second portion 51b, the third portion 51c, and the fourth portion 51d at different depths by the four ion implantations.

[0147] The concentration of hydrogen (H) in the first region 51 is, for example, 1×10 15 cm -3 More than 1×10 21 cm -3 Hydrogen (H) ion implantation is performed as follows:

[0148] By the ion implantation of hydrogen (H), carbon vacancies are formed in the first region 51. By each of the four ion implantations, carbon vacancies are formed in a first portion 51a, a second portion 51b, a third portion 51c, and a fourth portion 51d, each of which has a different depth.

[0149] The ion implantation of hydrogen (H) is performed, for example, at a temperature of 300° C. or higher. The ion implantation of hydrogen (H) is performed, for example, in a state where a holder on which the silicon carbide layer 10 is placed is maintained at a temperature of 300° C. or higher. By performing the ion implantation of hydrogen (H) at a temperature of 300° C. or higher, for example, deterioration in the crystallinity of the silicon carbide layer 10 is suppressed.

[0150] Next, using the mask material 50 as a mask, aluminum (Al) ions are implanted into the silicon carbide layer 10 (FIG. 19). The aluminum (Al) ion implantation is an example of a first ion implantation.

[0151] By ion implantation of aluminum (Al), aluminum (Al) is implanted into the second region 52. The second region 52 is shallower than the first region 51. The second region 52 overlaps with a portion of the first region 51. The second region 52 overlaps with, for example, a portion of the fourth portion 51d. The depth of the first region 51 is, for example, three times or more the depth of the second region 52.

[0152] The ion implantation of aluminum (Al) is carried out at a temperature of, for example, 300° C. or higher.

[0153] Next, a second heat treatment is performed at 300° C. or higher (FIG. 20). The second heat treatment is performed in a non-oxidizing atmosphere. For example, the second heat treatment is performed in an inert gas atmosphere. For example, the second heat treatment is performed in an argon gas atmosphere.

[0154] The second heat treatment causes aluminum (Al) to diffuse into the first regions 51, forming the p-pillar regions 28. The regions between the p-pillar regions 28 become the n-pillar regions 30.

[0155] When the ion implantation of aluminum (Al) is performed at a temperature of 300° C. or higher, aluminum (Al) diffuses into first region 51 even during the ion implantation of aluminum (Al). For example, if aluminum (Al) can be sufficiently diffused into first region 51 during the ion implantation of aluminum (Al), it is possible to omit the second heat treatment.

[0156] Next, a second ion implantation is performed to ion-implant carbon (C) into silicon carbide layer 10 using mask material 50 as a mask (FIG. 21). By the ion implantation of carbon (C), carbon (C) is implanted into third region 53. Third region 53 is shallower than first region 51.

[0157] The carbon (C) ion implantation is carried out at a temperature of, for example, 300° C. or higher.

[0158] Next, a third heat treatment is performed at 300° C. or higher (FIG. 22). The third heat treatment is performed in a non-oxidizing atmosphere. For example, the third heat treatment is performed in an inert gas atmosphere. For example, the third heat treatment is performed in an argon gas atmosphere.

[0159] The third heat treatment causes carbon (C) to diffuse into the p-pillar region .

[0160] When the carbon (C) ion implantation is performed at a temperature of 300° C. or higher, the carbon (C) diffuses into the p-pillar region 28 during the carbon (C) ion implantation. For example, if the carbon (C) can be sufficiently diffused into the p-pillar region 28 during the carbon (C) ion implantation, it is possible to omit the third heat treatment.

[0161] Next, aluminum (Al) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (FIG. 23). By the ion implantation of aluminum (Al), p + A field relief region 36 of the mold is formed.

[0162] Next, the mask material 50 is removed. The mask material 50 is removed by using, for example, a wet etching method.

[0163] Next, a carbon film 55 is formed on the surface of the silicon carbide layer 10 (FIG. 24).

[0164] Next, a first heat treatment is performed. The first heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The first heat treatment is performed in a non-oxidizing atmosphere. For example, the first heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0165] The first heat treatment activates the implanted aluminum (Al) and causes the implanted carbon (C) to fill the carbon vacancies formed by the implantation of hydrogen (H).

[0166] Next, using known process techniques, the gate insulating layer 18 and the gate electrode 16 are formed in the gate trench 22 (FIG. 25).

[0167] Next, using a known process technology, the interlayer insulating layer 20, the source electrode 12, and the drain electrode 14 are formed. By the above manufacturing method, the MOSFET 200 shown in FIG.

[0168] The MOSFET 200 has a trench gate structure, which makes it possible to reduce the on-resistance per unit area, as compared with, for example, the MOSFET 100 having a planar gate structure.

[0169] Moreover, the MOSFET 200 has an SJ structure formed by the p-pillar region 28 and the n-pillar region 30. Therefore, the MOSFET 200 can achieve a high breakdown voltage and a low on-resistance.

[0170] The MOSFE200 has a Z measured by Deep Level Transient Spectroscopy (DLTS) in the p-pillar region 28. 1 / 2 The level density is measured by DLTS in the n-pillar region 30. 1 / 2 The density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30 in the MOSFET 200. This maintains a balance between the time change in the depletion layer width in the p-pillar region 28 and the time change in the depletion layer width in the n-pillar region 30. This allows the MOSFET 200 to achieve a high breakdown voltage.

[0171] According to the method for manufacturing a semiconductor device of the second embodiment, similarly to the method for manufacturing a semiconductor device of the first embodiment, it is possible to form a deep p-type region in a silicon carbide layer by a simple manufacturing method with a small number of steps.

[0172] In the semiconductor device manufacturing method according to the second embodiment, for example, hydrogen (H) ion implantation and multiple ion implantations of p-type impurities are performed using the same mask material, which eliminates the need for alignment of ion implantations and allows for miniaturization of MOSFETs.

[0173] Furthermore, the method for manufacturing a semiconductor device according to the second embodiment does not rely on channeling ion implantation, and therefore it is possible to form a p-type region of the same depth regardless of the crystal orientation of the surface of silicon carbide layer 10. Therefore, according to the method for manufacturing a semiconductor device according to the second embodiment, it is possible to suppress variations in the depth of the p-type region.

[0174] As described above, according to the second embodiment, a semiconductor device with high breakdown voltage can be realized, and also according to the second embodiment, a manufacturing method for a semiconductor device that can easily form a deep p-type region can be realized.

[0175] (Third embodiment) The method for manufacturing a semiconductor device according to the third embodiment does not form an SJ structure, + The method of manufacturing the semiconductor device of the present embodiment differs from that of the first and second embodiments in that a deep contact region is formed. In the following, some of the contents that overlap with the first or second embodiment may be omitted.

[0176] 26 is a schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of the third embodiment. The semiconductor device of the third embodiment is a trench-gate vertical MOSFET 300 using silicon carbide. The MOSFET 300 is an n-channel MOSFET that uses electrons as carriers.

[0177] The MOSFET 300 includes a silicon carbide layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , and an interlayer insulating layer 20 .

[0178] The silicon carbide layer 10 includes a gate trench 22, + Drain region 24, n - a p-type drift region 26, a p-type body region 32, + Source region 34, p + The contact area 38 is of the same type.

[0179] p +The contact region 38 is located between the drift region 26 and the first face P1. The contact region 38 contacts the source electrode 12. The contact region 38 is provided between the two gate trenches 22. The depth of the contact region 38 is deeper than the depth of the body region 32.

[0180] The contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 38 is higher than the p-type impurity concentration of the body region 32. The p-type impurity concentration of the contact region 38 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0181] The deep contact region 38 in the MOSFET 300 reduces the electric field strength applied to the gate insulating layer 18 during the off operation of the MOSFET 300. The deep contact region 38 suppresses dielectric breakdown of the gate insulating layer 18 of the MOSFET 300, improving the reliability of the MOSFET 300.

[0182] Next, an example of a method for manufacturing the semiconductor device according to the third embodiment will be described.

[0183] 27, 28, 29, 30, 31, 32, 33, 34, and 35 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device of the third embodiment. Figures 27 to 35 show a cross section corresponding to FIG.

[0184] First, n + A drain region 24 and an n - A silicon carbide layer 10 having a type drift region 26 is prepared (FIG. 27). The drift region 26 is, for example, an epitaxially grown layer formed on the drain region 24.

[0185] Next, a mask material 50 having an opening is formed on the silicon carbide layer 10 (FIG. 28). The mask material 50 is, for example, a laminated film of a silicon oxide film 50a and a metal film 50b. The metal film 50b is, for example, tungsten.

[0186] Next, using the mask material 50 as a mask, hydrogen (H) is ion-implanted into the silicon carbide layer 10 (FIG. 29). Hydrogen (H) is an example of a substance. The ion-implantation of hydrogen (H) is an example of a first process.

[0187] By the ion implantation of hydrogen (H), hydrogen (H) is implanted into the first region 51. The ion implantation of hydrogen (H) includes multiple ion implantations. For example, the ion implantation of hydrogen (H) includes two ion implantations.

[0188] The two ion implantations are performed at different acceleration energies, and hydrogen (H) is implanted into the first portion 51a and the second portion 51b at different depths by the two ion implantations.

[0189] The concentration of hydrogen (H) in the first region 51 is, for example, 1×10 15 cm -3 More than 1×10 21 cm -3 Hydrogen (H) ion implantation is performed as follows:

[0190] By the ion implantation of hydrogen (H), carbon vacancies are formed in the first region 51. By each of the two ion implantations, carbon vacancies are formed in the first portion 51a and the second portion 51b at different depths.

[0191] The ion implantation of hydrogen (H) is performed, for example, at a temperature of 300° C. or higher. The ion implantation of hydrogen (H) is performed, for example, in a state where a holder on which the silicon carbide layer 10 is placed is maintained at a temperature of 300° C. or higher. By performing the ion implantation of hydrogen (H) at a temperature of 300° C. or higher, for example, deterioration in the crystallinity of the silicon carbide layer 10 is suppressed.

[0192] Next, using the mask material 50 as a mask, aluminum (Al) ions are implanted into the silicon carbide layer 10 (FIG. 30). The aluminum (Al) ion implantation is an example of a first ion implantation.

[0193] By ion implantation of aluminum (Al), aluminum (Al) is implanted into the second region 52. The second region 52 is shallower than the first region 51. The second region 52 overlaps, for example, with a part of the second portion 51b. The depth of the first region 51 is, for example, three times or more the depth of the second region 52.

[0194] The ion implantation of aluminum (Al) is carried out at a temperature of, for example, 300° C. or higher.

[0195] Next, a second heat treatment is performed at 300° C. or higher (FIG. 31). The second heat treatment is performed in a non-oxidizing atmosphere. For example, the second heat treatment is performed in an inert gas atmosphere. For example, the second heat treatment is performed in an argon gas atmosphere.

[0196] The second heat treatment causes aluminum (Al) to diffuse into the first region 51, forming p + A mold contact area 38 is formed.

[0197] When the ion implantation of aluminum (Al) is performed at a temperature of 300° C. or higher, aluminum (Al) diffuses into first region 51 even during the ion implantation of aluminum (Al). For example, if aluminum (Al) can be sufficiently diffused into first region 51 during the ion implantation of aluminum (Al), it is possible to omit the second heat treatment.

[0198] Next, a second ion implantation is performed to ion-implant carbon (C) into silicon carbide layer 10 using mask material 50 as a mask (FIG. 32). By the ion implantation of carbon (C), carbon (C) is implanted into third region 53. Third region 53 is shallower than first region 51.

[0199] The carbon (C) ion implantation is carried out at a temperature of, for example, 300° C. or higher.

[0200] Next, a third heat treatment is performed at 300° C. or higher (FIG. 33). The third heat treatment is performed in a non-oxidizing atmosphere. For example, the third heat treatment is performed in an inert gas atmosphere. For example, the third heat treatment is performed in an argon gas atmosphere.

[0201] The third heat treatment causes carbon (C) to diffuse into the contact region 38 .

[0202] When the carbon (C) ion implantation is performed at a temperature of 300° C. or higher, the carbon (C) diffuses into the contact region 38 during the carbon (C) ion implantation. For example, if the carbon (C) can be sufficiently diffused into the contact region 38 during the carbon (C) ion implantation, the third heat treatment can be omitted.

[0203] Next, the mask material 50 is removed. The mask material 50 is removed by using, for example, a wet etching method.

[0204] Next, a p-type body region 32 and an n-type body region 33 are formed in the epitaxial layer 11 by using a known photolithography method and ion implantation method. + A source region 34 is formed (FIG. 34).

[0205] Next, a carbon film 55 is formed on the surface of the silicon carbide layer 10 (FIG. 35).

[0206] Next, a first heat treatment is performed. The first heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The first heat treatment is performed in a non-oxidizing atmosphere. For example, the first heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0207] The first heat treatment activates the implanted aluminum (Al) and causes the implanted carbon (C) to fill the carbon vacancies formed by the implantation of hydrogen (H).

[0208] Next, using a known process technology, the gate trench 22, the gate insulating layer 18, the gate electrode 16, the interlayer insulating layer 20, the source electrode 12, and the drain electrode 14 are formed. By the above manufacturing method, the MOSFET 300 shown in FIG.

[0209] According to the manufacturing method of the semiconductor device of the third embodiment, it is possible to form a deep p-type region in a silicon carbide layer by a simple manufacturing method with a small number of steps, similar to the manufacturing method of the semiconductor device of the first embodiment. In addition, for example, ion implantation of hydrogen (H) and multiple ion implantations of p-type impurities are performed using the same mask material. Therefore, alignment of ion implantations is not required, and miniaturization of MOSFETs can be realized.

[0210] Furthermore, since the method does not rely on channeling ion implantation, it is possible to form a p-type region of the same depth regardless of the crystal orientation of the surface of the silicon carbide layer 10. Therefore, according to the method for manufacturing a semiconductor device of the third embodiment, it is possible to suppress variations in the depth of the p-type region.

[0211] As described above, according to the third embodiment, a manufacturing method for a semiconductor device that can easily form a deep p-type region can be realized.

[0212] In the first to third embodiments, the n-type impurity is, for example, nitrogen or phosphorus. It is also possible to use arsenic (As) or antimony (Sb) as the n-type impurity.

[0213] In the first to third embodiments, the p-type impurity is, for example, aluminum. As the p-type impurity, boron (B), gallium (Ga), and indium (In) can also be used.

[0214] In the first to third embodiments, the silicon carbide crystal structure has been described as 4H—SiC, but the present invention can also be applied to silicon carbide having other crystal structures, such as 6H—SiC and 3C—SiC.

[0215] In the first to third embodiments, the p-pillar region 28 or the contact region 38 has been described as an example of a deep p-type region, but the present invention can also be applied to other deep p-type regions formed in a silicon carbide layer.

[0216] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0217] 10 Silicon carbide layer 12 source electrode (first electrode) 14 Drain electrode (second electrode) 16 Gate electrode 18 Gate insulating layer 22 Gate trench (trench) 28 p pillar region (first silicon carbide region) 30 n-pillar region (second silicon carbide region) 32 Body region (third silicon carbide region) 34 source region (fourth silicon carbide region) 50 Masking material 50b metal film 51 First Area 52 Second Area 55 Carbon Film 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) P1 First surface (front surface) P2 Second Side

Claims

1. forming a mask material having an opening on a surface of a silicon carbide layer; performing a first process of injecting at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons into a first region of the silicon carbide layer using the mask material as a mask; performing a first ion implantation step, before or after the first treatment, of implanting a p-type impurity into a second region shallower than the first region using the mask material as a mask; After the first treatment and the first ion implantation, the mask material is stripped off; A method for manufacturing a semiconductor device, comprising: performing a first heat treatment at 1600° C. or higher after removing the mask material.

2. The method of claim 1 , wherein the first treatment comprises a plurality of treatments, each of the plurality of treatments implanting the at least one substance to a different depth in the silicon carbide layer.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first ion implantation is performed after said first treatment, and said first ion implantation is performed at a temperature of 300.degree. C. or higher.

4. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: performing a second heat treatment at 300[deg.] C. or more after said first treatment and said first ion implantation and before removing said mask material.

5. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: after said first ion implantation, and before said mask material is peeled off, performing a second ion implantation in which carbon (C) is ion-implanted using said mask material as a mask.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the second ion implantation is performed at a temperature of 300.degree. C. or higher.

7. 6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of: performing a third heat treatment at 300[deg.] C. or more after said second ion implantation and before removing said mask material.

8. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the depth of said first region is at least three times as large as the depth of said second region.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first region has a depth of 5 [mu]m or more.

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first treatment is carried out at a temperature of 300.degree. C. or higher.

11. The concentration of the at least one substance in the first region is 1×10 １５ cm －３ Above 1 x 10 ２１ cm －３ 2. The method of claim 1, wherein the semiconductor device is manufactured as follows:

12. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of forming a carbon film on a surface of said silicon carbide layer after said mask material is removed and before said first heat treatment.

13. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said mask material includes a metal film.

14. The method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of: forming a trench in said silicon carbide layer using said mask material as a mask, before said first treatment and said first ion implantation.

15. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said p-type impurity is aluminum (Al) or boron (B).

16. A first electrode; A second electrode; and a silicon carbide layer located between the first electrode and the second electrode, the silicon carbide layer having a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first direction and the second direction and facing the first surface, p-type first silicon carbide regions and n-type second silicon carbide regions alternately arranged in the first direction; a p-type third silicon carbide region located between the second silicon carbide region and the first surface; a fourth silicon carbide region of n-type located between the third silicon carbide region and the first surface; A silicon carbide layer comprising: a gate electrode provided on a side of the silicon carbide layer facing the third silicon carbide region and extending in the second direction; a gate insulating layer located between the gate electrode and the silicon carbide layer; Z measured by Deep Level Transient Spectroscopy (DLTS) of the first silicon carbide region １／２ The state density is measured by DLTS of the second silicon carbide region. １／２ A semiconductor device having a level density smaller than that of the semiconductor device.

17. the silicon carbide layer further includes a trench located on the first surface and extending in the second direction in the first surface, The semiconductor device according to claim 16 , wherein the gate electrode is provided in the trench.

18. The semiconductor device of claim 17 , wherein said first silicon carbide region is provided between said trench and said second surface.

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