Semiconductor device, electronic apparatus, and manufacturing method of semiconductor device

Abstract

To suppress a characteristic variation caused by a process variation.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a plurality of element separation parts; and a field effect transistor. The field effect transistor is provided between an upper surface part of a first element separation part and an upper surface part of a second element separation part of the plurality of element separation parts in a plan view. The field effect transistor comprises: a gate electrode; a fin part; a gate insulation film; and a convex part. The convex part is formed between an embedded part of the gate electrode and a side wall part of at least one of the first and second element separation parts, and has a width narrower than the fin part. In the convex part, an impurity of conductive type that is opposite to a conductive type of the fin part is distributed in a high concentration as compared with the impurity contained in an inner part of the semiconductor substrate other than the convex part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, an electronic device equipped with the semiconductor device, and a method for manufacturing the semiconductor device. [Background technology]

[0002] A solid-state imaging device (photodetector) is equipped with a source follower circuit that converts the charges photoelectrically converted by a photoelectric conversion unit into pixel signals based on the charges and outputs them. It is known that fin field effect transistors (hereinafter referred to as Fin-FETs) are often used in circuits within the device, including the source follower circuit, to improve characteristics.

[0003] For example, Patent Document 1 discloses a transistor having a gate electrode having a buried portion formed so as to be buried from a planar portion formed planarly on the surface of a semiconductor substrate toward the inside of the semiconductor substrate, and a channel region (fin portion) that contacts the side surface of the buried portion via an insulating film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-183636 A Summary of the Invention [Problem to be solved by the invention]

[0005] Among recessed gate Fin-FETs, those with shallow recesses of up to about 100 nm have a small footprint, are advantageous for miniaturization, and can be manufactured at low cost with fewer process steps. On the other hand, when a sharp silicon protrusion is formed between a tapered device isolation region (STI) and a silicon (Si) substrate, the protrusion is regarded as a tiny Fin-FET and can easily become a parasitic transistor. Furthermore, the height and width of the protrusion and device isolation region vary due to process variations, which ultimately becomes a cause of variation in the on-characteristics of the transistor.

[0006] The present disclosure has been made in view of the above circumstances, and has an object to provide a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device that are capable of suppressing characteristic variations caused by process variations. [Means for solving the problem]

[0007] One aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction, a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on a side of the first surface portion, and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, the field effect transistor including a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more field effect transistors embedded from the planar portion toward an interior of the semiconductor substrate. a gate electrode having a planar portion and a buried portion above the planar portion, a fin portion covered by the planar portion and the buried portion of the gate electrode and forming a channel, a gate insulating film arranged between the gate electrode and the fin portion, and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a narrower width than the fin portion, wherein impurities of a conductivity type opposite to that of the fin portion are distributed in a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion.

[0008] Another aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides in a thickness direction, a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side, and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, the field effect transistor having a flat portion formed in a planar manner on the first surface portion of the semiconductor substrate and a field effect transistor embedded from the flat portion toward the inside of the semiconductor substrate. the gate insulating film disposed between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a width narrower than that of the fin portion; and a convex portion insulating film disposed between the convex portion and the gate electrode, the convex portion insulating film being thicker than the gate insulating film covering the fin portion.

[0009] Another aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction, a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side, and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, the field effect transistor having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward an interior of the semiconductor substrate. the buried portion of the gate electrode and at least one of the sidewall portions of the first element isolation portion and the second element isolation portion, the convex portion having a narrower width than the fin portion, wherein the convex portion distributes impurities of a conductivity type opposite to that of the fin portion at a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion.

[0010] Another aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction, a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side, and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, the field effect transistor having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more field effect transistors embedded from the planar portion toward the inside of the semiconductor substrate. the gate insulating film disposed between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a width narrower than that of the fin portion; and a convex portion insulating film disposed between the convex portion and the gate electrode, the convex portion insulating film being thicker than the gate insulating film covering the fin portion.

[0011] Furthermore, another aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; forming a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having a top surface portion and a sidewall portion provided on the first surface portion side; forming a recessed portion in the thickness direction from the first surface portion of the semiconductor substrate between the first element isolation portion and the second element isolation portion among the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; distributing impurities of a conductivity type opposite to that of the fin portion in the convex portion at a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion; and covering the fin portion via a gate insulating film, and forming a gate electrode of the field effect transistor between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view illustrating a schematic configuration example of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 3] 6 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a second embodiment of the present disclosure. FIG. [Figure 4] 11 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a third embodiment of the present disclosure. FIG. [Diagram 5] 11 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. [Figure 6] FIG. 11 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 7] 13 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a sixth embodiment of the present disclosure. FIG. [Figure 8] FIG. 13 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 9A] 13A to 13C are cross-sectional views (part 1) illustrating a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 9B] 13A to 13C are cross-sectional views (part 2) illustrating a process procedure of the method for manufacturing a semiconductor device according to the seventh embodiment of the present disclosure. [Figure 9C] 13A to 13C are cross-sectional views (part 3) illustrating a process procedure of the method for manufacturing a semiconductor device according to the seventh embodiment of the present disclosure. [Figure 9D] 13A to 13C are cross-sectional views (part 4) illustrating a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 9E] 13A to 13C are cross-sectional views (part 5) illustrating a process procedure of the method for manufacturing a semiconductor device according to the seventh embodiment of the present disclosure. [Figure 10] FIG. 13 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 11]FIG. 13 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 12] FIG. 23 is a cross-sectional view illustrating a schematic configuration example of a semiconductor device according to a tenth embodiment of the present disclosure. [Figure 13] FIG. 23 is a diagram showing a schematic configuration of an example of a light detection device according to an eleventh embodiment of the present disclosure. [Figure 14] FIG. 23 is a diagram illustrating an example of a schematic configuration of a photodetector according to a twelfth embodiment of the present disclosure. [Figure 15] 15 is a circuit diagram showing an example of a sensor pixel and a readout circuit shown in FIG. 14. [Figure 16] FIG. 1 is a block diagram showing an example of the configuration of an electronic device. [Figure 17] 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the present technology is applied. [Figure 18] 18 is a block diagram showing an example of a functional configuration of a camera head and a CCU shown in FIG. 17. [Figure 19] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system to which the present technology is applied. [Figure 20] 20 is an explanatory diagram showing an example of the installation positions of the outside-of-vehicle information detection unit and the imaging unit shown in FIG. 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are given the same or similar reference numerals, and duplicated descriptions are omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc. differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0014] In this specification, the "first conductivity type" refers to either p-type or n-type, and the "second conductivity type" refers to either p-type or n-type that is different from the "first conductivity type." In addition, "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without "+" or "-". However, even if the semiconductor regions have the same "n" and "n" attached, it does not mean that the impurity density of each semiconductor region is strictly the same.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical ideas of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read. The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0016] <First embodiment> (Example of the configuration of a semiconductor device) Fig. 1 is a plan view showing a schematic configuration example of a semiconductor device 1 according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view showing a schematic configuration example of the semiconductor device 1 according to the first embodiment of the present disclosure. Fig. 2 shows a cross section taken along line A-A' in the plan view shown in Fig. 1.

[0017] As shown in Figures 1 and 2, the semiconductor device 1 of the first embodiment includes a semiconductor substrate 2, an N-type MOS (Metal Oxide Semiconductor) transistor 3 (an example of a "field effect transistor" in the present disclosure) provided on the semiconductor substrate 2, and a plurality of element isolation portions 5 extending in the thickness direction of the semiconductor substrate 2 (the direction indicated by the arrow Z in Figure 1).

[0018] The semiconductor substrate 2 is made of, for example, single crystal silicon. The semiconductor substrate 2 has a surface 2a (an example of a "first surface" in the present disclosure) and a back surface 2b (an example of a "second surface" in the present disclosure) located on the opposite side of the surface 2a. A MOS transistor 3 is provided on the surface 2a side of the semiconductor substrate 2. The element isolation portion 5 is an insulating film for electrically isolating adjacent elements in the horizontal direction, and is made of, for example, a silicon oxide film embedded in a trench. The MOS transistor 3 is provided between a first element isolation portion 51 and a second element isolation portion 52 among the multiple element isolation portions 5. The first element isolation portion 51 has a forward tapered structure and has an upper surface portion 51a on the surface 2a side of the semiconductor substrate 2 and a sidewall portion 51b extending in the thickness direction of the semiconductor substrate 2 (the direction indicated by the arrow Z in FIG. 2). The second element isolation portion 52 has a forward tapered structure and has an upper surface portion 52a on the surface 2a side of the semiconductor substrate 2 and a sidewall portion 52b extending in the thickness direction of the semiconductor substrate 2. Note that the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 are not at the same height as the surface 2a of the semiconductor substrate 2. Specifically, the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 may be higher than the surface 2a of the semiconductor substrate 2. The MOS transistor 3 is laid out between the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 in a plan view.

[0019] The MOS transistor 3 has a fin portion 10 in which a channel is formed, a gate insulating film 20, a gate electrode 30, and a source region 41 and a drain region 42 provided in the semiconductor substrate 2.

[0020] The fin portion 10 is, for example, a part of the semiconductor substrate 2, and is made of single crystal silicon. The conductivity type of the fin portion 10 is, for example, n-type. The gate insulating film 20 is provided so as to cover the upper surface and side surfaces of the fin portion 10. The upper surface of the fin portion 10 is part of the surface 2a of the semiconductor substrate 2. The gate insulating film 20 is, for example, made of a silicon oxide film. The fin portion 10 is, for example, long in the Y-axis direction and short in the X-axis direction.

[0021] The gate electrode 30 has a planar portion 31 and at least one buried portion 32, and covers the fin portion 10 via the gate insulating film 20. For example, the gate electrode 30 is disposed so as to face the upper surface and side surface of the fin portion 10 via the gate insulating film 20. This allows the gate electrode 30 to simultaneously apply a gate voltage to the upper surface and side surface of the fin portion 10. That is, the gate electrode 30 can simultaneously apply a gate voltage to the fin portion 10 from three directions, namely, the upper side and both the left and right sides. This allows the gate electrode 30 to completely deplete the fin portion 10. The gate electrode 30 is made of, for example, a polysilicon (Poly-Si) film doped with impurities.

[0022] The flat portion 31 of the gate electrode 30 is formed planarly on the surface 2a of the semiconductor substrate 2, part of the upper surface portion 51a of the first device isolation portion 51, and part of the upper surface portion 52a of the second device isolation portion 52. Of the multiple buried portions 32, the first buried portion 321 is located on the first device isolation portion 51 side and is buried from the flat portion 31 toward the inside of the semiconductor substrate 2. The second buried portion 322 is located on the second device isolation portion 52 side and is buried from the flat portion 31 toward the inside of the semiconductor substrate 2.

[0023] The source region 41 is provided on the surface 2a of the semiconductor substrate 2 and in its vicinity. In the Y-axis direction in FIG. 1, the source region 41 is connected to one side of the fin portion 10. The drain region 42 is provided on the surface 2a of the semiconductor substrate 2 and in its vicinity. In the Y-axis direction in FIG. 1, the drain region 42 is connected to the other side of the fin portion 10. A channel is formed between the source region 41 and the drain region 42 when the gate voltage applied to the gate electrode 30 exceeds a threshold voltage.

[0024] In the first embodiment, a recessed portion 51c is formed from the upper surface 51a of the first element isolation portion 51 in the thickness direction of the semiconductor substrate 2 (the direction indicated by Z in FIG. 2), and a recessed portion 52c is further formed from the upper surface 52a of the second element isolation portion 52 in the thickness direction of the semiconductor substrate 2. A first buried portion 321 of the gate electrode 30 is buried in the recessed portion 51c. A second buried portion 322 of the gate electrode 30 is buried in the recessed portion 52c. A protruding portion 621 having a width narrower than the fin portion 10 is formed between the recessed portion 51c and the semiconductor substrate 2. A protruding portion 622 having a width narrower than the fin portion 10 is further formed between the recessed portion 52c and the semiconductor substrate 2. A gate insulating film 20 is disposed around the protruding portions 621 and 622. Furthermore, the height of the tops of the protrusions 621 and 622 is lower than the upper surface of the fin portion 10 and higher than the bottoms of the respective recessed portions 51c and 52c.

[0025] These protruding parts 621, 622 are regarded as minute Fin-FETs and easily become parasitic transistors, and furthermore, the height and width of the element isolation part 5 vary due to process variations, which ultimately become a factor of variation in the on-characteristics of the transistor. Therefore, in the first embodiment of the present disclosure, impurities of a second conductivity type (e.g., p-type) opposite to the first conductivity type (e.g., n-type) of the fin part 10 are doped inside each of the protruding parts 621, 622 to form a high-concentration second conductivity type region 63 distributed at a higher concentration than the second conductivity type region 61 included inside the semiconductor substrate 2 other than the protruding parts 621, 622. This promotes the movement of carriers from the second conductivity type region 61 of the semiconductor substrate 2 to the fin part 10, and suppresses the movement of carriers to the protruding parts 621, 622. Therefore, it is possible to suppress characteristic variations caused by process variations.

[0026] <Effects of the First Embodiment> As described above, according to the first embodiment, the inside of each of the protruding portions 621, 622 is doped with impurities of the second conductivity type opposite to the first conductivity type of the fin portion 10 to form a high-concentration second conductivity type region 63 distributed at a higher concentration than the second conductivity type region 61 included in the inside of the semiconductor substrate 2 other than the protruding portions 621, 622, so that it is possible to prevent an inversion layer from being preferentially formed in the protruding portions 621, 622 rather than in the fin portion 10, thereby promoting the movement of carriers from the second conductivity type region 61 of the semiconductor substrate 2 to the fin portion 10 and suppressing the movement of carriers to the protruding portions 621, 622. As a result, it is possible to suppress characteristic variations caused by process variations.

[0027] <Second embodiment> 3 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1A according to a second embodiment of the present disclosure, in which the same parts as those in FIG. 2 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0028] In the second embodiment of the present disclosure, the gate electrode 30A of the MOS transistor 3A further includes a third buried portion 323. The third buried portion 323 is formed between the first buried portion 321 and the second buried portion 322. The first fin portion 11 is formed between the first buried portion 321 and the third buried portion 323. The second fin portion 12 is formed between the second buried portion 322 and the third buried portion 323. This allows the gate electrode 30A to simultaneously apply gate voltages in three directions to the top surface portion and the side surface portion of each of the first fin portion 11 and the second fin portion 12.

[0029] <Effects of the second embodiment> As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained, and the gate electrode 30A can simultaneously apply gate voltages in three directions to the upper and side portions of each of the first fin portion 11 and the second fin portion 12, thereby realizing a transistor with high driving capability.

[0030] <Third embodiment> 4 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1B according to a third embodiment of the present disclosure, in which the same parts as those in FIG. 2 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0031] In the third embodiment of the present disclosure, the first element isolation portion 51 is formed from the upper surface portion 51a in the thickness direction of the semiconductor substrate 2 (the direction indicated by the arrow Z in FIG. 4), and has a dug portion 51d in which the first buried portion 321 of the gate electrode 30 is buried. The second element isolation portion 52 is formed from the upper surface portion 52a in the thickness direction of the semiconductor substrate 2, and has a dug portion 52d in which the second buried portion 322 of the gate electrode 30 is buried.

[0032] The bottom of dug portion 51d is higher than the height of the top of protrusion 621. The bottom of dug portion 52d is higher than the height of the top of protrusion 622. In the third embodiment of the present disclosure, similarly to the above-described first embodiment, the inside of each of protrusions 621, 622 is doped with impurities of a second conductivity type opposite to the first conductivity type of fin portion 10, to form high-concentration second-conductivity type region 63 distributed at a higher concentration than second-conductivity type region 61 included inside semiconductor substrate 2 other than protrusions 621, 622.

[0033] <Effects of the Third Embodiment> As described above, the third embodiment also provides the same effects as the first embodiment.

[0034] <Fourth embodiment> 5 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1C according to a fourth embodiment of the present disclosure, in which the same parts as those in FIG. 2 are denoted by the same reference numerals and detailed description thereof will be omitted. In the fourth embodiment of the present disclosure, a convex insulating film 71 is disposed between the convex portion 621 and the first buried portion 321 of the gate electrode 30. In addition, a convex insulating film 72 is disposed between the convex portion 622 and the second buried portion 322 of the gate electrode 30. The convex insulating films 71, 72 are thicker than the gate insulating film 20 covering the fin portion 10 by at least 1 nm or more around the entire periphery of the convex portions 621, 622.

[0035] <Effects of the Fourth Embodiment> As described above, according to the fourth embodiment, the protrusion insulating films 71, 72 are disposed between the protrusions 621, 622 and the gate electrode 30, and the protrusion insulating films 71, 72 are formed to be thicker than the gate insulating film 20 covering the fin portion 10, thereby preventing an inversion layer from being preferentially formed on the protrusions 621, 622 rather than on the fin portion 10. This makes it possible to suppress characteristic variations caused by process variations.

[0036] <Fifth embodiment> 6 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1D according to a fifth embodiment of the present disclosure, in which the same parts as those in FIG. 2 and FIG. 5 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0037] In the fifth embodiment of the present disclosure, the same effects as those of the fourth embodiment can be obtained, and the gate electrode 30A can simultaneously apply gate voltages in three directions to the upper and side portions of each of the first fin portion 11 and the second fin portion 12, thereby realizing a transistor with high driving capability.

[0038] Sixth embodiment 7 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1E according to a sixth embodiment of the present disclosure, in which the same parts as those in FIGS. 4 and 5 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0039] In the sixth embodiment of the present disclosure, the same effects as those of the third and fourth embodiments can be obtained.

[0040] <Seventh embodiment> 8 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1F according to a seventh embodiment of the present disclosure, in which the same parts as those in FIG. 2 and FIG. 5 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0041] In the seventh embodiment of the present disclosure, the high concentration second conductivity type region 63 or the second conductivity type region is not formed inside each of the protrusions 621, 622. In addition, the height of the top of the protrusions 621, 622 is higher than the bottom of each of the recessed portions 51c, 52c, so that the protrusions are oxidized in all directions. This makes it easier to thicken the protrusion insulating films 71, 72.

[0042] (Method of manufacturing a semiconductor device) 9A to 9E are cross-sectional views showing the process steps of a method for manufacturing a semiconductor device 1F according to a seventh embodiment of the present disclosure. The semiconductor device 1F is manufactured using various types of equipment, such as a film forming equipment (including a CVD (Chemical Vapor Deposition) equipment and a sputtering equipment), an ion implantation equipment, a heat treatment equipment, an etching equipment, a CMP (Chemical Mechanical Polishing) equipment, and a bonding equipment. Hereinafter, these equipments are collectively referred to as manufacturing equipment.

[0043] In FIG. 9A, a semiconductor substrate 2 made of single crystal silicon is prepared. As shown in FIG. 9B, the manufacturing equipment forms a plurality of element isolation portions 5 in the semiconductor substrate 2. Next, in FIG. 9C, the manufacturing equipment forms an anti-reflection film 81 on the surface 2a of the semiconductor substrate 2, the upper surface portion 51a of the first element isolation portion 51, and the upper surface portion 52a of the second element isolation portion 52, and patterns a resist on the anti-reflection film 81 in a lithography process to form trenches 821 and 822 so as to overlap the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52. As a result, the fin portion 10 and the protrusions 621 and 622 are formed.

[0044] Next, in FIG. 9D(1), the manufacturing equipment removes the anti-reflection film 81 and the resist in a dry etching process, forms the gate insulating film 20 on the upper surface and side surface of the fin portion 10, forms the convex insulating film 71 around the convex portion 621, and forms the convex insulating film 721 around the convex portion 622. At this time, as shown in FIG. 9D(2), for example, an insulating material is formed on the convex portion 622, and a resist mask is formed on the insulating material by a well-known photography technique. Then, in the opening of the resist mask, an insulating material is deposited so that the thickness of the insulating material is thicker than the thickness of the gate insulating film 20. Then, the resist mask is removed.

[0045] Thereafter, in FIG. 9E, the manufacturing equipment forms gate electrode 30 in dug portion 51c of first element isolation portion 51, dug portion 52c of second element isolation portion 52, and on front surface 2a of semiconductor substrate 2.

[0046] <Effects of the Seventh Embodiment> As described above, according to the seventh embodiment, the protrusion insulating films 71, 72 are disposed between the protrusions 621, 622 and the gate electrode 30, and the protrusion insulating films 71, 72 are formed to be thicker than the gate insulating film 20 covering the fin portion 10, thereby preventing an inversion layer from being preferentially formed on the protrusions 621, 622 rather than on the fin portion 10. This makes it possible to suppress characteristic variations caused by process variations.

[0047] <Eighth embodiment> 10 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1G according to an eighth embodiment of the present disclosure, in which the same parts as those in FIG. 2 and FIG. 5 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0048] In the eighth embodiment of the present disclosure, the same effects as those of the seventh embodiment can be obtained, and the gate electrode 30A can simultaneously apply gate voltages in three directions to the upper and side portions of each of the first fin portion 11 and the second fin portion 12, thereby realizing a transistor with high driving capability.

[0049] <Ninth embodiment> 11 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1H according to a ninth embodiment of the present disclosure, in which the same parts as those in FIGS. 4 and 8 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0050] In the ninth embodiment of the present disclosure, the same effects as those of the third and seventh embodiments can be obtained.

[0051] <Tenth embodiment> 12 is a cross-sectional view showing a schematic configuration example of a semiconductor device 1I according to a tenth embodiment of the present disclosure, in which the same parts as those in FIG. 11 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0052] In the tenth embodiment of the present disclosure, a convex insulating film 91 is disposed between the convex portion 621 and the first buried portion 321 of the gate electrode 30. In addition, a convex insulating film 92 is disposed between the convex portion 622 and the second buried portion 322 of the gate electrode 30. The convex insulating film 91 is composed of a first portion 911 having a maximum first thickness that is thicker than the gate insulating film 20 covering the fin portion 10 at the top, and a second portion 912 that is thinner than the first thickness. The convex insulating film 91 gradually becomes thicker from the second portion 912 to the first portion 911.

[0053] The protrusion insulating film 92 is composed of a first portion 921 having a maximum first thickness that is thicker than the gate insulating film 20 covering the fin portion 10 at its top, and a second portion 922 having a thickness thinner than the first thickness. The protrusion insulating film 92 gradually becomes thicker from the second portion 922 to the first portion 921.

[0054] In the tenth embodiment of the present disclosure, the same effects as those of the seventh embodiment can be obtained.

[0055] <Eleventh embodiment> (An example of the first photodetector) Any one of the semiconductor device 1 according to the first embodiment, the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the third embodiment, the semiconductor device 1C according to the fourth embodiment, the semiconductor device 1D according to the fifth embodiment, the semiconductor device 1E according to the sixth embodiment, the semiconductor device 1F according to the seventh embodiment, the semiconductor device 1G according to the eighth embodiment, the semiconductor device 1H according to the ninth embodiment, and the semiconductor device 1I according to the tenth embodiment can be applied to the first photodetector. Hereinafter, an example of the first photodetector to which the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are applied will be described.

[0056] FIG. 13 shows a schematic configuration of an example of a photodetector according to an eleventh embodiment of the present disclosure. As shown in FIG. 13, the photodetector 1-1 of this example is configured to include a semiconductor substrate 11-1, a pixel region (so-called imaging region) 3-1 in which pixels 2-1 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on, for example, a silicon substrate, and a peripheral circuit section. The pixel 2-1 includes, for example, a photodiode serving as a photoelectric conversion element, and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be configured with, for example, three transistors, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor can be added to configure a total of four transistors. The equivalent circuit of the unit pixel is the same as that of a normal pixel, and therefore a detailed description thereof will be omitted. The pixel 2-1 can also have a shared pixel structure. In the third embodiment of the present disclosure, the MOS transistor 3 described in the first embodiment or the MOS transistor 3A described in the second embodiment is used for one or more of the plurality of pixel transistors.

[0057] This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor shared therewith.

[0058] The peripheral circuit section includes a vertical drive circuit 4-1, a column signal processing circuit 5-1, a horizontal drive circuit 6-1, an output circuit 7-1, a control circuit 8-1, and the like.

[0059] The control circuit 8-1 receives an input clock and data instructing the operation mode, etc., and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8-1 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4-1, column signal processing circuit 5-1, horizontal drive circuit 6-1, etc., based on a vertical synchronizing signal, a horizontal synchronizing signal, and a master clock. These signals are then input to the vertical drive circuit 4-1, column signal processing circuit 5-1, horizontal drive circuit 6-1, etc.

[0060] The vertical drive circuit 4-1 is, for example, configured by a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixel by row. That is, the vertical drive circuit 4-1 sequentially selects and scans each pixel 2-1 in the pixel region 3-1 by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in response to the amount of light received in, for example, a photodiode serving as a photoelectric conversion element of each pixel 2-1 to the column signal processing circuit 5-1 through a vertical signal line 9-1.

[0061] The column signal processing circuit 5-1 is arranged, for example, for each column of the pixels 2-1, and performs signal processing such as noise removal on signals output from one row of the pixels 2-1 for each pixel column. That is, the column signal processing circuit 5-1 performs signal processing such as CDS for removing fixed pattern noise specific to the pixels 2-1, signal amplification, AD conversion, etc. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5-1 and connected between the horizontal signal line 10-1.

[0062] The horizontal drive circuit 6-1 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5-1 in turn, and cause each of the column signal processing circuits 5-1 to output a pixel signal to the horizontal signal line 10-1.

[0063] The output circuit 7-1 processes signals sequentially supplied from each of the column signal processing circuits 5-1 through the horizontal signal line 10-1 and outputs the processed signals. For example, the output circuit 7-1 may only perform buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 12-1 exchanges signals with the outside.

[0064] As described above, according to the eleventh embodiment, even when applied to the photodetector 1-1, the same effects as those of the first to tenth embodiments can be obtained.

[0065] <Twelfth embodiment> (Example of application to a second photodetector) Any one of the semiconductor device 1 according to the first embodiment, the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the third embodiment, the semiconductor device 1C according to the fourth embodiment, the semiconductor device 1D according to the fifth embodiment, the semiconductor device 1E according to the sixth embodiment, the semiconductor device 1F according to the seventh embodiment, the semiconductor device 1G according to the eighth embodiment, the semiconductor device 1H according to the ninth embodiment, and the semiconductor device 1I according to the tenth embodiment can be applied to the second photodetector. An example of the second photodetector to which the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are applied will be described below.

[0066] 14 illustrates an example of a schematic configuration of a photodetector 1-2 according to a twelfth embodiment of the present disclosure. The photodetector 1-2 includes three substrates (a first substrate 10-2, a second substrate 20-2, and a third substrate 30-2). The photodetector 1-2 has a three-dimensional structure formed by bonding together the three substrates (the first substrate 10-2, the second substrate 20-2, and the third substrate 30-2). The first substrate 10-2, the second substrate 20-2, and the third substrate 30-2 are stacked in this order.

[0067] The first substrate 10-2 has a plurality of sensor pixels 12-2 that perform photoelectric conversion on a semiconductor substrate 11-2. The plurality of sensor pixels 12-2 are arranged in a matrix in a pixel region 13-2 on the first substrate 10-2. The second substrate 20-2 has a readout circuit 22-2 that outputs a pixel signal based on the charge output from the sensor pixel 12-2, one for every four sensor pixels 12-2, on a semiconductor substrate 21-2. The second substrate 20-2 has a plurality of pixel driving lines 23-2 extending in the row direction and a plurality of vertical signal lines 24-2 extending in the column direction. The third substrate 30-2 has a logic circuit 32-2 that processes pixel signals on a semiconductor substrate 31-2. The logic circuit 32-2 has, for example, a vertical driving circuit 33-2, a column signal processing circuit 34-2, a horizontal driving circuit 35-2, and a system control circuit 36-2. The logic circuit 32-2 (specifically, the horizontal drive circuit 35-2) outputs the output voltage Vout for each sensor pixel 12-2 to the outside. In the logic circuit 32-2, for example, a low-resistance region made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0068] The vertical driving circuit 33-2, for example, sequentially selects the plurality of sensor pixels 12-2 in row units. The column signal processing circuit 34-2, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12-2 in the row selected by the vertical driving circuit 33-2. The column signal processing circuit 34-2, for example, performs CDS processing to extract a signal level of the pixel signal and holds pixel data according to the amount of light received by each sensor pixel 12-2. The horizontal driving circuit 35-2, for example, sequentially outputs the pixel data held in the column signal processing circuit 34-2 to the outside. The system control circuit 36-2, for example, controls driving of each block (the vertical driving circuit 33-2, the column signal processing circuit 34-2, and the horizontal driving circuit 35-2) in the logic circuit 32-2.

[0069] Fig. 15 shows an example of a sensor pixel 12-2 and a readout circuit 22-2. In the following, a case where four sensor pixels 12-2 share one readout circuit 22-2 as shown in Fig. 15 will be described. Here, "shared" refers to the outputs of the four sensor pixels 12-2 being input to a common readout circuit 22-2.

[0070] Each sensor pixel 12-2 has a common component. In Fig. 15, in order to distinguish the components of each sensor pixel 12-2 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference number of the component of each sensor pixel 12-2. In the following, when it is necessary to distinguish the components of each sensor pixel 12-2 from one another, an identification number is added to the end of the reference number of the component of each sensor pixel 12-2, but when it is not necessary to distinguish the components of each sensor pixel 12-2 from one another, the identification number at the end of the reference number of the component of each sensor pixel 12-2 is omitted.

[0071] Each sensor pixel 12-2 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23-2. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0072] The floating diffusions FD of the sensor pixels 12-2 sharing one readout circuit 22-2 are electrically connected to each other and to the input terminal of the common readout circuit 22-2. The readout circuit 22-2 has, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted as necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22-2) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23-2 (see FIG. 14). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22-2) is electrically connected to the vertical signal line 24-2, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23-2 (see FIG. 8).

[0073] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22-2. The amplification transistor AMP generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34-2 via the vertical signal line 24-2. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors. In the fourth embodiment of the present disclosure, the MOS transistor 3 described in the first embodiment or the MOS transistor 3A described in the second embodiment is used for one or more of the plurality of pixel transistors.

[0074] <Other embodiments> As described above, the present technology has been described by the first to twelfth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present technology. If the gist of the technical content disclosed in one of the above embodiments is understood, it will be clear to a person skilled in the art that various alternative embodiments, examples, and operation techniques can be included in the present technology. In addition, the configurations disclosed in the first to twelfth embodiments can be appropriately combined within a range that does not cause contradictions. For example, the configurations disclosed in multiple different embodiments may be combined, and the configurations disclosed in multiple different modified examples of the same embodiment may be combined.

[0075] <Applications to electronic devices> Furthermore, the above-described photodetector device can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0076] FIG. 16 is a block diagram showing an example of the configuration of an electronic device. As shown in FIG. 16, electronic device 1010 includes an optical system 1020, a photodetector 1030, and a DSP (Digital Signal Processor) 1040, and is configured by connecting DSP 1040, a display device 1050, an operation system 1060, a memory 1080, a recording device 1090, and a power supply system 1100 via a bus 1070, and is capable of capturing still and moving images.

[0077] The optical system 1020 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 1030, forming an image on the light receiving surface (sensor portion) of the photodetector 1030.

[0078] The photodetector 1030 may be any of the photodetectors having the above-mentioned configuration examples. Electrons are accumulated in the photodetector 1030 for a certain period of time in accordance with an image formed on a light receiving surface via the optical system 1020. Then, a signal in accordance with the electrons accumulated in the photodetector 1030 is supplied to the DSP 1040.

[0079] The DSP 1040 performs various signal processing on the signal from the photodetector 1030 to obtain an image, and temporarily stores the image data in the memory 1080. The image data stored in the memory 1080 is recorded in the recording device 1090 or supplied to the display device 1050 to display the image. In addition, the operation system 1060 accepts various operations by the user and supplies operation signals to each block of the electronic device 1010, and the power supply system 1100 supplies power necessary to drive each block of the electronic device 1010.

[0080] <Application example to endoscopic surgery system> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0081] FIG. 17 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied. 17 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0082] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0083] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0084] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0085] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal. Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0086] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like. The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0087] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0088] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0089] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0090] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0091] FIG. 18 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG. The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0092] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0093] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 11402 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0094] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens. The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0095] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0096] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0097] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0098] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404. The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0099] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like. The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0100] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0101] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0102] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these. Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0103] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the endoscope 11100, the imaging unit 11402 of the camera head 11102, the image processing unit 11412 of the CCU 11201, and the like, among the above-described configurations. Specifically, the semiconductor device 1 in FIG. 1 can be applied to the imaging unit 10402. Although an endoscopic surgery system has been described here as an example, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0104] <Applications to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0105] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied. The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0106] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0107] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0108] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0109] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0110] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0111] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0112] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0113] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0114] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 16, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0115] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031. In FIG. 20, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0116] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0117] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0118] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0119] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0120] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0121] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0122] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 of the above-described configuration. Specifically, it can be applied to the semiconductor device 1 of FIG. 1.

[0123] The present disclosure can also be configured as follows. (1) a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion having a width narrower than that of the fin portion, the protrusion being formed between the buried portion of the gate electrode and at least one of a sidewall portion of the first element isolation portion and a sidewall portion of the second element isolation portion; having a semiconductor device in which impurities of a conductivity type opposite to that of the fin portion are distributed in the protruding portion at a higher concentration than impurities contained inside the semiconductor substrate other than the protruding portion; (2) The semiconductor device according to (1) above, wherein the protrusion is shorter in height than the fin portion. (3) The semiconductor device according to (1) above, wherein the convex portion is formed between a bottom portion of the buried portion of the gate electrode and at least one of the sidewall portions of the first element isolation portion and the second element isolation portion. (4) The gate electrode is a first buried portion formed on a first element isolation portion side among the plurality of buried portions; a second buried portion formed on the second element isolation portion side; a third buried portion formed between the first buried portion and the second buried portion, The fin portion is formed in plurality, The semiconductor device described in (1) above, wherein a first fin portion among the multiple fin portions is formed between the first buried portion and the third buried portion, and a second fin portion is formed between the second buried portion and the third buried portion. (5) The semiconductor device described in (1) above, wherein the first element isolation portion and the second element isolation portion are formed in the thickness direction from the upper surface portion and have a recessed portion into which the buried portion of the gate electrode is buried. (6) The semiconductor device according to (5) above, wherein a bottom of the recessed portion is lower than a top of the protruding portion. (7) The semiconductor device according to (5) above, wherein a bottom of the recessed portion is higher than a top of the protruding portion. (8) a protrusion insulating film disposed between the protrusion and the gate electrode, The semiconductor device according to (1) above, wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion. (9) The semiconductor device according to (8) above, wherein the protrusion insulating film is at least 1 nm thicker around the entire periphery of the protrusion than the gate insulating film covering the fin portion. (10) The semiconductor device described in (8) above, wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, and a second thickness other than the top of the convex portion that is thinner than the first thickness, and gradually becomes thicker from the second thickness to the first thickness. (11) a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion portion formed between the embedded portion of the gate electrode and at least one of a sidewall portion of the first element isolation portion and the second element isolation portion, the protrusion portion having a width narrower than that of the fin portion; a convex insulating film disposed between the convex portion and the gate electrode; having The protrusion insulating film is thicker than the gate insulating film covering the fin portion. (12) The semiconductor device according to (11) above, wherein the protrusion insulating film is at least 1 nm thicker around the entire periphery of the protrusion than the gate insulating film covering the fin portion. (13) The semiconductor device according to (11) above, wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, and a second thickness other than the top of the convex portion that is thinner than the first thickness, and gradually becomes thicker from the second thickness to the first thickness. (14) a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion having a width narrower than that of the fin portion, the protrusion being formed between the embedded portion of the gate electrode and at least one of a sidewall portion of the first device isolation portion and the second device isolation portion, an impurity having a conductivity type opposite to that of the fin portion is distributed in the protrusion at a higher concentration than the impurity contained inside the semiconductor substrate other than the protrusion; (15) a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion portion formed between the embedded portion of the gate electrode and at least one of a sidewall portion of the first element isolation portion and the second element isolation portion, the protrusion portion having a width narrower than that of the fin portion; a convex insulating film disposed between the convex portion and the gate electrode; having The electronic device includes a semiconductor device, wherein the protrusion insulating film is thicker than the gate insulating film that covers the fin portion. (16) preparing a semiconductor substrate having a first surface portion and a second surface portion positioned opposite each other in a thickness direction; forming a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; forming a recessed portion in the thickness direction from the first surface of the semiconductor substrate between a first element isolation portion and a second element isolation portion among the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; distributing impurities of a conductivity type opposite to that of the fin portion in the protruding portion at a higher concentration than impurities contained inside the semiconductor substrate other than the protruding portion; forming a gate electrode of the field effect transistor between a side wall portion of a first element isolation portion and a side wall portion of a second element isolation portion, the gate electrode covering the fin portion via a gate insulating film; A manufacturing method of a semiconductor device comprising: (17) preparing a semiconductor substrate having a first surface portion and a second surface portion positioned opposite each other in a thickness direction; forming a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; forming a recessed portion in the thickness direction from the first surface of the semiconductor substrate between a first element isolation portion and a second element isolation portion among the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; covering the fin portion via a gate insulating film, covering the convex portion via an insulating film for a convex portion that is thicker than the gate insulating film, and forming a gate electrode of the field effect transistor between a side wall portion of a first device isolation portion and a side wall portion of a second device isolation portion; A manufacturing method of a semiconductor device comprising: [Explanation of symbols]

[0124] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 11-1, 11-2, 21-2, 31-2 Semiconductor device 1-1,1-2 Photodetector 2. Semiconductor Substrate 2-1 Pixels 2a surface 2b Back side 3,3A (Metal Oxide Semiconductor) transistor 3-1 Pixel area 4-1 Vertical drive circuit 5. Element isolation section 5-1 Column signal processing circuit 6-1 Horizontal drive circuit 7-1 Output circuit 8-1 Control circuit 9-1 Vertical signal line 10 Fin section 11 First fin section 12 Second fin section 10-1 Horizontal signal line 10-2 First board 12-2 Sensor pixel 13-2 Pixel Area 20 Gate insulating film 20-2 Second board 22-2 Readout circuit 23-2 Pixel drive line 24-2 Vertical signal line 30,30A Gate electrode 30-2 Third board 32-2 Logic circuits 33-2 Vertical drive circuit 34-2 Column signal processing circuit 35-2 Horizontal drive circuit 36-2 System control circuit 41 Source Area 42 Drain Region 51 First element isolation portion 51a,52a Top part 51b,52b Side wall part 51c, 52c, 51d, 52d, 641, 642 Excavation 52 Second element isolation section 61 Second conductivity type region 621,622 Convex 63 High concentration second conductivity type region 71, 91, 92 Convex insulating film 81 Anti-reflection coating 821,822 Trench 1010 Electronic equipment 1020 Optical system 1030 Photodetector 1050 Display device 1060 Operation system 1070 Bus 1080 Memory 1090 Recording Device 1100 Power system 10402 Imaging unit 11000 Endoscopic surgery system 11100 Endoscope 11101 Telescope tube 11102 Camera head 11110 Surgical tools 11111 Insufflation tube 11112 Energy treatment device 11120 Support arm device 11131 Surgeon (Doctor) 11132 patient 11133 Patient Bed 11200 Cart 11201 Camera Control Unit (CCU) 11202 Display device 11203 Light source device 11204 Input device 11205 Treatment tool control device 11206 Insufflation device 11207 Recorder 11208 Printer 11400 Transmission cable 11401 Lens unit 11402,12031 Imaging section 11403 Drive unit 11404,11411 Communications Department 11405 Camera head control unit 11412 Image processing unit 11413 Control section 12000 Vehicle Control System 12001 Communication Networks 12010 Drive system control unit 12020 Body control unit 12030 External information detection unit 12040 In-vehicle information detection unit 12041 Driver status detection unit 12050 Integrated Control Unit 12051 Microcomputer 12052 Audio / Video Output Unit 12061 Audio Speaker 12062 Display section 12063 Instrument Panel 12100 Vehicles 12101,12102,12103,12104,12105 Imaging unit 12111,12112,12113,12114 Imaging range

Claims

1. a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion having a width narrower than that of the fin portion, the protrusion being formed between the buried portion of the gate electrode and at least one of a sidewall portion of the first element isolation portion and a sidewall portion of the second element isolation portion; having a first conductive type impurity having a conductivity type opposite to that of the fin portion is distributed in the protruding portion at a higher concentration than impurities contained inside the semiconductor substrate other than the protruding portion;

2. The semiconductor device according to claim 1 , wherein the protrusion portion has a height smaller than that of the fin portion.

3. 2. The semiconductor device according to claim 1, wherein said convex portion is formed between a bottom portion of said buried portion of said gate electrode and at least one sidewall portion of said first element isolation portion and said second element isolation portion.

4. The gate electrode is a first buried portion formed on a first element isolation portion side among the plurality of buried portions; a second buried portion formed on the second element isolation portion side; a third buried portion formed between the first buried portion and the second buried portion, The fin portion is formed in plurality, 2. The semiconductor device according to claim 1, wherein a first fin portion of the plurality of fin portions is formed between the first buried portion and the third buried portion, and a second fin portion is formed between the second buried portion and the third buried portion.

5. 2 . The semiconductor device according to claim 1 , wherein said first isolation portion and said second isolation portion are formed in said thickness direction from said upper surface portion and have a recessed portion into which said buried portion of said gate electrode is buried.

6. 6. The semiconductor device according to claim 5, wherein a bottom of said recessed portion is lower than a top of said protrusion.

7. 6. The semiconductor device according to claim 5, wherein a bottom of said recessed portion is higher than a top of said protrusion.

8. a protrusion insulating film disposed between the protrusion and the gate electrode, The semiconductor device according to claim 1 , wherein the protruding insulating film is thicker than the gate insulating film covering the fin portion.

9. 9. The semiconductor device according to claim 8, wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion by at least 1 nm around the entire periphery of the protrusion.

10. 9. The semiconductor device according to claim 8, wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, a second thickness other than the top of the convex portion that is thinner than the first thickness, and gradually becomes thicker from the second thickness to the first thickness.

11. a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion portion formed between the embedded portion of the gate electrode and at least one of a sidewall portion of the first device isolation portion and the second device isolation portion, the protrusion portion having a width narrower than that of the fin portion; a convex insulating film disposed between the convex portion and the gate electrode; having The protrusion insulating film is thicker than the gate insulating film covering the fin portion.

12. The semiconductor device according to claim 11 , wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion by at least 1 nm around the entire periphery of the protrusion.

13. 12. The semiconductor device according to claim 11, wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, a second thickness other than the top of the convex portion that is thinner than the first thickness, and gradually becomes thicker from the second thickness to the first thickness.

14. a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion portion formed between the embedded portion of the gate electrode and at least one of a sidewall portion of the first device isolation portion and the second device isolation portion, the protrusion portion having a width narrower than that of the fin portion; an impurity having a conductivity type opposite to that of the fin portion is distributed in the protrusion at a higher concentration than the impurity contained inside the semiconductor substrate other than the protrusion;

15. a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; a field effect transistor provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions in a plan view; Equipped with The field effect transistor is a gate electrode having a planar portion formed on the first surface of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion that is covered with the planar portion and the buried portion of the gate electrode and forms a channel; a gate insulating film disposed between the gate electrode and the fin portion; a protrusion portion formed between the embedded portion of the gate electrode and at least one of a sidewall portion of the first device isolation portion and the second device isolation portion, the protrusion portion having a width narrower than that of the fin portion; a convex insulating film disposed between the convex portion and the gate electrode; having The electronic device includes a semiconductor device, wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion.

16. preparing a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; forming a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; forming a recessed portion in the thickness direction from the first surface portion of the semiconductor substrate between a first element isolation portion and a second element isolation portion among the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; distributing impurities of a conductivity type opposite to that of the fin portion in the protruding portion at a higher concentration than impurities contained inside the semiconductor substrate other than the protruding portion; forming a gate electrode of the field effect transistor between a side wall portion of a first element isolation portion and a side wall portion of a second element isolation portion, the gate electrode covering the fin portion via a gate insulating film; A manufacturing method of a semiconductor device comprising:

17. preparing a semiconductor substrate having a first surface portion and a second surface portion positioned on opposite sides in a thickness direction; forming a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on a first surface portion side; forming a recessed portion in the thickness direction from the first surface portion of the semiconductor substrate between a first element isolation portion and a second element isolation portion among the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; covering the fin portion via a gate insulating film, covering the convex portion via an insulating film for a convex portion that is thicker than the gate insulating film, and forming a gate electrode of the field effect transistor between a side wall portion of a first device isolation portion and a side wall portion of a second device isolation portion; A manufacturing method of a semiconductor device comprising:

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