Semiconductor device and semiconductor memory device

Abstract

To provide a semiconductor device and a semiconductor memory device which can be manufactured with high quality.SOLUTION: A semiconductor device includes an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end, a first electrode in contact with the first end of the oxide semiconductor, a second electrode in contact with the second end of the oxide semiconductor, a gate electrode surrounding the oxide semiconductor via a first insulating film between the first end and the second end of the oxide semiconductor, and a metal film in contact with the first direction side of the gate electrode and including a tubular portion surrounding the oxide semiconductor via the first insulating film.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device and a semiconductor memory device. [Background technology]

[0002] Some semiconductor elements include an oxide semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication US2022 / 0285350 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing process of semiconductor elements including oxide semiconductors, there is a demand for technology for manufacturing high-quality semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device and a semiconductor memory device that enable the manufacture of high-quality semiconductor devices. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end, a first electrode in contact with the first end of the oxide semiconductor, a second electrode in contact with the second end of the oxide semiconductor, a gate electrode surrounding the oxide semiconductor via a first insulating film between the first end and the second end of the oxide semiconductor, and a metal film including a tubular portion in contact with the first direction side of the gate electrode and surrounding the oxide semiconductor via the first insulating film.

[0007] The semiconductor device according to the present disclosure comprises an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end, a first electrode in contact with the first end of the oxide semiconductor, a second electrode in contact with the second end of the oxide semiconductor, a first insulating film surrounding at least a portion of the oxide semiconductor on the first direction side, a gate electrode surrounding the oxide semiconductor via the first insulating film between the first end and the second end of the oxide semiconductor, a third insulating film in contact with a portion of a side of the first insulating film including an end on the first direction side, and a fourth insulating film in contact with the side of the third insulating film opposite to the first direction.

[0008] The semiconductor device according to the present disclosure comprises an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end, a first electrode in contact with the first end of the oxide semiconductor, a second electrode in contact with the second end of the oxide semiconductor, a first insulating film surrounding a portion of the oxide semiconductor on the first direction side, and a gate electrode surrounding the oxide semiconductor via the first insulating film between the first end and the second end of the oxide semiconductor, and an end of the first insulating film on the opposite side to the first direction is separated from the second electrode.

[0009] The semiconductor memory device of the present disclosure comprises the semiconductor device, a first capacitor electrode connected to the first electrode or the second electrode, a second capacitor electrode facing the first capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode. [Brief description of the drawings]

[0010] [Figure 1] 2 is a circuit diagram for explaining an example of a circuit configuration of a memory cell array according to the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor memory device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane. [Diagram 3]FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device of the first example of the first embodiment. [Figure 4] FIG. 1 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a first embodiment, showing a cross-sectional view parallel to a YZ plane of the semiconductor device. [Diagram 5] 5 is a cross-sectional view taken along line VV shown in FIGS. 3 and 4. FIG. [Figure 6] 4 is an enlarged view of a connection portion between an oxide semiconductor layer and an upper electrode in the first example of the first embodiment. FIG. [Figure 7] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 8] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 9] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 10] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 11] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 12] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 13] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 14] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 15] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 16] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 17] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 18]1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 19] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 20] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 21] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 22] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 23] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 24] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 25] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 26] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 27] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 28] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the second example of the first embodiment. [Figure 29] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device of the second example of the first embodiment. [Diagram 30] 4 is an enlarged view of a connection portion between an oxide semiconductor layer and an upper electrode in a second example of the first embodiment. FIG. [Diagram 31] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the third example of the first embodiment. [Diagram 32]FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to a third example of the first embodiment. [Diagram 33] 13 is an enlarged view of a connection portion between an oxide semiconductor layer and an upper electrode in a third example of the first embodiment. FIG. [Diagram 34] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the fourth example of the first embodiment. [Diagram 35] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fourth example of the first embodiment. [Diagram 36] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 37] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the fifth example of the first embodiment. [Figure 38] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fifth example of the first embodiment. [Figure 39] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a fifth example of the first embodiment. [Diagram 40] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a fifth example of the first embodiment. [Diagram 41] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a fifth example of the first embodiment. [Diagram 42] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a fifth example of the first embodiment. [Diagram 43] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a fifth example of the first embodiment. [Diagram 44] FIG. 11 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a second embodiment, showing a cross-sectional view parallel to the ZX plane. [Diagram 45]FIG. 13 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a second embodiment, showing a cross-sectional view parallel to the YZ plane. [Figure 46] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 47] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 48] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 49] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 50] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 51] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 52] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 53] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 54] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 55] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 56] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 57] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 58] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 59] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 60]10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 61] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate understanding of the description, the same components in each drawing are denoted by the same reference numerals as much as possible, and duplicated description will be omitted.

[0012] [First embodiment] The configuration of the semiconductor memory device according to the first embodiment will be described. Each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, the Y-axis, and the Z-axis form a right-handed three-dimensional Cartesian coordinate system. Hereinafter, the direction of the X-axis arrow may be called the X-axis + direction, and the direction opposite to the arrow may be called the X-axis - direction, and the same applies to the other axes. The Z-axis + direction and the Z-axis - direction may be called "upper" and "lower", respectively. Furthermore, the planes perpendicular to the X-axis, Y-axis, or Z-axis may be called the YZ plane, ZX plane, or XY plane, respectively. Furthermore, the Z-axis direction may be called the "vertical direction". "Upward", "downward", and "vertical direction" are terms that merely indicate the relative positional relationship in the drawing, and are not terms that define the orientation based on the vertical direction.

[0013] In addition, unless otherwise specifically explained, the dimensions of components shown in each drawing may be shown differently from their actual dimensions in order to make the explanation easier to understand.

[0014] In this specification, the term "connection" includes not only a physical connection but also an electrical connection, and unless otherwise specified, includes not only a direct connection but also an indirect connection.

[0015] In this specification, the term "formed above" does not only mean a case where the material is formed in contact with the material above, but also includes a case where the material is formed above via another object, unless otherwise specified. The same applies to "formed below" and the like.

[0016] The semiconductor memory device 101 according to the first embodiment is an oxide semiconductor random access memory (OS-RAM) and includes a memory cell array.

[0017] As shown in FIG. 1, the memory cell array includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0018] FIG. 1 shows a word line WL n , word line WL n+1 and word line WL n+2 (where n is a positive integer). Also, in FIG. 1, as an example of the bit line BL, m , bit line BL m+1 and bit line BL m+2 (where m is a positive integer.) The number of memory cells MC is not limited to the number shown in FIG.

[0019] A plurality of memory cells MC are arranged in, for example, a matrix to form a memory cell array. The memory cell MC includes a memory transistor MTR, which is a field effect transistor (FET), and a memory capacitor MCP.

[0020] A series of memory cells MC arranged in the row direction are connected to a word line WL (e.g., word line WL n A series of memory cells MC arranged in the column direction is connected to a bit line BL (e.g., bit line BL m+2 )

[0021] Specifically, the gate of the memory transistor MTR included in the memory cell MC is connected to a word line WL corresponding to the row to which the memory cell MC belongs, and one of the source and drain of the memory transistor MTR is connected to a bit line BL corresponding to the column to which the memory cell MC belongs.

[0022] One electrode of a memory capacitor MCP included in a memory cell MC is connected to the other of the source or drain of a memory transistor MTR included in the memory cell MC, and the other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0023] The memory cell MC is configured to be able to hold data by storing charge in the memory capacitor MCP due to a current flowing through the corresponding bit line BL, by switching the memory transistor MTR based on the potential of the corresponding word line WL.

[0024] As shown in FIG. 2, the semiconductor memory device 101 includes a semiconductor substrate 10, a circuit 11, a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35, 45 and 63.

[0025] Capacitor 20 includes a conductor 21, an insulating film 22 (an example of a "dielectric film"), a conductor 23, a capacitor electrode 24 (an example of a "first capacitor electrode"), and a capacitor electrode 25 (an example of a "second capacitor electrode").

[0026] The semiconductor device 30 includes a field effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 (an example of a "first electrode") provided above the field effect transistor 40, and a lower electrode 32 (an example of a "second electrode") provided below the field effect transistor 40.

[0027] The field effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor") corresponding to a channel, a gate insulating film 43 (an example of a "first insulating film"), and a conductive layer 42 (an example of a "gate electrode").

[0028] The oxide semiconductor layer 70 is formed in the insulating layer 45, and has an upper end 70a (an example of a "first end") and a lower end 70b (an example of a "second end"). The oxide semiconductor layer 70 is a columnar body extending in the Z-axis + direction (an example of a "first direction") from the lower end 70b to the upper end 70a. The oxide semiconductor layer 70 forms a channel of the field effect transistor 40, and the oxide semiconductor layer 70 has an amorphous structure. The conductive layer 42 contains, for example, tungsten.

[0029] The conductive layer 42 functions as a gate electrode of the field-effect transistor 40, and surrounds the oxide semiconductor layer 70 between an upper end 70a and a lower end 70b of the oxide semiconductor layer 70 with a gate insulating film 43 interposed therebetween.

[0030] The gate insulating film 43 includes, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen.

[0031] The upper electrode 50 is formed in the positive Z-axis direction with respect to the oxide semiconductor layer 70, and is in contact with an upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0032] The metal film 50c includes tungsten (W). The metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70 and includes a metal oxide. The metal oxide includes, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin-oxide (ITO).

[0033] The barrier metal layer 50b contains titanium and nitrogen, and is formed between the metal oxide layer 50a and the metal film 50c. In this embodiment, the barrier metal layer 50b is made of, for example, titanium nitride (TiN).

[0034] The lower electrode 32 is in contact with a lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 is formed of, for example, an indium-tin-oxide (ITO) layer containing a metal oxide such as ITO.

[0035] The lower electrode 32 is not limited to ITO, and may be made of at least one of the following elements: indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0036] The circuit 11 constitutes peripheral circuits such as a decoder for selecting a specific memory cell MC from among a plurality of memory cells MC, i.e., capacitors 20 and field effect transistors 40, of the semiconductor memory device 101, a sense amplifier connected to the bit line BL, and a register constituted by an SRAM. The circuit 11 may include a CMOS circuit having field effect transistors, that is, a P-channel field effect transistor (Pch-FET) and an N-channel field effect transistor (Nch-FET), formed by a CMOS process.

[0037] The field effect transistors of the circuit 11 can be formed using a semiconductor substrate 10 such as a single crystal silicon substrate. The Pch-FET and Nch-FET are so-called horizontal field effect transistors that have a channel region, a source region, and a drain region in the semiconductor substrate 10 and have a channel for flowing carriers in the X-axis direction or the Y-axis direction approximately parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. The semiconductor substrate 10 may have a conductivity type of P type to N type. For convenience, FIG. 2 illustrates an example of the field effect transistor of the circuit 11.

[0038] The capacitor 20 is a memory capacitor MCP included in the memory cell MC (see FIG. 1). Although four capacitors 20 are illustrated in FIG. 2, the number of capacitors 20 is not limited to four.

[0039] In this embodiment, the capacitor 20 is provided above the semiconductor substrate 10. The capacitor electrode 24 of the capacitor 20 is connected to the conductor 21 and the lower electrode 32. The capacitor electrode 25 faces the capacitor electrode 24. The insulating film 22 is provided between the capacitor electrodes 24 and 25.

[0040] The capacitor 20 is a three-dimensional capacitor such as a pillar-type capacitor. Note that, as the capacitor of this embodiment, other capacitors having a configuration capable of storing electric charge may be adopted.

[0041] The conductor 21 abuts against the lower end face of the lower electrode 32 and has a shape extending downward from that end. The capacitor electrode 24 is formed so as to cover the lower electrode 32 and the conductor 21. The insulating film 22 is formed so as to cover the capacitor electrode 24. The capacitor electrode 25 surrounds a lower portion of the insulating film 22 and has a lower end abutting against the upper end face of the conductor 23.

[0042] The conductor 21 may include a material such as amorphous silicon. The insulating film 22 may include a material such as hafnium oxide. The conductor 23 and the capacitor electrodes 24 and 25 may include a material such as tungsten (W) and titanium nitride (TiN).

[0043] The conductor 33 includes a wiring that electrically connects the circuit 11 and the semiconductor device 30. The conductor 33 may include a via wiring, and has a via wiring that extends in the Z-axis direction as shown in Fig. 2, for example, and connects the word line WL and the circuit 11 provided on the semiconductor substrate 10. The conductor 33 includes, for example, copper.

[0044] The insulating layer 34 is provided between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0045] The insulating layer 35 is provided above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0046] The semiconductor device 30 is provided above the capacitor 20. A field effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC (see FIG. 1).

[0047] In the semiconductor device 30, the field effect transistor 40 is provided above the lower electrode 32. In particular, the oxide semiconductor layer 70 of the field effect transistor 40 is located in a direction away from the semiconductor substrate 10 with respect to the lower electrode 32, that is, above the lower electrode 32.

[0048] The upper electrode 50 is located in a direction away from the semiconductor substrate 10, i.e., above the oxide semiconductor layer 70. With this configuration, the field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (up-down direction) that is approximately perpendicular to the surface of the semiconductor substrate 10.

[0049] The oxide semiconductor layer 70 is a semiconductor in which oxygen vacancies serve as donors, and contains indium (In), zinc (Zn), and gallium (Ga) as metal elements. In particular, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, that is, IGZO (InGaZnO). The oxide semiconductor layer 70 may be another type of oxide semiconductor.

[0050] Fig. 3 shows a cross-sectional view of the semiconductor device 30 as seen at a cross-section 70ZX parallel to the ZX plane, which is included in the oxide semiconductor layer 70. Fig. 4 shows a cross-sectional view of the semiconductor device 30 as seen at a cross-section 70YZ parallel to the YZ plane, which is included in the oxide semiconductor layer 70. Fig. 5 is a cross-sectional view taken along the cutting line V-V shown in Figs. 3 and 4. Fig. 6 is an enlarged view of a connection portion between the oxide semiconductor layer and the upper electrode.

[0051] Hereinafter, a first example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a first example of the first embodiment) will be described.

[0052] (First Example of First Embodiment) 3 to 6, in the first example of the first embodiment, the semiconductor device 30 further includes a metal spacer film 311 (an example of a "metal film"). The gate insulating film 43 includes insulating films 43a and 43b. The insulating layer 45 includes insulating films 45a, 45b, and 45c.

[0053] The multiple conductive layers 42 are repeatedly provided in the + direction of the X-axis. The multiple oxide semiconductor layers 70 are arranged two-dimensionally. That is, some of the multiple oxide semiconductor layers 70 are provided along the + direction of the Y-axis (an example of a "second direction"). Also, some of the multiple oxide semiconductor layers 70 are provided along the + direction of the X-axis.

[0054] The conductive layer 42 extends along the +Y direction of the Y axis, and surrounds, via a plurality of gate insulating films 43, the plurality of oxide semiconductor layers 70 provided along the +Y direction of the Y axis.

[0055] In detail, the conductive layer 42 includes a plurality of surrounding portions 42b and at least one connecting portion 42c. The surrounding portions 42b respectively surround the plurality of oxide semiconductor layers 70 via the gate insulating film 43. The connecting portion 42c connects the surrounding portions 42b to each other.

[0056] When the conductive layer 42 is viewed from above, the width in the X-axis direction of the connecting portion 42c is narrower than the width in the X-axis direction of the surrounding portion 42b (see FIG. 5).

[0057] The metal spacer film 311 is provided on the Z-axis + direction side of the conductive layer 42. The metal spacer film 311 contains, for example, titanium, tantalum, tungsten, platinum, ruthenium, nickel, cobalt, palladium, gold, or copper, or nitrides of titanium, tantalum, and tungsten. The metal spacer film 311 includes a plurality of cylindrical portions 311a (an example of a "tubular portion") and at least one plate-shaped portion 311b.

[0058] The multiple cylindrical portions 311a contact the positive Z-axis direction side of the multiple surrounding portions 42b of the conductive layer 42. The multiple cylindrical portions 311a respectively surround the multiple oxide semiconductor layers 70 with the gate insulating film 43 interposed therebetween.

[0059] In detail, the lower end of the cylindrical portion 311a forms an annular surface that contacts the upper surface 42a of the conductive layer 42. The upper end of the cylindrical portion 311a forms an annular surface that does not contact the upper electrode 50.

[0060] Both ends of the plate-shaped portion 311b contact two cylindrical portions 311a adjacent in the Y-axis direction. The plate-shaped portion 311b is provided above the connecting portion 42c, and the bottom surface of the plate-shaped portion 311b contacts the connecting portion 42c. The plate-shaped portion 311b extends approximately parallel to the XY plane.

[0061] The insulating films 45a and 45b are provided above and below the conductive layer 42, respectively. The insulating films 45a and 45b are made of, for example, an oxide of silicon. The insulating film 45a has a hole 401 (an example of a "first hole") through which the oxide semiconductor layer 70 penetrates (see FIG. 6).

[0062] Cylindrical portion 311a of metal spacer film 311 is inserted into a part of hole portion 401 on the negative Z-axis direction side (see FIG. 6). Hole portion 401 and cylindrical portion 311a form step portion 411 (an example of a "first step portion"). In detail, step portion 411 is formed between inner wall 401a of hole portion 401 above cylindrical portion 311a and inner circumferential surface 311aa of cylindrical portion 311a.

[0063] The insulating film 45c separates two conductive layers 42 adjacent in the +X-axis direction. In particular, the insulating film 45c is located between two conductive layers 42 adjacent in the +X-axis direction, and extends substantially parallel to the Y-axis.

[0064] An upper end of the insulating film 45c is connected to the lower surface of the insulating film 45a. A lower end of the insulating film 45c is buried in the insulating film 45b. In this embodiment, the insulating films 45a and 45c are integrally formed.

[0065] The gate insulating film 43 is cylindrical and surrounds the entire side surface of the oxide semiconductor layer 70. The gate insulating film 43 is bent along the inner circumferential surface 311aa of the cylindrical portion 311a and the step portion 411, so that a step portion 43bd (an example of a "second step portion") that contacts the step portion 411 is formed on the outer circumferential surface of the gate insulating film 43 (see FIG. 6). No step is formed on the inner circumferential surface of the gate insulating film 43.

[0066] In detail, the gate insulating film 43 includes a cylindrical insulating film 43b (an example of a "first film") and a cylindrical insulating film 43a (an example of a "second film"). The insulating film 43a includes, for example, an oxide of silicon. The insulating film 43b includes, for example, a nitride of silicon.

[0067] The insulating film 43a is provided between the insulating film 43b and the oxide semiconductor layer 70. That is, the gate insulating film 43 has two layers: the insulating film 43b and the insulating film 43a that is provided closer to the oxide semiconductor layer 70 than the insulating film 43b.

[0068] The insulating film 43b is bent along the inner circumferential surface 311aa of the cylindrical portion 311a, the step portion 411, and the inner wall 401a of the hole portion 401. Due to this bending, a step portion 43bd and a step portion 43be (an example of a "fifth step portion") are formed on the outer circumferential surface and the inner circumferential surface of the insulating film 43b, respectively.

[0069] The insulating film 43a is bent along the inner circumferential surface 311aa of the cylindrical portion 311a and the step portion 411 via the insulating film 43b. This bending forms a step portion 43ad (an example of a "sixth step portion") on the outer circumferential surface of the insulating film 43a. The step portion 43ad contacts a step portion 43be of the insulating film 43b. On the other hand, no step is formed on the inner circumferential surface of the insulating film 43a.

[0070] The upper end faces of the insulating films 43a and 43b are in contact with the metal oxide layer 50a of the upper electrode 50. That is, the upper part of the gate insulating film 43 extends outward between the upper end of the cylindrical portion 311a and the upper electrode 50. The distance between the upper electrode 50 and the upper end of the cylindrical portion 311a is 4 nm or more and 30 nm or less.

[0071] [Method of manufacturing semiconductor device] A method for manufacturing the semiconductor device 30 will be described below as an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0072] 7, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are provided in this order above the insulating layer 35. The insulating film 45b, the conductive layer 42, and the insulating film 45ba extend substantially parallel to the XY plane. A transistor hole TH (an example of a "second hole") is formed extending substantially parallel to the Z axis and penetrating the insulating film 45ba, the conductive layer 42, and the insulating film 45b, and then cleaned. The lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0073] 8, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30. As a result, the transistor hole TH is filled with the sacrificial amorphous silicon layer 170.

[0074] 9, the sacrificial amorphous silicon layer 170 is etched back to remove an upper part of the sacrificial amorphous silicon layer 170 and expose an upper surface of the insulating film 45ba. At this time, the upper end of the sacrificial amorphous silicon layer 170 is located, for example, inside the transistor hole TH below the opening of the transistor hole TH and above the conductive layer 42.

[0075] Next, as shown in FIG. 10, the insulating film 45ba is removed by etching.

[0076] 11, a metal spacer film 311 is formed above the semiconductor device 30. As a result, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42a of the conductive layer 42 are covered with the metal spacer film 311.

[0077] 12, a mask is formed by performing a film formation, resist coating, exposure, development, and peeling on the surface of the semiconductor device 30 by a lithography method, and then a groove portion 45ca is formed in the semiconductor device 30 by etching, the groove portion 45ca penetrating to the insulating film 45b and extending substantially parallel to the Y-axis. As a result, the metal spacer film 311 is separated into a cylindrical portion 311a and a plate-shaped portion 311b. The conductive layer 42 is also separated into a plurality of electrodes extending substantially parallel to the Y-axis and repeatedly provided in the + direction of the X-axis. These electrodes correspond to the word lines WL (see FIG. 1).

[0078] The surrounding portion 42b of the conductive layer 42 is formed in a self-aligned manner with respect to the transistor hole TH (self-align process). In detail, even if the mask formation position by the lithography method is shifted, the cylindrical portion 311a of the metal spacer film 311 provided on the side surface of the sacrificial amorphous silicon layer 170 functions as a mask, so that the surrounding portion 42b of the conductive layer 42 is formed in a self-aligned manner around the transistor hole TH.

[0079] Next, as shown in FIG. 13, insulating films 45c and 45a are integrally formed above the semiconductor device 30.

[0080] Next, as shown in FIG. 14, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing, so that the upper surface of the metal spacer film 311 is exposed from the insulating film 45a.

[0081] 15, an upper part of the metal spacer film 311 is removed by etching. This forms a step portion 411 located at an upper end of the cylindrical portion 311a of the metal spacer film 311. The vertical height of the cylindrical portion 311a can be adjusted according to the amount of etching of the metal spacer film 311. In other words, the vertical position of the step portion 411 can be adjusted according to the amount of etching of the metal spacer film 311.

[0082] Next, as shown in FIG. 16, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0083] Next, an insulating film 43b is formed above the semiconductor device 30 as shown in FIG.

[0084] Next, an insulating film 43a is formed above the semiconductor device 30 as shown in FIG.

[0085] Next, as shown in FIG. 19, the upper part of the semiconductor device 30 is etched back by reactive ion etching to expose the insulating film 45a and the lower electrode 32 at the bottom of the transistor hole TH.

[0086] 20, an oxide semiconductor layer 70 is formed inside the transistor hole TH. Then, the upper surface of the semiconductor device 30 is chemically and mechanically polished.

[0087] 21, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30. Then, a LPHM (Landing Pad Hard Mask) film 50e containing, for example, an oxide of silicon is formed above the metal film 50c.

[0088] 22, a mask is formed by performing a film formation, resist coating, exposure, development, and peeling on the surface of the semiconductor device 30 by a lithography method, and then an upper electrode 50 functioning as a landing pad is formed by etching on the semiconductor device 30. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0089] 23, an LP liner film 50d containing, for example, an oxide of silicon is formed on the upper surface of the semiconductor device 30. An insulating layer 63 is formed above the LP liner film 50d to fill the gaps caused by the LP liner film 50d. The insulating layer 63 contains, for example, an oxide of silicon. Then, the upper surface of the semiconductor device 30 is chemically mechanically polished.

[0090] 24 and 25, a barrier metal layer 51a, a conductive layer 51b, and a barrier metal layer 51c are formed from bottom to top on the upper surface of the semiconductor device 30. The barrier metal layers 51a and 51c include, for example, titanium nitride. The conductive layer 51b includes, for example, tungsten.

[0091] Then, bit line hard mask (BLHM) films 66a and 66b are formed from bottom to top on the upper surface of the barrier metal layer 51c. The BLHM films 66a and 66b include, for example, a silicon nitride and a silicon oxide, respectively.

[0092] 26 and 27, a mask is formed by performing a film formation, resist coating, exposure, development, and peeling on the surface of the semiconductor device 30 by a lithography method, and then a groove portion 66ca is formed in the semiconductor device 30 by etching, the groove portion 66ca penetrating through the insulating layer 63 and the metal film 50c and extending substantially parallel to the X-axis. As a result, the barrier metal layer 51a, the conductive layer 51b, and the barrier metal layer 51c are separated into electrodes extending substantially parallel to the X-axis and repeatedly provided in the +Y-axis direction. These electrodes correspond to the bit lines BL (see FIG. 1).

[0093] 3 and 4, an insulating film 66c filling the groove portion 66ca is formed above the semiconductor device 30. The insulating film 66c includes, for example, an oxide of silicon.

[0094] (effect) When the upper surface of the semiconductor device 30 is chemically mechanically polished after the insulating film 45a is formed (see FIG. 14), if the polishing is performed until the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a, over-polishing of the sacrificial amorphous silicon layer 170 may occur at the end of the array region where the two-dimensionally arranged transistor holes TH are provided.

[0095] 14, when the upper surface of the semiconductor device 30 is chemically mechanically polished after the insulating film 45a is formed, the polishing is completed when the upper surface of the metal spacer film 311 is exposed from the insulating film 45a. This makes it possible to suppress over-polishing of the sacrificial amorphous silicon layer 170 at the end of the array region.

[0096] In addition, the area of ​​the gate electrode can be increased by forming the conductive cylindrical portion 311a above the surrounding portion 42b of the conductive layer 42. This can reduce the electrical resistance of the word line WL. In addition, the channel region that is turned on in the oxide semiconductor layer 70 can be increased, so that the on-current Ion can be increased.

[0097] A second example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a second example of the first embodiment) will be described below.

[0098] (Second Example of First Embodiment) As shown in FIGS. 28 to 30, the semiconductor device 30 of the second example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in FIGS. 3 to 6 in that the step portion 411 is positioned lower.

[0099] As the gate insulating film 43 bends along the inner surface 311aa of the cylindrical portion 311a, the step portion 411, and the inner wall 401a of the hole portion 401, step portions 43bd and 43ae (examples of a "third step portion") are formed on the outer and inner surfaces of the gate insulating film 43, respectively (see Figure 6).

[0100] In detail, the insulating film 43b is bent along the inner circumferential surface 311aa of the cylindrical portion 311a, the step portion 411, and the inner wall 401a of the hole portion 401. Due to this bending, the outer circumferential surface and the inner circumferential surface of the insulating film 43b are formed with step portions 43bd and 43be, respectively. The step portion 43bd is in contact with the step portion 411.

[0101] The insulating film 43a is bent along the inner circumferential surface 311aa of the cylindrical portion 311a, the step portion 411, and the inner wall 401a of the hole portion 401 via the insulating film 43b. Due to this bending, step portions 43ad and 43ae are formed on the outer circumferential surface and the inner circumferential surface of the insulating film 43a, respectively. The step portion 43ad is in contact with the step portion 43be of the insulating film 43b.

[0102] The outer peripheral surface of the oxide semiconductor layer 70 is aligned, via the gate insulating film 43, along the inner peripheral surface 311aa of the cylindrical portion 311a, the step portion 411, and the inner wall 401a of the hole portion 401, so that a step portion 70c (an example of a "fourth step portion") that contacts the step portion 43ae is formed in the oxide semiconductor layer 70.

[0103] The diameter of the oxide semiconductor layer 70 above the step portion 70c is larger than the diameter of the oxide semiconductor layer 70 below the step portion 70c. With this configuration, the contact area between the upper electrode 50 and the upper end 70a of the oxide semiconductor layer 70 can be increased, thereby reducing the on-resistance and increasing the on-current Ion.

[0104] [Manufacturing method of the semiconductor device 30 according to the second example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the second example of the first embodiment, as shown in Fig. 15, the amount of the metal spacer film 311 removed by etching is increased. This allows the step portion 411 to be formed further downward compared to the semiconductor device 30 of the first example of the first embodiment (see Fig. 6).

[0105] Hereinafter, a third example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a third example of the first embodiment) will be described.

[0106] (Third example of the first embodiment) As shown in FIGS. 31 to 33, the semiconductor device 30 of the third example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in FIGS. 3 to 6 in that the step portion 411 is located higher.

[0107] The insulating film 43b is bent along the inner circumferential surface 311aa of the cylindrical portion 311a and the step portion 411. Due to this bending, a step portion 43bd that contacts the step portion 411 is formed on the outer circumferential surface of the insulating film 43b. On the other hand, no step is formed on the inner circumferential surface of the insulating film 43b.

[0108] The insulating film 43a is not bent. Therefore, no steps are formed on the outer and inner peripheral surfaces of the insulating film 43a. In other words, only the insulating film 43b extends outward and wraps around between the upper end of the cylindrical portion 311a and the upper electrode 50.

[0109] [Manufacturing method of the semiconductor device 30 according to the third example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the third example of the first embodiment, the amount of the metal spacer film 311 removed by etching is reduced as shown in Fig. 15. This allows the step portion 411 to be formed higher than in the semiconductor device 30 of the first example of the first embodiment (see Fig. 6).

[0110] Hereinafter, a fourth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a fourth example of the first embodiment) will be described.

[0111] (Fourth Example of First Embodiment) As shown in Figures 34 and 35, the semiconductor device 30 of the fourth example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 to 6 in that the plate-shaped portion 311b of the metal spacer film 311 is not provided above the connecting portion 42c of the conductive layer 42.

[0112] The connecting portion 42c of the conductive layer 42 contacts an insulating film 45a (an example of a "second insulating film") provided between the cylindrical portions 311a. In this manner, by using a configuration in which the conductive plate-like portion 311b is not provided, it is possible to prevent malfunctions from occurring at unexpected locations in the circuit formed in the semiconductor device 30.

[0113] [Manufacturing method of the semiconductor device 30 according to the fourth example of the first embodiment] In a manufacturing method of the semiconductor device 30 of the fourth example of the first embodiment, after a metal spacer film 311 is formed above the semiconductor device 30 (see FIG. 11), the metal spacer film 311 except for the cylindrical portion 311a is removed by reactive ion etching, as shown in FIG. 36.

[0114] Then, as shown in FIG. 12, a groove 45ca is formed by etching, penetrating to the insulating film 45b and extending substantially parallel to the Y-axis.

[0115] A fifth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as the fifth example of the first embodiment) will be described below.

[0116] (Fifth Example of First Embodiment) As shown in Figures 37 and 38, the semiconductor device 30 of the fifth example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 to 6 in that a liner film 301 is further provided to cover a portion of the lower part of the gate insulating film 43.

[0117] A hole 601 for accommodating at least a portion of the oxide semiconductor layer 70 is formed by the surrounding portion 42b of the conductive layer 42 and the cylindrical portion 311a of the metal spacer film 311. In this embodiment, the hole 601 accommodates a portion of the oxide semiconductor layer 70.

[0118] A step surface 601a facing the negative Z-axis direction is formed on an inner wall 601b of the hole 601. The step surface 601a is located between the conductive layer 42 and the upper electrode 50. The step surface 601a has an annular shape when viewed from below.

[0119] In this embodiment, the inner diameter of the lower end of the cylindrical portion 311a in the hole 601 is smaller than the inner diameter of the upper part of the surrounding portion 42b, so that the portion of the lower end face of the cylindrical portion 311a near the center forms a step surface 601a. ​​The upper surface 42a of the conductive layer 42 and the step surface 601a are aligned.

[0120] The liner film 301 is located at least between the conductive layer 42 and the insulating film 45b and the gate insulating film 43. The liner film 301 surrounds a part of a lower portion of the oxide semiconductor layer 70 from the outside of the gate insulating film 43 over the entire periphery. In detail, a lower end of the liner film 301 contacts the lower electrode 32. An upper end of the liner film 301 contacts a step surface 601a of the hole portion 601, i.e., a lower end surface of the cylindrical portion 311a.

[0121] The liner film 301 contains, for example, at least one of silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one of oxygen and nitrogen. In this embodiment, the liner film 301 contains silicon nitride. The liner film 301 may contain silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide, strontium oxide, or the like.

[0122] [Manufacturing method of the semiconductor device 30 according to the fifth example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the fifth example of the first embodiment, a transistor hole TH is formed extending substantially parallel to the Z axis and penetrating the insulating film 45ba, the conductive layer 42, and the insulating film 45b, and then cleaned (see FIG. 7), and then a liner film 301 having a thickness of 2 nm or more is formed above the semiconductor device 30 by, for example, atomic layer deposition, as shown in FIG. 39. As a result, the inner wall of the transistor hole TH is covered with the liner film 301, and the lower electrode 32 is not exposed.

[0123] 40, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30. As a result, the transistor hole TH is filled with the sacrificial amorphous silicon layer 170.

[0124] Next, as shown in FIG. 41, the sacrificial amorphous silicon layer 170 is etched back, thereby removing an upper portion of the sacrificial amorphous silicon layer 170 and exposing the upper surface of the insulating film 45ba.

[0125] 42, the insulating film 45ba is removed by etching. Then, the liner film 301 exposed above the conductive layer 42 is removed by etching. As a result, the upper surface 42a of the conductive layer 42 and the upper end of the liner film 301 are aligned.

[0126] 43, a metal spacer film 311 is formed above the semiconductor device 30. As a result, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42a of the conductive layer 42 are covered with the metal spacer film 311.

[0127] [Second embodiment] A semiconductor device 30B according to the second embodiment will be described. In the second and subsequent embodiments, the description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects and advantages due to the same configuration will not be mentioned in each embodiment.

[0128] Fig. 44 shows a cross-sectional view of the semiconductor device 30B when viewed at a cross section 70ZX parallel to the ZX plane and included in the oxide semiconductor layer 70. Fig. 45 shows a cross-sectional view of the semiconductor device 30B when viewed at a cross section 70YZ parallel to the YZ plane and included in the oxide semiconductor layer 70.

[0129] As shown in Figures 44 and 45, compared to the semiconductor device 30 shown in Figures 3 to 6, the semiconductor device 30B of the second embodiment has a spacer film 711 instead of the metal spacer film 311, and further has an insulating film 501 (an example of a "third insulating film").

[0130] The insulating film 501 contacts a part, including the end on the +Z-axis direction side, of the side surface of the gate insulating film 43. In this embodiment, the insulating film 501 surrounds a part of the gate insulating film 43 on the +Z-axis direction side.

[0131] In detail, the insulating film 501 is a film extending approximately parallel to the XY plane, and functions as a hard mask during manufacturing. The lower surface of the insulating film 501 contacts the upper surface of the insulating film 45a (an example of a "fourth insulating film"). The upper surface of the insulating film 501 contacts the lower surface of the upper electrode 50. The insulating film 501 is penetrated by the gate insulating film 43 and the oxide semiconductor layer 70.

[0132] The insulating film 501 is made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, or magnesium oxide.

[0133] The oxygen concentration in the insulating film 501 is lower than the oxygen concentration in the gate insulating film 43. With this configuration, a dipole generated by oxygen moving from the gate insulating film 43 to the insulating film 501 can increase the carriers in the extension region, thereby increasing the on-current Ion.

[0134] The spacer film 711 is an insulating film. Specifically, the spacer film 711 is, for example, an oxide of silicon. The spacer film 711 includes a plurality of cylindrical portions 711a and at least one plate-shaped portion 711b.

[0135] The shape of the cylindrical portion 711a of the spacer film 711 is similar to the shape of the cylindrical portion 311a of the metal spacer film 311. The shape of the plate-like portion 711b of the spacer film 711 is similar to the shape of the plate-like portion 711b of the metal spacer film 311.

[0136] The lower end of the cylindrical portion 711a forms an annular surface in contact with the upper surface 42a of the conductive layer 42. The upper end of the cylindrical portion 711a forms an annular surface in contact with the insulating film 501.

[0137] The gate insulating film 43 surrounds a part of the oxide semiconductor layer 70 on the positive side in the Z axis direction. In particular, the end of the gate insulating film 43 on the negative side in the Z axis direction is separated from the lower electrode 32. The end of the gate insulating film 43 on the negative side in the Z axis direction is located above the lower electrode 32 and below the conductive layer 42.

[0138] [Method of manufacturing semiconductor device] Hereinafter, a method for manufacturing the semiconductor device 30B will be described as an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0139] 46, a transistor hole TH is formed, which extends substantially parallel to the Z axis and penetrates partway through the insulating film 45b via the insulating film 45ba and the conductive layer 42, and is then cleaned. At the bottom of the transistor hole TH, the insulating film 45b is exposed, but the lower electrode 32 is not exposed.

[0140] 47, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30B. As a result, the transistor hole TH is filled with the sacrificial amorphous silicon layer 170.

[0141] Next, as shown in FIG. 48, the sacrificial amorphous silicon layer 170 is etched back, thereby removing an upper portion of the sacrificial amorphous silicon layer 170 and exposing the upper surface of the insulating film 45ba.

[0142] Next, as shown in FIG. 49, the insulating film 45ba is removed by etching.

[0143] 50, a spacer film 711 is formed above the semiconductor device 30B. As a result, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42a of the conductive layer 42 are covered with the spacer film 711.

[0144] 51, a mask is formed by performing a film formation, resist coating, exposure, development, and peeling on the surface of the semiconductor device 30B by lithography, and then a groove portion 45ca is formed in the semiconductor device 30B by etching, the groove portion 45ca penetrating to the insulating film 45b and extending substantially parallel to the Y-axis. As a result, the spacer film 711 is separated into a cylindrical portion 711a and a plate-shaped portion 711b. The conductive layer 42 is also separated into a plurality of electrodes extending substantially parallel to the Y-axis and repeatedly provided in the + direction of the X-axis. These electrodes correspond to the word lines WL (see FIG. 1).

[0145] 52, insulating films 45c and 45a are integrally formed above the semiconductor device 30B. Then, the upper surface of the semiconductor device 30B is chemically mechanically polished, whereby the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a.

[0146] Next, as shown in FIG. 53, an upper part of the insulating film 45a and an upper part of the cylindrical portion 711a are removed by etching, so that an upper part of the sacrificial amorphous silicon layer 170 protrudes from the insulating film 45a and the cylindrical portion 711a.

[0147] Next, as shown in FIG. 54, an insulating film 501 is formed above the semiconductor device 30B.

[0148] Next, as shown in FIG. 55, the upper surface of the semiconductor device 30B is chemically and mechanically polished, so that the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 501.

[0149] 56, the upper part of the semiconductor device 30B is etched back by wet etching to remove the sacrificial amorphous silicon layer 170. The insulating film 45b is exposed at the bottom of the transistor hole TH.

[0150] Next, as shown in FIG. 57, an insulating film 43b is formed above the semiconductor device 30B.

[0151] Next, as shown in FIG. 58, an insulating film 43a is formed above the semiconductor device 30B.

[0152] Next, as shown in FIG. 59, the upper part of the semiconductor device 30B is etched back by reactive ion etching to expose the insulating film 501 and the lower electrode 32 at the bottom of the transistor hole TH.

[0153] Next, an oxide semiconductor layer 70 is formed inside the transistor hole TH as shown in Fig. 60. Then, the upper surface of the semiconductor device 30B is chemically and mechanically polished.

[0154] 61, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30B. Then, an LPHM film 50e containing, for example, an oxide of silicon is formed above the metal film 50c.

[0155] (effect) If the insulating film 501 is not formed, when the upper part of the semiconductor device 30B is etched back by wet etching and the sacrificial amorphous silicon layer 170 is removed, a part of the upper part of the insulating film 45a may also be removed.

[0156] For example, if the wet etching time is shortened in order to suppress the amount of removal of the insulating film 45a, it may become impossible to sufficiently remove the sacrificial amorphous silicon layer 170. Thus, there is a trade-off between the removal of the sacrificial amorphous silicon layer 170 and the suppression of damage to the insulating film 45a caused by wet etching.

[0157] In contrast, in this embodiment, as shown in FIG. 56, an insulating film 501 functioning as a hard mask is provided above the insulating film 45a, so that even if the wet etching time is extended to the extent that the sacrificial amorphous silicon layer 170 can be removed, the insulating film 501 can suppress damage to the insulating film 45a caused by the wet etching.

[0158] 59, when the upper part of the semiconductor device 30B is etched back by reactive ion etching, the insulating film 501 can prevent the periphery of the transistor hole TH from being damaged. This can prevent the upper diameter of the transistor hole TH from expanding and the transistor hole TH from opening in a trumpet shape.

[0159] (a) the first insulating film includes a cylindrical first film and a cylindrical second film provided between the first film and the oxide semiconductor; By bending the first film along the inner surface of the tubular portion, the first step portion, and the inner wall of the hole portion, the second step portion and the fifth step portion are formed on the outer surface and inner surface of the first film, respectively.

[0160] (b) the first insulating film includes a cylindrical first film and a cylindrical second film provided between the first film and the oxide semiconductor; the first film is bent along an inner circumferential surface of the cylindrical portion and the first step portion, whereby the second step portion is formed on an outer circumferential surface of the first film; The inner circumferential surface of the first film is free of steps.

[0161] (c) the second film is bent along the inner circumferential surface of the cylindrical portion and the first step portion through the first film, whereby a sixth step portion is formed on the outer circumferential surface of the second film; The inner circumferential surface of the second film is free of steps.

[0162] (d) No steps are formed in the second film.

[0163] (e) The metal film includes titanium, tantalum, tungsten, platinum, ruthenium, nickel, cobalt, palladium, gold, or copper, or nitrides of titanium, tantalum, and tungsten.

[0164] (f) The third insulating film is silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, or magnesium oxide.

[0165] (g) The second electrode contains at least one element of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0166] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Any design modifications made by a person skilled in the art to these specific examples are also included within the scope of the present disclosure as long as they have the features of the present disclosure. The elements of each of the above-mentioned specific examples and their arrangements, conditions, shapes, etc. are not limited to those exemplified and can be changed as appropriate. The combination of each of the elements of each of the above-mentioned specific examples can be changed as appropriate as long as no technical contradiction occurs. [Explanation of symbols]

[0167] 10...Semiconductor substrate 11...Circuit 20…Capacitor 21...Conductor 22...Insulating film 23...Conductor 24, 25...Capacitor electrodes 30, 30B...Semiconductor device 32…Lower electrode 33...Conductor 34, 35…Insulating layer 40...Field effect transistor 42...Conductive layer 42a...side 42b…Encirclement 42c...Connection part 43...Gate insulating film 43a, 43b...insulating film 43ad, 43ae, 43bd, 43be...Steps 45…Insulating layer 45a, 45b, 45ba, 45c...insulating film 45ca…Groove 50…Top electrode 50a...metal oxide layer 50b...Barrier metal layer 50c…Metal film 70...Oxide semiconductor layer 70a…Top end 70b…lower end 70c…Stepped section 101...Semiconductor memory device 170…Sacrificial amorphous silicon layer 301...Liner membrane 311…Metal spacer film 311a...Cylindrical part 311aa…Inner peripheral surface 311b…Plate-shaped part 401...Hole 401a…Inner wall 401b…Step surface 411…Step 501...insulating film 601...Hole 601a…Step surface 601b…Inner wall 711...Spacer membrane 711a...Cylindrical part 711b…Plate-shaped part TH: Transistor Hall

Claims

1. an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a gate electrode surrounding the oxide semiconductor via a first insulating film between the first end and the second end of the oxide semiconductor; a metal film including a tubular portion in contact with the gate electrode on the first direction side and surrounding the oxide semiconductor via the first insulating film, Semiconductor device.

2. The semiconductor device includes: a plurality of the oxide semiconductors provided along a second direction intersecting the first direction; the gate electrode extends along the second direction and includes a plurality of surrounding portions surrounding the plurality of oxide semiconductors via the first insulating film, and at least one connecting portion connecting the surrounding portions to each other; the metal film includes a plurality of the cylindrical portions each in contact with the plurality of the surrounding portions, and at least one plate-like portion having both ends in contact with the cylindrical portions and a bottom surface in contact with the connecting portion; The semiconductor device according to claim 1 .

3. The semiconductor device includes: a plurality of the oxide semiconductors provided along a second direction intersecting the first direction; the gate electrode extends along the second direction and includes a plurality of surrounding portions surrounding the plurality of oxide semiconductors via the first insulating film, and at least one connecting portion connecting the surrounding portions to each other; the metal film includes a plurality of the cylindrical portions each in contact with the surrounding portions, the connecting portion is in contact with a second insulating film provided between the cylindrical portions; The semiconductor device according to claim 1 .

4. The semiconductor device includes: a second insulating film provided on the first direction side of the gate electrode and having a first hole through which the oxide semiconductor passes; The cylindrical portion is inserted into a portion of the first hole portion on a side opposite to the first direction, A first step portion is formed by the first hole portion and the cylindrical portion. The semiconductor device according to claim 1 .

5. The first insulating film is cylindrical, the first insulating film is bent along an inner circumferential surface of the cylindrical portion and the first step portion, so that a second step portion is formed on an outer circumferential surface of the first insulating film and is in contact with the first step portion; The semiconductor device according to claim 4.

6. The inner circumferential surface of the first insulating film is free of steps. The semiconductor device according to claim 5 .

7. the first insulating film is further bent along the inner wall of the first hole portion, so that a third step portion is formed on an inner peripheral surface of the first insulating film. The semiconductor device according to claim 5 .

8. The oxide semiconductor is columnar, an outer circumferential surface of the oxide semiconductor is aligned along an inner circumferential surface of the cylindrical portion, the first step portion, and an inner wall of the first hole portion via the first insulating film, so that a fourth step portion in contact with the third step portion is formed in the oxide semiconductor. The semiconductor device according to claim 7.

9. The distance between the first electrode and the cylindrical portion is 4 nm or more and 30 nm or less. The semiconductor device according to claim 1 .

10. an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a first insulating film surrounding at least a portion of the oxide semiconductor on the first direction side; a gate electrode surrounding the oxide semiconductor via the first insulating film between the first end and the second end of the oxide semiconductor; a third insulating film in contact with a portion of a side surface of the first insulating film, the portion including an end portion on the first direction side; a fourth insulating film in contact with the third insulating film on a side opposite to the first direction, Semiconductor device.

11. the third insulating film surrounds a portion of the first insulating film on the first direction side; The semiconductor device according to claim 10.

12. The third insulating film is in contact with the first electrode. The semiconductor device according to claim 10.

13. an oxygen concentration in the third insulating film is lower than an oxygen concentration in the first insulating film; The semiconductor device according to claim 10.

14. an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a first insulating film surrounding a portion of the oxide semiconductor on the first direction side; a gate electrode surrounding the oxide semiconductor via the first insulating film between the first end and the second end of the oxide semiconductor, an end portion of the first insulating film on a side opposite to the first direction and the second electrode are spaced apart from each other; Semiconductor device.

15. The semiconductor device includes: a plurality of the oxide semiconductors provided along a second direction intersecting the first direction; the gate electrode extends along the second direction and includes a plurality of surrounding portions surrounding the plurality of oxide semiconductors via the first insulating film, and at least one connecting portion connecting the surrounding portions to each other; The width of the connecting portion is narrower than the width of the surrounding portion.

15. The semiconductor device according to claim 1, 10 or 14.

16. a second hole portion through which the oxide semiconductor passes is formed in the gate electrode; the gate electrode is formed in a self-aligned manner with respect to the second hole; 15. The semiconductor device according to claim 1, 10 or 14.

17. The semiconductor device according to claim 1, 10 or 14; a first capacitor electrode connected to the first electrode or the second electrode; a second capacitor electrode facing the first capacitor electrode; a dielectric film provided between the first capacitor electrode and the second capacitor electrode. Semiconductor memory device.

Images