Driving device and semiconductor device

Abstract

To provide a driving device and a semiconductor device, capable of reducing a switching loss of a reverse conducting type IGBT.SOLUTION: A driving device comprises: a control part; and a driving part. The control part determines any one of a first mode and a second mode to be set. The first mode is set in the case where a current direction flowing in a semiconductor device is determined as a forward direction. The second mode is set in the case where a current flowing in the semiconductor device is a reverse direction. The semiconductor device contains a reverse conductive type IGBT having two gate electrodes. The driving part generates an independent driving signal for the two gate electrodes of the semiconductor device in accordance with the setting of the control part. The driving part drives the two gate electrodes so as to reduce an off time of the semiconductor device in the first mode. The driving part drives the two gate electrodes so as to reduce a reverse recover time of a diode operation of the semiconductor device in the second mode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a drive device and a semiconductor device. [Background technology]

[0002] IGBTs (Insulated Gate Bipolar Transistors) are widely used as semiconductor elements for power control. There are reverse conducting IGBTs that integrate an IGBT with a diode. In such reverse conducting IGBTs, if you try to reduce the switching loss of the integrated diode, the conduction loss increases.

[0003] There is a demand for a power module (semiconductor device) equipped with a reverse conducting IGBT and a drive device that reduces the switching loss of the diode of the reverse conducting IGBT. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-117044 A Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments provide a drive device and a semiconductor device capable of reducing switching loss during diode operation of a reverse conducting IGBT. [Means for solving the problem]

[0006] A drive device according to an embodiment includes a control unit that determines and sets either a first mode, which is set when a direction of a current flowing through a semiconductor element including a reverse conducting IGBT having a first gate electrode and a second gate electrode, or a second mode, which is set when a direction of a current flowing through the semiconductor element is a forward direction, and a drive unit that generates a first drive signal and outputs it to the first gate electrode and generates a second drive signal and outputs it to the second gate electrode in accordance with the setting of the control unit. The control unit controls the drive unit based on a control signal including an ON command to turn on the semiconductor element and an OFF command to turn off the semiconductor element. The driving unit, in the first mode, transitions the first drive signal to an on voltage at which the semiconductor element is turned on at the timing of the on command, transitions the first drive signal to an off voltage at which the semiconductor element is turned off at the timing of the off command, transitions the second drive signal to the on voltage at the timing of the on command, and transitions the second signal to the off voltage a predetermined first time before the first drive signal transitions to the off voltage, and in the second mode, transitions the first drive signal to the on voltage a predetermined second time after it is detected that the current flowing through the semiconductor element is in the reverse direction, and transitions it to the off voltage for a predetermined third time, and maintains the second drive signal at the off voltage. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic block diagram illustrating a power module according to an embodiment. [Diagram 2] 5 is a schematic timing chart for explaining the operation of the drive device for the power module according to the embodiment. [Diagram 3] 2 is a schematic cross-sectional view illustrating a switching element that is a part of a power module according to an embodiment. FIG. [Figure 4] 4(a) to 4(c) are schematic cross-sectional views for explaining the operation of the switching element. [Diagram 5] 5(a) to 5(c) are schematic cross-sectional views for explaining the operation of the switching element. [Figure 6] FIG. 4 is a schematic graph showing an example of characteristics when the power module according to the embodiment is operated. [Figure 7] 7(a) and 7(b) are schematic timing charts for explaining the operation of the drive device for the power module of the comparative example. [Figure 8] 8(a) and 8(b) are schematic cross-sectional views for explaining the operation of a switching element that is a part of a power module of a comparative example. [Figure 9] 9(a) and 9(b) are schematic graphs showing an example of characteristics when the power module of the comparative example is operated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate.

[0009] FIG. 1 is a schematic block diagram illustrating a power module according to an embodiment. As shown in Fig. 1, a power module (semiconductor device) 10 according to the embodiment includes a switching element (semiconductor element) 20 and a driving device 30. The power module 10 has a plurality of terminals. The plurality of terminals includes a signal input terminal 11a, power supply terminals 11b, 11c, a ground terminal 11d, a collector output terminal 11e, and an emitter output terminal 11f. The power module 10 has a case 12, and the switching element 20 and the driving device 30 are housed in the case 12. The plurality of terminals are disposed on, for example, the case 12. The case 12 is formed of, for example, an insulating material.

[0010] The power module 10 is connected to, for example, a control device via a signal input terminal 11a. The control device generates and outputs a control signal VG. The control signal VG is input to the signal input terminal 11a. The drive device 30 drives the switching element 20 based on the control signal VG. The control signal VG includes a command to turn on the switching element 20 and a command to turn off the switching element 20. The control signal VG is, for example, a gate signal for switching the switching element 20.

[0011] The control signal VG is, for example, a signal having a pulse-like waveform. The switching element 20 can be turned on when the control signal VG is at H level, and can be turned off when the control signal VG is at L level. The control signal VG is not limited to a pulse signal, and may be a digital signal or an analog signal having on and off phase information, as long as it can set the on and off timings of the switching element 20. In the following, the control signal VG turning on the switching element 20 may be referred to as an on command, and turning off the switching element 20 may be referred to as an off command.

[0012] The power supply terminals 11b and 11c are connected to a power supply for operating the drive device 30. In this example, a low voltage power supply VDD1 for the control unit 32 of the drive device 30 is supplied to the power supply terminal 11b, and a high voltage power supply VDD2 for the first drive unit 34 and second drive unit 36 ​​of the drive device 30 is supplied to the power supply terminal 11c. The ground terminal 11d receives, for example, a ground potential VSS of the low voltage power supply and the high voltage power supply.

[0013] The collector output terminal 11e and the emitter output terminal 11f are connected to the collector electrode C1 and the emitter electrode E1 of the switching element 20, respectively. The collector electrode C1 is connected to an external circuit via the collector output terminal 11e. The emitter electrode E1 is connected to an external circuit via the emitter output terminal 11f. The external circuit is, for example, a DC power supply line constituting a power conversion circuit, another switching element, or a load circuit.

[0014] The driving device 30 has output terminals D1 and D2. The switching element 20 has a first gate electrode G1 and a second gate electrode G2. The output terminal D1 is connected to the first gate electrode G1, and the output terminal D2 is connected to the second gate electrode G2.

[0015] The driver 30 outputs a first drive signal V1 from an output terminal D1 to the first gate electrode G1, and outputs a second drive signal V2 from an output terminal D2 to the second gate electrode G2.

[0016] The switching element 20 is turned on and off in accordance with the first drive signal V1 and the second drive signal V2.

[0017] In the following, unless otherwise specified, the switching element 20 will be described as an n-type reverse conducting IGBT. The current flowing into the collector electrode C1 of the switching element 20 and flowing out from the emitter electrode E1 may be referred to as a forward current. The current flowing into the emitter electrode E1 of the switching element 20 and flowing out from the collector electrode C1 may be referred to as a reverse current. The control of the forward current by the switching element 20 may be referred to as a forward operation or forward operation. The control of the reverse current by the switching element 20 may be referred to as a reverse operation, reverse operation, or diode operation. When the switching element is a p-type reverse conducting IGBT, the current flowing into the emitter electrode E1 and flowing out from the collector electrode C1 is the forward current, and the current flowing into the collector electrode C1 and flowing out from the emitter electrode is the reverse current.

[0018] When the switching element 20 passes a forward current, it is said that the switching element 20 is on, and the on state during forward operation is sometimes referred to as the on state. When the switching element 20 blocks the forward current, it is said that the switching element 20 is off, and the state in which the forward current is blocked is sometimes referred to as the off state.

[0019] In the power module 10 according to the embodiment, when the switching element 20 is in an off state, the switching element 20 is capable of passing a reverse current. The switching element 20 is a reverse conducting IGBT.

[0020] In the power module 10 according to the embodiment, the drive device 30 has a plurality of operation modes. The plurality of operation modes include a normal mode (first mode) and a diode mode (second mode). In the normal mode, the drive device 30 controls the forward current by turning on or off the switching element 20 according to an on command or an off command of the control signal VG.

[0021] The diode mode is effective when the control signal VG is in the OFF command state. The driving device 30 transitions to the diode mode when it detects that a reverse current flows through the switching element 20. The diode mode is released when the driving device 30 inputs an ON command of the control signal VG.

[0022] The driving device 30, for example, detects a current flowing through the switching element 20 and determines the direction of the detected current to determine whether the current is a forward current or a reverse current. In the example of Fig. 1, the current detector 40 detects the current through the switching element 20. The determination of the operation mode is not limited to detecting the current flowing through the switching element 20. For example, the driving device 30 may detect a voltage difference between the voltage of the collector electrode C1 and the voltage of the emitter electrode E1 and determine the direction of the current flowing through the switching element 20 based on the sign of the detected voltage difference.

[0023] In the diode mode, the driver 30 performs a carrier recovery operation to recover carriers of the switching element 20. More specifically, as described later in relation to FIG. 2 and FIG. 3, the driver 30 cuts off the injection of minority carriers by recovering electrons, which are majority carriers, supplied to the n-type base layer of the switching element 20 operating as a diode, using the first drive signal V1 and the second drive signal V2. Holes, which are excess minority carriers injected into the n-type base layer, are recovered. By recovering the majority carriers and the minority carriers at an appropriate timing, it is possible to improve the reverse recovery characteristics while suppressing an increase in loss in the diode operation.

[0024] The configuration of the driving device 30 will be described. As shown in FIG. 1, the driving device 30 includes a control unit 32, a first driving unit 34, and a second driving unit 36. The control unit 32 is connected to the signal input terminal 11a. The control unit 32 inputs a control signal VG via the signal input terminal 11a. In the example of FIG. 1, the control unit 32 inputs a detection value of the emitter current IE via a current detection terminal D3 provided in the driving device 30. The control unit 32 determines the direction of the current flowing through the switching element 20 based on the detection value of the emitter current IE. For example, when the sign of the detection value of the emitter current IE is positive, the control unit 32 determines that the current flowing through the switching element 20 is a forward current. When the sign of the emitter current is negative, the control unit 32 determines that the current flowing through the switching element 20 is a reverse current.

[0025] The control unit 32 determines the operation mode in the case of an OFF command. When the control unit 32 determines that no reverse current flows through the switching element 20, it sets the operation mode to the normal mode. When the control unit 32 determines that a reverse current flows through the switching element 20, it sets the operation mode to the diode mode. The control unit 32 determines whether or not a reverse current flows through the switching element 20 based on, for example, a preset threshold value. An appropriate arbitrary value is set as the threshold value. When the absolute value of the magnitude of the detected reverse current is greater than the absolute value of the threshold value, the control unit 32 determines that a reverse current flows through the switching element 20.

[0026] The control unit 32 outputs commands to the first drive unit 34 and the second drive unit 36 ​​so as to generate drive signals according to the set operation mode.

[0027] The first driving section 34 generates a first driving signal V1 based on a command from the control section 32, and outputs it to the first gate electrode G1 via an output terminal D1. The second driving section 36 generates a second driving signal V2 based on a command from the control section 32, and outputs it to the second gate electrode G2 via an output terminal D2.

[0028] The first drive signal V1 is applied between the first gate electrode G1 and the emitter electrode E1 of the switching element 20. The second drive signal V2 is applied between the second gate electrode G2 of the switching element 20 and the emitter electrode E1.

[0029] In the normal mode, the first drive unit 34 transitions the first drive signal V1 to a voltage higher than the gate threshold voltage of the switching element 20 in response to the timing of the ON command of the control signal VG. The voltage higher than the gate threshold voltage of the switching element 20 is called the ON voltage VON. The ON voltage VON is, for example, about +15V.

[0030] In the normal mode, the first drive unit 34 transitions the first drive signal V1 to a voltage sufficiently lower than the gate threshold voltage of the switching element 20 in response to the timing of the OFF command of the control signal VG. The voltage sufficiently lower than the gate threshold voltage of the switching element 20 is called the OFF voltage VOFF. The OFF voltage VOFF is, for example, about -15V.

[0031] In the normal mode, the second drive section 36 transitions the second drive signal V2 to an on voltage VON in response to the timing of an on command of the control signal VG.

[0032] In the normal mode, the second drive section 36 transitions the second drive signal V2 to the off voltage VOFF at a timing earlier than the timing of the off command of the control signal VG.

[0033] In this way, in the normal mode, the drive device 30 outputs the first drive signal V1 to the first gate electrode G1 and the second drive signal V2 to the second gate electrode G2, thereby quickly turning off the switching element 20. Driving the switching element 20 in the normal mode using the second drive signal V2 that transitions to the off voltage VOFF before the timing of the off command of the control signal VG is sometimes called "double gate drive."

[0034] In the diode mode, the first drive unit 34 maintains the first drive signal V1 at the off voltage VOFF when the reverse current is detected. After the control unit 32 detects the reverse current, the first drive unit 34 transitions the first drive signal V1 to the on voltage VON at a preset timing, maintains the on voltage VON for a preset period, and then transitions it to the off voltage VOFF. This recovers majority carriers and blocks the injection of minority carriers.

[0035] In the diode mode, the second drive section 36 outputs the second drive signal V2 that is maintained at the off voltage VOFF, thereby continuing the injection of minority carriers and collecting surplus minority carriers.

[0036] The operation of the driving device 30 will now be described in detail with reference to a timing chart. FIG. 2 is a schematic timing chart for explaining the operation of the driving device for the power module according to the embodiment. The top diagram in Figure 2 shows the change over time of the control signal VG. "ON" is the ON command, and "OFF" is the OFF command. In this example, the control signal VG is a two-level signal, with an H level indicating an ON command and an L level indicating an OFF command. The second diagram in FIG. 2 shows the change over time of the first drive signal V1. The bottom diagram in FIG. 2 shows the change over time of the second drive signal V2. In the example of FIG. 2, the period from time t1 to time t4 is the normal mode. The period from time t4 to time t7 is the diode mode. The control unit 32, the first drive unit 34, and the second drive unit 36 ​​each have a response delay, but for simplicity, these response delays are omitted in the timing chart of FIG. 2. Specifically, at each time, the delay time occurring between the control signal VG and the first drive signal V1 is omitted, and the delay time occurring between the control signal VG and the second drive signal V2 is omitted. The same applies to FIG. 7(a) and FIG. 7(b).

[0037] 2, at time t1, the control signal VG transitions to an ON command. In response to the ON command of the control signal VG, the control unit 32 sets the operation mode to the normal mode. The control unit 32 commands the first drive unit 34 and the second drive unit 36 ​​to operate in the normal mode.

[0038] The first drive unit 34 transitions the first drive signal V1 to an on-voltage VON and outputs it based on a command from the control unit 32. The second drive unit 36 ​​transitions the second drive signal V2 to an on-voltage VON and outputs it. This turns on the switching element 20 and puts it into an on state.

[0039] Time t2 is a time before time t3. Time t3 is the time when the control signal VG transitions to an OFF command. At time t2, the second drive unit 36 ​​transitions the second drive signal V2 to an OFF voltage VOFF and outputs it. In the period from time t2 to time t3, the first drive unit 34 maintains the first drive signal V1 at an ON voltage VON and outputs it. By such double gate drive, in the normal mode, the switching element 20 can be quickly turned off. The time (first time) td_off from time t2 to time t3 is, for example, preset in the control unit 32.

[0040] In the period from time t3 to time t4, the switching element 20 is in the off state in the normal mode. For example, if the switching element 20 forms a bridge circuit, the other switching elements in the bridge circuit are on in the period from time t3 to time t4. A voltage higher than that applied to the emitter electrode E1 is applied to the collector electrode C1 of the switching element 20.

[0041] At time t4, the control unit 32 detects a reverse current. Since the control signal VG is an OFF command and the control unit 32 has detected a reverse current in the switching element 20, the control unit 32 transitions the operation mode to the diode mode. The control unit 32 starts issuing commands to the first drive unit 34 and the second drive unit 36 ​​to operate in the diode mode.

[0042] For example, when the switching element 20 constitutes a bridge circuit, at time t4, another switching element in the bridge circuit is turned off, and the back electromotive force of the load generated by the turning off of that switching element causes the switching element 20 to operate as a diode. In the diode operation, a voltage higher than that applied to the collector electrode C1 of the switching element 20 is applied to the emitter electrode E1 of the switching element 20.

[0043] At time t5, the control unit 32 commands the first driving unit 34 and the second driving unit 36 ​​to perform majority carrier recovery operation. The first driving unit 34 transitions the first driving signal V1 to the on voltage VON. The second driving unit 36 ​​maintains the second driving signal V2 at the off voltage VOFF.

[0044] At time t6, the first drive section 34 transitions the first drive signal V1 to the off voltage VOFF.

[0045] The period from time t5 to time t6 is referred to as majority carrier recovery time (third time) te. The majority carrier recovery time te is set in advance, for example, in the control unit 32. Furthermore, the timing (second time) te0 at which the majority carrier recovery time te starts is appropriately set in advance, for example, based on the timing at which the reverse current is detected.

[0046] During majority carrier recovery time te, in some regions of the switching element 20, electrons, which are majority carriers, are collected to the emitter electrode E1 side, and the injection of holes, which are minority carriers, is blocked. At this time, the off-voltage VOFF is applied to the second gate electrode G2. Therefore, in other regions of the switching element 20, the injection and collection of holes continues.

[0047] In the period from time t6 to time t7, the collector electrode C1 of the switching element 20 transitions from a voltage lower than that of the emitter electrode E1 to a voltage higher than that of the emitter electrode E1. Since the voltage of the collector electrode C1 is higher than the voltage of the emitter electrode E1, excess holes are collected on the emitter electrode E1 side.

[0048] For example, if the switching element 20 constitutes a bridge circuit, the period from time t4 to time t7 is a dead time period in the bridge circuit. During the dead time period, both the switching element 20 and other switching elements are turned off. For example, if the bridge circuit controls the output by PWM (Pulse Width Modulation), the output cannot be controlled during the dead time period, so it is preferable that the dead time period is short.

[0049] At time t7, the control signal VG transitions to an ON command. In response to the ON command of the control signal VG, the control unit 32 releases the diode mode and transitions the operation mode to the normal mode.

[0050] As will be described later in relation to FIG. 3 to FIG. 5(c), the switching element 20 has a fourth region 20d that is necessary for the configuration of the switching element 20 in addition to the cell region 20e that mainly operates in the forward direction and operates as a diode. In the cell region 20e, the charge amount of the holes to be injected is controlled by the first drive signal V1 and the second drive signal V2. The fourth region 20d is not provided with a means for controlling the injected charge amount of the holes. The fourth region 20d is a region in which the first control electrode 22a and the second control electrode 22b are not provided. The fourth region 20d may include a conductor 22c2. The fourth region 20d is a non-cell region or a finger region. The non-cell region may include a finger region that connects the control electrodes of the switching elements 20 to each other. The non-cell region is a region adjacent to the cell region and does not include a switching element.

[0051] During diode operation, the voltage of the emitter electrode E1 is higher than the voltage of the collector electrode C1. Therefore, in the fourth region 20d, holes are injected from the second semiconductor region 21b, which is a p-type base layer electrically connected to the emitter electrode E1, to the first semiconductor region 21a, which is an n-type base layer. When the voltage difference between the voltage of the emitter electrode E1 and the voltage of the collector electrode is reversed, a reverse recovery current flows, and the reverse recovery characteristic of the switching element 20 is reduced.

[0052] In the power module 10 according to the embodiment, the driving device 30 operates as described above to control the amount of holes injected in the cell region 20e, thereby suppressing the amount of holes injected in the fourth region 20d. This suppresses the reverse recovery current in the fourth region 20d, improving the reverse recovery characteristics of the switching element 20.

[0053] Next, with reference to a diagram showing the structure of the switching element 20, it will be described how the carrier recovery process improves the reverse recovery characteristics in diode operation. FIG. 3 is a schematic cross-sectional view illustrating a switching element that is a part of the power module according to the embodiment.

[0054] As shown in FIG. 3, the switching element 20 has two systems of control electrodes. Specifically, the switching element 20 has a semiconductor portion 21, a first electrode 24, a second electrode 25, a first control electrode 22a, and a second control electrode 22b. The first electrode 24 is electrically connected to the emitter electrode E1. The second electrode 25 is electrically connected to the collector electrode C1. The first control electrode 22a and the second control electrode 22b are electrically connected to the first gate electrode G1 and the second gate electrode G2, respectively. The first gate electrode G1 and the second gate electrode G2 are electrically separated from each other.

[0055] The semiconductor portion 21 is provided between the first electrode 24 and the second electrode 25. The semiconductor portion 21 includes, for example, silicon. The first electrode 24 and the second electrode 25 are metal layers including, for example, aluminum, titanium, or the like. The direction from the first electrode 24 toward the second electrode 25 is defined as the Z direction. One of the directions intersecting with the Z direction is defined as the X direction. One of the directions intersecting with the Z direction and the X direction is defined as the Y direction. The X direction, the Y direction, and the Z direction are, for example, directions perpendicular to each other. The semiconductor portion 21 extends in the X direction and the Y direction.

[0056] The first control electrode 22a and the second control electrode 22b are provided between the semiconductor portion 21 and the first electrode 24, and are electrically separated from each other. The first control electrode 22a and the second control electrode 22b are each disposed inside a trench provided in the semiconductor portion 21, and each extend into the semiconductor portion 21. In FIG. 3, the first control electrode 22a and the second control electrode 22b have, for example, a stripe shape extending in the Y direction, and are arranged in the X direction. In FIG. 3, in order to avoid complication in the illustration, the first control electrode 22a and the second control electrode 22b are drawn one by one in one region, but a plurality of first control electrodes 22a and a plurality of second control electrodes 22b may be provided in one region. The plurality of first control electrodes 22a and the plurality of second control electrodes 22b each have a stripe shape extending in the Y direction, and are arranged in the X direction. The plurality of first control electrodes 22a and the plurality of second control electrodes 22b are not limited to a stripe shape, but may be formed in a dot shape in an XY plane view, and the dot-shaped control electrodes may be arranged in a matrix. The same applies to Figures 4(a) to 5(c), 7(a) and 7(b).

[0057] The first control electrode 22a is electrically isolated from the semiconductor portion 21 by an insulating film 23a. The second control electrode 22b is electrically isolated from the semiconductor portion 21 by an insulating film 23b.

[0058] Conductors 22c1 and 22c2 are provided between the semiconductor portion 21 and the first electrode 24. The conductor 22c1 is provided between the first control electrode 22a and the second control electrode 22b. The conductor 22c2 is provided between the first control electrode 22a or the second control electrode 22b that is closest to the outer edge of the cell region 20e and the non-cell region. The conductors 22c1 and 22c2 are disposed inside trenches provided in the semiconductor portion 21 and extend into the semiconductor portion 21. The conductor 22c1 is electrically isolated from the semiconductor portion 21 by the insulating film 23c1. The conductor 22c2 is electrically isolated from the semiconductor portion 21 by the insulating film 23c2. The conductors 22c1 and 22c2 are electrically connected to the emitter electrode E1.

[0059] The first electrode 24 is provided on the first control electrode 22a, the second control electrode 22b, and the conductors 22c1 and 22c2. The first control electrode 22a, the second control electrode 22b, and the conductors 22c1 and 22c2 are electrically isolated from the first electrode 24 by an interlayer insulating film.

[0060] The semiconductor portion 21 includes a first semiconductor region 21a, a second semiconductor region 21b, a third semiconductor region 21c, a first portion 21d1 of the fourth semiconductor region, a second portion 21d2 of the fourth semiconductor region, a third portion 21e1 of the fifth semiconductor region, and a fourth portion 21e2 of the fifth semiconductor region. The first semiconductor region 21a is of the first conductive type. The second semiconductor region 21b is of the second conductive type. The third semiconductor region 21c is of the first conductive type. The first portion 21d1 and the second portion 21d2 are of the second conductive type. The third portion 21e1 and the fourth portion 21e2 are of the first conductive type. In the following description, the first conductive type is n-type and the second conductive type is p-type.

[0061] The first control electrode 22a, the second control electrode 22b and the conductors 22c1, 22c2 extend into the first semiconductor region 21a from the front surface side of the semiconductor portion 21. The first semiconductor region 21a is, for example, an n-type base layer.

[0062] The second semiconductor region 21b is provided between the first semiconductor region 21a and the first electrode 24. The second semiconductor region 21b faces the first control electrode 22a via the insulating film 23a. The second semiconductor region 21b faces the second control electrode 22b via the insulating film 23b. The second semiconductor region 21b faces the conductor 22c1 via the insulating film 23c1. The second semiconductor region 21b faces the conductor 22c2 via the insulating film 23c2. The second semiconductor region 21b is, for example, a p-type base layer. The insulating films 23a and 23b function as gate insulating films.

[0063] The third semiconductor region 21c is selectively provided between the second semiconductor region 21b and the first electrode 24. The third semiconductor region 21c faces the first control electrode 22a via the insulating film 23a. The third semiconductor region 21c is electrically connected to the first electrode 24. The third semiconductor region 21c is, for example, an n-type emitter layer.

[0064] The fourth semiconductor region 21d is provided between the second electrode 25 and the first semiconductor region 21a. The fifth semiconductor region 21e is provided between the second electrode 25 and the first semiconductor region 21a. The fourth semiconductor region 21d includes a first portion 21d1 and a second portion 21d2. The fifth semiconductor region 21e includes a third portion 21e1 and a fourth portion 21e2.

[0065] The semiconductor portion 21 further includes a sixth semiconductor region 21f of the second conductivity type. The sixth semiconductor region 21f is selectively provided between the second semiconductor region 21b and the first electrode 24. The sixth semiconductor region 21f faces the second control electrode 22b via the insulating film 23b. The sixth semiconductor region 21f faces the conductor 22c1 via the insulating film 23c1. The sixth semiconductor region 21f faces the conductor 22c2 via the insulating film 23c2. The sixth semiconductor region 21f is, for example, a p-type contact layer. The impurity concentration of the second conductivity type in the sixth semiconductor region 21f is higher than the impurity concentration of the second conductivity type in the second semiconductor region 21b.

[0066] The semiconductor portion 21 further includes a seventh semiconductor region 21g of the first conductivity type. The seventh semiconductor region 21g is provided between the first semiconductor region 21a and the fourth semiconductor region 21d. The seventh semiconductor region 21g is also provided between the first semiconductor region 21a and the fifth semiconductor region. The seventh semiconductor region 21g is, for example, an n-type buffer layer, and contains a higher concentration of impurities of the first conductivity type than the concentration of impurities of the first conductivity type in the first semiconductor region 21a.

[0067] The switching element 20 includes a first region 20a, a second region 20b, a third region 20c, and a fourth region 20d.

[0068] The first region 20a is a region of the first electrode 24, the semiconductor portion 21, and the second electrode 25 that corresponds to the first control electrode 22a.

[0069] The second region 20b is a region of the first electrode 24, the semiconductor portion 21, and the second electrode 25 that corresponds to the second control electrode 22b.

[0070] The third region 20c is a region of the first electrode 24, the semiconductor portion 21, and the second electrode 25 that corresponds to the conductor 22c1.

[0071] The region consisting of the first region 20a, the second region 20b, and the third region 20c is called a cell region 20e. In the cell region 20e, the third region 20c is disposed between the first region 20a and the second region 20b.

[0072] The fourth region 20d is adjacent to the cell region 20e. The fourth region 20d is a region of the first electrode 24, the semiconductor portion 21, and the second electrode 25 that corresponds to the conductor 22c2 and the fourth portion 21e2.

[0073] The conductor 22c2 is provided in the fourth region 20d near the boundary with the cell region 20e.

[0074] The fourth region 20d is, for example, a finger region that connects together the wirings drawn from the first control electrodes 22a provided in the first region 20a. The fourth region 20d is, for example, a region that connects together the wirings drawn from the second control electrodes 22b provided in the second region 20b. The wirings from the first control electrodes 22a and the second control electrodes 22b are provided on an interlayer insulating film provided on the second semiconductor region 21b.

[0075] The fourth region 20d may be provided adjacent to the cell region 20e, and may be provided adjacent to the first region 20a, or may be provided adjacent to the second region 20b as in the specific example of Fig. 3. The fourth region 20d may be provided between two cell regions 20e, or may be provided surrounding the cell region 20e. The fourth region 20d may be provided surrounding the cell region 20e.

[0076] The first portion 21d1 is electrically connected to the second electrode 25. The second portion 21d2 is electrically connected to the second electrode 25. The first portion 21d1 and the second portion 21d2 are, for example, a part of a p-type collector layer. The third portion 21e1 is electrically connected to the second electrode 25. The third portion 21e1 is, for example, a part of an n-type contact layer. In FIG. 3, the p-type collector layer and the n-type contact layer are arranged in a stripe shape extending in the Y direction and aligned in the X direction. The p-type collector layer and the n-type contact layer may be arranged in a stripe shape aligned in any direction on the XY plane. The p-type collector layer and the n-type contact layer may be arranged in a lattice shape or a dot shape on the XY plane. The fourth portion 21e2 is electrically connected to the second electrode 25. The fourth portion 21e2 is provided in a non-cell region.

[0077] A plurality of conductors 22c1 may be provided continuously between the first control electrode 22a and the second control electrode 22b. It is not necessary to provide the conductors 22c1 between all of the first control electrodes 22a and the second control electrodes 22b. A plurality of first control electrodes 22a may be provided continuously. A plurality of second control electrodes 22b may be provided continuously. The number of first control electrodes 22a and the number of second control electrodes 22b in one cell portion may be different. For example, a plurality of second control electrodes 22b provided continuously may be provided between two adjacent first control electrodes 22a.

[0078] The functions of the first region 20a, the second region 20b, the third region 20c and the fourth region 20d are as follows. In the normal mode, the first region 20a and the second region 20b function as an IGBT and control the forward current. In the normal mode, the second region 20b collects holes when the switching element 20 is turned off, improving the turn-off speed. In the normal mode, the third region 20c and the fourth region 20d assist the first region 20a and the second region 20b in collecting holes when the switching element 20 is turned off.

[0079] In the diode mode, the first region 20a forms an inversion layer in the second semiconductor region 21b to collect electrons, thereby blocking hole injection in the first region 20a. Also, the first region 20a forms an inversion layer in the first semiconductor region 21a to collect holes. In the diode mode, the second region 20b forms an accumulation layer in the second semiconductor region 21b and forms an inversion layer in the first semiconductor region 21a to continue hole injection.

[0080] In the diode mode, the third region 20c and the fourth region 20d assist in collecting excess holes injected into the first region 20a and the second region 20b, respectively.

[0081] 4(a) to 5(c) are schematic cross-sectional views for explaining the operation of the switching element. 4(a) to 4(c) show the operation when the switching element 20 operates in the forward direction. The mechanism by which the double gate drive speeds up the turn-off operation of the switching element 20 will be described with reference to FIG. 4(a) to FIG. 4(c). Figures 5(a) to 5(c) show the operation when the switching element 20 operates as a diode. The mechanism by which the reverse recovery characteristics are improved in the diode mode by the carrier recovery operation will be described with reference to Figures 5(a) to 5(c). In Figures 4(a) to 5(c), electrons are represented by "-" and holes are represented by "+". The same applies to Figures 8(a) and 8(b).

[0082] FIG. 4(a) shows the operation when the switching element 20 is turned on, and shows the operation at the timing corresponding to the time t1 in FIG. 2. At the timing corresponding to the time t1 in FIG. 2, the first drive signal V1 supplied to the first gate electrode G1 transitions to the on-voltage VON. By applying the on-voltage VON to the first control electrode 22a, an inversion layer is formed in the second semiconductor region 21b of the first region 20a. Electrons supplied from the third semiconductor region 21c are supplied to the first semiconductor region 21a through the inversion layer. Thereafter, holes supplied from the first portion 21d1 are injected into the first semiconductor region 21a, and the switching element 20 is turned on as an IGBT.

[0083] Fig. 4(b) shows the operation of the switching element 20 when it is turned off by double gate driving. Fig. 4(b) shows the operation of the switching element 20 at a timing corresponding to time t2 in Fig. 2. The first gate electrode G1 is supplied with the first drive signal V1 that maintains the on-voltage VON. As a result, electrons are continuously supplied to the first semiconductor region 21a via the inversion layer formed in the second semiconductor region 21b.

[0084] The second gate electrode G2 is supplied with the second drive signal V2, which has transitioned to the off voltage VOFF. By applying the off voltage VOFF to the second control electrode 22b, an accumulation layer is formed in the second semiconductor region 21b of the second region 20b. Most of the holes injected into the first semiconductor region 21a in the second region 20b are discharged to the emitter electrode E1 side via the inversion layer of the first semiconductor region 21a and the accumulation layer of the second semiconductor region 21b. Some of the holes injected into the second region 20b are discharged to the emitter electrode E1 side via the second semiconductor regions 21b of the third region 20c and the fourth region 20d.

[0085] 4(c) shows the operation of the switching element 20 when the switching element 20 is turned off by an off command of the control signal VG. FIG. 4(c) shows the operation of the switching element 20 at a timing corresponding to time t3 in FIG. 2. At a timing corresponding to time t3 in FIG. 2, the first drive signal V1 supplied to the first gate electrode G1 transitions to an off voltage VOFF. Therefore, an inversion layer is formed in the first semiconductor region 21a of the first region 20a, and an accumulation layer is formed in the second semiconductor region 21b. Holes in the first semiconductor region 21a are discharged via the inversion layer in the first semiconductor region 21a and the accumulation layer in the second semiconductor region 21b.

[0086] In the second region 20b, the second drive signal V2 supplied to the second gate electrode G2 maintains the off voltage VOFF, and holes in the first semiconductor region 21a continue to be discharged to the emitter electrode E1 via the inversion layer in the first semiconductor region 21a and the accumulation layer in the second semiconductor region 21b.

[0087] In this way, by controlling the second gate electrode G2 with the second drive signal V2, the holes in the first semiconductor region 21a are discharged in advance, so that the switching element 20 can be quickly turned off.

[0088] Fig. 5(a) shows the operation at the timing corresponding to time t4 in Fig. 2. The first drive signal V1 supplied to the first gate electrode G1 is an off voltage VOFF, and in the first region 20a, an inversion layer is formed in the first semiconductor region 21a facing the first control electrode 22a. In the first region 20a, an accumulation layer is formed in the second semiconductor region 21b facing the first control electrode 22a. Holes in the second semiconductor region 21b are injected into the first semiconductor region 21a via the accumulation layer in the second semiconductor region 21b and the inversion layer in the first semiconductor region 21a.

[0089] The second drive signal V2 supplied to the second gate electrode G2 is an off voltage VOFF, and in the second region 20b, an inversion layer is formed in the first semiconductor region 21a facing the second control electrode 22b. Also, an accumulation layer is formed in the second semiconductor region 21b facing the second control electrode 22b. Holes in the second semiconductor region 21b are injected into the first semiconductor region 21a via the accumulation layer in the second semiconductor region 21b and the inversion layer in the first semiconductor region 21a.

[0090] In the first region 20a and the second region 20b, holes are injected through the accumulation layer, so that the conduction loss in the diode operation can be reduced.

[0091] Fig. 5(b) shows the operation in a period corresponding to the majority carrier recovery time te shown in Fig. 2. As shown in Fig. 5(b), when the first drive signal V1 supplied to the first gate electrode G1 transitions to an on-voltage VON, an inversion layer is formed in the second semiconductor region 21b facing the first control electrode 22a in the first region 20a. Since the voltage on the emitter electrode E1 side is higher than the voltage on the collector electrode C1 side, electrons supplied from the third portion 21e1 of the third region 20c are collected to the emitter electrode E1 via the inversion layer in the second semiconductor region 21b, and the injection of holes in the first region 20a is blocked.

[0092] During the majority carrier recovery time te, the second drive signal V2 supplied to the second gate electrode G1 is maintained at the off voltage VOFF. Therefore, in the second region 20b, a state in which an inversion layer is formed is maintained in the first semiconductor region 21b facing the first control electrode 22a. In the second semiconductor region 21b, a state in which an accumulation layer is formed is maintained in the second semiconductor region 21b facing the second control electrode 22b. In the second region 20b, holes are continuously injected into the first semiconductor region 21a via the accumulation layer of the second semiconductor region 21b and the inversion layer of the first semiconductor region 21a.

[0093] In the diode mode, a voltage higher than that of the collector electrode C1 is applied to the emitter electrode E1. The first electrode 24 electrically connected to the emitter electrode E1 is provided over the entire surface of the second semiconductor region 21b in each region. The amount of charge of the holes that can be injected from the second semiconductor region 21b to the first semiconductor region 21a is determined according to the amount of energy input to the switching element 20. In other words, by injecting holes equivalent to the amount of charge of the holes blocked during the majority carrier recovery time te into the first semiconductor region 21a of the second region 20b, the amount of holes injected into the fourth region 20d can be suppressed as shown by the dashed arrow in FIG. 5(b).

[0094] FIG. 5(c) shows the minority carrier recovery operation, and represents the operation in the period corresponding to time t6 to time t7 in FIG. 2. In the period corresponding to time t6 to time t7, the voltage difference between the collector electrode C1 and the emitter electrode E1 is reversed, and the voltage on the emitter electrode E1 side becomes lower than the voltage on the collector electrode C1 side. When the first drive signal V1 supplied to the first gate electrode G1 transitions to the off voltage VOFF, an inversion layer is formed in the first semiconductor region 21a facing the first control electrode 22a in the first region 20a. Also, an accumulation layer is formed in the second semiconductor region 21b facing the first control electrode 22a in the first semiconductor region 21a. Therefore, the holes in the first semiconductor region 21a are discharged to the emitter electrode E1 via the accumulation layer in the second semiconductor region 21b and the inversion layer in the first semiconductor region 21a.

[0095] The second drive signal V2 supplied to the second gate electrode G2 is maintained at the off voltage VOFF. In the second region 20b, the inversion layer in the first semiconductor region 21a and the accumulation layer in the second semiconductor region 21b are also maintained, and holes are discharged to the emitter electrode E1 side through the inversion layer and the accumulation layer.

[0096] The holes in the first region 20a and the holes in the second region 20b are also diverted to the seventh semiconductor region 21f in the third region 20c and are discharged.

[0097] In the fourth region 20d, some of the holes in the adjacent second region 20b are diverted and discharged.

[0098] In diode operation, a reverse current flows in the first semiconductor region 21a due to the flow of holes, which are minority carriers, and electrons, which are majority carriers. The reverse recovery phenomenon occurs because the lifetime of holes in the first semiconductor region 21a is long, so that it takes a long time for them to recombine with electrons, and the reverse current continues to flow even if the voltage between the collector electrode C1 and the emitter electrode E1 is reversed. In the power module 10 according to the embodiment, electrons are collected in advance from the first semiconductor region 21a into which holes are injected, and the injection of holes is blocked. This reduces the current due to recombination and improves the reverse recovery characteristics of the switching element 20.

[0099] In the power module 10 according to the embodiment, during the majority carrier recovery time te, holes are injected into a part of the cell region 20e adjacent to the fourth region 20d, and the injection of holes in the first region 20a is blocked. Meanwhile, in the first region 20a, excess holes generated by blocking the injection of holes are injected into the first semiconductor region 21a through an accumulation layer formed in the second semiconductor region 21b in the second region 20b. This suppresses the amount of holes injected from the second semiconductor region 21b to the first semiconductor region 21a in the fourth region 20d. Therefore, the influence of the reverse recovery characteristic in the fourth region 20d is reduced, and the reverse recovery characteristic of the switching element 20 is improved.

[0100] FIG. 6 is a schematic graph showing an example of characteristics when the power module according to the embodiment is operated. The horizontal axis of Fig. 6 represents the majority carrier recovery time te. The vertical axis represents the switching loss Err due to reverse recovery operation during diode operation. In Fig. 6, the switching loss Err is expressed as a relative value when the switching loss Err when the majority carrier recovery time te is 0 is set to 1.0. The scale of the majority carrier recovery time te is arbitrary.

[0101] As shown in Fig. 6, the longer the majority carrier recovery time te, the more the switching loss Err is reduced. By making the majority carrier recovery time te sufficiently long, the switching loss Err can be reduced by 40% or more compared to when the majority carrier recovery time te is set to 0.

[0102] Hereinafter, the relationship between the amount of holes injected into the cell region 20e and the fourth region 20d and the reverse recovery characteristics will be described with reference to the operation of a drive device for a power module of a comparative example. 7(a) and 7(b) are schematic timing charts for explaining the operation of the drive device for the power module of the comparative example. 7(a) differs from the timing chart shown in Fig. 2 in that the second drive signal V2 is 0 V from time t4 to time t5. In the timing chart of Fig. 7(a), the second drive signal V2 is also 0 V during the period from time t3 to time t4. FIG. 7(b) differs from the timing chart shown in FIG. 2 in that the second drive signal V2 is the on-voltage VON from time t4 to time t5.

[0103] 8(a) and 8(b) are schematic cross-sectional views for explaining the operation of a switching element that is a part of a power module of a comparative example. Figures 8(a) and 8(b) respectively show the operation in the period corresponding to time t5 to time t6 in Figures 7(a) and 7(b), and correspond to Figure 5(b).

[0104] As shown in Fig. 8(a), in the period corresponding to time t5 to time t6 in Fig. 7(a), in the first region 20a, an inversion layer is formed in the second semiconductor region 21b, and electrons supplied to the first semiconductor region 21a are discharged to the emitter electrode E1 through the inversion layer, which is the same as the case of Fig. 5(b).

[0105] In the second region 20b, the second drive signal V2 supplied to the second gate electrode G2 is 0 V, so that no accumulation layer is formed in the second semiconductor region 21b of the second region 20b. Therefore, in each of the second region 20b, the third region 20c, and the fourth region 20d, holes are injected with an amount of charge according to the junction area between the second semiconductor region 21b and the first semiconductor region 21a.

[0106] In the case of Fig. 5(b), holes are injected into the second region 20b through an accumulation layer formed in the second semiconductor region 21b, so that the amount of charge of holes that can be injected per junction area can be made larger than that in the case of Fig. 8(a). By making the amount of charge of holes injected into the second region 20b larger than the sum of the amount of charge of holes injected into the second region 20b in the case of Fig. 8(a) and the amount of charge of holes injected into the third region 20c, the amount of charge of holes injected into the fourth region 20d can be made smaller.

[0107] As shown in Fig. 8(b), in the period corresponding to time t5 to time t6 in Fig. 7(b), the second drive signal V2 supplied to the second gate electrode G2 is set to the off voltage VOFF, so that an inversion layer is formed in the second semiconductor region 21b of the second region 20b. In the second region 20b, the sixth semiconductor region 21f of the same second conductivity type as the second semiconductor region 21b is provided on the second semiconductor region 21b, so that electrons cannot be discharged to the emitter electrode E1 side through the inversion layer. Therefore, neither electrons nor holes can move in the second region 20b, and no reverse current flows.

[0108] Since the voltage of the emitter electrode E1 is higher than the voltage of the collector electrode C1, in each of the third region 20d and the fourth region 20d, holes are injected into the first semiconductor region 21a according to the junction area between the second semiconductor region 21b and the first semiconductor region 21a. In the example of FIG. 8(b), the junction area in the fourth region 20d is larger than the junction area in the third region 20c, so a larger amount of holes is injected into the first semiconductor region 21a. Compared to the case of FIG. 5(b), the amount of charge of the holes injected into the first semiconductor region 21a in the fourth region 20d is larger by the amount of excess holes injected through the accumulation layer in the second region 20b, and this amount may be larger than the case of FIG. 8(a).

[0109] In this way, by controlling the amount of charge of holes injected into the second region 20b with the voltage value applied to the second control electrode 22b, the amount of charge of holes injected into the first semiconductor region 21a of the fourth region 20d can be controlled, and the reverse recovery characteristics can be controlled.

[0110] 9(a) and 9(b) are schematic graphs showing an example of characteristics when the power module of the comparative example is operated. FIG. 9(a) is a graph comparing plots of the dependence of switching loss Err on majority carrier recovery time te when the power module is operated according to the timing chart of FIG. 7(a) with the plots shown in FIG. 6. In FIG. 9(a), plot "I" is a graph for the embodiment shown in FIG. 6. "II" is a graph for the comparative example shown in the timing chart of FIG. 7(a). The scales of the vertical axis and the horizontal axis are the same as those in FIG. 6. In the plot "II", the Err value is expressed as a relative value when the Err at te=0 in the plot "I" is set to 1.0.

[0111] As shown in FIG. 9(a), the switching loss can be reduced by making the majority carrier recovery time te sufficiently long.

[0112] FIG. 9(b) is a graph comparing plots of the dependence of switching loss Err on majority carrier recovery time te when the power module is operated according to the timing chart of FIG. 7(b) with the plots shown in FIG. 6. In FIG. 9(b), plot "I" is a graph for the embodiment shown in FIG. 6. "III" is a graph for the comparative example represented by the timing chart of FIG. 7(b). The scales of the vertical axis and the horizontal axis are the same as those in FIG. 6.

[0113] As shown in FIG. 9(b), in the case of the embodiment, it is understood that the switching loss Err can be improved over the entire range of the majority carrier recovery time te.

[0114] In this way, during the majority carrier recovery time te, the switching loss Err can change depending on the magnitude of the second drive signal V2 supplied to the second gate electrode G2. In the power module 10 according to the embodiment, during the majority carrier recovery time te, the second drive signal V2 is set sufficiently lower than the gate threshold voltage, thereby suppressing the injection of holes due to the supply of excess electrons in the fourth region 20d, and improving the reverse recovery characteristics.

[0115] In the above, an example in which the fourth region 20d is provided adjacent to the second region 20b has been described, but the same applies to the case in which the fourth region 20d is provided adjacent to the first region 20a.

[0116] The effects of the power module 10 according to the embodiment will be described. The switching element 20 of the power module 10 according to the embodiment is a reverse conducting IGBT having a first gate electrode G1 and a second gate electrode G2 that can be controlled independently. The driving device 30 supplies a first driving signal V1 and a second driving signal V2 to the first gate electrode G1 and the second gate electrode G2, respectively, independently.

[0117] The drive device 30 determines the operation mode of the power module 10 based on the command of the control signal VG and the current flowing through the switching element 20. When the drive device 30 detects that a forward current flows through the switching element 20, it sets the operation mode to the normal mode and turns the switching element 20 on and off according to the control signal VG.

[0118] The driving device 30 sets the operation mode to the diode mode when it detects that a reverse current flows through the switching element 20. When the driving device 30 set to the diode mode detects that the control signal VG is an ON command, it cancels the diode mode and sets the operation mode to the normal mode.

[0119] In the diode mode, the driver 30 starts a carrier recovery operation a predetermined time after detecting a reverse current. In the carrier recovery operation, the driver 30 first executes a majority carrier recovery process. In the majority carrier recovery process, the driver 30 transitions the first drive signal V1 supplied to the first gate electrode G1 to a voltage sufficiently higher than the gate threshold voltage and continues the transition for a predetermined period of majority carrier recovery time te. During the majority carrier recovery time te, the driver 30 maintains the second drive signal V2 supplied to the second gate electrode G2 at a voltage sufficiently lower than the gate threshold voltage of the switching element 20.

[0120] This allows majority carriers supplied to the first semiconductor region 21a to be collected and the injection of minority carriers to be blocked. By suppressing the injection of minority carriers, the reverse recovery characteristics of the switching element 20 in diode operation can be improved.

[0121] The switching element 20 has a semiconductor portion 21, a first electrode 24, a second electrode 25, a first control electrode 22a, and a second control electrode 22b. In the switching element 20, the first electrode 24 is electrically connected to an emitter electrode E1, and the second electrode 25 is electrically connected to a collector electrode C1. In the switching element 20, the first control electrode 22a is electrically connected to a first gate electrode G1, and the second control electrode 22b is electrically connected to a second gate electrode G2.

[0122] In the power module 10 according to the embodiment, the switching element 20 is provided with a fourth region 20d adjacent to a cell region 20e including regions corresponding to the first control electrode 22a and the second control electrode 22b. In the diode mode, the fourth region 20d is formed so as to supply minority carriers to the first semiconductor region 21a.

[0123] In the power module 10 according to the embodiment, during the majority carrier recovery time te, the voltage applied to the second control electrode 22b is maintained at a value lower than the gate threshold voltage of the switching element 20. This allows the injection of minority carriers to continue in the second region 20b, and makes it possible to suppress the injection of minority carriers in the fourth region 20d.

[0124] By making the voltage applied to the second control electrode 22b sufficiently lower than the gate threshold voltage, an inversion layer is reliably formed in the first semiconductor region 21a, and an accumulation layer is reliably formed in the second semiconductor region 21b in the second region 20b, so that a sufficient amount of holes can be injected. The injection of a sufficient amount of holes promotes the supply of electrons from the fourth region 20d, suppresses the supply of electrons to the fourth region 20d, and suppresses the injection of holes. Since the voltage difference between the first electrode 24 and the second electrode 25 is inverted during reverse recovery in the diode operation, the excess holes in the first semiconductor region 21a can be discharged by forming an accumulation layer in the second semiconductor region 21b in both the first region 20a and the second region 20b. Therefore, the reverse recovery current is suppressed, and the reverse recovery operation is improved.

[0125] Although the embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0126] The embodiments include the following aspects.

[0127] (Appendix 1) a control unit that determines and sets either a first mode, which is set when a direction of a current flowing in a semiconductor element including a reverse conducting IGBT having a first gate electrode and a second gate electrode is a forward direction, or a second mode, which is set when a direction of a current flowing in the semiconductor element is a reverse direction; a drive unit that generates a first drive signal and outputs it to the first gate electrode according to a setting of the control unit, and generates a second drive signal and outputs it to the second gate electrode; Equipped with the control unit controls the drive unit based on a control signal including an ON command for turning on the semiconductor element and an OFF command for turning off the semiconductor element; The drive unit is In the first mode, At the timing of the ON command, the first drive signal is transitioned to an ON voltage at which the semiconductor element is turned ON, and at the timing of the OFF command, the first drive signal is transitioned to an OFF voltage at which the semiconductor element is turned OFF; transitioning the second drive signal to the ON voltage at the timing of the ON command, and transitioning the second signal to the OFF voltage a predetermined first time before the first drive signal transitions to the OFF voltage; In the second mode, a second time after it is detected that the current flowing through the semiconductor element is in a reverse direction, the first drive signal is transitioned to the on voltage, and then transitioned to the off voltage for a third time; A drive device that maintains the second drive signal at the off voltage.

[0128] (Appendix 2) In the second mode, the on-voltage is: When the semiconductor element is an n-type, the positive value is higher than the gate threshold voltage of the semiconductor element, 2. The driving device according to claim 1, wherein when the semiconductor element is a p-type, the gate threshold voltage is a negative value lower than the gate threshold voltage of the semiconductor element.

[0129] (Appendix 3) In the first mode, the voltage at which the semiconductor element is turned off is If the semiconductor element is an n-type, it is a negative value. 2. The driving device according to claim 1, wherein the value is positive when the semiconductor element is a p-type.

[0130] (Appendix 4) The control unit determines a direction of a current in the semiconductor element during a period of the OFF command, 4. The drive device according to claim 1, wherein, when the second mode is set, the second mode is cancelled and the first mode is set at the timing of the ON command.

[0131] (Appendix 5) 5. The driving device according to claim 1, wherein the control unit determines a direction of a current in the semiconductor element by detecting a current in the semiconductor element.

[0132] (Appendix 6) 5. The driving device according to claim 1, wherein the control unit determines a direction of a current in the semiconductor element by detecting a voltage between two main electrodes of the semiconductor element.

[0133] (Appendix 7) A drive device according to any one of appendix 1 to 6, The semiconductor element; a case for accommodating the driving device and the semiconductor element therein; Equipped with The first gate electrode is electrically connected to a first output of the driving device, and the second gate electrode is electrically connected to a second output of the driving device.

[0134] (Appendix 8) The semiconductor device is A cell region and a non-cell region provided adjacent to the cell region, A first electrode; A second electrode; A semiconductor portion provided between the first electrode and the second electrode; Including, The semiconductor portion of the cell region is a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first electrode and the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided between the first electrode and the second semiconductor region and electrically connected to the first electrode; a fourth semiconductor region of the second conductivity type selectively provided between the first semiconductor region and the second electrode and connected to the second electrode; a fifth semiconductor region of the first conductivity type selectively provided between the first semiconductor region and the second electrode and connected to the second electrode; a first control electrode selectively provided between the first electrode and the first semiconductor region and electrically isolated from the first electrode and the semiconductor region; a second control electrode selectively provided between the first electrode and the first semiconductor region and electrically isolated from the first electrode, the semiconductor region, and the first control electrode; Including, The non-cell region is The first semiconductor region; the second semiconductor region; 8. The semiconductor device according to claim 7, further comprising a fifth semiconductor region of the first conductivity type provided between the first layer and the second electrode and electrically connected to the second electrode. [Explanation of symbols]

[0135] 10...power module, 12...case, 20...switching element, 21...semiconductor portion, 21a...first semiconductor region, 21b...second semiconductor region, 21c...third semiconductor region, 21d1...first portion, 21d2...second portion, 21e1...third portion, 21e2...fourth portion, 21f...sixth semiconductor region, 22a...first control electrode, 22b...second control electrode, 22c1, 22c2...conductor, 23a, 23b, 23c1, 23c2...insulating film, 24...first electrode, 25...second electrode, 30...drive device, 32...control portion, 34...first drive portion, 36...second drive portion, 40...current detector

Claims

1. a control unit that determines and sets either a first mode, which is set when a direction of a current flowing in a semiconductor element including a reverse conducting IGBT having a first gate electrode and a second gate electrode is a forward direction, or a second mode, which is set when a direction of a current flowing in the semiconductor element is a reverse direction; a drive section that generates a first drive signal and outputs it to the first gate electrode, and generates a second drive signal and outputs it to the second gate electrode, according to a setting of the control section; Equipped with the control unit controls the drive unit based on a control signal including an ON command for turning on the semiconductor element and an OFF command for turning off the semiconductor element; The drive unit is In the first mode, At the timing of the ON command, the first drive signal is transitioned to an ON voltage at which the semiconductor element is turned ON, and at the timing of the OFF command, the first drive signal is transitioned to an OFF voltage at which the semiconductor element is turned OFF; transitioning the second drive signal to the ON voltage at the timing of the ON command, and transitioning the second signal to the OFF voltage a predetermined first time before the first drive signal transitions to the OFF voltage; In the second mode, a second time after it is detected that the current flowing through the semiconductor element is in a reverse direction, the first drive signal is transitioned to the on voltage, and the first drive signal is transitioned to the off voltage for a third time; A drive device that maintains the second drive signal at the off voltage.

2. In the second mode, the on-voltage is: When the semiconductor element is an n-type, the positive value is higher than the gate threshold voltage of the semiconductor element, 2. The drive device according to claim 1, wherein when said semiconductor element is a p-type, said potential is a negative value lower than a gate threshold voltage of said semiconductor element.

3. In the first mode, the off-voltage is: If the semiconductor element is an n-type, it is a negative value.

2. The driving device according to claim 1, wherein when the semiconductor element is a p-type, the value is positive.

4. The control unit determines a direction of a current in the semiconductor element during a period of the OFF command, 2. The drive device according to claim 1, wherein, when the second mode is set, the second mode is released at the timing of the ON command and the first mode is set.

5. The drive device according to claim 1 , wherein the control unit determines a direction of a current in the semiconductor element by detecting a current in the semiconductor element.

6. 2. The driving device according to claim 1, wherein the control unit determines a direction of a current in the semiconductor element by detecting a voltage between two main electrodes of the semiconductor element.

7. A drive device according to any one of claims 1 to 6, The semiconductor element; a case for accommodating the driving device and the semiconductor element therein; Equipped with The first gate electrode is electrically connected to a first output of the driving device, and the second gate electrode is electrically connected to a second output of the driving device.

8. The semiconductor device is A cell region and a non-cell region provided adjacent to the cell region, A first electrode; A second electrode; A semiconductor portion provided between the first electrode and the second electrode; Including, The semiconductor portion of the cell region is a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first electrode and the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided between the first electrode and the second semiconductor region and electrically connected to the first electrode; a fourth semiconductor region of the second conductivity type selectively provided between the first semiconductor region and the second electrode and connected to the second electrode; a fifth semiconductor region of the first conductivity type selectively provided between the first semiconductor region and the second electrode and connected to the second electrode; a first control electrode selectively provided between the first electrode and the first semiconductor region and electrically isolated from the first electrode and the semiconductor region; a second control electrode selectively provided between the first electrode and the first semiconductor region and electrically isolated from the first electrode, the semiconductor region, and the first control electrode; Including, The non-cell region is The first semiconductor region; The second semiconductor region; 8. The semiconductor device according to claim 7, further comprising a fifth semiconductor region of the first conductivity type provided between the first layer and the second electrode and electrically connected to the second electrode.

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