Memory system

Abstract

To provide a memory system capable of improving performance on reconstruction of a logical physical address conversion table.SOLUTION: A controller periodically performs first processing including: (1) processing for selecting one address conversion information from N address conversion information of a first table region and another address conversion information N / 2 after or before the selected one address conversion information; (2) processing for acquiring the selected one address conversion information and the selected another address conversion information from a volatile memory; (3) processing for writing the acquired one address conversion information and an update log into a first block; and (4) processing for writing the acquired another address conversion information and the update log into a second block.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art In recent years, a solid-state drive (SSD) that includes a nonvolatile memory and a controller that controls the nonvolatile memory is known as a memory system that has become widespread.

[0003] In memory systems such as SSDs, the correspondence between the logical addresses associated with data received from the outside and the physical addresses in the non-volatile memory where that data is stored is managed using a logical-to-physical address translation table (L2P table).

[0004] The L2P table is stored in a volatile memory such as a RAM included in the memory system. The L2P table is updated, for example, by writing data to the non-volatile memory based on a write command from the host, or by performing a data copy process associated with garbage collection performed on the non-volatile memory.

[0005] For example, if the power supply to the memory system is cut off, the information stored in the volatile memory is lost. For this reason, the memory system executes a process of saving backup data of the L2P table in a non-volatile memory, and a process of reconstructing the L2P table on the volatile memory when the power to the memory system is restored.

[0006] Even if power to the memory system is restored, the host cannot access the memory system until the reconstruction of the L2P table is completed. Furthermore, if the L2P table cannot be correctly reconstructed, the latest data corresponding to the read target logical address specified by a read command from the host cannot be correctly read from the non-volatile memory.

[0007] Therefore, there is a need for a technique that can improve the performance of rebuilding L2P tables in memory systems. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] U.S. Pat. No. 10,776,153 [Patent Document 2] U.S. Pat. No. 10,713,157 [Patent Document 3] U.S. Pat. No. 10,990,526 [Patent Document 4] U.S. Pat. No. 9,946,489 [Patent Document 5] U.S. Pat. No. 10,496,533 [Patent Document 6] U.S. Pat. No. 11,237,959 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of the present invention is to provide a memory system capable of improving the performance related to the reconstruction of a logical-physical address translation table. [Means for solving the problem]

[0010] According to an embodiment, a memory system connectable to a host includes a non-volatile memory including a plurality of blocks, a volatile memory, and a controller. The controller manages the correspondence between each logical address included in the logical address space of the memory system and each physical address of the non-volatile memory by using a logical-physical address conversion table stored in the volatile memory. The logical-physical address conversion table includes at least a first table area. The first table area holds N pieces of address conversion information respectively corresponding to N small logical address ranges. The N is an integer multiple of 2. The controller periodically executes a first process including: (1) a process of selecting one piece of address conversion information from the N pieces of address conversion information to be written to the first block of the non-volatile memory so that the N pieces of address conversion information of the first table area are stored in a first order in the first block of the non-volatile memory, and selecting, from the N pieces of address conversion information, address conversion information that is N / 2 pieces behind or before the selected one piece of address conversion information as another piece of address conversion information to be written to a second block of the non-volatile memory; (2) a process of acquiring the selected one piece of address conversion information and the other selected address conversion information from the first table area on the volatile memory; (3) a process of writing, to the first block, the acquired one piece of address conversion information and an update log indicating update contents for all address conversion information of the first table area that was updated after acquiring the one piece of address conversion information and the other address conversion information; and (4) a process of writing, to the second block, the other acquired address conversion information and the update log.In response to power being restored to the memory system after power supply to the memory system is cut off, the controller reads the N / 2 pieces of address conversion information last written to the first block and the N / 2 update logs last written to the first block from the first block, reads the N / 2 pieces of address conversion information last written to the second block and the N / 2 update logs last written to the second block from the second block, and reconstructs the first table area of ​​the logical-physical address conversion table on the volatile memory based on the N / 2 pieces of address conversion information read from the first block, the N / 2 pieces of address conversion information read from the second block, and the N / 2 update logs read from either the first block or the second block. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] 1 is a block diagram showing an example of the internal configuration of a nonvolatile memory included in a memory system according to an embodiment. [Diagram 3] FIG. 2 is a block diagram showing an example of a functional configuration of a CPU included in the memory system according to the embodiment. [Figure 4] FIG. 2 is a diagram showing an example of a configuration showing the relationship between multiple channels and multiple NAND flash memory dies used in the memory system according to the embodiment. [Diagram 5] FIG. 2 is a diagram showing an example of the configuration of a superblock used in the memory system according to the embodiment. [Figure 6] 1A and 1B are diagrams showing an example of the configuration of an L2P table used in a memory system according to an embodiment, and an example of the configuration showing the relationship between a plurality of table areas of the L2P table and a plurality of L2P flash blocks. [Figure 7] 1 is a diagram showing an example of a configuration showing the relationship between a plurality of LBA ranges and a plurality of table areas of an L2P table in a memory system according to an embodiment. [Figure 8] 1 is a diagram showing an example of the configuration of each of a plurality of L2P fragments stored in an L2P table used in a memory system according to an embodiment. [Figure 9] 1 is a diagram showing an example of a configuration showing the relationship between a plurality of LBA ranges, a plurality of table areas of an L2P table, a plurality of log buffers, and a plurality of L2P flash blocks in a memory system according to an embodiment. FIG. [Figure 10] 4 is a diagram showing a first example of an update log in the memory system according to the embodiment. [Figure 11] FIG. 11 is a diagram showing a second example of an update log in the memory system according to the embodiment. [Figure 12] FIG. 13 is a diagram showing a third example of an update log in the memory system according to the embodiment. [Figure 13] 11 is a diagram showing a first example of a lost LBA list saving process of the memory system according to the embodiment. FIG. [Figure 14] FIG. 2 is a diagram showing a first example of a configuration for duplicating backup data of an L2P table used in the memory system according to the embodiment. [Figure 15] FIG. 13 is a diagram showing a second configuration example for duplicating backup data of an L2P table used in the memory system according to the embodiment. [Figure 16] 11 is a diagram showing a first example of an address translation information / update log saving process of the memory system according to the embodiment. [Figure 17] FIG. 11 is a diagram showing a first example of an L2P table rebuild process of the memory system according to the embodiment. [Figure 18] 11 is a diagram showing a second example of the address translation information / update log saving process of the memory system according to the embodiment. FIG. [Figure 19] FIG. 11 is a diagram showing a second example of the L2P table rebuild process of the memory system according to the embodiment. [Figure 20] FIG. 11 is a diagram showing a third example of the L2P table rebuild process of the memory system according to the embodiment. [Figure 21]11 is a flowchart showing the procedure of an address translation information / update log storage process of the memory system according to the embodiment. [Figure 22] 11 is a flowchart showing the procedure of an L2P table rebuild process of the memory system according to the embodiment. [Figure 23] FIG. 13 is a block diagram showing an example of a configuration illustrating updating of an L2P table in garbage collection processing of the memory system according to the embodiment. [Figure 24] FIG. 2 is a block diagram showing a first example of a configuration showing log recording in garbage collection processing of the memory system according to the embodiment. [Diagram 25] FIG. 11 is a block diagram showing a second example of a configuration showing log recording in garbage collection processing of the memory system according to the embodiment. [Figure 26] 11 is a flowchart showing a log recording process of the memory system according to the embodiment. [Figure 27] 11 is a flowchart showing another procedure of the L2P table rebuild process of the memory system according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment will be described with reference to the drawings. First, the configuration of an information processing system including a memory system according to an embodiment will be described. Fig. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment and a host. The information processing system 1 includes a host (host device) 2 and an SSD (Solid State Drive) 3 as a memory system.

[0013] The host 2 is an information processing device such as a personal computer, a server computer, or a mobile device. The host 2 is connected to the SSD 3 and can access the SSD 3. Specifically, the host 2 issues a write command to the SSD 3 to write data. The host 2 also issues a read command to the SSD 3 to read data.

[0014] The SSD3 is also called a storage device, and is capable of writing data to an internal non-volatile memory and reading data from the internal non-volatile memory.

[0015] The communication between the SSD 3 and the host 2 is performed via a bus 4. The bus 4 is a transmission path that connects the host 2 and the SSD 3. The bus 4 is, for example, a PCI express TM (PCIe TM ) bus. The bus 4 is a full-duplex transmission path. The full-duplex transmission path includes both a transmission path for transmitting data and input / output (I / O) commands from the host 2 to the SSD 3, and a transmission path for transmitting data and responses from the SSD 3 to the host 2. The I / O command is issued from the host 2 to the SSD 3 and is a write command for writing data to the nonvolatile memory, or a read command for reading data from the nonvolatile memory.

[0016] The logical interface for connecting the host 2 and the SSD 3 may be, for example, Serial Attached SCSI (SAS), Serial ATA (SATA), or NVM Express. TM (NVMe TM ) may be used.

[0017] Next, the internal configuration of the host 2 will be described.

[0018] The host 2 includes a processor 21 and a memory 22 , and the processor 21 and the memory 22 are interconnected via an internal bus 20 .

[0019] The processor 21 is, for example, a CPU (Central Processing Unit). The processor 21 executes software (host software) loaded from the SSD 3 to the memory 22. The host 2 may include a storage device other than the SSD 3. In this case, the host software may be loaded from the other storage device to the memory 22. The host software includes, for example, an operating system, a file system, a device driver, and an application program.

[0020] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is realized by, for example, a random access memory such as a dynamic random access memory (DRAM).

[0021] Next, we will explain the internal configuration of the SSD 3. Here, it is assumed that the nonvolatile memory included in the SSD 3 is a NAND type flash memory, but it may be other flash memory, or other nonvolatile memory such as MRAM, ReRAM, FeRAM, or phase change memory.

[0022] The SSD 3 includes a controller 5 and a NAND flash memory 6. The SSD 3 may further include a random access memory, for example, a dynamic random access memory (DRAM) 7 which is a volatile memory.

[0023] The controller 5 is a memory controller. The controller 5 is, for example, a control circuit such as a System-on-a-Chip (SoC). The controller 5 is electrically connected to each of the NAND flash memory 6 and the DRAM 7. The controller 5 processes various commands received from the host 2. When the controller 5 receives a write command from the host 2, the controller 5 executes a process of writing data to the NAND flash memory 6 based on the received write command. When the controller 5 receives a read command from the host 2, the controller 5 executes a process of reading data from the NAND flash memory 6 based on the received read command.

[0024] For example, a Toggle interface or an Open NAND Flash Interface (ONFI) is used as a physical interface connecting the controller 5 and the NAND flash memory 6. The controller 5 can be realized by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and a processor.

[0025] The NAND type flash memory 6 may be a two-dimensional flash memory or a three-dimensional flash memory. Hereinafter, the NAND type flash memory 6 will be referred to as the NAND memory 6.

[0026] The DRAM 7 is a volatile memory. The DRAM 7 is used, for example, to temporarily store data to be written to the NAND memory 6. The storage area of ​​the DRAM 7 is also used to store various management data used by the controller 5.

[0027] The SSD 3 further includes a power supply circuit 8. The power supply circuit 8 is a power supply control circuit. The power supply circuit 8 is connected to the controller 5, the NAND memory 6, the DRAM 7, etc., and supplies power supplied from the host 2 to each component of the SSD 3, such as the controller 5, the NAND memory 6, and the DRAM 7. The power supply circuit 8 is also capable of communicating with the controller 5. The communication between the power supply circuit 8 and the controller 5 is performed, for example, when an unexpected power loss occurs, in order for the power supply circuit 8 to notify the controller 5 of the occurrence of the power loss.

[0028] Next, the internal configuration of the controller 5 will be described.

[0029] The controller 5 includes a host interface (I / F) 51, a CPU 52, an SRAM 53, a direct memory access controller (DMAC) 54, an ECC processing circuit 55, a DRAM interface (I / F) 56, and a NAND interface (I / F) 57. The host interface 51, the CPU 52, the SRAM 53, the DMAC 54, the ECC processing circuit 55, the DRAM interface 56, and the NAND interface 57 are interconnected via a bus 50.

[0030] The host interface 51 is a host interface circuit that executes communication with the host 2. The host interface 51 is, for example, a PCIe controller. Alternatively, if the SSD 3 has a configuration in which a network interface controller is built in, the host interface 51 may be realized as a part of the network interface controller. The host interface 51 receives various commands from the host 2. These commands include a write command, a read command, and the like.

[0031] The CPU 52 is a processor. The CPU 52 controls the host interface 51, the SRAM 53, the DMAC 54, the ECC processing circuit 55, the DRAM interface 56, and the NAND interface 57. In response to the supply of power to the SSD 3, the CPU 52 loads a control program (firmware) from the NAND memory 6 or a ROM (not shown) into the SRAM 53, and executes the firmware to perform various processes. The firmware may be loaded into the DRAM 7.

[0032] The controller 5 may include two or more CPUs 52. In this case, the controller 5 can execute various processes in parallel.

[0033] The CPU 52, for example, as a flash translation layer (FTL), manages data stored in the NAND memory 6 and manages blocks included in the NAND memory 6. The management of data stored in the NAND memory 6 includes, for example, management of address conversion information. The address conversion information is also referred to as mapping information or logical-to-physical address conversion information. The CPU 52 uses a logical-to-physical address translation table (L2P table) 71 to manage the address conversion information.

[0034] In the NAND memory 6, new data cannot be directly overwritten in an area in a block where data has already been written. Therefore, when updating data that has already been written, the controller 5 writes the new data in an unwritten area in that block (or another block), and treats the previous data as invalid data. In other words, when data corresponding to a certain logical address is updated, the controller 5 writes the updated data to a different storage location in the NAND memory 6, rather than to the storage location in the NAND memory 6 where the previous data is stored. The controller 5 then updates the L2P table 71 so that the logical address is associated with a physical address corresponding to this different storage location.

[0035] Management of each block in the NAND memory 6 includes management of defective blocks (bad blocks), wear leveling (WL), garbage collection (GC), and the like.

[0036] Bad block management is block address management to prevent new data from being written to bad blocks to which data can no longer be written properly. Wear leveling is a process for leveling out data written to the NAND memory 6 so that it is not concentrated in a specific block. Garbage collection is a process for reducing the number of blocks containing a mixture of valid data and invalid data and for increasing the number of free blocks. A free block is a block that does not contain valid data.

[0037] Valid data is data stored in a storage location corresponding to the latest physical address associated with a logical address. For example, data stored in a storage location of the NAND memory 6 referenced by the L2P table 71, that is, data associated with a logical address and managed by the controller 5 as the latest data, is valid data. Valid data is data that may be read by the host 2 later.

[0038] Invalid data is data stored in a storage location of the NAND memory 6 that is not referenced by the L2P table 71. For example, data stored in a storage location of the NAND memory 6 that corresponds to a physical address that is not associated with any logical address, that is, data that is not managed by the controller 5 as the latest data in association with a logical address, is invalid data. Invalid data is data that is no longer likely to be read by the host 2.

[0039] The SRAM 53 is a volatile memory and is used, for example, as a working area for the CPU 52.

[0040] The DMAC 54 executes data transfer between the memory 22 of the host 2 and the DRAM 7 (or SRAM 53) under the control of the CPU 52. When data is to be transferred from the memory 22 of the host 2 to the DRAM 7 (or SRAM 53), the CPU 52 specifies to the DMAC 54 a source address indicating the memory area in the memory 22 of the host 2 where the data is stored, the size of the data, and a destination address indicating the memory area in the DRAM 7 (or SRAM 53) to which the data is to be transferred.

[0041] The ECC processing circuit 55 is a circuit that executes data encoding and decoding. In the encoding process, the ECC processing circuit 55 adds an error correction code (ECC) as a redundant code to data to be written to the NAND memory 6. When data is read from the NAND memory 6, the ECC processing circuit 55 executes a decoding process. In the decoding process, the ECC processing circuit 55 uses the ECC added to the data read from the NAND memory 6 to perform error correction on the data.

[0042] The DRAM interface 56 is a circuit that controls the DRAM 7. The DRAM interface 56 controls the DRAM 7 under the control of the CPU 52.

[0043] The NAND interface 57 is a circuit that controls the NAND memory 6. The NAND interface 57 controls the NAND memory 6 under the control of the CPU 52. Communication between the NAND interface 57 and the NAND memory 6 is performed in accordance with, for example, the Toggle NAND flash interface or the Open NAND Flash Interface (ONFI). When the NAND memory 6 includes multiple NAND flash memory dies, the NAND interface 57 can be connected to the multiple NAND flash memory dies, respectively, via, for example, multiple channels (Ch).

[0044] Next, a description will be given of the information stored in the NAND memory 6. The NAND memory 6 stores user data 61 and an L2P table 62.

[0045] The user data 61 is data written to the NAND memory 6 based on a write command received from the host 2.

[0046] The L2P table 62 is a table stored in the NAND memory 6 as a backup of the L2P table 71 stored in the DRAM 7. That is, the L2P table 62 holds backup data of the L2P table 71. This backup data is information necessary for reconstructing the L2P table 71.

[0047] Next, there will be described the information stored in the DRAM 7. The DRAM 7 includes an L2P table 71, log buffers 72-0, . . . , 72-n, a data buffer 73, an LBA list 74, and an LBA range / block management table 75.

[0048] The L2P table 71 is a table that holds the address conversion information described above. That is, the controller 5 manages the correspondence between each of the logical addresses included in the logical address space of the SSD 3 and each of the physical addresses of the NAND memory 6 by using the L2P table 71. Each logical address in the logical address space of the SSD 3 is an address used by the host 2 to access the SSD 3. The logical address is, for example, a logical block address (LBA). The physical address is, for example, a physical block address (PBA). The physical address (PBA) is expressed by, for example, a combination of a block address, a page address, and an offset address within the page. Note that, when the NAND memory 6 includes a plurality of NAND memory chips, the physical address (PBA) is expressed by, for example, a combination of a chip address, a block address, a page address, and an offset address within the page.

[0049] The L2P table 71 may include one or more table areas. In other words, the L2P table 71 includes at least a first table area. The first table area is a table area that holds N pieces of address translation information corresponding to N small logical address ranges, respectively. N is an integer equal to or greater than 2. Preferably, N is an integer multiple of 2.

[0050] When the L2P table 71 includes only the first table area, the first table area covers the entire logical address range included in the logical address space of the SSD 3.

[0051] On the other hand, when the L2P table 71 includes at least a first table area and a second table area, the first table area and the second table area cover different logical address ranges in the logical address space. For example, the first table area covers a first logical address range in the logical address space, and the second table area covers a second logical address range in the logical address space that follows the first logical address range. The number of small logical address ranges included in each of the first logical address range and the second logical address range is N. That is, the N pieces of address translation information in the first table area correspond to the N small logical address ranges belonging to the first logical address range, respectively. The second table area also holds N pieces of address translation information corresponding to the N small logical address ranges belonging to the second logical address range, respectively. Hereinafter, each logical address range is also referred to as an LBA range.

[0052] Each small logical address range is a set of one or more logical addresses. For example, assume that each small logical address range includes 32 consecutive logical addresses. In this case, the address translation information corresponding to a certain small logical address range includes 32 physical addresses associated with the 32 consecutive logical addresses belonging to this small logical address range. Note that, in the following, a case where each small logical address range includes a plurality of consecutive logical addresses will be mainly described, but the number of logical addresses included in each small logical address range may be one. The configuration of the L2P table 71 will be described in detail later with reference to FIG. 6.

[0053] The log buffers 72-0, ..., 72-n are buffers for holding update logs, and correspond to, for example, a plurality of table areas of the L2P table 71, respectively.

[0054] The data buffer 73 is a buffer that temporarily holds data to be written to the NAND memory 6 or data read from the NAND memory 6 .

[0055] The LBA list 74 is a list that holds LBAs corresponding to data that has not been completely written to the NAND memory 6 .

[0056] The LBA range / block management table 75 is a table that holds information indicating the correspondence between a plurality of LBA ranges and a plurality of L2P flash blocks. For each LBA range, the LBA range / block management table 75 holds the block address of the L2P flash block assigned to that LBA range. The L2P flash block assigned to a certain LBA range is used to hold the backup data of the L2P table 71 corresponding to that LBA range.

[0057] The SSD 3 further includes a capacitor 81. The capacitor 81 is an element capable of storing power. The capacitor 81 is electrically connected to the power supply circuit 8. When the value of the power supply voltage supplied from the host 2 drops without a power cutoff advance notice from the host 2, for example, when an unexpected power loss occurs, the power supply circuit 8 supplies the power stored in the capacitor 81 to each component of the SSD 3. The power supply circuit 8 also notifies the controller 5 via the bus 50 of the occurrence of such an unexpected power loss. The power cutoff advance notice is a notice that notifies the SSD 3 that the power supply to the SSD 3 will be cut off. When the power supply of the host 2 is turned off, the host 2 transmits a power cutoff advance notice to the SSD 3 in advance to notify that the power supply will be cut off soon. The power cutoff advance notice is, for example, a Shutdown Notification defined in the NVMe standard, or a STANDBY IMMEDIATE command defined in the SATA standard.

[0058] The power stored in the capacitor 81 can be used, for example, by the controller 5 to execute a Power Loss Protection (PLP) operation. In the PLP operation, the controller 5 writes information stored in the volatile memory (DRAM 7 or SRAM 53) to the NAND memory 6.

[0059] Next, a description will be given of the internal configuration of the NAND memory 6. Fig. 2 is a block diagram showing an example of the internal configuration of a non-volatile memory included in the memory system according to the embodiment.

[0060] The NAND memory 6 includes a memory cell array 60. The memory cell array 60 includes a plurality of memory cells arranged in a matrix.

[0061] The memory cell array 60 of the NAND memory 6 includes a plurality of blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 includes a plurality of pages (here, pages P0 to Py-1). Each of the blocks BLK0 to BLKx-1 functions as a unit of a data erase operation. A block may also be referred to as an "erase block," a "physical block," or a "flash block." Each of the pages P0 to Py-1 is a unit of each of a data write operation and a data read operation.

[0062] 3 is a block diagram showing an example of a functional configuration of the CPU 52 included in the memory system according to the embodiment. The configuration of each function of the CPU 52 will be described below in order with reference to FIGS.

[0063] The CPU 52 functions as a write control unit 521, a read control unit 522, a garbage collection control unit 523, an L2P table management unit 524, a lost LBA list storage unit 525, and an L2P table rebuild processing unit 526. Note that a part or all of each function of the CPU 52 may be realized by dedicated hardware of the controller 5.

[0064] <Light control unit 521> First, the process executed by the write control unit 521 will be described below.

[0065] The write control unit 521 executes a process corresponding to a write command received from the host 2. The write command specifies, for example, a start logical address (start LBA), a data size, and a data pointer. The start LBA indicates the first logical block (destination LBA) to which the write data associated with the write command should be written. One logical block (sector) is the smallest unit of data that can be specified by an LBA. The size of one logical block is, for example, 512 bytes or 4K bytes. The data size indicates the size of the write data. The data size may be expressed, for example, by the number of logical blocks (the number of LBAs) to be written, or by bytes. The data pointer is a memory address indicating the memory area of ​​the memory 22 in which the write data is stored. The write command may further specify an area identifier indicating any one of the multiple areas of the NAND memory 6. The write control unit 521 executes a data acquisition process, a write destination block allocation process, a write destination determination process, an L2P update process, a completion response notification process, and a write process based on the write command received from the host 2.

[0066] The data acquisition process is a process for acquiring write data from the memory 22 of the host 2 based on the data pointer and the data size. By acquiring the write data from the memory 22 of the host 2, the write control unit 521 receives the write data from the host 2. The received write data is temporarily stored in the data buffer 73.

[0067] The write destination block allocation process is a process of allocating a write destination block to which the received write data should be written. The write control unit 521 allocates a write destination block to each of the multiple areas so that the multiple write destination blocks correspond to the multiple areas in a one-to-one relationship. If a write destination block for the area specified by the received write command has already been allocated, there is no need to execute a process of allocating a new write destination block to the area specified by the received write command.

[0068] The write destination determination process is a process for determining the write destination of the received write data, that is, the storage location (write destination storage location) in the NAND memory 6 to which this write data should be written. The physical address indicating the write destination storage location is represented by, for example, the block address of the write destination block to which the write data should be written, and an address (offset address) indicating the storage location in this write destination block to which the write data should be written.

[0069] The L2P update process is a process for updating the L2P table 71 on the DRAM 7 so that a logical address (start LBA) corresponding to the write data is associated with a physical address of a storage location (write destination storage location) in the NAND memory 6 determined as the write destination of the write data. The L2P update process may be executed when the write destination storage location is determined, that is, when the write data is received from the host 2. Alternatively, the L2P update process may be executed after the received write data is actually written to the NAND memory 6.

[0070] The completion response notification process is a process for notifying the host 2 of a completion response indicating the completion of processing of the received write command. The completion response notification process may be executed, for example, at the point in time when write data is received from the host 2.

[0071] The write process is a process of writing the write data stored in the data buffer 73 to the NAND memory 6.

[0072] <Read control unit 522> Next, the process executed by the read control unit 522 will be described below.

[0073] The read control unit 522 executes processing corresponding to the read command received from the host 2. The read command specifies, for example, a start logical address (start LBA), a data size, and a data pointer. The start LBA indicates the first logical block (read target LBA) in which the read target data is stored. The data size indicates the size of the read target data. The data pointer is a memory address indicating a memory area of ​​the memory 22 of the host 2 to which the read target data read from the NAND memory 6 should be transferred. The read command may further specify an area identifier indicating the area of ​​the NAND memory 6 in which the read target data is stored. The read control unit 522 executes address resolution processing, read processing, data transfer processing, and completion response notification processing based on the read command received from the host 2.

[0074] The address resolution process is a process of obtaining a physical address associated with an LBA (start LBA) corresponding to the read target data by referring to the L2P table 71 on the DRAM 7. The read process is a process of reading the read target data from the NAND memory 6 based on the obtained physical address. The read target data is temporarily stored in the data buffer 73. The data transfer process is a process of transferring the read target data stored in the data buffer 73 to a memory area of ​​the memory 22 indicated by the data pointer. The completion response notification process is a process of notifying the host 2 of a completion response indicating the completion of the processing of the read command.

[0075] <Garbage collection control unit 523> Next, the process executed by the garbage collection control unit 523 will be described below.

[0076] The garbage collection control unit 523 executes garbage collection (GC) processing on the NAND memory 6. The GC processing includes GC target block selection processing, data copy processing, and L2P update processing.

[0077] The GC target block selection process is a process of selecting a GC target block (also called a copy source block) which is a block to be subjected to garbage collection. The blocks of the NAND memory 6 are broadly classified into active blocks and free blocks. An active block is a block in which valid data is stored. A free block is a block in which valid data is not stored. The garbage collection control unit 523 selects one or more blocks containing a mixture of valid data and invalid data as a GC target block (copy source block) from a set of active blocks. For example, one or more blocks with a smaller amount of valid data may be selected as the copy source block.

[0078] The data copy process is a process of copying data from a source storage location in the NAND memory 6 to a destination storage location. The source storage location is a storage location in the source block where valid data is stored. The destination storage location is a storage location in the destination block to which the valid data should be copied. The garbage collection control unit 523 reads valid data from the source storage location in the source block, and writes the read valid data to the destination storage location in the destination block. When all valid data in the source block is copied to the destination block by this data copy process, the source block is released as a free block that does not contain valid data.

[0079] The L2P update process is a process for updating the L2P table 71 on the DRAM 7 so that the physical address associated with the logical address corresponding to the copied valid data is changed from the old physical address to the new physical address. Here, the old physical address is a physical address indicating the source storage location, and the new physical address is a physical address indicating the destination storage location.

[0080] In the L2P update process, the garbage collection control unit 523 obtains from the L2P table 71 the physical address associated with the logical address corresponding to the copied valid data.

[0081] When the obtained physical address matches the old physical address, the garbage collection control unit 523 updates the L2P table 71 so that the new physical address is associated with the logical address corresponding to the copied data.

[0082] On the other hand, when the obtained physical address does not match the old physical address, the garbage collection control unit 523 does not update the L2P table 71. This is because when the obtained physical address does not match the old physical address, new data corresponding to the data to be copied may have been written to the NAND memory 6 during the execution of the data copy process. The garbage collection control unit 523 updates the L2P table 71 on the condition that the obtained physical address matches the old physical address. Therefore, even if new data corresponding to the data to be copied is written to the NAND memory 6 during the execution of the data copy process, it is possible to prevent the physical address corresponding to the storage location where the new data is written from being changed to the physical address corresponding to the storage location where the old data (copied data) is copied.

[0083] <L2P table management unit 524> Next, the processing executed by the L2P table management unit 524 will be described below.

[0084] The L2P table management unit 524 manages the L2P table 71. The L2P table management unit 524 divides the L2P table 71 into one or more table areas corresponding to one or more LBA ranges respectively. In the following, it is assumed that the L2P table 71 is divided into a plurality of table areas, and the L2P table management unit 524 executes update log management processing and address translation information / update log storage processing for each LBA range, that is, for each table area. Note that the L2P table 71 does not necessarily have to be divided into a plurality of table areas. In this case, the update log management processing and the address translation information / update log storage processing are executed for one table area covering the entire logical address space of the L2P table 71.

[0085] The update log management process uses a plurality of log buffers 72-0, ..., 72-n, which are associated with a plurality of table areas in a one-to-one relationship, to manage an update log indicating update contents for N pieces of address translation information for each table area. For example, assume that in a table area corresponding to a certain LBA range, a physical address (PBA) associated with LBA10 belonging to this LBA range is updated from physical address (PBA) = 5 to physical address (PBA) = 10. In this case, the L2P table management unit 524 stores an update log indicating that new PBA10 is associated with LBA10 in the log buffer corresponding to this table area.

[0086] The address translation information / update log save process is a process of periodically writing, for each table area of ​​the L2P table 71, N pieces of address translation information of the table area and an update log indicating update contents for the N pieces of address translation information to a block (L2P flash block) of the NAND memory 6. For example, assume a case where the address translation information / update log save process for the first table area corresponding to the first LBA range is executed. In this case, the L2P table management unit 524 periodically executes a first process including: (1) a process of selecting one piece of address translation information to be written to the first L2P flash block from the N pieces of address translation information so that the N pieces of address translation information of the first table area are stored in the first order in the first block (first L2P flash block) corresponding to the first table area; (2) a process of acquiring the selected piece of address translation information from the first table area on the DRAM 7; and (3) a process of writing the acquired piece of address translation information and an update log indicating the update contents of all the address translation information of the first table area that was updated after acquiring the piece of address translation information to the first L2P flash block. Here, the first order may be an order in which the N pieces of address translation information are consecutively arranged. For example, the first order may be ascending order, descending order, or any other order.

[0087] The address translation information / update log storage process for each of the other table areas of the L2P table 71 is also executed in a similar procedure to the address translation information / update log storage process for the first table area.

[0088] For example, assume that an address translation information / update log save process is executed for a second table area corresponding to a second LBA range subsequent to a first LBA range. In this case, the L2P table management unit 524 periodically executes a second process including: (1) a process of selecting one piece of address translation information to be written to another L2P flash block from the N pieces of address translation information in the second table area so that the N pieces of address translation information in the second table area are stored in the first order in another block (another L2P flash block) corresponding to the second table area; (2) a process of acquiring the selected piece of address translation information from the second table area on the DRAM 7; and (3) a process of writing the piece of address translation information acquired from the second table area and an update log indicating update contents for all the address translation information in the second table area that has been updated after acquiring the piece of address translation information from the second table area to the other L2P flash block.

[0089] In this way, by periodically executing the address translation information / update log saving process for each table area of ​​the L2P table 71, in each L2P flash block, multiple address translation information / update log pairs, each of which includes a pair of address translation information for the table area corresponding to the L2P flash block and an update log indicating the update contents of this address translation information, are stored in chronological order.

[0090] In this manner, in this embodiment, a plurality of address translation information and update log pairs are stored in the NAND memory 6 as backup data for the L2P table 71.

[0091] (Double processing) Next, a process of duplicating the backup data of the L2P table 71 performed by the L2P table management unit 524 will be described. In duplicating the backup data, the backup data (a plurality of address translation information / update log pairs) of the L2P table 71 is stored in two L2P flash blocks of the NAND memory 6. This makes it possible to safely store a plurality of address translation information / update log pairs in the NAND memory 6. Therefore, even if an error occurs such that the backup data cannot be normally read from one of these two L2P flash blocks, the L2P table 71 can be reconstructed using the backup data in the other L2P flash block.

[0092] In this embodiment, in order to improve the performance related to the reconstruction of the L2P table 71, more specifically, to shorten the time required to reconstruct the L2P table 71 while safely storing the L2P table 71, the L2P table management unit 524 executes the address translation information / update log storage process in the following procedure when duplicating the backup data of the L2P table 71. Here, it is assumed that the backup data (a plurality of address translation information / update log pairs) of the first table area corresponding to the first LBA range is stored in the first L2P flash block and the second L2P flash block.

[0093] The L2P table management unit 524 performs the following process: (1) selects one piece of address translation information to be written to the first L2P flash block from the N pieces of address translation information such that the N pieces of address translation information of the first table area are stored in the first L2P flash block in a first order, and selects, from the N pieces of address translation information, address translation information that is N / 2 pieces behind or before the selected one piece of address translation information as another piece of address translation information to be written to the second L2P flash block; and (2) stores the selected one piece of address translation information and the selected another piece of address translation information in a first order. The device periodically executes a first process including: (1) a process of acquiring address translation information from a first table area on the DRAM 7; (2) a process of writing, to a first L2P flash block, the acquired piece of address translation information and an update log indicating update contents for all address translation information in the first table area that was updated after acquiring the piece of address translation information and the other address translation information; and (3) a process of writing, to a first L2P flash block, the other acquired address translation information and an update log that is the same as the update log written to the first L2P flash block.

[0094] Here, assume that N=4. In this case, in the first process, for example, the first address translation information and the first update log are written to, for example, page P0 of the first L2P flash block, and the third address translation information and the first update log are written to, for example, page P0 of the second L2P flash block.

[0095] In the second first process, for example, the second address translation information and the second update log are written to, for example, page P1 of the first L2P flash block, and the fourth address translation information and the second update log are written to, for example, page P1 of the second L2P flash block.

[0096] In the third first process, for example, the third address translation information and the third update log are written to, for example, page P2 of the first L2P flash block, and the first address translation information and the third update log are written to, for example, page P2 of the second L2P flash block.

[0097] In the fourth first process, for example, the fourth address translation information and the fourth update log are written to, for example, page P3 of the first L2P flash block, and the second address translation information and the fourth update log are written to, for example, page P3 of the second L2P flash block.

[0098] Here, attention is focused on the first address translation information. The first address translation information written to the first L2P flash block in the first first process does not reflect the contents of the first and subsequent update logs. On the other hand, the first address translation information written to the second L2P flash block in the third first process already reflects the first and second update logs.

[0099] In this way, the first address translation information written in the second L2P flash block contains newer updates than the first address translation information written in the first L2P flash block.

[0100] Therefore, by copying the first address translation information written in the second L2P flash block to DRAM 7, the latest contents of the first address translation information can be reconstructed on DRAM 7 without reflecting the contents of the first update log and the second update log in the first address translation information on DRAM 7.

[0101] Next, attention is given to the second address translation information. The second address translation information written to the first L2P flash block in the second first process does not reflect the contents of the second and subsequent update logs. On the other hand, the second address translation information written to the second L2P flash block in the fourth first process already reflects the first update log, the second update log, and the third update log.

[0102] In this manner, the second address translation information written to the second L2P flash block contains newer updates than the second address translation information written to the first L2P flash block.

[0103] Therefore, by copying the second address translation information written to the second L2P flash block to DRAM 7, the latest contents of the second address translation information can be reconstructed on DRAM 7 without reflecting the contents of the first update log, the second update log, and the third update log in the second address translation information on DRAM 7.

[0104] In this manner, in this embodiment, a duplication process (also referred to as a time-staggered duplication process) can be executed in which address translation information at different times is stored in two L2P flash blocks. In this manner, by executing the time-staggered duplication process for the first table area, the first table area of ​​the L2P table 71 can be safely stored in the NAND memory 6, and the time required for rebuilding the first table area of ​​the L2P table 71 can be shortened. Therefore, the performance related to the reconstruction of the L2P table 71 can be improved in that the first table area can be safely stored in the NAND memory 6 while the time required for rebuilding the first table area can be shortened.

[0105] (GC-compatible address conversion information / update log storage process) Furthermore, in this embodiment, in order to improve the performance of rebuilding the L2P table 71, more specifically, in order to enable the L2P table 71 to be correctly rebuilt even if new data corresponding to the data to be copied is written to the NAND memory 6 during execution of a data copy process for GC, a process of saving an update log capable of distinguishing between an update of the L2P table 71 based on GC and an update of the L2P table 71 based on a write command may be executed in the NAND memory 6. In this case, the L2P table management unit 524 executes the address translation information / update log saving process in the following procedure. Here, it is assumed that the backup data (a plurality of address translation information / update log pairs) of the first table area is saved in the first L2P flash block.

[0106] That is, the L2P table management unit 524 periodically executes a first process including: (1) a process of selecting one piece of address translation information to be written to the first L2P flash block from the N pieces of address translation information so that the N pieces of address translation information of the first table area are stored in the first order in the first L2P flash block; (2) a process of acquiring the selected piece of address translation information from the first table area on the DRAM 7; and (3) a process of writing the acquired piece of address translation information and an update log indicating the update contents for all of the address conversion information of the first table area that was updated after the acquisition of the piece of address conversion information to the first L2P flash block.

[0107] Here, when the first table area of ​​the L2P table 71 is updated by writing data to the NAND memory 6 based on a write command received from the host 2, the update log written to the first L2P flash block includes a first type log including a logical address corresponding to this data and a physical address indicating the storage location in the NAND memory 6 determined as the write destination for this data.

[0108] On the other hand, when the first table area of ​​the L2P table 71 is updated by copying data from a source memory location of the NAND memory 6 to a destination memory location of the NAND memory 6, which is performed in the GC for the NAND memory 6, the update log written to the first L2P flash block includes a second type log including a logical address corresponding to the copied data, a new physical address indicating the destination memory location, and an old physical address indicating the source memory location.

[0109] As a result, in the process of reconstructing the first table area, it is possible to execute a process of acquiring a physical address associated with a logical address corresponding to the copied data from the first table area, and reflecting the contents of this log in the first table area on the condition that the acquired physical address matches the old physical address. Therefore, even if new data corresponding to the data to be copied is written to the NAND memory 6 during the data copy process, it is possible to prevent the physical address corresponding to the write destination storage location of the new data from being changed to the physical address corresponding to the copy destination storage location of the old data (copied data). As a result, it is possible to improve the performance of reconstruction of the L2P table 71 in that the L2P table 71 can be correctly reconstructed even if new data corresponding to the data to be copied is written to the NAND memory 6 during the data copy process for GC.

[0110] The address translation information / update log saving process corresponding to GC may be executed in combination with the time difference duplication process. In this case, the L2P table management unit 524 performs the process of (1) selecting one piece of address translation information to be written to the first L2P flash block from the N pieces of address translation information in the first table area so that the N pieces of address translation information in the first table area are stored in the first order in the first L2P flash block, and selecting, from the N pieces of address translation information, address translation information that is N / 2 pieces behind or before the selected one piece of address translation information as another piece of address translation information to be written to the second L2P flash block; and (2) storing the selected one piece of address translation information and the selected another piece of address translation information in a first order. The above-mentioned first process is periodically performed by repeatedly executing the following processes: (1) a process of acquiring address translation information from a first table area on DRAM7; (2) a process of writing, to a first L2P flash block, the acquired piece of address translation information and an update log indicating the update contents for all address translation information in the first table area that was updated after acquiring the piece of address translation information and the other address translation information; and (3) a process of writing, to a second L2P flash block, the other acquired address translation information and an update log that is the same as the update log written to the first L2P flash block.

[0111] In this way, in the time-staggered duplex process, the same update log is written to both of the two L2P flash blocks. Each of the update logs written to both of the two L2P flash blocks may include two types of logs, that is, the first type log and the second type log described above.

[0112] (Duplication processing for each table area) In the time-difference duplication process, the backup data of the L2P table 71 may be stored in two L2P flash blocks for each table area. For example, assume that the L2P table 71 includes a first table area and a second table area, the first table area covers a first LBA range in the logical address space of the SSD 3, and the second table area covers a second LBA range in the logical address space of the SSD 3 that follows the first LBA range. In this case, the L2P table management unit 524 executes the address translation information / update log storage process in the following procedure.

[0113] That is, as described above, the L2P table management unit 524 assigns a first block (first L2P flash block) and a second block (second L2P flash block) to the first table area, and assigns a third block (third L2P flash block) and a fourth block (fourth L2P flash block) to the second table area.

[0114] The L2P table management unit 524 executes the time difference duplication process for the first table area and the time difference duplication process for the second table area in parallel. The time difference duplication process for the first table area is executed in the above-mentioned procedure. The time difference duplication process for the second table area is executed in the following procedure.

[0115] That is, the L2P table management unit 524 performs the process of (1) selecting one piece of address translation information to be written to the third L2P flash block from the N pieces of address translation information in the second table area so that the N pieces of address translation information in the second table area are stored in the third L2P flash block in the first order, and selecting, from the N pieces of address translation information in the second table area, address translation information that is N / 2 pieces behind or before the selected one piece of address translation information as another piece of address translation information to be written to the fourth L2P flash block; and (2) storing the selected one piece of address translation information and the selected another piece of address translation information in the fourth L2P flash block. The DARM7 periodically executes a second process including: (1) a process of acquiring address translation information from a second table area on the DARM7; (2) a process of writing, to a third L2P flash block, one piece of address translation information acquired from the second table area and an update log indicating update contents for all address translation information in the second table area that was updated after acquiring the one piece of address translation information from the second table area and the other address translation information; and (3) a process of writing, to a fourth L2P flash block, another piece of address translation information acquired from the second table area and an update log that is the same as the update log written to the third L2P flash block.

[0116] (Log buffer management) When the L2P table management unit 524 receives a power cutoff advance notice from the host 2 or when an unexpected power loss occurs, the L2P table management unit 524 judges whether or not an update log that has not been saved in the L2P flash block exists in any of the log buffers 72-0, ..., 72-n. When an update log that has not been saved in the L2P flash block that corresponds to a certain table area exists in the log buffer that corresponds to this table area, the L2P table management unit 524 writes the update log that has not been saved to the L2P flash block. When an unexpected power loss occurs, the process of writing the update log that has not been saved to the L2P flash block is executed using the power stored in the capacitor. That is, the update log stored in the log buffer 72 is included in the PLP target data that is data that should be saved in the NAND memory 6 when an unexpected power loss occurs.

[0117] For example, the L2P table management unit 524 manages an update log indicating update contents for N pieces of address translation information in the first table area and an update log indicating update contents for address translation information in the second table area using the log buffer 72-0 and the log buffer 72-1, respectively. When a power cutoff advance notice is received from the host 2 or an unexpected power loss occurs, if there is an update log in the log buffer 72-0 that has not yet been saved in the L2P flash block corresponding to the first table area, the L2P table management unit 524 writes the update log in the log buffer 72-0 to the L2P flash block corresponding to the first table area. Also, if there is an update log in the log buffer 72-1 that has not yet been saved in the L2P flash block corresponding to the second table area, the L2P table management unit 524 writes the update log in the log buffer 72-1 to the L2P flash block corresponding to the second table area.

[0118] <Lost LBA list storage section 525> Next, the process executed by the lost LBA list storage unit 525 will be described below.

[0119] (Lost LBA list saving process) The lost LBA list saving unit 525 performs a lost LBA list saving process. The lost LBA list saving process is a process for saving a list of logical addresses corresponding to write data that has been lost due to an unexpected power loss.

[0120] The lost LBA list storage unit 525 executes a lost LBA list storage process for each table area of ​​the L2P table 71.

[0121] For example, in the lost LBA list saving process for the first table area, the lost LBA list saving unit 525 saves a list (first list) of logical addresses corresponding to write data lost due to unexpected power loss among write data to be written in the first LBA range corresponding to the first table area, in the L2P flash block corresponding to the first table area. Note that, in the case where the time difference duplication process is being executed, the first list is saved in both of the two L2P flash blocks corresponding to the first table area.

[0122] Also, for example, in the lost LBA list saving process for the second table area, the lost LBA list saving unit 525 saves a list (second list) of logical addresses corresponding to write data lost due to unexpected power loss among write data to be written in the second LBA range corresponding to the second table area, in the L2P flash block corresponding to the second table area. Note that, in the case where the time difference duplication process is being executed, the second list is saved in both of the two L2P flash blocks corresponding to the second table area.

[0123] The first list is a set of remaining logical addresses, excluding the set of logical addresses corresponding to write data that has been received from the host 2 and is to be written to the first LBA range, and the set of logical addresses corresponding to write data that has been written to the NAND memory 6.

[0124] The second list is a set of remaining logical addresses, excluding the set of logical addresses corresponding to write data that has been received from the host 2 and is to be written to the second LBA range, and the set of logical addresses corresponding to write data that has been written to the NAND memory 6.

[0125] The first list and the second list are generated based on the LBA list 74 stored in the DRAM 7. The LBA list 74 is a collection of logical addresses corresponding to all data that has been received from the host 2 and has not yet been written to the NAND memory 6.

[0126] The lost LBA list saving process is executed using the first method or the second method.

[0127] In the first method, the lost LBA list storage unit 525 uses the power stored in the capacitor 81 in response to the occurrence of an unexpected power loss to write the first list and the second list to the L2P flash block corresponding to the first table area and the L2P flash block corresponding to the second table area, respectively. In this way, in the first method, when an unexpected power loss occurs, the first list and the second list are stored in the L2P flash block corresponding to the first table area and the L2P flash block corresponding to the second table area, respectively. Note that when a power cutoff advance notice is received from the host 2, the controller 5 starts a shutdown (graceful shutdown) process and writes all write data already received from the host 2 to the NAND memory 6. The host 2 does not cut off the supply of power to the SSD 3 until the completion of the graceful shutdown process is notified from the controller 5. Therefore, since no write data is lost, it is not necessary to store the lost LBA list in the L2P flash block.

[0128] In the second method, in response to an unexpected power loss, the lost LBA list storage unit 524 writes the first list and the second list to a predetermined one block of the NAND memory 6 using the power stored in the capacitor 81. The predetermined one block may be, for example, a single level cell block (SLC block). The SLC block is a block in which data is written using the SLC mode which is a program mode in which 1 bit of data is written per memory cell. Note that each L2P flash block may be any of an SLC block, a triple level cell block (TLC block), and a quad level cell block (QLC block). The TLC block is a block in which data is written using the TLC mode which is a program mode in which 3 bits of data are written per memory cell. The QLC block is a block in which data is written using the QLC mode which is a program mode in which 4 bits of data are written per memory cell. Then, in response to the restoration of power to the SSD 3, the lost LBA list storage unit 524 copies the first list and the second list from the predetermined one block to the L2P flash block corresponding to the first table area and the L2P flash block corresponding to the second table area, respectively. In this way, in the second method, when an unexpected power loss occurs, the first list and the second list are not respectively allocated to the L2P flash block corresponding to the first table area and the L2P flash block corresponding to the second table area, but when the power to the SSD 3 is restored, the first list and the second list are respectively allocated to the L2P flash block corresponding to the first table area and the L2P flash block corresponding to the second table area.

[0129] <L2P table rebuild processing unit 526> Next, some processes related to the L2P table executed by the L2P table rebuild processing unit 526 will be described below.

[0130] (Rebuild processing of L2P table) The L2P table rebuild processor 526 executes an L2P table rebuild process for each table area of ​​the L2P table 71. The L2P table rebuild process is a process for reconstructing the latest address conversion information of each table area of ​​the L2P table 71 on the DRAM 7 based on a predetermined number of pieces of address conversion information and a predetermined number of update logs stored in each L2P flash block.

[0131] The rebuild process is executed in response to the power supply to the SSD 3 being cut off and then being restored to the SSD 3. In either case of a case where power supply to the SSD 3 is cut off due to an unexpected power loss and then being restored to the SSD 3, or a case where power supply to the SSD 3 is cut off due to completion of a graceful shutdown process and then being restored to the SSD 3, the L2P table rebuild processor 526 can execute the rebuild process in the following procedure.

[0132] Before executing the L2P table rebuild process, the L2P table rebuild processor 526 may notify the host 2 that the SSD 3 is ready to process an I / O command. When an I / O command specifying a logical address belonging to a certain logical address range (LBA range) is received from the host 2, the L2P table rebuild processor 526 selects an L2P flash block corresponding to this LBA range from among a plurality of L2P flash blocks. Then, based on the N pieces of address translation information and the N update logs of the table area stored in the selected L2P flash block, the L2P table rebuild processor 526 reconstructs the latest address translation information of the table area corresponding to this LBA range on the DRAM 7. When power to the SSD 3 is restored after an unexpected power loss occurs, the latest address translation information to be reconstructed is the address translation information of this table area in the L2P table 71 immediately before the unexpected power loss occurs.

[0133] (Rebuild process for time-difference duplication) Next, a rebuild process for rebuilding the first table area on the DRAM 7 in a case where the time-staggered duplication process is being executed on the first table area will be described.

[0134] That is, the L2P table rebuild processing unit 526 reads the N / 2 pieces of address translation information last written to the first L2P flash block and the N / 2 pieces of update logs last written to the first L2P flash block from the first L2P flash block, and reads the N / 2 pieces of address translation information last written to the second L2P flash block and the N / 2 pieces of update logs last written to the second L2P flash block from the second L2P flash block. As a result, the N / 2 pieces of address translation information read from the first L2P flash block and the N / 2 pieces of address translation information read from the second L2P flash block are different from each other. Therefore, a total of N pieces of address translation information required for rebuilding the first table area can be read from the first L2P flash block and the second L2P flash block. Furthermore, the N / 2 update logs read from the first L2P flash block are the same as the N / 2 update logs read from the second L2P flash block.

[0135] The L2P table rebuild processing unit 526 reconstructs the first table area on the DRAM 7 based on the N / 2 pieces of address translation information read from the first L2P flash block, the N / 2 pieces of address translation information read from the second L2P flash block, and the N / 2 update logs read from either the first L2P flash block or the second L2P flash block.

[0136] In the case where time-lag duplication is not used, N pieces of address translation information and N update logs are required to reconstruct the first table area.

[0137] On the other hand, in the case where time-difference duplication is used, the latest N / 2 pieces of address translation information can be obtained from the first L2P flash block, and the latest other N / 2 pieces of address translation information can be obtained from the second L2P flash block. The latest N / 2 pieces of address translation information and the latest other N / 2 pieces of address translation information already reflect the contents of the oldest N / 2 update logs out of the N update logs. Therefore, in the case where time-difference duplication is used, the first table area can be reconstructed on the DRAM 7 without using the oldest N / 2 update logs.

[0138] (Order of update log reflection) In the case where time-staggered duplication is used, the L2P table rebuild processor 526 reflects the contents of N / 2 update logs in the address translation information in the following procedure.

[0139] That is, the L2P table rebuild processor 526 first stores in the DRAM 7 the N / 2 pieces of address translation information read from the first L2P flash block, and then stores in the DRAM 7 the N / 2 pieces of address translation information read from the second L2P flash block.

[0140] Next, the L2P table rebuild processor 526 selects an update log in chronological order from the N / 2 update logs read from either the first L2P flash block or the second L2P flash block.

[0141] Next, the L2P table rebuild processor 526 selects, from a total of N pieces of address translation information including the N / 2 pieces of address translation information read from the first L2P flash block and the N / 2 pieces of address translation information read from the second L2P flash block, a group of address translation information acquired from the area of ​​the first table on the DRAM 7 before the selected update log was written to the first L2P flash block and the second L2P flash block. Then, the L2P table rebuild processor 526 reflects the contents of the selected update log in the selected group of address translation information.

[0142] For example, when N=4, assume that a pair of the fourth address translation information and the fourth update log and a pair of the third address translation information and the third update log are read from the first L2P flash block, and a pair of the second address translation information and the fourth update log and a pair of the first address translation information and the third update log are read from the second L2P flash block.

[0143] In this case, the third update log is selected as the oldest update log. The address translation information acquired from the DRAM 7 before the third update log was written to the first L2P flash block and the second L2P flash block is the third address translation information read from the first L2P flash block and the first address translation information read from the second L2P flash block. Therefore, the contents of the third update log are reflected in the third address translation information and the first address translation information.

[0144] Next, the fourth update log is selected as the oldest update log. The address translation information acquired from the area of ​​the first table on the DRAM 7 before the fourth update log was written to the first L2P flash block and the second L2P flash block is the third address translation information and the fourth address translation information read from the first L2P flash block, and the first address translation information and the second address translation information read from the second L2P flash block. Therefore, the contents of the fourth update log are reflected in the third address translation information, the fourth address translation information, the first address translation information, and the second address translation information.

[0145] In a case where time-staggered duplication is not used, the L2P table rebuild processor 526 reads, from the L2P flash block corresponding to the area of ​​the first table, the N pieces of address translation information last written to the L2P flash block and the N update logs last written to the L2P flash block. Next, the L2P table rebuild processor 526 selects an update log from the read N update logs in chronological order. Then, from the N pieces of address translation information read from the L2P flash block, the L2P table rebuild processor 526 selects a group of address translation information acquired from the DRAM 7 before the selected update log was written to the L2P flash block, and reflects the contents of the selected update log in the selected group of address translation information.

[0146] (Rebuild process when an error occurs that prevents data from being read normally from one of the two L2P flash blocks) When data cannot be read normally from either the first L2P flash block or the second L2P flash block, the L2P table rebuild processor 526 executes the rebuild process in the following procedure.

[0147] That is, when the L2P table rebuild processor 526 cannot normally read data from one of the first L2P flash block and the second L2P flash block, it reads, from the other L2P flash block, the N pieces of address translation information last written to the other of the first L2P flash block and the second L2P flash block and the N update logs last written to the other L2P flash block. Then, the L2P table rebuild processor 526 reconstructs the first table area based on the N pieces of address translation information read from the other L2P flash block and the N update logs read from the other L2P flash block.

[0148] (Processing using the lost LBA list) After rebuilding the first table area, the L2P table rebuild processor 526 determines whether a list of logical addresses corresponding to the lost write data is stored in the L2P flash block corresponding to the first table area. If a list of logical addresses corresponding to the lost write data is stored in the L2P flash block, the L2P table rebuild processor 526 updates the rebuilt first table area based on the list stored in the L2P flash block such that a value indicating an error is associated with each of the logical addresses corresponding to the lost write data.

[0149] In this manner, the address translation information of the first table area is reconstructed, and further, a value indicating an error is associated with each of the logical addresses corresponding to the lost write data.

[0150] (Rebuild process when address conversion information / update log save process corresponding to GC is executed) Next, a rebuild process corresponding to the case where the address conversion information / update log saving process corresponding to GC is executed will be described. When the address conversion information / update log saving process corresponding to GC is executed, the L2P table rebuild processor 526 executes the rebuild process in the following procedure. Here, it is assumed that the first table area is rebuilt in the case where the time difference duplication process for the first table area is not used.

[0151] That is, the L2P table rebuild processor 526 reads, from the first L2P flash block, the N pieces of address conversion information last written to the first L2P flash block and the N update logs last written to the first L2P flash block. Then, the L2P table rebuild processor 526 reconstructs the first table area on the DRAM 7 based on the N pieces of address conversion information that have been read and the N update logs that have been read.

[0152] In rebuilding the first table area, the L2P table rebuild processor 526 determines whether or not the read N update logs include a second type log. If the read N update logs include a second type log, the L2P table rebuild processor 526 acquires a physical address corresponding to the logical address included in the second type log from the first table area on the DRAM 7. Then, the L2P table rebuild processor 526 determines whether or not the old physical address included in the second type log matches the acquired physical address.

[0153] If the old physical address included in the second type log matches the acquired physical address, the L2P table rebuild processing unit 526 reflects the contents of the second type log in the first table area on the DRAM 7 so that the new physical address included in the second type log is associated with the logical address included in the second type log.

[0154] On the other hand, if the old physical address included in the second type log does not match the acquired physical address, the L2P table rebuild processor 526 does not reflect the content of the second type log in the first table area on the DRAM 7.

[0155] In this way, the L2P table rebuild processor 526 executes a process of reflecting the contents of the second type log in the first table area on the condition that the physical address acquired from the first table area matches the old physical address. Therefore, even if new data corresponding to the data to be copied is written to the NAND memory 6 during the data copy process, the physical address corresponding to the write destination storage location of the new data can be prevented from being changed to the physical address corresponding to the copy destination storage location of the old data (copied data).

[0156] Even when the address conversion information / update log saving process corresponding to GC is executed for each of the other table areas, the L2P table rebuild processor 526 executes the rebuild process for each of the other table areas in the same procedure as the above-described rebuild process for the first table area, in the following procedure.

[0157] For example, assume that processing is performed on a second table area that corresponds to a second LBA range following the first LBA range.

[0158] The L2P table rebuild processor 526 reads, from the second L2P flash block, the N pieces of address translation information last written to the second L2P flash block and the N update logs last written to the second L2P flash block. Then, the L2P table rebuild processor 526 reconstructs the second table area on the DRAM 7 based on the N pieces of address translation information that have been read and the N update logs that have been read.

[0159] In rebuilding the second table area, the L2P table rebuild processor 526 determines whether or not the read N update logs include a second type log. If the read N update logs include a second type log, the L2P table rebuild processor 526 acquires a physical address corresponding to the logical address included in the second type log from the second table area on the DRAM 7. Then, the L2P table rebuild processor 526 determines whether or not the old physical address included in the second type log matches the acquired physical address.

[0160] If the old physical address included in the second type log matches the acquired physical address, the L2P table rebuild processing unit 526 reflects the contents of the second type log in the second table area on the DRAM 7 so that the new physical address included in the second type log is associated with the logical address included in the second type log.

[0161] On the other hand, if the old physical address included in the second type log does not match the acquired physical address, the L2P table rebuild processor 526 does not reflect the content of the second type log in the second table area on the DRAM 7.

[0162] The above-mentioned (1) time-difference duplication processing, (2) address conversion information / update log saving processing corresponding to GC, (3) duplication processing for each table area, (4) lost LBA list saving processing, etc. can be executed in any suitable combination.

[0163] As described above using Figure 3, each function of CPU 52 shown in Figure 3, namely, write control unit 521, read control unit 522, garbage collection control unit 523, L2P table management unit 524, lost LBA list storage unit 525, and L2P table rebuild processing unit 526, performs various types of processing.

[0164] Next, a configuration of the NAND memory 6 including a plurality of NAND flash memory dies will be described. Fig. 4 is a block diagram showing a configuration example showing the relationship between a plurality of channels and a plurality of NAND flash memory dies used in the memory system according to the embodiment.

[0165] Each of the multiple NAND flash memory dies can operate independently. Therefore, the NAND flash memory dies are treated as a unit that can operate in parallel. In FIG. 4, 16 channels Ch.1 to Ch.16 are connected to the NAND interface (I / F) 57, and two NAND flash memory dies are connected to each of the 16 channels Ch.1 to Ch.16.

[0166] In this case, 16 NAND flash memory dies #1 to #16 connected to channels Ch.1 to Ch.16 may be configured as bank #0, and the remaining 16 NAND flash memory dies #17 to #32 connected to channels Ch.1 to Ch.16 may be configured as bank #1. A bank is treated as a unit for operating multiple memory dies in parallel by bank interleaving. In the configuration example of FIG. 4, a maximum of 32 NAND flash memory dies can be operated in parallel by 16 channels and bank interleaving using two banks.

[0167] The data erase operation may be performed in units of one block (physical block) or in units of a block group including a set of multiple physical blocks that can operate in parallel. A block group is also referred to as a super block.

[0168] One block group, that is, one superblock including a set of multiple physical blocks, may include, but is not limited to, a total of 32 physical blocks selected one by one from the NAND flash memory dies #1 to #32. Each of the NAND flash memory dies #1 to #32 may have a multi-plane configuration. For example, when each of the NAND flash memory dies #1 to #32 has a multi-plane configuration including two planes, one superblock may include a total of 64 physical blocks selected one by one from the 64 planes corresponding to the NAND flash memory dies #1 to #32.

[0169] FIG. 5 illustrates an example of one superblock (SB) including 32 physical blocks (here, physical block BLK2 of NAND flash memory die #1, physical block BLK3 of NAND flash memory die #2, physical block BLK7 of NAND flash memory die #3, physical block BLK4 in NAND flash memory die #4, physical block BLK6 in NAND flash memory die #5, ..., physical block BLK3 in NAND flash memory die #32).

[0170] It should be noted that a configuration in which one superblock includes only one physical block may be used, in which case one superblock is equivalent to one physical block.

[0171] A superblock includes the same number of logical pages as the pages (physical pages) P0 to Py-1 included in each of the physical blocks constituting the superblock. A logical page is also called a superpage. One superpage includes 32 physical pages, the same number as the number of physical blocks included in the superblock. For example, the first superpage of the illustrated superblock includes a set of physical pages P1 of physical blocks BLK2, BLK3, BLK7, BLK4, BLK6, ..., BLK3 of each of the NAND flash memory dies #0, #2, #3, #4, #5, ..., #32.

[0172] (Configuration of L2P Table 71) Next, a description will be given of the configuration of the L2P table 71. Fig. 6 is a diagram showing a configuration example of the L2P table 71 used in the memory system according to the embodiment, and a configuration example showing the relationship between a plurality of table areas of the L2P table 71 and a plurality of L2P flash blocks.

[0173] Here, it is assumed that the logical address space of SSD 3 is divided into n+1 LBA ranges. The logical address space includes LBA range #0, LBA range #1, LBA range #2, ..., LBA range #n.

[0174] The shortcut table 710 is a table that holds the relationship between the LBA and the memory address that indicates the memory location where the L2P fragment of the L2P table 71 is stored.

[0175] The L2P table 71 of the DRAM 7 includes a plurality of L2P fragments. Each of the plurality of L2P fragments is address translation information corresponding to one small logical address range. Each of the plurality of L2P fragments may include a plurality of physical addresses corresponding to a plurality of consecutive logical addresses included in the corresponding small logical address range. For example, one L2P fragment may include a predetermined number of physical addresses corresponding to a predetermined number of consecutive logical addresses.

[0176] The L2P table 71 is divided into a table area T0 corresponding to LBA range #0, a table area T1 corresponding to LBA range #1, a table area T2 corresponding to LBA range #2, ..., a table area Tn corresponding to LBA range #n. Each of the table areas T0 to Tn includes N L2P fragments. In Fig. 6, an example is shown in which each table area includes four L2P fragments (L2P fragments #0 to #3).

[0177] The L2P table 71 includes an L2P fragment (#0) 711-00, an L2P fragment (#1) 711-01, an L2P fragment (#2) 711-02, and an L2P fragment (#3) 711-03 as a set of L2P fragments corresponding to the LBA range #0. The L2P fragment (#0) 711-00 is address translation information corresponding to the first small LBA range of the four small LBA ranges obtained by dividing the LBA range #0. The L2P fragment (#1) 711-01 is address translation information corresponding to the second small LBA range of the four small LBA ranges. The L2P fragment (#2) 711-02 is address translation information corresponding to the third small LBA range of the four small LBA ranges. The L2P fragment (#3) 711-03 is address translation information corresponding to the first small LBA range of the four small LBA ranges.

[0178] The L2P table 71 includes an L2P fragment (#0) 711-10, an L2P fragment (#1) 711-11, an L2P fragment (#2) 711-12, and an L2P fragment (#3) 711-13 as a set of L2P fragments corresponding to the LBA range #1.

[0179] The L2P table 71 includes an L2P fragment (#0) 711-20, an L2P fragment (#1) 711-21, an L2P fragment (#2) 711-22, and an L2P fragment (#3) 711-23 as a set of L2P fragments corresponding to the LBA range #2.

[0180] Furthermore, the L2P table 71 includes an L2P fragment (#0) 711-n0, an L2P fragment (#1) 711-n1, an L2P fragment (#2) 711-n2, and an L2P fragment (#3) 711-n3 as a set of L2P fragments corresponding to the LBA range #n.

[0181] The shortcut table 710 includes the same number of pointers as the total number of L2P fragments included in the L2P table 71. Each of these pointers indicates the memory address of the memory area in the DRAM 7 where the L2P fragment corresponding to that pointer is stored.

[0182] The L2P table 62 of the NAND memory 6 holds information used to back up the address translation information of each table area of ​​the L2P table 71. In a case where time-staggered duplication is performed for each table area, the L2P table 62 is stored in 2×(n+1) L2P flash blocks that correspond to the LBA ranges #0 to #n (i.e., table areas T0 to Tn) in a one-to-two relationship. The L2P flash blocks (#00) 62-00 and (#01) 62-01 are blocks that correspond to the LBA range #0. The L2P flash blocks (#10) 62-10 and (#11) 62-11 are blocks that correspond to the LBA range #1. The L2P flash blocks (#20) 62-20 and (#21) 62-21 are blocks that correspond to the LBA range #2. Furthermore, L2P flash blocks (#n0) 62-n0 and (#n1) 62-n1 are blocks corresponding to the LBA range #n.

[0183] 6 shows a case where two L2P flash blocks are assigned to one LBA range, that is, the LBA range and the L2P flash block correspond to each other in a one-to-two relationship, but in a case where time-staggered duplication is not performed, only one L2P flash block may be assigned to one LBA range. In this case, the LBA range and the L2P flash block correspond to each other in a one-to-one relationship. When the LBA range and the L2P flash block correspond to each other in a one-to-one relationship, N pieces of address translation information of one table area are backed up by one L2P flash block.

[0184] The address translation information / update log storage process for each of the table areas T0, T1, T2 to Tn in the case where the LBA range and the L2P flash block correspond in a one-to-one relationship will be described below.

[0185] (Address conversion information / update log saving process for table area T0) The address translation information / update log saving process for table area T0 will be described. When L2P flash block (#00) 62-00 is allocated to table area T0, the controller 5 writes, for example, L2P fragment (#1) 711-01, L2P fragment (#2) 711-02, and L2P fragment (#3) 711-03 to page P0 of L2P flash block (#00) 62-00.

[0186] After this, the controller 5 acquires the L2P fragment (#0) 711-00 from the table area T0. Then, the controller 5 waits until the amount of update logs accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of update logs accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#0) 711-00 and the update log (update log +0) stored in the log buffer 72-0 to page P1 of the L2P flash block (#00) 62-00. When the update log (update log +0) stored in the log buffer 72-0 is written to page P1, the log buffer 72-0 becomes free and does not contain any unsaved update logs. The L2P fragment (#0) 711-00 has already been acquired from the table area T0 before the update logs accumulated in the log buffer 72-0 are written to page P1. Therefore, the update log +0 indicates the update contents for all of L2P fragment (#0) 711-00 to L2P fragment (#3) 711-03 that were updated after L2P fragment (#0) 711-00 was acquired. For example, if the physical address associated with LBAi of the predetermined number of LBAs corresponding to L2P fragment (#0) 711-00 is updated from PBA10 to PBA20, and the physical address associated with LBAj of the predetermined number of logical addresses corresponding to L2P fragment (#1) 711-01 is updated from PBA30 to PBA40, the update log +0 includes a log that is update information indicating that PBA20 is associated with LBAi, and a log that is update information indicating that PBA40 is associated with LBAj.

[0187] After writing the L2P fragment (#0) 711-00 and the update log +0 to page P1 of the L2P flash block (#00) 62-00, the controller 5 acquires the L2P fragment (#1) 711-01 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#1) 711-01 and the update log (update log +1) stored in the log buffer 72-0 to page P2 of the L2P flash block (#00) 62-00. The L2P fragment (#1) 711-01 has already been acquired from the table area T0 before writing the update log accumulated in the log buffer 72-0 to page P2. Therefore, the update log +1 indicates the update contents for all L2P fragments in the table area T0 that were updated after the L2P fragment (#1) 711-01 was acquired.

[0188] After writing the L2P fragment (#1) 711-01 and the update log +1 to page P2 of the L2P flash block (#00) 62-00, the controller 5 acquires the L2P fragment (#2) 711-02 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#2) 711-02 and the update log (update log +2) stored in the log buffer 72-0 to page P3 of the L2P flash block 62-0. The L2P fragment (#2) 711-02 has already been acquired from the table area T0 before writing the update log accumulated in the log buffer 72-0 to page P3. Therefore, the update log +2 indicates the update contents for all L2P fragments in the table area T0 that were updated after the L2P fragment (#2) 711-02 was acquired.

[0189] After writing the L2P fragment (#2) 711-02 and the update log +2 to page P3 of the L2P flash block (#00) 62-00, the controller 5 acquires the L2P fragment (#3) 711-03 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#3) 711-03 and the update log (update log +3) stored in the log buffer 72-0 to page P4 of the L2P flash block (#00) 62-00. The L2P fragment (#3) 711-03 has already been acquired from the table area T0 before writing the update log accumulated in the log buffer 72-0 to page P4. Therefore, the update log +3 indicates the update contents for all L2P fragments in the table area T0 that were updated after the L2P fragment (#3) 711-03 was acquired.

[0190] After writing the L2P fragment (#3) 711-03 and the update log +3 to page P4 of the L2P flash block (#00) 62-00, the controller 5 acquires the L2P fragment (#0) 711-00 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#0) 711-00 and the update log (update log +4) stored in the log buffer 72-0 to page P5 of the L2P flash block (#00) 62-00. The L2P fragment (#0) 711-00 has already been acquired from the table area T0 before writing the update log accumulated in the log buffer 72-0 to page P5. Therefore, the update log +4 indicates the update contents for all L2P fragments in the table area T0 that were updated after the L2P fragment (#0) 711-00 was acquired.

[0191] After writing the L2P fragment (#0) 711-00 and update log +4 to page P5 of the L2P flash block (#00) 62-00, the controller 5 obtains the L2P fragment (#1) 711-01 from the table area T0. Then, the controller 5 waits until the amount of update logs newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold value.

[0192] Here, it is assumed that a first unexpected power loss occurs. The timing at which the first unexpected power loss occurs is referred to as the first timing.

[0193] The controller 5 judges whether or not a new unsaved update log that has not yet been saved in the L2P flash block (#00) 62-00 is stored in the log buffer 72-0. If a new unsaved update log that has not yet been saved in the L2P flash block (#00) 62-00 is stored in the log buffer 72-0, the controller 5 writes the acquired L2P fragment (#1) 711-01 and the update log (update log+5) stored in the log buffer 72-0 to page P6 of the L2P flash block (#00) 62-00. Then, the controller 5 writes a lost LBA list corresponding to the LBA range #0 to page P7 of the L2P flash block (#00) 62-00. The lost LBA list corresponding to the LBA range #0 is a list of LBAs corresponding to write data that has been lost due to an unexpected power loss among the write data that should be written to the LBA range #0.

[0194] In this way, the controller 5 writes the L2P fragment and the update log to the L2P flash block (#00) 62-00 according to the amount of the update log accumulated in the log buffer 72-0. Furthermore, when an unexpected power loss occurs, the controller 5 writes the update log and the L2P fragment to the L2P flash block (#00) 62-00 regardless of the amount of the update log accumulated in the log buffer 72-0. This makes it possible to prevent the update log accumulated in the log buffer 72-0 from being lost. Furthermore, when an unexpected power loss occurs, the controller 5 writes the lost LBA list to the L2P flash block (#00) 62-00. This makes it possible for the controller 5 to record, in the L2P flash block (#00) 62-00, each of the LBAs of the write data that was lost due to the unexpected power loss among the write data that was to be written to the LBA range #0 without completing writing to the NAND memory 6. When performing the graceful shutdown process, the controller 5 may wait until the amount of update logs stored in the log buffer 72-0 reaches a threshold, or may write the update logs and the L2P fragments to the L2P flash block (#00) 62-00 when the amount of update logs stored in the log buffer 72-0 reaches the threshold. If the amount of update logs stored in the log buffer 72-0 does not reach the threshold even after a predetermined time has elapsed since the reception of the power cutoff advance notice, the controller 5 may write the update logs and the L2P fragments to the L2P flash block (#00) 62-00 regardless of the amount of update logs stored in the log buffer 72-0. In addition, in the graceful shutdown process, the process of writing the lost LBA list corresponding to the LBA range #0 to the page P7 of the L2P flash block (#00) 62-00 is not performed.

[0195] When the power to the SSD is restored, the SSD3 starts operating again. The timing at which the SSD3 starts operating again after the first unexpected power loss is referred to as the second timing.

[0196] After the power to the SSD3 is restored and the SSD3 starts operating again, the controller 5 acquires the L2P fragment (#2) 711-02 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#2) 711-02 and the update log (update log+6) stored in the log buffer 72-0 to page P8 of the L2P flash block (#00) 62-00.

[0197] After writing the L2P fragment (#2) 711-02 and the update log +6 to page P8 of the L2P flash block (#00) 62-00, the controller 5 acquires the L2P fragment (#3) 711-03 from the table area T0. The controller 5 then waits until the amount of update logs newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of update logs newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#3) 711-03 and the update log (update log +7) stored in the log buffer 72-0 to page P9 of the L2P flash block (#00) 62-00.

[0198] After writing the L2P fragment (#3) 711-03 and the update log+7 to page P9 of the L2P flash block (#00) 62-00, the controller 5 obtains the L2P fragment (#0) 711-00 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold value.

[0199] Here, it is assumed that a second unexpected power loss occurs. The timing at which the second unexpected power loss occurs is referred to as the third timing.

[0200] The controller 5 judges whether or not a new update log that has not yet been saved in the L2P flash block (#00) 62-00 is stored in the log buffer 72-0. If a new update log that has not yet been saved in the L2P flash block (#00) 62-00 is stored in the log buffer 72-0, the controller 5 writes the acquired L2P fragment (#0) 711-00 and the update log (update log+8) stored in the log buffer 72-0 to page P10 of the L2P flash block (#00) 62-00. Then, the controller 5 writes a lost LBA list corresponding to the LBA range #0 to page P11 of the L2P flash block (#00) 62-00.

[0201] When power to the SSD is restored, SSD3 starts working again. The timing at which SSD3 starts working again after the second unexpected power loss is called the fourth timing.

[0202] After the power to the SSD3 is restored and the SSD3 starts operating again, the controller 5 acquires the L2P fragment (#1) 711-01 from the table area T0. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-0 corresponding to the LBA range #0 reaches the threshold, the controller 5 writes the acquired L2P fragment (#1) 711-01 and the update log (update log+9) stored in the log buffer 72-0 to page P12 of the L2P flash block (#00) 62-00.

[0203] Then, similar to the operation described above, the controller 5 writes the L2P fragment (#2) 711-02 and the update log (update log +10) to page P13 of the L2P flash block (#00) 62-00. Then, the controller 5 writes the L2P fragment (#3) 711-03 and the update log (update log +11) to page P14 of the L2P flash block (#00) 62-00.

[0204] Next, the address translation information / update log storage process for the table areas T1, T2 to Tn, which is executed in parallel with the address translation information / update log storage process for the table area T0, will be described in order.

[0205] (Address conversion information / update log saving process for table area T1) First, the address translation information / update log saving process for table area T1 will be described. When L2P flash block (#10) 62-10 is allocated to table area T1, the controller 5 writes L2P fragment (#1) 711-11, L2P fragment (#2) 711-12, and L2P fragment (#3) 711-13 to page P0 of L2P flash block (#10) 62-10.

[0206] After that, the controller 5 acquires the L2P fragment (#0) 711-10 from the table area T1. Then, the controller 5 waits until the amount of update logs accumulated in the log buffer 72-1 corresponding to the LBA range #1 reaches a threshold. When the amount of update logs accumulated in the log buffer 72-1 corresponding to the LBA range #1 reaches the threshold, the controller 5 writes the acquired L2P fragment (#0) 711-10 and the update log (update log+0) stored in the log buffer 72-1 to page P1 of the L2P flash block (#10) 62-10.

[0207] After writing the L2P fragment (#0) 711-10 and the update log +0 to page P1 of the L2P flash block (#10) 62-10, the controller 5 obtains the L2P fragment (#1) 711-11 from the table area T1. The controller 5 waits until the amount of update logs accumulated in the log buffer 72-1 corresponding to the LBA range #1 reaches a threshold. When the amount of update logs accumulated in the log buffer 72-1 reaches the threshold, the controller 5 writes the obtained L2P fragment (#1) 711-11 and the update log (update log +1) stored in the log buffer 72-1 to page P2 of the L2P flash block (#10) 62-10. If the amount by which the address translation information in table area T1 is updated is less than the amount by which the address translation information in table area T0 is updated, the number of L2P fragment-update log pairs written to L2P flash block (#10) 62-10 will be less than the number of L2P fragment-update log pairs written to L2P flash block (#00) 62-00.

[0208] If a first unexpected power loss occurs at the first timing described above after writing the L2P fragment (#1) 711-11 and update log +1 to page P2 of the L2P flash block (#10) 62-10, and if no new update log that has not been saved in the L2P flash block (#10) 62-10 is stored in the log buffer 72-1 at the time this first unexpected power loss occurs, the controller 5 writes a lost LBA list corresponding to LBA range #1 to page P3 of the L2P flash block (#10) 62-10.

[0209] After the power to the SSD 3 is restored and the SSD 3 starts operating again at the second timing described above, the controller 5 acquires the L2P fragment (#2) 711-12 from the table area T1. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-1 corresponding to the LBA range #1 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-1 corresponding to the LBA range #1 reaches the threshold, the controller 5 writes the acquired L2P fragment (#2) 711-12 and the update log (update log+2) stored in the log buffer 72-1 to page P4 of the L2P flash block (#10) 62-10.

[0210] Then, similar to the above operations, the controller 5 writes the L2P fragment (#3) 711-13 and the update log +3 to page P5 of the L2P flash block (#10) 62-10. Then, the controller 5 writes the L2P fragment (#0) 711-10 and the update log +4 to page P6 of the L2P flash block (#10) 62-10.

[0211] Here, if a second unexpected power loss occurs at the third timing described above, the controller 5 writes the lost LBA list corresponding to LBA range #1 to page P7 of the L2P flash block (#10) 62-10. Note that if writing of all write data to be written to LBA range #1 has been completed, there is no lost LBA list corresponding to LBA range #1. The process of writing the lost LBA list to page P7 of the L2P flash block (#10) 62-10 is not executed.

[0212] (Address conversion information / update log saving process for table area T2) Next, the address translation information / update log saving process for table area T2 will be described. When L2P flash block (#20) 62-20 is allocated to table area T2, the controller 5 writes L2P fragment (#1) 711-21, L2P fragment (#2) 711-22, and L2P fragment (#3) 711-23 to page P0 of L2P flash block (#20) 62-20.

[0213] After that, the controller 5 obtains the L2P fragment (#0) 711-20 from the table area T2. Then, the controller 5 waits until the amount of update logs accumulated in the log buffer 72-2 corresponding to the LBA range #2 reaches a threshold. When the amount of update logs accumulated in the log buffer 72-2 corresponding to the LBA range #2 reaches the threshold, the controller 5 writes the obtained L2P fragment (#0) 711-20 and the update log (update log+0) stored in the log buffer 72-2 to page P1 of the L2P flash block (#20) 62-20.

[0214] After writing the L2P fragment (#0) 711-20 and the update log +0 to page P1 of the L2P flash block (#20) 62-20, the controller 5 obtains the L2P fragment (#1) 711-21 from the table area T2. The controller 5 waits until the amount of update logs accumulated in the log buffer 72-2 corresponding to the LBA range #2 reaches a threshold. When the amount of update logs accumulated in the log buffer 72-2 reaches the threshold, the controller 5 writes the obtained L2P fragment (#1) 711-21 and the update log (update log +1) stored in the log buffer 72-2 to page P2 of the L2P flash block (#20) 62-20.

[0215] If a first unexpected power loss occurs at the first timing described above after writing the L2P fragment (#1) 711-21 and update log +1 to page P2 of the L2P flash block (#20) 62-20, and if the update log that has not been saved in the L2P flash block (#20) 62-20 is not stored in the log buffer 72-2 when the first unexpected power loss occurs, the controller 5 writes a lost LBA list corresponding to LBA range #2 to page P3 of the L2P flash block (#20) 62-20.

[0216] After the power to the SSD3 is restored and the SSD3 starts operating again at the second timing described above, the controller 5 acquires the L2P fragment (#2) 711-22 from the table area T2. Then, the controller 5 waits until the amount of the update log newly accumulated in the log buffer 72-2 corresponding to the LBA range #2 reaches a threshold. When the amount of the update log newly accumulated in the log buffer 72-2 corresponding to the LBA range #2 reaches the threshold, the controller 5 writes the acquired L2P fragment (#2) 711-22 and the update log (update log+2) stored in the log buffer 72-2 to page P4 of the L2P flash block (#20) 62-20.

[0217] Then, similar to the above operations, the controller 5 writes the L2P fragment (#3) 711-23 and the update log +3 to page P5 of the L2P flash block (#20) 62-20. Then, the controller 5 writes the L2P fragment (#0) 711-20 and the update log +4 to page P6 of the L2P flash block (#20) 62-20.

[0218] If a second unexpected power loss occurs at the third timing described above after writing the L2P fragment (#0) 711-20 and update log +4 to page P6 of the L2P flash block (#20) 62-20, and if the update log that has not been saved in the L2P flash block (#20) 62-20 is not stored in the log buffer 72-2 when the second unexpected power loss occurs, the controller 5 writes a lost LBA list corresponding to LBA range #2 to page P7 of the L2P flash block (#20) 62-20.

[0219] After power to SSD 3 is restored and SSD 3 starts operating again at the fourth timing described above, the controller 5 writes L2P fragment (#1) 711-21 and update log +5 to page P8 of L2P flash block (#20) 62-20 in the same manner as the above operations. Then, the controller 5 writes L2P fragment (#2) 711-22 and update log +6 to page P9 of L2P flash block (#20) 62-20. Then, the controller 5 writes L2P fragment (#3) 711-23 and update log +7 to page P10 of L2P flash block (#20) 62-20.

[0220] (Address conversion information / update log saving process for table area Tn) Next, the address translation information / update log saving process for table area Tn will be described. When L2P flash block (#n0) 62-n0 is allocated to table area Tn, the controller 5 writes, for example, L2P fragment (#1) 711-n1, L2P fragment (#2) 711-n2, and L2P fragment (#3) 711-n3 to page P0 of L2P flash block (#n0) 62-n0.

[0221] After this, the controller 5 performs a process of writing L2P fragment (#0) 711-n0 and update log +0 to page P1 of the L2P flash block (#n0) 62-n0, a process of writing L2P fragment (#1) 711-n1 and update log +1 to page P2 of the L2P flash block (#n0) 62-n0, and a process of writing L2P fragment (#2) 711-n2 and update log +2 to page P3 of the L2P flash block (#n0) 62-n0, in the same manner as the address translation information / update log storage process for the table areas T0 to T2. The L2P flash block (#n0) 62-n0 executes the following processes: a process of writing L2P fragment (#3) 711-n3 and update log +3 to page P4 of the L2P flash block (#n0) 62-n0; a process of writing L2P fragment (#0) 711-n0 and update log +4 to page P5 of the L2P flash block (#n0) 62-n0; and a process of writing L2P fragment (#1) 711-n1 and update log +5 to page P6 of the L2P flash block (#n0) 62-n0.

[0222] If a first unexpected power loss occurs at the first timing described above after writing L2P fragment (#1) 711-n1 and update log +5 to page P6 of L2P flash block (#n0) 62-n0, and if the update log that has not been saved in L2P flash block (#n0) 62-n0 is not stored in the log buffer 72-n when the first unexpected power loss occurs, the controller 5 writes a lost LBA list corresponding to LBA range #n to page P7 of L2P flash block (#n0) 62-n0.

[0223] After power to SSD3 is restored and SSD3 starts operating again at the second timing described above, the controller 5 writes L2P fragment (#2) 711-n2 and update log +6 to page P8 of L2P flash block (#n0) 62-n0.

[0224] If a second unexpected power loss occurs at the third timing described above after writing L2P fragment (#2) 711-n2 and update log +6 to page P8 of L2P flash block (#n0) 62-n0, and if the update log that has not been saved in L2P flash block (#n0) 62-n0 is not stored in the log buffer 72-n when the second unexpected power loss occurs, the controller 5 writes a lost LBA list corresponding to LBA range #n to page P9 of L2P flash block (#n0) 62-n0.

[0225] As described above, the process of saving the address translation information / update log for each of the table areas T0, T1, T2 to Tn is executed.

[0226] Next, a description will be given of a plurality of LBA ranges obtained by dividing the logical address space (LBA space) of the SSD 3. Fig. 7 is a diagram showing a configuration example showing the relationship between a plurality of LBA ranges and a plurality of table areas of the L2P table 71 in the memory system according to the embodiment.

[0227] Here, the LBA space of SSD3 is made up of 1000×(n+1) LBAs from LBA0 to LBA1000n+999. The LBA space is divided into n+1 LBA ranges. Each LBA range contains the same number of LBAs. One LBA range is made up of, for example, 1000 consecutive LBAs.

[0228] LBA range #0 consists of 1000 LBAs from LBA0 to LBA999. LBA range #1 consists of 1000 LBAs from LBA1000 to LBA1999. LBA range #2 consists of 1000 LBAs from LBA2000 to LBA2999. Furthermore, LBA range #n consists of 1000 LBAs from LBA1000n to LBA1000n+999.

[0229] The L2P table 71 includes a plurality of L2P fragments 711-00 to 711-n3. Each of the L2P fragments 711-00 to 711-n3 includes, as address conversion information, information indicating 250 physical addresses corresponding respectively to 250 consecutive LBAs.

[0230] L2P fragment (#0) 711-00 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #0, from LBA0 to LBA249. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#0) 711-00 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA0 to LBA249.

[0231] L2P fragment (#1) 711-01 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #0, from LBA 250 to LBA 499. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#1) 711-01 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA 250 to LBA 499.

[0232] L2P fragment (#2) 711-02 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #0, from LBA500 to LBA749. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#2) 711-02 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA500 to LBA749.

[0233] L2P fragment (#3) 711-03 includes information indicating 250 physical addresses corresponding to the 250 LBAs from LBA 750 to LBA 999 included in LBA range #0. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#3) 711-03 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA 750 to LBA 999.

[0234] L2P fragment (#0) 711-10 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #1, from LBA1000 to LBA1249. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#0) 711-10 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA1000 to LBA1249.

[0235] L2P fragment (#1) 711-11 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #1, from LBA1250 to LBA1499. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#1) 711-11 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA1250 to LBA1499.

[0236] L2P fragment (#2) 711-12 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #1, from LBA1500 to LBA1749. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#2) 711-12 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA1500 to LBA1749.

[0237] L2P fragment (#3) 711-13 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #1, from LBA1750 to LBA1999. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#3) 711-13 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA1750 to LBA1999.

[0238] L2P fragment (#0) 711-20 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #2, from LBA2000 to LBA2249. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#0) 711-20 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA2000 to LBA2249.

[0239] L2P fragment (#1) 711-21 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #2, from LBA2250 to LBA2499. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#1) 711-21 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA2250 to LBA2499.

[0240] L2P fragment (#2) 711-22 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #2, from LBA2500 to LBA2749. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#2) 711-22 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs, from LBA2500 to LBA2749.

[0241] L2P fragment (#3) 711-23 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #2, from LBA 2750 to LBA 2999. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#3) 711-23 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA 2750 to LBA 2999.

[0242] Furthermore, L2P fragment (#0) 711-n0 includes information indicating 250 physical addresses corresponding to the 250 LBAs from LBA1000n to LBA1000n+249 included in LBA range #n. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#0) 711-n0 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA1000n to LBA1000n+249.

[0243] L2P fragment (#1) 711-n1 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #n, from LBA250 to LBA1000n+499. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#1) 711-n1 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA1000n+250 to LBA1000n+499.

[0244] L2P fragment (#2) 711-n2 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #n, from LBA1000n+500 to LBA1000n+749. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#2) 711-n2 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA1000n+500 to LBA1000n+749.

[0245] L2P fragment (#3) 711-n3 includes information indicating 250 physical addresses corresponding to the 250 LBAs included in LBA range #n, from LBA1000n+750 to LBA1000n+999. A memory address indicating the storage area of ​​DRAM 7 in which L2P fragment (#3) 711-n3 is stored is stored in an entry in shortcut table 710 that corresponds to the LBAs from LBA1000n+750 to LBA1000n+999.

[0246] Next, an L2P fragment will be described. Fig. 8 is a diagram showing an example of an L2P fragment used in the memory system according to the embodiment. In Fig. 8, an L2P fragment (#0) 711-00 is shown.

[0247] The L2P fragment (#0) 711-00 includes information indicating each of the 250 physical addresses corresponding to the 250 LBAs from LBA0 to LBA249.

[0248] The first entry of L2P fragment (#0) 711-00 holds information indicating PBA10, which is a physical address corresponding to LBA0. The second entry of L2P fragment (#0) 711-00 holds information indicating PBA11, which is a physical address corresponding to LBA1. The third entry of L2P fragment (#0) 711-00 holds information indicating PBA20, which is a physical address corresponding to LBA2. The fourth entry of L2P fragment (#0) 711-00 holds information indicating PBA50, which is a physical address corresponding to LBA3. The fifth entry of L2P fragment (#0) 711-00 holds information indicating PBA30, which is a physical address corresponding to LBA4. Similarly, the 250th entry of L2P fragment (#0) 711-00 holds information indicating PBA300, which is a physical address corresponding to LBA249. In addition, in the entry associated with the LBA corresponding to the lost data, a value indicating that an error (an uncorrectable data error) has occurred is stored instead of the PBA.

[0249] Next, the relationship between the table area, the log buffer, and the L2P table will be described. Fig. 9 is a diagram showing a configuration example showing the relationship between a plurality of LBA ranges, a plurality of table areas of the L2P table 71, a plurality of log buffers, and a plurality of L2P flash blocks in a memory system according to an embodiment.

[0250] The log buffer 72-0 and the L2P flash block (#00) 62-00 and L2P flash block (#01) 62-01 of the L2P table 62 are associated with the table area T0 (L2P fragments (#0 to #3) 711-00 to 711-03) of the L2P table 71 corresponding to the LBA range #0.

[0251] A log buffer 72-1 and L2P flash blocks (#10) 62-10 and (#11) 62-11 of the L2P table 62 correspond to table area T1 (L2P fragments (#0 to #3) 711-10 to 711-13) of the L2P table 71 corresponding to the LBA range #1.

[0252] A log buffer 72-2 and L2P flash blocks (#20) 62-20 and (#21) 62-21 of the L2P table 62 are associated with table area T2 (L2P fragments (#0 to #3) 711-20 to 711-23) of the L2P table 71 corresponding to the LBA range #2.

[0253] Furthermore, a table area Tn (L2P fragments (#0 to #3) 711-n0 to 711-n3) of the L2P table 71 corresponding to the LBA range #n is associated with a log buffer 72-n, and L2P flash blocks (#n0) 62-n0 and (#n1) 62-n1 of the L2P table 62.

[0254] When address translation information relating to a certain LBA included in the LBA range #0 is updated, the controller 5 stores an update log relating to this update in the log buffer 72-0. When the amount of update logs accumulated in the log buffer 72-0 reaches a threshold, the controller 5 writes one of the L2P fragments L2P fragment (#0) 711-00, L2P fragment (#1) 711-01, L2P fragment (#2) 711-02, and L2P fragment (#3) 711-03 of the L2P table 71 and the update log accumulated in the log buffer 72-0 to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01. In this case, in the time difference duplication process, different fragments are written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01. Furthermore, the same update log is written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01. When the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01 becomes full, the controller 5 selects a new flash block in the NAND memory 6 and assigns the selected flash block as the L2P flash block corresponding to the LBA range #0. Then, the controller 5 writes the next L2P fragment and the update log to the new L2P flash block. Then, when the pair of L2P fragment (#0) 711-00 and the update log, the pair of L2P fragment (#1) 711-01 and the update log, the pair of L2P fragment (#2) 711-02 and the update log, and the pair of L2P fragment (#3) 711-03 and the update log are aligned in the new L2P flash block, the controller 5 deallocates the original L2P flash block (#00) 62-00 or the original L2P flash block (#01) 62-01 for LBA range #0.This is because it is possible to reconstruct L2P fragment (#0) 711-00, L2P fragment (#1) 711-01, L2P fragment (#2) 711-02, and L2P fragment (#3) 711-03 in table area T0 of L2P table 71 using only the information stored in the new L2P flash block.

[0255] When address translation information for a certain LBA included in LBA range #1 is updated, the controller 5 stores an update log for this update in the log buffer 72-1. When the amount of update logs accumulated in the log buffer 72-1 reaches a threshold, the controller 5 writes one L2P fragment out of L2P fragment (#0) 711-10, L2P fragment (#1) 711-11, L2P fragment (#2) 711-12, and L2P fragment (#3) 711-13 of the L2P table 71 and the update log accumulated in the log buffer 72-1 to the L2P flash block (#10) 62-10 and the L2P flash block (#11) 62-11. When the L2P flash block (#10) 62-10 or the L2P flash block (#11) 62-11 becomes full, the controller 5 selects a new flash block in the NAND memory 6 and assigns the selected flash block as the L2P flash block corresponding to the LBA range #1. Then, the controller 5 writes the next L2P fragment and the update log to the new L2P flash block. Then, when the pair of the L2P fragment (#0) 711-10 and the update log, the pair of the L2P fragment (#1) 711-11 and the update log, the pair of the L2P fragment (#2) 711-12 and the update log, and the pair of the L2P fragment (#3) 711-13 and the update log are all aligned in the new L2P flash block, the controller 5 releases the assignment of the original L2P flash block (#10) 62-10 or the original L2P flash block (#11) 62-11 to the LBA range #1.

[0256] When address translation information related to an LBA included in LBA range #2 is updated, the controller 5 stores an update log related to this update in the log buffer 72-2. When the amount of update logs accumulated in the log buffer 72-2 reaches a threshold, the controller 5 writes one of the L2P fragments (#0) 711-20, L2P fragment (#1) 711-21, L2P fragment (#2) 711-22, and L2P fragment (#3) 711-23 of the L2P table 71 and the update log accumulated in the log buffer 72-2 to the L2P flash block (#20) 62-20 and the L2P flash block (#21) 62-21. When the L2P flash block (#20) 62-20 or the L2P flash block (#21) 62-21 becomes full, the controller 5 selects a new flash block in the NAND memory 6 and allocates the selected flash block as the L2P flash block corresponding to the LBA range #2. Then, the controller 5 writes the next L2P fragment and the update log to the new L2P flash block. Then, when the pair of the L2P fragment (#0) 711-20 and the update log, the pair of the L2P fragment (#1) 711-21 and the update log, the pair of the L2P fragment (#2) 711-22 and the update log, and the pair of the L2P fragment (#3) 711-23 and the update log are all aligned in the new L2P flash block, the controller 5 releases the allocation of the original L2P flash block (#20) 62-20 or the original L2P flash block (#21) 62-21 to the LBA range #2.

[0257] Furthermore, when address translation information related to an LBA included in the LBA range #n is updated, the controller 5 stores an update log related to this update in the log buffer 72-n. When the amount of update logs accumulated in the log buffer 72-n reaches a threshold, the controller 5 writes one L2P fragment out of the L2P fragment (#0) 711-n0, the L2P fragment (#1) 711-n1, the L2P fragment (#2) 711-n2, and the L2P fragment (#3) 711-n3 of the L2P table 71 and the update log accumulated in the log buffer 72-n to the L2P flash block (#n0) 62-n0 and the L2P flash block (#n1) 62-n1. When the L2P flash block (#n0) 62-n0 or the L2P flash block (#n1) 62-n1 becomes full, the controller 5 selects a new flash block in the NAND memory 6 and assigns the selected flash block as the L2P flash block corresponding to the LBA range #n. Then, the controller 5 writes the next L2P fragment and the update log to the new L2P flash block. Then, when the pair of the L2P fragment (#0) 711-n0 and the update log, the pair of the L2P fragment (#1) 711-n1 and the update log, the pair of the L2P fragment (#2) 711-n2 and the update log, and the pair of the L2P fragment (#3) 711-n3 and the update log are all aligned in the new L2P flash block, the controller 5 releases the assignment of the original L2P flash block (#n0) 62-n0 or the original L2P flash block (#n1) 62-n1 to the LBA range #n.

[0258] Next, a first example of the update log will be described. Fig. 10 is a diagram showing a first example of the update log in the memory system according to the embodiment.

[0259] 10 includes, for example, m+1 logs (log #0, log #1, ..., log #m). In the following, it is assumed that the update log +x is an update log written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 corresponding to the LBA range #0.

[0260] Each of log #0, log #1, ..., log #m includes, for each piece of data to be written to LBA range #0, an identifier indicating the format of the log, an LBA corresponding to this data, and a PBA indicating the storage location in NAND memory 6 determined as the write destination for this data.

[0261] For example, the identifier included in log #1 indicates that log #1 is in a first format including a pair of an LBA and a PBA as shown in FIG. 10. A log of the first format is one of the first type logs. The first type log is a log that is stored in the log buffer 72-0 when the table area T0 of the L2P table 71 is updated by writing data to the NAND memory 6 based on a write command received from the host 2. The first type log includes an LBA corresponding to the data written to the NAND memory 6, and a PBA indicating the storage location in the NAND memory 6 determined as the write destination of this data.

[0262] For example, the LBA contained in log #1 indicates the logical address of certain data to be written in LBA range #0. The LBA contained in log #1 is only the lower bit portion of the bit length required to represent each LBA. The LBA contained in any log, log #0, log #1, ..., log #m, belongs to LBA range #0. Therefore, the upper bit portion that identifies LBA range #0 is not necessary.

[0263] The PBA included in log #1 indicates a physical address newly mapped to the LBA included in log #1. In other words, the PBA included in log #1 is a physical address indicating a storage location in the NAND memory 6 determined as a write destination of the data corresponding to the LBA included in log #1.

[0264] Next, a second example of the update log will be described below. Fig. 11 is a diagram showing a second example of the update log in the memory system according to the embodiment.

[0265] An update log +x in FIG. 11 is an update log written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 corresponding to the LBA range #0.

[0266] Each of the logs #0, #1, ..., #m includes, for each data to be written in the LBA range #0, an identifier indicating the type of the log, an LBA corresponding to the data, a PBA indicating a storage location in the NAND memory 6 determined as a write destination of the data, and information indicating the length (data size) of the data. The identifier included in the log #1 indicates that the log #1 is in the second format including an LBA, a PBA, and a length as shown in FIG. 11. The log of the second format is also one of the logs of the first type. The length (data size) is expressed by, for example, the number of sectors. In a case where data having a size equivalent to a plurality of sectors is written relatively frequently to the NAND memory 6, by using the format of the update log+x in FIG. 11, it becomes possible to hold address translation information corresponding to more LBAs in one update log+x than when the format of the update log+x in FIG. 10 is used.

[0267] Next, a third example of the update log will be described below with reference to Fig. 12, which is a diagram showing a third example of the update log in the memory system according to the embodiment.

[0268] An update log +x in FIG. 12 is an update log written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 corresponding to the LBA range #0.

[0269] Here, it is assumed that the log #1 among the multiple logs included in the update log +x is a second type log. The second type log is a log stored in the log buffer 72-0 when the table area T0 of the L2P table 71 is updated by copying data from a source storage location to a destination storage location in the NAND memory 6 in garbage collection.

[0270] At this time, log #1 includes an identifier indicating the format of this log, an LBA corresponding to the copied data, a new physical address (new PBA) indicating the destination storage location, information indicating the length (data size) of this data, and an old physical address (old PBA) indicating the source storage location.

[0271] The identifier included in log #1 indicates that log #1 is in a third format that includes at least an LBA, a new PBA, and an old PBA, as shown in Fig. 12. A log in the third format is treated as a log of the second type.

[0272] The LBAs included in log #1 indicate the logical addresses of the data copied in LBA range #0. The LBAs included in log #1, like the LBAs included in the logs of the first format, are only the lower bit portion of the bit length required to represent each LBA. All the LBAs included in any of the logs, log #0, log #1, ..., log #m, belong to LBA range #0. Therefore, the upper bit portion that identifies LBA range #0 is not necessary.

[0273] The new PBA included in log #1 indicates a physical address newly mapped to the LBA included in log #1. In other words, the new PBA included in log #1 is a physical address indicating a storage location in the NAND memory 6 determined as a copy destination of the data corresponding to the LBA included in log #1.

[0274] The length of the data contained in log #1 is represented, for example, by the number of sectors.

[0275] The old PBA included in log #1 indicates the physical address that was mapped to the LBA included in log #1 before it was mapped to the new PBA. In other words, the old PBA included in log #1 is a physical address that indicates the storage location of the copy source in the NAND memory 6 where the data corresponding to the LBA included in log #1 was stored.

[0276] Next, a process for saving the lost LBA list will be described with reference to Fig. 13, which is a diagram showing an example of a lost LBA list saving process of the memory system according to the embodiment.

[0277] When an unexpected power loss occurs in the SSD 3, the power supply circuit 8 supplies the power stored in the capacitor 81 to each component of the SSD 3. The power supply circuit 8 also notifies the controller 5 that an unexpected power loss has occurred. The controller 5 starts a process of saving the PLP target data stored in the DRAM 7 to the NAND memory 6. The PLP target data includes, for example, the L2P table 71 and a list of LBAs corresponding to write data that has not been completely written to the NAND memory 6. The lost LBA list saving unit 525 obtains a list of LBAs corresponding to write data that has not been completely written to the NAND memory 6 from the LBA list 74 of the DRAM 7. The write data that has not been completely written is data that is lost due to an unexpected power loss.

[0278] The lost LBA list storage unit 525 generates lost LBA lists #0 to #n corresponding to the LBA ranges #0 to #n, respectively, based on the acquired list of LBAs. Lost LBA list #0 is a list indicating a collection of LBAs corresponding to write data lost due to unexpected power loss among write data to be written to LBA range #0. Lost LBA list #1 is a list indicating a collection of LBAs corresponding to write data lost due to unexpected power loss among write data to be written to LBA range #1. Lost LBA list #n is a list indicating a collection of LBAs corresponding to write data lost due to unexpected power loss among write data to be written to LBA range #n. In this case, the lost LBA list storage unit 525 stores, among the LBAs stored in the LBA list 74, the set of LBAs belonging to LBA range #0 in lost LBA list #0, the set of LBAs belonging to LBA range #1 in lost LBA list #1, the set of LBAs belonging to LBA range #2 in lost LBA list #2, and the set of LBAs belonging to LBA range #n in lost LBA list #n.

[0279] The lost LBA list storage unit 525 refers to the LBA range / block management table 75 to identify the L2P flash blocks (#00) 62-00 to (#n1) 62-n1 that are assigned to the LBA ranges #0 to #n, respectively. The lost LBA list storage unit 525 writes lost LBA list #0 to L2P flash block (#00) 62-00 and L2P flash block (#01) 62-01, writes lost LBA list #1 to L2P flash block (#10) 62-10 and L2P flash block (#11) 62-11, writes lost LBA list #2 to L2P flash block (#20) 62-20 and L2P flash block (#21) 62-21, and writes lost LBA list #n to L2P flash block (#n0) 62-n0 and L2P flash block (#n1) 62-n1.

[0280] As a result, the controller 5 uses the power stored in the capacitor 81 to store the lost LBA lists #0 to #n in the L2P flash block (#00) 62-00 to the L2P flash block (#n1) 62-n1, respectively.

[0281] Next, a configuration example of two L2P flash blocks associated with each table area included in the L2P table 71 will be described. Fig. 14 is a diagram showing a first configuration example for duplicating backup data of an L2P table used in a memory system according to an embodiment. In Fig. 14, a first L2P flash block (Primary L2P FB) (#00) 62-00 and a second L2P flash block (Secondary L2P FB) (#01) 62-01 are associated with a table area T0 of the L2P table 62.

[0282] In Fig. 14(a), pages P0 to P7 of the first L2P flash block (#00) 62-00 are shown, and in Fig. 14(b), pages P0 to P7 of the second L2P flash block (#01) 62-01 are shown.

[0283] Page P0 of the first L2P flash block (#00) 62-00 stores L2P fragment #0 and update log +0. Furthermore, page P0 of the second L2P flash block (#01) 62-01 stores L2P fragments #0 to #2.

[0284] The controller 5 retrieves L2P fragments #1 and #3 from the DRAM 7. After retrieving L2P fragments #1 and #3, the controller 5 retrieves from the log buffer 72-0 an update log +1 indicating the update contents of all L2P fragments in table area T0 that were updated. The controller 5 writes L2P fragment #1 and the update log +1 to page P1 of the first L2P flash block (#00) 62-00, and writes L2P fragment #3 and the update log +1 to page P1 of the second L2P flash block (#01) 62-01.

[0285] Next, the controller 5 retrieves L2P fragments #0 and #2 from the DRAM 7. It retrieves from the log buffer 72-0 an update log +2 indicating the update contents of all L2P fragments in table area T0 that were updated after retrieving L2P fragments #0 and #2. The controller 5 writes L2P fragment #2 and the update log +2 to page P2 of the first L2P flash block (#00) 62-00, and writes L2P fragment #0 and the update log +2 to page P2 of the second L2P flash block (#01) 62-01.

[0286] Next, the controller 5 retrieves L2P fragments #1 and #3 from the DRAM 7. It retrieves from the log buffer 72-0 an update log +3 indicating the update contents of all L2P fragments in table area T0 that were updated after retrieving L2P fragments #1 and #3. The controller 5 writes L2P fragment #3 and the update log +3 to page P3 of the first L2P flash block (#00) 62-00, and writes L2P fragment #1 and the update log +3 to page P3 of the second L2P flash block (#01) 62-01.

[0287] Next, the controller 5 retrieves L2P fragments #0 and #2 from the DRAM 7. It retrieves from the log buffer 72-0 an update log +4 indicating the update contents of all L2P fragments in table area T0 that were updated after retrieving L2P fragments #0 and #2. The controller 5 writes L2P fragment #0 and the update log +4 to page P4 of the first L2P flash block (#00) 62-00, and writes L2P fragment #2 and the update log +4 to page P4 of the second L2P flash block (#01) 62-01.

[0288] Next, the controller 5 retrieves L2P fragments #1 and #3 from the DRAM 7. It retrieves from the log buffer 72-0 an update log +5 indicating the update contents of all L2P fragments in table area T0 that were updated after retrieving L2P fragments #1 and #3. The controller 5 writes L2P fragment #1 and the update log +5 to page P5 of the first L2P flash block (#00) 62-00, and writes L2P fragment #3 and the update log +5 to page P5 of the second L2P flash block (#01) 62-01.

[0289] Next, the controller 5 retrieves L2P fragments #0 and #2 from the DRAM 7. It retrieves from the log buffer 72-0 an update log +6 indicating the update contents of all L2P fragments in table area T0 that were updated after retrieving L2P fragments #0 and #2. The controller 5 writes L2P fragment #2 and the update log +6 to page P6 of the first L2P flash block (#00) 62-00, and writes L2P fragment #0 and the update log +6 to page P6 of the second L2P flash block (#01) 62-01.

[0290] Next, the controller 5 retrieves L2P fragments #1 and #3 from the DRAM 7. It retrieves from the log buffer 72-0 an update log +7 indicating the update contents of all L2P fragments in table area T0 that were updated after retrieving L2P fragments #1 and #3. The controller 5 writes L2P fragment #3 and the update log +7 to page P7 of the first L2P flash block (#00) 62-00, and writes L2P fragment #1 and the update log +7 to page P7 of the second L2P flash block (#01) 62-01.

[0291] In this way, the controller 5 writes the L2P fragments and the update log to each page of the first L2P flash block (#00) 62-00 in the order of L2P fragments #0, #1, #2, and #3. When writing the L2P fragments and the update log to the first L2P flash block (#00) 62-00, the controller 5 also writes the L2P fragments and the update log to the second L2P flash block (#01) 62-01. At this time, since the number of L2P fragments included in the table area T0 is four, the L2P fragment written to the second L2P flash block is the L2P fragment two fragments behind or two fragments before the L2P fragment written to the first L2P flash block. Also, the update log written to the second L2P flash block (#01) 62-01 is the same information as the update log written to the first L2P flash block (#00) 62-00.

[0292] Next, assume that an unexpected power loss occurs after writing the L2P fragments and the update log+7 to page P7 of the first L2P flash block (#00) 62-00 and the second L2P flash block (#01) 62-01 in Fig. 14, and that unwritten data exists in the NAND memory 6. Fig. 15 is a diagram showing a second configuration example for duplicating backup data in the memory system according to the embodiment. Fig. 15 shows two L2P flash blocks corresponding to one table area.

[0293] If an unexpected power loss occurs after writing L2P fragment #3 and update log +7 to page P7 of the first L2P flash block (#00) 62-00 and writing L2P fragment #1 and update log +7 to page P7 of the second L2P flash block (#01) 62-01, the controller 5 writes a lost LBA list to page P8 of the first L2P flash block (#00) 62-00 and page P8 of the second L2P flash block (#01) 62-01. The lost LBA list is a list of LBAs corresponding to write data that has not been completely written to the NAND memory 6 when the unexpected power loss occurs.

[0294] Next, the address translation information / update log saving process for the table area T0 corresponding to the LBA range #0 and the L2P table rebuild process for the table area T0 will be described with reference to FIGS.

[0295] (Address conversion information / update log saving process) First, an example of the address translation information / update log storage process will be described below mainly with reference to FIG. 16 (first example), FIG. 18 (second example), and FIG. 21 (flowchart).

[0296] (Address conversion information / update log saving process (first example)) FIG. 16 is a diagram illustrating a first example of a process for saving address translation information in the memory system according to the embodiment.

[0297] (Step 1) The L2P table management unit 524 of the controller 5 acquires the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 from the table area T0 of the L2P table 71. As the address translation information (L2P fragments (#0 to #3) 711-00 to 03) in the table area T0 of the L2P table 71 is updated, the amount of update logs accumulated in the log buffer 72-0 increases. Thereafter, when the amount of update logs accumulated in the log buffer 72-0 reaches a threshold, the L2P table management unit 524 writes the acquired L2P fragment #0 and the update log +0 accumulated in the log buffer 72-0 to page P1 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #2 and the update log +0 to page P1 of the L2P flash block (#01) 62-01. The process of acquiring the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 from the table area T0 of the L2P table 71 is performed, for example, before a new update log is stored in the log buffer 72-0. The timing of acquiring the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 may be any time before a new update log is stored in the log buffer 72-0 and before the amount of update logs accumulated in the log buffer 72-0 reaches a threshold value. In the following, it is assumed that the next L2P fragment is acquired from the table area T0 of the L2P table 71 immediately after a certain update log is written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01.

[0298] (Step 2) Next, the L2P table management unit 524 acquires the L2P fragment (#1) 711-01 and the L2P fragment (#3) 711-03 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 again reaching the threshold, the L2P table management unit 524 writes the acquired L2P fragment #1 and the update log +1 accumulated in the log buffer 72-0 to page P2 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #3 and the update log +1 to page P2 of the L2P flash block (#01) 62-01.

[0299] (Step 3) Next, the L2P table management unit 524 acquires the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 again reaching the threshold, the L2P table management unit 524 writes the acquired L2P fragment #2 and the update log +2 accumulated in the log buffer 72-0 to page P3 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #0 and the update log +2 to page P3 of the L2P flash block (#01) 62-01.

[0300] (Step 4) Next, the L2P table management unit 524 acquires the L2P fragment (#1) 711-01 and the L2P fragment (#3) 711-03 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 again reaching the threshold value, the L2P table management unit 524 writes the acquired L2P fragment #3 and the update log +3 accumulated in the log buffer 72-0 to page P4 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #1 and the update log +3 to page P4 of the L2P flash block (#01) 62-01.

[0301] (Step 5) Next, the L2P table management unit 524 acquires the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 again reaching the threshold, the L2P table management unit 524 writes the acquired L2P fragment #0 and the update log +4 accumulated in the log buffer 72-0 to page P5 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #2 and the update log +4 to page P5 of the L2P flash block (#01) 62-01.

[0302] (Step 6) Next, the L2P table management unit 524 acquires the L2P fragment (#1) 711-01 and the L2P fragment (#3) 711-03 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 again reaching the threshold value, the L2P table management unit 524 writes the acquired L2P fragment #1 and the update log +5 accumulated in the log buffer 72-0 to page P6 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #3 and the update log +5 to page P6 of the L2P flash block (#01) 62-01.

[0303] (Step 7) Next, the L2P table management unit 524 acquires the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 again reaching the threshold, the L2P table management unit 524 writes the acquired L2P fragment #2 and the update log +6 accumulated in the log buffer 72-0 to page P7 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #0 and the update log +6 to the L2P flash block (#01) 62-01.

[0304] (Step 8) Next, the L2P table management unit 524 acquires the L2P fragment (#1) 711-01 and the L2P fragment (#3) 711-03 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 reaching a threshold value, the L2P table management unit 524 writes the acquired L2P fragment #3 and the update log +7 accumulated in the log buffer 72-0 to page P8 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #1 and the update log +7 to page P8 of the L2P flash block (#01) 62-01.

[0305] (Step 9) Next, the L2P table management unit 524 acquires the L2P fragment (#0) 711-00 and the L2P fragment (#2) 711-02 from the table area T0 of the L2P table 71. Thereafter, in response to the amount of update logs accumulated in the log buffer 72-0 reaching a threshold value, the L2P table management unit 524 writes the acquired L2P fragment #0 and the update log +8 accumulated in the log buffer 72-0 to page P9 of the L2P flash block (#00) 62-00, and writes the acquired L2P fragment #2 and the update log +8 to page P9 of the L2P flash block (#01) 62-01.

[0306] In this way, the controller 5 periodically executes the process of writing the update log stored in the log buffer 72-0 and the L2P fragment obtained from the L2P table 71 to two L2P flash blocks.

[0307] (L2P table rebuild process) Next, examples of the L2P table rebuild process will be described below with reference to FIG. 17 (first example), FIG. 19 (second example), FIG. 20 (third example), and FIG. 22 (flowchart).

[0308] (L2P table rebuild process (first example)) FIG. 17 is a diagram illustrating a first example of an L2P table rebuild process in the memory system according to the embodiment.

[0309] 17, it is assumed that in step 9 in FIG. 16, L2P fragment #0 and update log +8 are written to page P9 of L2P flash block (#00) 62-00 and L2P fragment #2 and update log +8 are written to L2P flash block (#01) 62-01, and then SSD 3 executes a shutdown (graceful shutdown) process in response to a power cutoff advance notice from host 2, and then power to SSD 3 is restored, and the update log that should be stored in NAND memory 6 was not present in log buffer 72-0 when the power cutoff advance notice was received.

[0310] (Step 10) When power to SSD 3 is restored, the L2P table rebuild processor 526 reads L2P fragment #0 and update log +8 from page 9 of the L2P flash block (#00) 62-00, and reads L2P fragment #2 and update log +8 from page P9 of the L2P flash block (#01) 62-01. Both pages 9 are pages to which data was last written in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01.

[0311] (Step 11) The L2P table rebuild processor 526 writes the L2P fragment #0 and L2P fragment #2 read in step 10 to the DRAM 7. By the processing of steps 10 and 11, the latest L2P fragment #0 of the multiple L2P fragments #0 stored in the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01 is copied from the L2P flash block (#00) 62-00 to the DRAM 7. Also, by the processing of steps 10 and 11, the latest L2P fragment #2 of the multiple L2P fragments #2 stored in the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01 is copied from the L2P flash block (#01) 62-01 to the DRAM 7.

[0312] (Step 12) The L2P table rebuild processor 526 reads the L2P fragment #3, the L2P fragment #1, and the update log+7 from page 8 of the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01.

[0313] (Step 13) The L2P table rebuild processor 526 writes the L2P fragments #1 and #3 read in step 12 to the DRAM 7. By the processing of steps 12 and 13, the latest L2P fragment #3 of the multiple L2P fragments #3 stored in the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01 is copied from the L2P flash block (#00) 62-00 to the DRAM 7. Also, by the processing of steps 12 and 13, the latest L2P fragment #1 of the multiple L2P fragments #1 stored in the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01 is copied from the L2P flash block (#00) 62-00 to the DRAM 7.

[0314] (Step 14) The L2P table rebuild processor 526 reflects the contents of the update log +7 read in step 12 only to the L2P fragment #1 and L2P fragment #3 copied to the DRAM 7. That is, the contents of the update log (here, the update log +7) that is paired with the L2P fragment #1 and L2P fragment #3 and stored in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 are reflected only to the L2P fragment #1 and L2P fragment #3 copied to the DRAM 7. Each of the L2P fragments #2 and #0 stored in the L2P flash block 62-0 is newer information than the update log +7. The contents of the update log +7 have already been reflected in the L2P fragments #2 and #0 copied to the DRAM 7. For this reason, the execution of the process of reflecting the contents of the update log +7 in the L2P fragments #2 and #0 is omitted. This makes it possible to reduce the time required for the L2P table rebuild process.

[0315] (Step 15) The L2P table rebuild processing unit 526 reflects the contents of the update log+8 read in step 10 in the L2P fragments #0 to #3 copied to the DRAM 7. That is, the contents of the update log (here, the update log+8) that is paired with the L2P fragments #2 and #0 and that is stored in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 are reflected in the L2P fragments #0 to #3 copied to the DRAM 7.

[0316] In this way, the controller 5 reads out the L2P fragments and update logs stored in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01, and reconstructs the latest address translation information (L2P fragments #0 to #3) of the table area T0 of the L2P table 71. The controller 5 can also reconstruct the entire table area T0 by reading out two pages of L2P fragments and update logs from each of the two L2P flash blocks.

[0317] Next, an example of the address translation information / update log saving process and the lost LBA list saving process will be described.

[0318] (Address conversion information / update log saving process (second example)) 18 is a diagram showing a second example of the address translation information / update log saving process of the memory system according to the embodiment. Here, it is assumed that an unexpected power loss occurs in the SSD 3.

[0319] The controller 5 executes operations similar to those from step 1 to step 8 in Fig. 16. Here, it is assumed that after the write operation in step 8 is completed, update logs that have not been saved in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 are stored in the log buffer 72-0 when an unexpected power loss occurs.

[0320] (Step 9) If an unexpected power loss occurs after the write operation of the L2P fragment and the update log in step 8 is completed, the L2P table management unit 524 judges whether or not update logs that are not saved in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 are stored in the log buffer 72-0. If update logs that are not saved in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 are stored in the log buffer 72-0, the controller 5 writes the lost LBA list to page P9 of the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01. The lost LBA list written to page P9 of the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 is a list of LBAs belonging to the LBA range #0 among the LBAs corresponding to write data that has not been completely written to the NAND memory 6. The lost LBA lists written to the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 have the same contents.

[0321] (L2P table rebuild process (second example)) Next, a second example of the L2P table rebuild process will be described below. Fig. 19 is a diagram showing a second example of the L2P table rebuild process in the memory system according to the embodiment.

[0322] In FIG. 19, it is assumed that power to SSD3 is restored after step 9 in FIG.

[0323] (Step 10) The L2P table rebuild processor 526 reads the lost LBA list from page 9 of the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01. Page 9 is the page to which data was last written in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01. The L2P table rebuild processor 526 may read the lost LBA list from either the L2P flash block (#00) 62-00 or the L2P flash block (#01) 62-01, or may read the lost LBA list from both the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01.

[0324] (Step 11) The L2P table rebuild processor 526 reads L2P fragment #3 and update log +7 from page 8 of the L2P flash block (#00) 62-00, and reads L2P fragment #1 and update log +7 from page 8 of the L2P flash block (#01) 62-01.

[0325] (Step 12) The L2P table rebuild processor 526 writes the L2P fragment #1 and L2P fragment #3 read in step 11 to the DRAM 7. By the processes of steps 11 and 12, the latest L2P fragment #3 of the multiple L2P fragments #3 stored in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 is copied from the L2P flash block (#00) 62-00 to the DRAM 7, and the latest L2P fragment #1 of the multiple L2P fragments #1 stored in the L2P flash block (#00) 62-00 and the L2P flash block (#01) 62-01 is copied from the L2P flash block (#01) 62-01 to the DRAM 7.

[0326] (Step 13) The L2P table rebuild processor 526 reads L2P fragment #2 and update log +6 from page 7 of the L2P flash block (#00) 62-00, and reads L2P fragment #0 and update log +6 from page 7 of the L2P flash block (#01) 62-01.

[0327] (Step 14) The L2P table rebuild processor 526 writes the L2P fragment #0 and L2P fragment #2 read in step 13 to the DRAM 7. By the processes of steps 13 and 14, the latest L2P fragment #2 of the multiple L2P fragments #2 stored in the L2P flash block (#00) 62-00 is copied from the L2P flash block (#00) 62-00 to the DRAM 7, and the latest L2P fragment #0 of the multiple L2P fragments #0 stored in the L2P flash block (#01) 62-01 is copied from the L2P flash block (#01) 62-01 to the DRAM 7.

[0328] (Step 15) The L2P table rebuild processor 526 reflects the contents of the update log +6 read in step 13 in the L2P fragment #0 and L2P fragment #2 copied to the DRAM 7.

[0329] (Step 16) The L2P table rebuild processing unit 526 reflects the contents of the update log+7 read in step 11 in L2P fragment #0, L2P fragment #1, L2P fragment #2, and L2P fragment #3 copied to the DRAM 7. Through the above processing, the address translation information (L2P fragments #0 to #3) of the table area T0 immediately before the unexpected power loss occurs is reconstructed in the DRAM 7.

[0330] (Step 17) Based on the lost LBA list read in step 10, the L2P table rebuild processing unit 526 updates the address conversion information (L2P fragments #0 to #3) in the table area T0 so that a value indicating an error (uncorrectable data error) is associated with each LBA corresponding to the lost write data.

[0331] In this way, when the controller 5 reads the lost LBA list when restoring the table area T0, the controller 5 changes the address translation information stored in the table area T0 restored using the L2P fragment written to the L2P flash block before the lost LBA list was written to a value indicating an error. This allows the controller 5 to notify the host 2 of an error even when a read command specifying an LBA corresponding to write data lost in the past is received from the host 2. This makes it possible to prevent a malfunction in which data different from the data corresponding to the LBA specified by the read command is erroneously returned to the host 2.

[0332] (L2P table rebuild process (third example)) Next, a third example of the L2P table rebuild process when data cannot be read from one of the two L2P flash blocks associated with one table area will be described. Fig. 20 is a diagram showing a third example of the L2P table rebuild process executed in the memory system according to the embodiment. The L2P table rebuild process in Fig. 20 can be executed after the address conversion information / update log save process described in Fig. 16.

[0333] 20 illustrates a case in which, after L2P fragment #0, L2P fragment #2, and update log+8 are written to page P9 of L2P flash block (#00) 62-00 and L2P flash block (#01) 62-01 in step 9 in FIG. 16, SSD 3 executes a shutdown (graceful shutdown) process in response to a power shutdown advance notice from host 2, and then power to SSD 3 is restored, the update log that should be saved in NAND memory 6 was not present in log buffer 72-0 when the power shutdown advance notice was received, and data cannot be read from L2P flash block (#01) 62-01 when power to SSD 3 is restored.

[0334] (Step 10) When power to the SSD 3 is restored, the L2P table rebuild processor 526 reads the L2P fragment #0 and the update log +8 from page 9 of the L2P flash block (#00) 62-00. Page 9 is the page to which data was last written in the L2P flash block (#00) 62-00.

[0335] (Step 11) The L2P table rebuild processing unit 526 writes the L2P fragment #0 read in step 10 to the DRAM 7. By the processing of steps 10 and 11, the latest L2P fragment #0 of the multiple L2P fragments #0 stored in the L2P flash block (#00) 62-00 is copied from the L2P flash block (#00) 62-00 to the DRAM 7.

[0336] (Step 12) The L2P table rebuild processor 526 reads the L2P fragment #3 and update log+7 from page 8 of the L2P flash block (#00) 62-00.

[0337] (Step 13) The L2P table rebuild processor 526 writes the L2P fragment #3 read in step 12 to the DRAM 7. By the processes of steps 12 and 13, the latest L2P fragment #3 of the multiple L2P fragments #3 stored in the L2P flash block (#00) 62-00 is copied from the L2P flash block (#00) 62-00 to the DRAM 7.

[0338] (Step 14) The L2P table rebuild processor 526 reads the L2P fragment #2 and the update log +6 from page 7 of the L2P flash block (#00) 62-00.

[0339] (Step 15) The L2P table rebuild processor 526 writes the L2P fragment #2 read in step 14 to the DRAM 7. By the processes of steps 14 and 15, the latest L2P fragment #2 of the multiple L2P fragments #2 stored in the L2P flash block (#00) 62-00 is copied from the L2P flash block (#00) 62-00 to the DRAM 7.

[0340] (Step 16) The L2P table rebuild processor 526 reads the L2P fragment #1 and update log +5 from page 6 of the L2P flash block (#00) 62-00.

[0341] (Step 17) The L2P table rebuild processor 526 writes the L2P fragment #1 read in step 16 to the DRAM 7. By the processes of steps 16 and 17, the latest L2P fragment #1 of the multiple L2P fragments #1 stored in the L2P flash block (#00) 62-00 is copied from the L2P flash block (#00) 62-00 to the DRAM 7.

[0342] (Step 18) The L2P table rebuild processor 526 reflects the contents of the update log +5 read in step 16 only in the L2P fragment (#1) 711-01 copied to the DRAM 7. That is, the contents of the update log (here, update log +5) that is paired with the L2P fragment #1 and stored in the L2P flash block (#00) 62-00 are reflected only in the L2P fragment (#1) 711-01 copied to the DRAM 7. Each of the L2P fragments #2, #3, and #0 stored in the L2P flash block (#00) 62-00 is newer information than the update log +5. The contents of the update log +5 have already been reflected in the L2P fragments (#2) 711-02, (#3) 711-03, and (#0) 711-00 copied to the DRAM 7. Therefore, the process of reflecting the contents of update log+5 in L2P fragments (#2) 711-02, (#3) 711-03, and (#0) 711-00 is omitted, thereby making it possible to reduce the time required for the L2P rebuild process.

[0343] (Step 19) The L2P table rebuild processor 526 reflects the contents of the update log +6 read in step 14 only to the L2P fragment (#1) 711-01 and the L2P fragment (#2) 711-02 copied to the DRAM 7. That is, the contents of the update log (here, the update log +6) that is paired with the L2P fragment #2 and stored in the L2P flash block (#00) 62-00 are reflected only to the L2P fragments (#1) 711-01 and (#2) 711-02 copied to the DRAM 7. Each of the L2P fragments #3 and #0 stored in the L2P flash block (#00) 62-00 is newer information than the update log +6. The contents of the update log +6 have already been reflected in the L2P fragments (#3) 711-03 and (#0) 711-00 copied to the DRAM 7. For this reason, the process of reflecting the contents of update log +6 in L2P fragments (#3) 711-03 and (#0) 711-00 is omitted.

[0344] (Step 20) The L2P table rebuild processor 526 reflects the contents of the update log +7 read in step 12 only to the L2P fragment (#1) 711-01, the L2P fragment (#2) 711-02, and the L2P fragment (#3) 711-03 copied to the DRAM 7. That is, the contents of the update log (here, the update log +7) that is paired with the L2P fragment #3 and stored in the L2P flash block (#00) 62-00 is reflected only to the L2P fragments (#1) 711-01, (#2) 711-02, and (#3) 711-03 copied to the DRAM 7. The L2P fragment #0 stored in the L2P flash block (#00) 62-00 is newer information than the update log +7. The contents of the update log +7 have already been reflected in the L2P fragment (#0) 711-00 copied to the DRAM 7. Therefore, the process of reflecting the contents of update log+7 in L2P fragment (#2) 711-02 is omitted.

[0345] (Step 21) The L2P table rebuild processing unit 526 reflects the contents of the update log +8 read in step 10 in the L2P fragment (#0) 711-00, the L2P fragment (#1) 711-01, the L2P fragment (#2) 711-02, and the L2P fragment (#3) 711-03 copied to the DRAM 7.

[0346] In this way, when the controller 5 is unable to read data from one of the two L2P flash blocks associated with the table area T0, the controller 5 reconstructs the table area T0 of the L2P table 71 by reading data from the other L2P flash block. That is, when the controller 5 is unable to read data from the L2P flash block (#01) 62-01, the controller 5 reconstructs the latest address translation information (L2P fragments #0 to #3) of the table area T0 of the L2P table 71 by reading only the L2P fragments and update logs stored in the L2P flash block (#00) 62-00. Also, when the controller 5 is unable to read data from the L2P flash block (#00) 62-00, the controller 5 reconstructs the table area T0 by using the L2P fragments and update logs stored in the L2P flash block (#01) 62-01.

[0347] (Address conversion information / update log saving process (flowchart)) Next, a procedure of the address conversion information / update log storage process when performing the time difference duplication process will be described. Fig. 21 is a flowchart showing the procedure of the address conversion information / update log storage process executed in the memory system according to the embodiment.

[0348] First, the controller 5 judges whether or not the amount of update logs accumulated in the log buffer corresponding to any one of the LBA ranges has reached a threshold value (step S101).

[0349] If the amount of update logs accumulated in the log buffer corresponding to any of the LBA ranges has not reached the threshold value (No in step S101), the controller 5 waits until the amount of update logs reaches the threshold value.

[0350] When the amount of update logs accumulated in the log buffer corresponding to any LBA range reaches a threshold value (Yes in step S101), the controller 5 selects an L2P fragment (first fragment) to be written to a first block associated with the LBA range from among a plurality of L2P fragments included in the table area of ​​the L2P table 71 corresponding to the LBA range (step S102). The L2P fragment selected in S102 may be acquired in advance from the table area of ​​the L2P table 71. In addition, the first fragment selected in S102 is, for example, an L2P fragment following the latest L2P fragment written to the first block in the first sequence. When the latest L2P fragment written to the first block is the last L2P fragment in the first sequence, the first L2P fragment in the first sequence is selected as the first fragment.

[0351] The controller 5 selects, from among the multiple L2P fragments included in this table area, a fragment that is N / 2 fragments behind or before the first fragment selected in S102 as an L2P fragment (second fragment) to be written to the second block (step S103), where N is the number of L2P fragments included in the table area corresponding to this LBA range.

[0352] The controller 5 obtains the first fragment selected in S102 and the second fragment selected in S103 from the L2P table 71 in the DRAM 7 (step S104).

[0353] The controller 5 acquires the update log from the log buffer 72 (step S105).

[0354] The controller 5 writes the first fragment obtained in S104 and the update log obtained in S105 to the first block, and writes the first fragment obtained in S104 and the update log obtained in S105 to the second block (step S106).

[0355] Thereafter, the controller 5 may next obtain from the table area of ​​the L2P table 71 the L2P fragment to be written to the first block or the second block.

[0356] (L2P table rebuild process (flowchart)) Next, the procedure of the L2P table rebuild process will be described. Fig. 22 is a flowchart showing the procedure of the L2P table rebuild process executed in the memory system according to the embodiment. Here, in Fig. 22, a case will be described where the L2P table 71 is composed of one table area.

[0357] First, the controller 5 determines whether or not the power to the SSD 3 has been restored (step S201).

[0358] If the power to the SSD 3 has not been restored (No in step S201), the controller 5 waits.

[0359] When the power to the SSD 3 is restored (Yes in step S201), the controller 5 notifies the host 2 that the SSD 3 is in a ready state (step S202).

[0360] The controller 5 determines whether or not data can be read from both of the two L2P flash blocks allocated to the table area of ​​the L2P table 71 (step S203).

[0361] If data can be read from both of the two L2P flash blocks (Yes in step S203), the controller 5 reads, from the first block of the two L2P flash blocks, the N / 2 L2P fragments last written to the first block and the update logs written together with each of the N / 2 L2P fragments (step S204). The update logs written together with each of the N / 2 L2P fragments are the update logs stored in the same page as the L2P fragments.

[0362] Then, the controller 5 reads, from the second block of the two L2P flash blocks, the N / 2 L2P fragments that were last written to the second block and the update logs that were written together with each of the N / 2 L2P fragments (step S205). The read process of S204 and the read process of S205 may be executed at the same timing.

[0363] If data cannot be read from either of the two L2P flash blocks (No in step S203), the controller 5 reads the N L2P fragments and the update logs written together with each of the N L2P fragments from a readable L2P flash block of the two L2P flash blocks (step S206). The update logs written together with each of the N L2P fragments are update logs stored in the same page as the L2P fragment.

[0364] The controller 5 executes a process of reconstructing the L2P table 71 on the DRAM 7 by using the L2P fragment and update log read in S204 and S205, or S206 (step S407).

[0365] When the L2P table 71 has multiple table areas, the controller 5 may select a specific table area and preferentially reconstruct it on the DRAM 7. After notifying the host 2 of the ready state in S202, the controller 5 may preferentially reconstruct a table area corresponding to an LBA range to which the logical address specified by the received I / O command belongs.

[0366] Next, a case will be described where the second type log described in Fig. 12 is used. Fig. 23 is a block diagram showing a configuration example showing update of the L2P table in garbage collection processing in the memory system according to the embodiment.

[0367] The garbage collection control unit 523 of the controller 5 starts garbage collection processing in response to the number of free blocks in the SSD 3 becoming equal to or less than a threshold value. Here, in the garbage collection processing, the garbage collection control unit 523 selects the block BLK10 of the NAND memory 6 as a copy source block. For example, the garbage collection control unit 523 selects a block having a low ratio of valid data as a copy source block from among a plurality of active blocks managed in the SSD 3. In addition, the garbage collection control unit 523 selects the block BLK100 from among the free blocks as a copy destination block. For example, the garbage collection control unit 523 selects a block in which the program / erase cycle progresses slowly from among a plurality of free blocks as a copy destination block.

[0368] In page P0 of block BLK10 selected as the copy source block, the storage locations specified by offsets +0 to +3 are indicated by physical addresses PBA(x) to PBA(x+3), respectively. Also, in page P1, the storage locations specified by offsets +0 to +3 are indicated by physical addresses PBA(x+4) to PBA(x+7), respectively.

[0369] The storage locations indicated by the physical addresses PBA(x) to PBA(x+3) store data D1 to D4, respectively. The data D1 to D4 correspond to the logical addresses LBA10 to LBA13, respectively. The storage locations indicated by the physical addresses PBA(x+4) to PBA(x+7) store data D5 to D8, respectively. The data D5 to D8 correspond to the logical addresses LBA20, 21, 40, and 41, respectively.

[0370] Here, among the data stored in block BLK10, only data D5 and data D7 are valid data. The garbage collection control unit 523 selects the storage location indicated by PBA(x+4) and the storage location indicated by PBA(x+6) as copy source storage locations.

[0371] The garbage collection control unit 523 writes the data stored in the source memory location to the destination block. Data D5 stored in the memory location indicated by PBA(x+4) is written to the memory location of page P0, offset +0 of block BLK100. As a result, the physical address indicating the memory location where the data corresponding to LBA20 is stored becomes PBA(z). Data D7 stored in the memory location indicated by PBA(x+6) is written to the memory location of page P0, offset +1 of block BLK100. As a result, the physical address indicating the memory location where the data corresponding to LBA40 is stored becomes PBA(z+1).

[0372] As a result of copying the data, mapping information of the logical address corresponding to the copied data is updated in the L2P table 71 on the DRAM 7. The mapping of LBA20 is updated from PBA(x+4) to PBA(z). Also, the mapping of LBA40 is updated from PBA(x+6) to PBA(z+1). As a result, the data stored in the memory locations indicated by PBA(x+4) and PBA(x+6) becomes invalid data.

[0373] In this way, in garbage collection, the mapping of the LBA is updated regardless of the write command received from the host 2. In updating the mapping in garbage collection, the controller 5 judges whether the PBA indicating the source storage location matches the PBA before the update. Then, only when the two PBAs match, the controller 5 updates the mapping information to the PBA indicating the destination storage location. This makes it possible to prevent the L2P table 71 from being updated from the mapping information indicating the storage location where the new data has been written to the mapping information indicating the storage location where the data has been copied by the garbage collection, when data writing based on a write command received from the host 2 occurs during garbage collection.

[0374] For this reason, the log stored in the log buffer 72 includes the physical address (old PBA) indicating the storage location of the copy source in the case of updating mapping information based on garbage collection.

[0375] First, a case will be described where data similar to that in Fig. 23 is copied. Fig. 24 is a block diagram showing a first example of a configuration showing the recording of a log in a garbage collection process in the memory system according to the embodiment.

[0376] 24, when the data copy by the garbage collection described in FIG 23 is executed, a new log is stored in the log buffer 72. In response to the data D5 being copied from the block BLK10 to the block BLK100, the controller 5 stores the first log in the log buffer 72.

[0377] The identifier of the first log indicates that this log is a log of the second type. For example, the identifier is a value indicating 1.

[0378] The LBA of the first log indicates LBA20, which is the logical address corresponding to the copied data.

[0379] The new PBA of the first log indicates PBA(z), which is a physical address indicating the storage location of the copy destination.

[0380] The length of the first log corresponds to the size of the copied data. For example, if the size of the corresponding data is the same as the size of one sector, the length is 1.

[0381] The old PBA of the first log indicates PBA(x+4), which is a physical address indicating the storage location of the copy source.

[0382] Then, the controller 5 stores a second log in the log buffer 72 in response to the data D7 being copied from block BLK10 to block BLK100.

[0383] The second log identifier indicates that this log is a second type log. For example, the identifier is a value indicating 1.

[0384] The LBA of the second log indicates LBA40, which is the logical address corresponding to the copied data.

[0385] The new PBA of the second log indicates PBA(z+1), which is a physical address indicating the storage location of the copy destination.

[0386] The length of the second log corresponds to the size of the copied data. For example, if the size of the corresponding data is the same as the size of one sector, the length is 1.

[0387] The old PBA of the second log indicates PBA(x+6), which is a physical address indicating the memory location of the copy source.

[0388] When the L2P table rebuild processing unit 526 of the controller 5 rebuilds the L2P table 71, if the update log read from the L2P flash block includes a second type log, the L2P table rebuild processing unit 526 obtains the PBA corresponding to the LBA included in this second type log from the L2P table 71 on the DRAM 7.

[0389] If the old PBA included in this second type log matches the PBA obtained from the L2P table 71, the L2P table rebuild processing unit 526 reflects the contents of this second type log in the L2P table 71 on the DRAM 7 so that the new PBA included in this second type log is associated with the LBA included in this second type log.

[0390] If the old PBA included in this second type log does not match the PBA obtained from the L2P table 71, the L2P table rebuild processor 526 does not reflect the contents of this second type log in the L2P table 71 on the DRAM 7. This is because, for example, the mapping of the logical addresses included in this second type log has been updated by a write operation based on a write command received from the host 2 during the copy operation corresponding to this second type log.

[0391] Next, a case where sequentially written data is copied will be described. Fig. 25 is a block diagram showing a second configuration example showing the recording of logs in garbage collection processing in the memory system according to the embodiment.

[0392] 25, it is assumed that the garbage collection control unit 523 of the controller 5 selects block BLK20 of the NAND memory 6 as the copy source block. In addition, the garbage collection control unit 523 selects block BLK200 of the free blocks as the copy destination block.

[0393] In page P0 of block BLK20 selected as the copy source block, the storage locations specified by offsets +0 to +3 are indicated by physical addresses PBA(v) to PBA(v+3), respectively. Also, in page P1, the storage locations specified by offsets +0 to +3 are indicated by physical addresses PBA(v+4) to PBA(v+7), respectively.

[0394] The storage locations indicated by the physical addresses PBA(v) to PBA(v+3) store data D11 to D14, respectively. The data D11 to D14 correspond to the logical addresses LBA30 to 33, respectively. The storage locations indicated by the physical addresses PBA(v+4) to PBA(v+7) store data D15 to D18, respectively. The data D15 to D18 correspond to the logical addresses LBA50 to 53, respectively. That is, the storage locations indicated by the physical addresses PBA(v) to PBA(v+3) store sequential data starting from LBA30. The storage locations indicated by the physical addresses PBA(v+4) to PBA(v+7) store sequential data starting from LBA50.

[0395] Here, of the data stored in block BLK20, only data D15 to D18 are valid data. Garbage collection control unit 523 selects each of the storage locations indicated by PBA(v+4) to PBA(v+7) as copy source storage locations.

[0396] The garbage collection control unit 523 writes the data stored in the source memory location to the destination block. Data D15-D18 stored in the memory locations indicated by PBA(v+4)-PBA(v+7), respectively, are written to memory locations at offsets +0-+3, page P0, of block BLK200, respectively. As a result, the physical addresses indicating the memory locations where the data corresponding to LBA50-LBA53, respectively, are stored become PBA(w)-PBA(w+3). Therefore, sequential data starting from LBA50 is stored in the memory locations indicated by PBA(w)-PBA(w+3), respectively.

[0397] 25, by copying the data, mapping information of the logical addresses corresponding to the copied data is updated in the L2P table 71 on the DRAM 7. The mappings of LBA50 to LBA53 are updated from PBA(v+4) to PBA(v+7) to PBA(w) to PBA(w+3), respectively. As a result, the data stored in the storage locations indicated by PBA(v+4) to PBA(v+7) becomes invalid data.

[0398] In response to the execution of this data copy, the controller 5 stores a log in the log buffer 72. At this time, since the LBAs corresponding to the respective copied data are consecutive, one log corresponding to the entire copied data is stored in the log buffer 72.

[0399] The identifier of the log indicates that this log is a log of the second type. For example, the identifier is a value indicating 1.

[0400] The LBA of the log indicates LBA50, which is the logical address corresponding to the first data of the copied sequential data.

[0401] The new PBA of the log indicates PBA(w), which is a physical address indicating the first storage location among multiple destination storage locations to which sequential data has been copied.

[0402] The log length corresponds to the size of the copied data. For example, if the total size of the copied sequential data is equal to the size of four sectors, then the length shows 4.

[0403] The old PBA of the log indicates PBA(v+4), which is a physical address indicating the first storage location among a plurality of source storage locations to which sequential data has been copied.

[0404] In this way, when data corresponding to each of consecutive LBAs is copied together during garbage collection, a log including the LBA, new PBA, old PBA corresponding to the first data of the copied data, and the size of the entire copied data is stored in log buffer 72.

[0405] When this log is read out when rebuilding the L2P table 71, the L2P table rebuild processor 526 acquires PBAs corresponding to each of the consecutive LBAs corresponding to this log from the L2P table 71. Then, the L2P table rebuild processor 526 identifies LBAs among the consecutive LBAs corresponding to this log that satisfy the condition that the corresponding old PBA matches the PBA acquired from the L2P table 71. The L2P table rebuild processor 526 reflects the contents of this log in the L2P table 71 on the DRAM 7 only for the identified LBAs so that each new PBA corresponding to the identified LBA is associated with the identified LBA.

[0406] For an LBA whose corresponding old PBA does not match the PBA obtained from the L2P table 71, the L2P table rebuild processor 526 does not reflect the contents of this log in the L2P table 71 on the DRAM 7.

[0407] Next, the log recording process will be described with reference to a flowchart shown in FIG 26, which is a flow chart showing the log recording process of the memory system according to the embodiment.

[0408] The controller 5 determines whether or not an update of the L2P table 71 on the DRAM 7 has occurred (step S301).

[0409] If no update of the L2P table 71 has occurred (No in S301), the controller 5 waits.

[0410] When an update of the L2P table 71 has occurred (Yes in S301), the controller 5 determines whether or not the update of the L2P table 71 determined in S301 has occurred due to garbage collection (step S302).

[0411] If the update of the L2P table 71 determined in S301 is due to something other than garbage collection (No in S302), the controller 5 stores a first type log including a write destination LBA and a write destination PBA in the log buffer 72 (step S303). An update of the L2P table 71 due to something other than garbage collection is, for example, an update of the L2P table 71 due to writing of data based on a write command received from the host 2. In this case, the first type log includes the LBA specified by the write command as the write destination LBA, and includes, as the write destination PBA, a PBA indicating the storage location in the NAND memory 6 where the data associated with the write command has been written. The first type log may further include an identifier indicating that it is the first type, and a length indicating the size of the data associated with the write command.

[0412] If the update of the L2P table 71 determined in S301 is due to garbage collection (Yes in S302), the controller 5 stores a second type log including the copy target LBA, the copy destination PBA, and the copy source PBA in the log buffer 72 (step S304). In this case, the second type log includes the LBA corresponding to the copied data as the copy target LBA, includes the PBA indicating the storage location where the copied data was written as the copy destination PBA, and includes the PBA indicating the original storage location where the copied data was stored as the copy source PBA. The second type log may further include an identifier indicating that it is the second type, and a length indicating the size of the copied data.

[0413] Next, an L2P table rebuild process in the case where the second type log may be used will be described below. Fig. 27 is a flowchart showing another procedure of the L2P table rebuild process in the memory system according to the embodiment.

[0414] First, the controller 5 determines whether or not the power to the SSD 3 has been restored (step S401).

[0415] If the power to the SSD 3 has not been restored (No in step S401), the controller 5 waits.

[0416] When the power to the SSD 3 is restored (Yes in step S401), the controller 5 notifies the host 2 that the SSD 3 is in a ready state (step S402).

[0417] The controller 5 determines whether or not data can be read from both of the two L2P flash blocks allocated to the table area of ​​the L2P table 71 (step S403).

[0418] If data can be read from both of the two L2P flash blocks (Yes in step S403), the controller 5 reads from the first block of the two L2P flash blocks the N / 2 L2P fragments last written to the first block and the update log written together with each of the N / 2 L2P fragments (step S404).

[0419] Then, the controller 5 reads, from the second block of the two L2P flash blocks, the N / 2 L2P fragments that were last written to the second block and the update logs that were written together with the N / 2 L2P fragments (step S405). The read process of S404 and the read process of S405 may be executed at the same timing.

[0420] If data cannot be read from either of the two L2P flash blocks (No in step S403), the controller 5 reads the N L2P fragments and the update logs written together with each of the N L2P fragments from the readable L2P flash block of the two L2P flash blocks (step S406).

[0421] The controller 5 determines whether or not the update logs read in S204 and S205, or S206, include a second type log (step S407).

[0422] If a second type log is included (Yes in S407), the controller 5 judges whether or not the old PBA included in this second type log matches the PBA currently mapped to the LBA included in this second type log (step S408). The PBA currently mapped to the LBA included in this second type log is the PBA associated with the LBA included in this second type log in the L2P table 71 on the DRAM 7 when judging whether or not to reflect the contents of this second type log.

[0423] If the old PBA included in this second type log does not match the PBA currently mapped to the LBA included in this second type log (No in S408), the controller 5 does not use this second type log (step S409).

[0424] Also, if the second type log is not included (No in S407), or if the old PBA included in the second type log matches the PBA currently mapped to the LBA included in this second type log (Yes in S408), the controller 5 uses this log (step S410). That is, the controller 5 reflects the contents of this log in the L2P table 71 on the DRAM 7.

[0425] Based on the results of S407 to S410, the controller 5 executes processing to reconstruct the L2P table 71 on the DRAM 7 by using the L2P fragment and update log read in S204 and S205, or S206 (step S411).

[0426] As described above, according to this embodiment, the controller 5 selects one L2P fragment to be written to a first L2P flash block from the N L2P fragments such that the N L2P fragments included in the table area of ​​the L2P table 71 are stored in the first order in the L2P flash block of the NAND memory 6, and selects, from the N L2P fragments, an L2P fragment that is N / 2 fragments behind or before the one L2P fragment to be written to the first L2P flash block as an L2P fragment to be written to a second L2P flash block. The controller 5 acquires the two selected L2P fragments from the table area of ​​the L2P table 71 on the DRAM 7. The controller 5 acquires from the log buffer 72 an update log indicating the update contents of all the L2P fragments in this table area that have been updated after acquiring the two L2P fragments. The controller 5 writes the acquired L2P fragment and the update log to the two L2P flash blocks.

[0427] In response to power being restored to the SSD 3 after the supply of power to the SSD 3 is cut off, the controller 5 reads the last written N / 2 L2P fragments and the update log from each of the two L2P flash blocks associated with the table area of ​​the L2P table 71. The controller 5 reconstructs the table area of ​​the L2P table 71 on the DRAM 7 using the N L2P fragments and the N / 2 update logs read from the two L2P flash blocks.

[0428] As a result, the number of update logs read by the controller 5 to reconstruct the table area of ​​the L2P table 71 is N / 2 less than when the update logs are read from one L2P flash block, so the controller 5 can reconstruct the L2P table 71 more quickly than when the number of L2P flash blocks allocated to a certain table area is one.

[0429] Furthermore, when the table area of ​​the L2P table 71 on the DRAM 7 is updated based on garbage collection, the controller 5 stores a second type log in the log buffer 72. The second type log includes an LBA corresponding to the copied data, a new PBA indicating the destination storage location, and an old PBA indicating the source storage location.

[0430] When reconstructing the L2P table 71, if the update log read from the L2P flash block includes a second type log, the controller 5 determines whether or not the PBA associated in the L2P table 71 with the LBA included in the second type log matches the old PBA included in the second type log. If the PBA associated in the L2P table 71 with the LBA included in the second type log matches the old PBA included in the second type log, the controller 5 reflects the contents of this second type log in the L2P table 71. If the PBA associated in the L2P table 71 with the LBA included in the second type log does not match the old PBA included in the second type log, the controller 5 does not reflect the contents of this second type log in the L2P table 71.

[0431] This allows the controller 5 to prevent the mapping of the copy target LBA from being overwritten by the mapping update in the copy operation by the garbage collection process when a write operation based on a write command received from the host 2 is executed during the copy operation in the garbage collection process. Therefore, the controller 5 can reconstruct the L2P table 71 more accurately.

[0432] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0433] 1. Information processing system 2. Host 3…SSD 4. Bus 5. Controller 6. Non-volatile memory 7…DRAM 8…Power circuit 20…Internal bus 21…Processor 22…Memory 50…Bus 51...Host interface 52…CPU 53…SRAM 54…DMAC 55…ECC processing circuit 56…DRAM interface 57...NAND interface 61...User data 62…L2P table 71…L2P table 72...Log buffer 73...Data buffer 74…LBA list 75...LBA range / block management table 81…Capacitor 521...Light control unit 522...Lead control section 523: Garbage collection control unit 524...L2P table management section 525…Lost LBA list storage section 526...L2P table rebuild processing unit

Claims

1. 1. A memory system connectable to a host, comprising: a non-volatile memory including a plurality of blocks; A volatile memory; a controller configured to manage a correspondence between each of the logical addresses included in a logical address space of the memory system and each of the physical addresses of the non-volatile memory by using a logical-physical address conversion table stored in the volatile memory, the logical-physical address conversion table including at least a first table area, the first table area holding N pieces of address conversion information respectively corresponding to N small logical address ranges, the N being an integer multiple of 2; The controller: (1) A process of selecting one piece of address conversion information to be written to a first block of the non-volatile memory from the N pieces of address conversion information so that the N pieces of address conversion information of the first table area are stored in a first order in the first block of the non-volatile memory, and selecting, from the N pieces of address conversion information, address conversion information that is N / 2 pieces behind or before the selected one piece of address conversion information as another piece of address conversion information to be written to a second block of the non-volatile memory; (2) a process of acquiring the selected one piece of address translation information and the selected other piece of address translation information from the first table area on the volatile memory; (3) a process of writing, to the first block, the one piece of acquired address translation information and an update log indicating update contents of all the address translation information in the first table area that has been updated after the acquisition of the one piece of address translation information and the other address translation information; (4) periodically executing a first process including a process of writing the acquired different address translation information and the update log to the second block; in response to power being restored to the memory system after power supply to the memory system is cut off, the memory system is configured to read, from the first block, the N / 2 pieces of address conversion information last written to the first block and the N / 2 update logs last written to the first block, and read, from the second block, the N / 2 pieces of address conversion information last written to the second block and the N / 2 update logs last written to the second block, and reconstruct the first table area of ​​the logical-physical address conversion table on the volatile memory based on the N / 2 pieces of address conversion information read from the first block, the N / 2 pieces of address conversion information read from the second block, and the N / 2 update logs read from either the first block or the second block. Memory system.

2. when the first table area of ​​the logical-physical address conversion table is updated by writing data to the non-volatile memory based on a write command received from the host, the update log includes a first type log including a logical address corresponding to the data and a physical address indicating a storage location in the non-volatile memory determined as a write destination of the data, when the first table area of ​​the logical-physical address conversion table is updated by copying data from a source memory location of the non-volatile memory to a destination memory location of the non-volatile memory executed in garbage collection for the non-volatile memory, the update log includes a second type log including a logical address corresponding to the copied data, a new physical address indicating the destination memory location, and an old physical address indicating the source memory location; The controller: When rebuilding the first table area, determining whether the N / 2 update logs read from either the first block or the second block include a log of the second type; and further configured to, when the N / 2 update logs include the second type log, obtain a physical address corresponding to the logical address included in the second type log from the first table area of ​​the logical-physical address conversion table on the volatile memory, and, when an old physical address included in the second type log matches the obtained physical address, reflect the content of the second type log in the first table area of ​​the logical-physical address conversion table on the volatile memory so that the new physical address included in the second type log is associated with the logical address included in the second type log, and, when the old physical address included in the second type log does not match the obtained physical address, not reflect the content of the second type log in the first table area of ​​the logical-physical address conversion table on the volatile memory.

2. The memory system of claim 1.

3. The controller: and further configured, when the power supply to the memory system is cut off due to an unexpected power loss, to write, to the first block and the second block, a first list indicating a list of logical addresses corresponding to data lost due to the unexpected power loss among data received from the host, using power stored in a capacitor of the memory system.

2. The memory system of claim 1.

4. The controller: and updating the reconstructed first table area based on the first list when the first list is stored in the first block and the second block, such that a value indicating an error is associated with each of the logical addresses corresponding to the lost data, respectively.

4. The memory system of claim 3.

5. The controller: when data cannot be normally read from one of the first block and the second block, N pieces of address conversion information last written to the other of the first block and the second block and N pieces of update logs last written to the other block are read from the other block, and the first table area of ​​the logical-physical address conversion table is reconstructed on the volatile memory based on the N pieces of address conversion information read from the other block and the N pieces of update logs read from the other block.

2. The memory system of claim 1.

6. The controller: When rebuilding the first table area, storing the N / 2 pieces of address translation information read from the first block in the volatile memory; storing the N / 2 pieces of address translation information read from the second block in the volatile memory; selecting an update log in chronological order from the N / 2 update logs read from either the first block or the second block; selecting, from N pieces of address translation information including the N / 2 pieces of address translation information read from the first block and the N / 2 pieces of address translation information read from the second block, a group of address translation information obtained from the first table area in the volatile memory before a time point when the selected update log was written to the first block and the second block; The selected update log is configured to reflect the contents of the selected group of address translation information.

2. The memory system of claim 1.

7. the first table area covers the entire logical address range included in the logical address space; 2. The memory system of claim 1.

8. the logical-physical address conversion table includes at least the first table area and a second table area; the first table area covers a first logical address range of the logical address space, and the second table area covers a second logical address range of the logical address space subsequent to the first logical address range; the N pieces of address translation information in the first table area correspond to N small logical address ranges belonging to the first logical address range, respectively; the second table area holds N pieces of address translation information corresponding to N small logical address ranges belonging to the second logical address range, respectively; 2. The memory system of claim 1.

9. The controller: allocating the first block and the second block to the first table area, and allocating a third block and a fourth block to the second table area; (1) a process of selecting one piece of address conversion information to be written to the third block from the N pieces of address conversion information in the second table area so that the N pieces of address conversion information in the second table area are stored in the third block in the first order, and selecting, from the N pieces of address conversion information in the second table area, address conversion information that is N / 2 pieces behind or before the selected one piece of address conversion information as another piece of address conversion information to be written to a fourth block of the non-volatile memory; (2) a process of acquiring the one address translation information selected from the N pieces of address translation information in the second table area and the other address translation information selected from the N pieces of address translation information in the second table area from the second table area on the volatile memory; (3) a process of writing, into the third block, the one piece of address translation information acquired from the second table area and an update log indicating update contents for all of the address translation information in the second table area that has been updated after the one piece of address translation information and the other address translation information are acquired from the second table area; (4) periodically executing a second process including a process of writing, to the fourth block, another address translation information acquired from the second table area and the update log indicating update contents for all the address translation information in the second table area; and in response to power being restored to the memory system after power supply to the memory system is cut off, the memory system is further configured to read, from the third block, the N / 2 pieces of address conversion information last written to the third block and the N / 2 update logs last written to the third block, and read, from the fourth block, the N / 2 pieces of address conversion information last written to the fourth block and the N / 2 update logs last written to the fourth block, and reconstruct the second table area of ​​the logical-physical address conversion table on the volatile memory based on the N / 2 pieces of address conversion information read from the third block, the N / 2 pieces of address conversion information read from the fourth block, and the N / 2 update logs read from either the third block or the fourth block.

9. The memory system of claim 8.

10. 1. A memory system connectable to a host, comprising: a non-volatile memory including a plurality of blocks; A volatile memory; a controller configured to manage a correspondence between each of the logical addresses included in a logical address space of the memory system and each of the physical addresses of the non-volatile memory by using a logical-physical address conversion table stored in the volatile memory, the logical-physical address conversion table including at least a first table area, the first table area holding N pieces of address conversion information respectively corresponding to N small logical address ranges, the N being an integer of 2 or more, The controller: (1) a process of selecting one piece of address translation information to be written to a first block of the non-volatile memory from the N pieces of address translation information in the first table area so that the N pieces of address translation information in the first block are stored in a first order in the first block of the non-volatile memory; (2) a process of acquiring the selected piece of address translation information from the first table area on the volatile memory; (3) periodically executing a first process including a process of writing to the first block the acquired one piece of address conversion information and an update log indicating update contents for all address conversion information of the first table area that has been updated after the acquisition of the one piece of address conversion information, wherein when the first table area of ​​the logical-physical address conversion table is updated by writing data to the non-volatile memory based on a write command received from the host, the update log includes a first type log including a logical address corresponding to the data and a physical address indicating a storage location in the non-volatile memory determined as a write destination for the data, and when the first table area of ​​the logical-physical address conversion table is updated by copying data from a source storage location to a destination storage location in the non-volatile memory that is executed in garbage collection for the non-volatile memory, the update log includes a second type log including a logical address corresponding to the copied data, an old physical address indicating the source storage location, and a new physical address indicating the destination storage location; in response to power being restored to the memory system after power has been removed from the memory system; reading, from the first block, the N pieces of address conversion information last written to the first block and the N pieces of update logs last written to the first block, and reconstructing the first table area of ​​the logical-physical address conversion table on the volatile memory based on the N pieces of address conversion information that have been read and the N pieces of update logs that have been read; In the reconstruction of the first table area, Determining whether the N update logs include a log of the second type; when the read N update logs include a second type log, a physical address corresponding to the logical address included in the second type log is obtained from the first table area of ​​the logical-physical address conversion table on the volatile memory, when an old physical address included in the second type log matches the obtained physical address, the content of the second type log is reflected in the first table area of ​​the logical-physical address conversion table on the volatile memory so that the new physical address included in the second type log is associated with the logical address included in the second type log, and when the old physical address included in the second type log does not match the obtained physical address, the content of the second type log is not reflected in the first table area of ​​the logical-physical address conversion table on the volatile memory. Memory system.

11. The N is an integer multiple of 2, The controller: (1) a process of selecting one piece of address conversion information from the N pieces of address conversion information so that the N pieces of address conversion information of the first table area are stored in the first block of the non-volatile memory in the first order, and selecting, from the N pieces of address conversion information, address conversion information that is N / 2 pieces behind or before the selected one piece of address conversion information as another piece of address conversion information to be written to a second block of the non-volatile memory; (2) a process of acquiring the selected one piece of address translation information and the selected other piece of address translation information from the first table area on the volatile memory; (3) a process of writing, to the first block, the one piece of acquired address translation information and an update log indicating update contents of all the address translation information in the first table area that has been updated after the acquisition of the one piece of address translation information and the other address translation information; (4) writing the acquired different address translation information and the update log to the second block. By repeatedly executing the first process, the first process is periodically executed; If data can be read normally from both the first block and the second block, In the reconstruction of the first table area, the memory controller is further configured to read, from the first block, the N / 2 pieces of address conversion information last written to the first block and the N / 2 update logs last written to the first block, read, from the second block, the N / 2 pieces of address conversion information last written to the second block and the N / 2 update logs last written to the second block, and reconstruct the first table area of ​​the logical-physical address conversion table on the volatile memory based on the N / 2 pieces of address conversion information read from the first block, the N / 2 pieces of address conversion information read from the second block, and the N / 2 update logs read from either the first block or the second block. The memory system of claim 10.

12. The controller: and further configured, when the power supply to the memory system is cut off due to an unexpected power loss, to write, to the first block, a first list indicating a list of logical addresses each corresponding to data lost due to the unexpected power loss among data received from the host, using power stored in a capacitor of the memory system. The memory system of claim 10.

13. The controller: and if the first list is stored in the first block, the method is further configured to update the reconstructed first table area based on the first list such that a value indicating an error is associated with each of the logical addresses corresponding to the lost data respectively.

13. The memory system of claim 12.

14. The controller: When rebuilding the first table area, storing the N pieces of address translation information read from the first block in the volatile memory; Selecting an update log from the N update logs read from the first block in order of oldest to newest; selecting, from the N pieces of address translation information read from the first block, a group of address translation information acquired from the first table area on the volatile memory before the selected update log was written to the first block; The selected update log is configured to reflect the contents of the selected group of address translation information. The memory system of claim 10.

15. the first table area covers the entire logical address range included in the logical address space; The memory system of claim 10.

16. the logical-physical address conversion table includes at least the first table area and a second table area; the first table area covers a first logical address range of the logical address space, and the second table area covers a second logical address range of the logical address space subsequent to the first logical address range; the N pieces of address translation information in the first table area correspond to N small logical address ranges belonging to the first logical address range, respectively; the second table area holds N pieces of address translation information corresponding to N small logical address ranges belonging to the second logical address range, respectively; The memory system of claim 10.

17. The controller: allocating the first block to the first table area and allocating the second block to the second table area; (1) a process of selecting one piece of address translation information to be written to the second block from the N pieces of address translation information in the second table area so that the N pieces of address translation information in the second table area are stored in the second block in the first order; (2) a process of acquiring the selected piece of address translation information from the second table area on the volatile memory; (3) periodically executing a second process including a process of writing, to the second block, one piece of address translation information acquired from the second table area and an update log indicating update contents for all address translation information of the second table area that has been updated after the acquisition of the one piece of address translation information from the second table area; in response to power being restored to the memory system after power supply to the memory system is cut off, reading from the second block the N pieces of address conversion information last written to the second block and the N pieces of update logs last written to the second block, and reconstructing the second table area of ​​the logical-physical address conversion table on the volatile memory based on the N pieces of address conversion information read from the second block and the N pieces of update logs read from the second block; In the reconstruction of the second table area, determining whether the N update logs read from the second block include a log of the second type; when the N update logs read from the second block include the second type log, a physical address corresponding to the logical address included in the second type log is obtained from the second table area of ​​the logical-physical address conversion table on the volatile memory, and when an old physical address included in the second type log matches the obtained physical address, the content of the second type log is reflected in the second table area of ​​the logical-physical address conversion table on the volatile memory so that the new physical address included in the second type log is associated with the logical address included in the second type log, and when the old physical address included in the second type log does not match the obtained physical address, the content of the second type log is not reflected in the second table area of ​​the logical-physical address conversion table on the volatile memory.

17. The memory system of claim 16.

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