Memory system

Abstract

To realize a memory system capable of improving the fairness of utilization of a nonvolatile memory corresponding to a plurality of logical address spaces.SOLUTION: A memory system comprises a nonvolatile memory and a controller. The controller is configured to: communicate with a host having a plurality of queues; provide the host with a plurality of logical address spaces each of which is allocated with one or more queues among the plurality of queues; calculate a plurality of first usage amounts of the nonvolatile memory each of which corresponds to the plurality of logical address spaces; select a first queue for which a command should be acquired from the plurality of queues on the basis of the plurality of the first usage amounts; acquire a first command from the first queue; calculate a predicted usage amount of the nonvolatile memory corresponding to the first command; and update a second usage amount corresponding to the first logical address space to which the first queue is assigned among the plurality of first usage amounts, using the predicted usage amount.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a technique for controlling a non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memories have become widespread. Solid-state drives (SSDs) equipped with NAND-type flash memories are known as one such memory system. SSDs are used as the main storage of various computing devices.

[0003] The memory system performs processing on the non-volatile memory in response to a command received from the host.

[0004] More specifically, the host is provided with, for example, a submission queue (SQ), which is capable of storing one or more commands to be executed in the memory system.

[0005] The memory system receives a command from the host by retrieving the command from the submission queue, and performs processing according to the received command. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2022 / 0326890 [Patent Document 2] US Patent Application Publication No. 2020 / 0089537 [Patent Document 3] US Patent Application Publication No. 2019 / 0332276 [Patent Document 4] Patent Publication No. 2022-021026 Summary of the Invention [Problem to be solved by the invention]

[0007] The submission queues may be assigned to a logical address space, which includes one or more logical addresses, which are addresses used by a host to address storage areas of the memory system.

[0008] The memory system may provide a host with a plurality of logical address spaces. Each of the plurality of logical address spaces is also referred to as a namespace. For example, one or more submission queues are assigned to each of the plurality of logical address spaces. For example, commands that specify logical addresses in the corresponding logical address space are stored in each submission queue.

[0009] One embodiment provides a memory system capable of improving fairness in the use of non-volatile memories corresponding to a plurality of logical address spaces. [Means for solving the problem]

[0010] According to an embodiment, a memory system includes a non-volatile memory and a controller. The controller communicates with a host having a plurality of queues, each capable of storing one or more commands. The controller provides the host with a plurality of logical address spaces, each assigned with one or more of the plurality of queues. The controller calculates a plurality of first usage amounts of the non-volatile memory, each corresponding to the plurality of logical address spaces. The controller selects a first queue from the plurality of queues from which a command should be retrieved based on the plurality of first usage amounts. The controller retrieves the first command from the first queue. The controller calculates a predicted usage amount of the non-volatile memory according to the first command. The controller updates a second usage amount, among the plurality of first usage amounts, corresponding to a first logical address space to which the first queue is assigned, using the predicted usage amount. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of a NAND memory chip included in the memory system of the embodiment. [Diagram 3] 4 is a diagram showing an example of a group management table used in the memory system of the embodiment. [Figure 4] 11 is a diagram showing an example of a group-NAND usage time management table used in the memory system of the embodiment. [Diagram 5] 11 is a diagram showing an example of a namespace-NAND usage time management table used in the memory system of the embodiment. [Figure 6] FIG. 13 is a diagram showing an example in which the use of the NAND flash memory is unfair between two submission queues in a memory system according to a comparative example. [Figure 7] 11 is a diagram showing an example in which the use of the NAND flash memory is fair between two submission queues in the memory system of the embodiment. [Figure 8] FIG. 1 is a block diagram showing a configuration of a memory system of a comparative example. [Figure 9] FIG. 13 is a diagram showing a controller in a comparative example memory system that can manage a sufficient number of commands to use the NAND flash memory fairly among management units. [Figure 10] FIG. 13 is a diagram showing a controller in a comparative example memory system in a case where a sufficient number of commands cannot be managed to use the NAND flash memory fairly among management units. [Figure 11] FIG. 2 is a block diagram showing a specific example of the configuration of a controller in the memory system according to the embodiment. [Figure 12] 4 is a diagram showing an example of a write method for a NAND flash memory in the memory system of the embodiment; [Figure 13] 4 is a diagram showing an example of the relationship between commands from a host and usage time of a NAND flash memory in the memory system of the embodiment. [Figure 14] 10 is a flowchart illustrating an example of a procedure of a NAND usage time update process executed in the memory system of the embodiment. [Figure 15] 1 is a flowchart illustrating an example of a procedure of a priority control process executed in the memory system of the embodiment. [Figure 16] 13 is a diagram showing another example of the namespace-NAND usage time management table used in the memory system of the embodiment. [Figure 17] 10 is a flowchart illustrating another example of the procedure of the use time update process executed in the memory system of the embodiment. [Figure 18] 10 is a flowchart illustrating another example of the procedure of the priority control process executed in the memory system of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment will be described with reference to the drawings.

[0013] First, the configuration of an information processing system including a memory system according to an embodiment will be described with reference to Fig. 1. The information processing system 1 includes a host device 2 and a memory system 3.

[0014] The host device 2 may be a storage server that stores a large amount of diverse data in the memory system 3, or may be a personal computer. Hereinafter, the host device 2 will also be referred to as a host 2.

[0015] The memory system 3 is a storage device configured to write data to a nonvolatile memory and read data from the nonvolatile memory. The nonvolatile memory is, for example, a NAND flash memory 4. The memory system 3 is also called a storage device or a semiconductor storage device. The memory system 3 is realized, for example, as a solid state drive (SSD) including the NAND flash memory 4. In the following, a case where the nonvolatile memory is the NAND flash memory 4 will be mainly illustrated.

[0016] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2, or may be connected to the host 2 via a cable or a network.

[0017] The interface for connecting the host 2 and the memory system 3 is PCI Express. TM (PCIe TM ), Ethernet TM , Fiber channel, NVM Express TM (NVMe TM ) and other standards.

[0018] The host 2 includes, for example, a CPU 21 and a random access memory (RAM) 22. The CPU 21 and the RAM 22 are connected via a bus 20, for example.

[0019] The CPU 21 is, for example, at least one processor. The CPU 21 controls the operation of various components within the host 2.

[0020] The RAM 22 is a volatile memory. The RAM 22 is realized as, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). The storage area of ​​the RAM 22 is allocated as, for example, a plurality of submission queues 25.

[0021] Each of the multiple submission queues 25 is a queue for storing a request issued by the host 2 to the memory system 3. That is, the host 2 transmits a request to the memory system 3 via the submission queue 25. The request issued by the host 2 to the memory system 3 is, for example, a command. Hereinafter, the request issued by the host 2 to the memory system 3 is also referred to as a command or a host command. Each submission queue 25 includes multiple slots into which the host 2 writes the command to be issued. The position (i.e., the slot) in the submission queue 25 where the host 2 should write the command is indicated by an SQ tail pointer. The leading position in the submission queue 25 of the command to be fetched by the memory system 3 is indicated by an SQ head pointer.

[0022] The host 2 writes a command to the position indicated by the SQ tail pointer in the submission queue 25 (i.e., issues a command). Then, the host 2 adds 1 to the SQ tail pointer. Note that if the value obtained by adding 1 to the SQ tail pointer reaches the number of slots in the submission queue 25 (i.e., the queue size), the host 2 sets the SQ tail pointer to 0. Then, the host 2 writes the updated value of the SQ tail pointer to the SQ tail doorbell register in the memory system 3.

[0023] 1, three commands are stored in the submission queue 25. The number of commands stored in the submission queue 25 corresponds to the difference between the SQ head pointer and the SQ tail pointer.

[0024] The memory system 3 includes, for example, a NAND flash memory 4, a DRAM 5, and a controller 6.

[0025] The NAND flash memory 4 includes one or more NAND memory chips 41. The one or more NAND memory chips 41 are, for example, N NAND memory chips 41-1, ..., and 41-N, where N is an integer equal to or greater than 1. In the following, a case where the NAND flash memory 4 includes N NAND memory chips 41-1, ..., and 41-N will be mainly illustrated. An unspecified one of the N NAND memory chips 41-1, ..., and 41-N will also be referred to as the NAND memory chip 41.

[0026] FIG. 2 shows a configuration example of a NAND memory chip 41. The NAND memory chip 41 includes, for example, one or more planes 42. Each of the one or more planes 42 is a unit that performs a data write operation and a data read operation. The number of planes 42 included in the NAND memory chip 41 is arbitrary. FIG. 2 illustrates a case where the NAND memory chip 41 includes four planes 42. The four planes are a 0th plane 42-0, a first plane 42-1, a second plane 42-2, and a third plane 42-3. Hereinafter, an unspecified one of the one or more planes 42 is also referred to as a plane 42.

[0027] The plane 42 includes a memory cell array 421. The memory cell array 421 includes a plurality of blocks B0, B1, B2, ..., and Bm-1, each including a plurality of memory cells arranged in a matrix. The plurality of blocks B0, B1, B2, ..., and Bm-1 each function as a minimum unit of a data erase operation. A block may also be referred to as an erase block or a physical block. The plurality of blocks B0, B1, B2, ..., and Bm-1 each include a plurality of pages P0, ..., and Pn-1. The plurality of pages P0, ..., and Pn-1 each include a plurality of memory cells connected to a single word line. The plurality of pages P0, ..., and Pn-1 each function as a unit of a data write operation and a data read operation. Note that a word line may function as a unit of a data write operation and a data read operation.

[0028] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, called the maximum number of P / E cycles. One P / E cycle for a block includes a data erase operation to put all memory cells in the block into an erased state, and a program operation to write data to each page of the block.

[0029] The NAND memory chip 41 may be implemented as a flash memory configured to store multiple bits per memory cell.

[0030] Examples of flash memories configured to store multiple bits per memory cell include multi-level cell (MLC, or 4LC) flash memories, triple-level cell (TLC, or 8LC) flash memories, and quad-level cell (QLC, or 16LC) flash memories. MLC flash memories can store two bits of data per memory cell. TLC flash memories can store three bits of data per memory cell. QLC flash memories can store four bits of data per memory cell. Flash memories configured to store one bit per memory cell are also called single-level cell (SLC, or 2LC) flash memories.

[0031] When the NAND memory chip 41 is realized as an MLC flash memory, two pages of data are written to multiple memory cells connected to the same word line by writing two bits of data per memory cell. The two pages of data are composed of Lower page data and Upper page data. Any area (e.g., one or more arbitrary blocks) in the MLC flash memory can be used as an area (SLC area) that can store only one bit per memory cell. In the operation of writing data to the SLC area, only one page of data is written to multiple memory cells connected to the same word line by writing one bit of data per memory cell.

[0032] When the NAND memory chip 41 is realized as a TLC flash memory, three pages of data are written to multiple memory cells connected to the same word line by writing three bits of data per memory cell. The three pages of data are composed of lower page data, middle page data, and upper page data. Any area (for example, one or more arbitrary blocks) in the TLC flash memory may be used as the above-mentioned SLC area, or may be used as an MLC area capable of storing two bits per memory cell. The SLC area and the MLC area may be set in units smaller than a block. In the MLC area, only two pages of data are written to multiple memory cells connected to the same word line by writing two bits of data per memory cell.

[0033] When the NAND memory chip 41 is realized as a QLC flash memory, four pages of data are written to multiple memory cells connected to the same word line by writing four bits of data per memory cell. Any area (e.g., one or more arbitrary blocks) in the QLC flash memory may be used as an SLC area, an MLC area, or a TLC area capable of storing three bits per memory cell. The SLC area, the MLC area, and the TLC area may be set in units smaller than a block. In the TLC area, only three pages of data are written to multiple memory cells connected to the same word line by writing three bits of data per memory cell.

[0034] Note that NAND memory chip 41 may be configured to store 5 or more bits per memory cell, but even in this case, any area of ​​NAND memory chip 41 may be used as an area in which only 4 or less bits of data per memory cell are written.

[0035] Return to Figure 1.

[0036] The DRAM 5 is a volatile memory. The storage area of ​​the DRAM 5 is allocated as, for example, a storage area for firmware (FW), a cache area for a logical-physical address conversion table 50, a storage area for a group management table 51, a group-NAND usage time management table 52, and a namespace-NAND usage time management table (NS-NAND usage time management table) 53.

[0037] The FW is a program for controlling the operation of the controller 6. The FW is loaded from the NAND flash memory 4 to the DRAM 5, for example.

[0038] The logical-physical address conversion table 50 is a table for managing mapping between each logical address and each physical address. A logical address is an address used by the host 2 to address a storage area of ​​the memory system 3. The logical address is, for example, a logical block address (LBA).

[0039] The group management table 51 is a table for managing groups of the submission queues 25. A group is a management unit to which one or more submission queues 25 belong. For example, one or more submission queues 25 having the same priority for fetching commands by the memory system 3 belong to one group. A specific configuration example of the group management table 51 will be described later with reference to FIG. 3. In the following description, it means that the higher the priority value of a submission queue 25, the higher the priority is given to fetching commands.

[0040] The group-NAND usage time management table 52 is a table for managing the NAND usage time for each group. The NAND usage time is the time during which the NAND flash memory 4 is used. The NAND usage time of a group is the cumulative total time during which the NAND flash memory 4 is used in response to commands fetched from the submission queue 25 belonging to the group. A specific configuration example of the group-NAND usage time management table 52 will be described later with reference to FIG. 4.

[0041] The NS-NAND usage time management table 53 is a table for managing the NAND usage time for each namespace. The NAND usage time of a namespace is the cumulative total time that the NAND flash memory 4 has been used in response to commands fetched from the submission queue 25 assigned to that namespace. A specific configuration example of the NS-NAND usage time management table 53 will be described later with reference to FIG.

[0042] A namespace is a logical address space including one or more logical addresses. The memory system 3 may provide a plurality of namespaces to the host 2. A namespace is identified by a namespace ID, and each namespace has an independent logical address space. For example, one or more submission queues 25 are assigned to each of the plurality of namespaces. For example, a command specifying a logical address in the corresponding namespace (i.e., the corresponding logical address space) is stored in each submission queue 25. In addition, one or more groups are associated with each of the plurality of namespaces. At least one of the submission queues 25 assigned to the associated namespace may belong to each of the one or more groups.

[0043] The storage area of ​​the DRAM 5 may be further allocated as a buffer area for temporarily storing data. The buffer areas are, for example, a write buffer 54 and a read buffer 55. The write buffer 54 temporarily stores user data to be written to the NAND flash memory 4. The read buffer 55 temporarily stores user data read from the NAND flash memory 4.

[0044] The controller 6 may be realized by a circuit such as a system-on-a-chip (SoC). The controller 6 is configured to control the NAND flash memory 4. The functions of each unit in the controller 6 may be realized by dedicated hardware in the controller 6, or may be realized by a processor that executes the FW.

[0045] The controller 6 may function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 4. The data management performed by the FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 4, and (2) processing for concealing the difference between page-based data read / write operations and block-based data erase operations. The block management includes bad block management, wear leveling, and garbage collection.

[0046] The management of the mapping between each logical address and each physical address is performed, for example, by using a logical-physical address conversion table 50. The controller 6 uses the logical-physical address conversion table 50 to manage the mapping between each logical address and each physical address in a specific management size unit. A physical address corresponding to a certain logical address indicates a physical storage location in the NAND flash memory 4 to which data of this logical address is written. The controller 6 uses the logical-physical address conversion table 50 to manage a plurality of storage areas obtained by logically dividing the storage area of ​​the NAND flash memory 4. These multiple storage areas correspond to a plurality of logical addresses, respectively. That is, each of these multiple storage areas is specified by one logical address. The logical-physical address conversion table 50 may be loaded from the NAND flash memory 4 to the DRAM 5 when the memory system 3 is started up.

[0047] Data can be written to one memory cell only once per P / E cycle. Therefore, the controller 6 writes updated data corresponding to a certain logical address to a different physical storage location, not to the physical storage location where the previous data corresponding to this logical address is stored. Then, the controller 6 invalidates the previous data by updating the logical-physical address conversion table 50 so as to associate this logical address with this different physical storage location. Data referenced by the logical-physical address conversion table 50 (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address is called invalid data. Valid data is data that may be read by the host 2 later. Invalid data is data that may no longer be read by the host 2.

[0048] Also, the controller 6 may perform a write operation on the NAND memory chip 41 in, for example, any of SLC mode, MLC mode, TLC mode, and QLC mode. The SLC mode is a mode in which one bit is written per memory cell. The MLC mode is a mode in which two bits are written per memory cell. The TLC mode is a mode in which three bits are written per memory cell. The QLC mode is a mode in which four bits are written per memory cell.

[0049] The controller 6 includes, for example, a DRAM interface (DRAM I / F) 11, an SRAM 12, and a memory controller 13. The DRAM I / F 11, the SRAM 12, and the memory controller 13 are connected via, for example, a bus 10.

[0050] The DRAM I / F 11 functions as a DRAM control circuit configured to control access to the DRAM 5 .

[0051] The SRAM 12 is a volatile memory. The storage area of ​​the SRAM 12 is allocated as, for example, one or more intermediate queues 15. The intermediate queue 15 is a queue capable of storing requests to the NAND flash memory 4. A request to the NAND flash memory 4 is referred to as a NAND request. The NAND request is generated based on a command fetched from the submission queue 25. The one or more intermediate queues 15 correspond to, for example, one or more groups. A certain intermediate queue 15 stores a NAND request corresponding to a command fetched from the submission queue 25 belonging to the group corresponding to the intermediate queue 15. The intermediate queue 15 may accumulate NAND requests whose corresponding processing has not yet been executed. The one or more NAND requests stored in the intermediate queue 15 are processed by the memory controller 13 in a specific order (for example, in the order in which they were stored). The processed NAND requests are discarded from the intermediate queue 15.

[0052] The storage area of ​​the SRAM 12 may be allocated as a storage area for at least one of the FW, the logical-physical address conversion table 50, the group management table 51, the group-NAND use time management table 52, and the NS-NAND use time management table 53. The storage area of ​​the SRAM 12 may be allocated as a write buffer 54 and a read buffer 55.

[0053] The memory controller 13 is configured to control various processes for the NAND flash memory 4. Specifically, the memory controller 13 fetches a command from each of the multiple submission queues 25, and executes a process according to the fetched command for the NAND flash memory 4. The memory controller 13 includes a front-end unit 16 and a back-end unit 17.

[0054] The front end unit 16 controls communication between the host 2 and the memory system 3. For example, commands and data are transmitted from the host 2 to the memory system 3 through the communication.

[0055] The front-end unit 16 controls acquisition (i.e., fetching) of commands from the multiple submission queues 25. Specifically, the front-end unit 16 selects a target submission queue 25 from which to fetch a command (hereinafter also referred to as a fetch target submission queue 25) from the multiple submission queues 25. The front-end unit 16 fetches commands sequentially from the top of the fetch target submission queue 25. The commands to be fetched are, for example, input / output (I / O) commands and various control commands. The I / O commands may include a write command and a read command. The control commands may include an unmap command (trim command) and a flush command.

[0056] The front-end unit 16 can generate one or more requests (NAND requests) to the NAND flash memory 4 based on the command fetched from the submission queue 25. The front-end unit 16 stores the generated NAND request in the intermediate queue 15 corresponding to the group to which the submission queue 25 belongs.

[0057] Specifically, for example, when a read command is fetched from the submission queue 25, the front-end unit 16 generates one or more NAND requests for the NAND flash memory 4 based on the read command. The NAND request generated based on the read command is, for example, a data read request for the NAND flash memory 4. A data read request for the NAND flash memory 4 is also simply referred to as a read request. For example, when the size of data read in one data read operation for the NAND flash memory 4 (more specifically, the NAND memory chip 41) is 16 KB, one read request is a request to read 16 KB of data. The size of data read in one data read operation for the NAND memory chip 41 is also referred to as a read unit. The read unit is equal to the size of one page of data, for example.

[0058] Also, for example, when a write command is fetched from the submission queue 25, the front-end unit 16 generates one or more NAND requests for the NAND flash memory 4 based on the write command. The NAND request generated based on the write command is, for example, a request to write data to the NAND flash memory 4. A request to write data to the NAND flash memory 4 is also simply referred to as a write request. For example, when the size of data written in one data write operation to the NAND flash memory 4 (more specifically, the NAND memory chip 41) is 192 KB, one write request is a request to write 192 KB of data. The size of data written in one data write operation to the NAND memory chip 41 is also referred to as a write unit. The write unit is, for example, equal to an integer multiple of the size of one page of data.

[0059] The back-end unit 17 electrically connects the controller 6 and the NAND flash memory 4. The back-end unit 17 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0060] The back-end unit 17 functions as a memory control circuit configured to control the NAND flash memory 4. The back-end unit 17 may be connected to a plurality of NAND memory chips 41 via a plurality of channels. By driving the plurality of NAND memory chips 41 in parallel, the bandwidth of access between the controller 6 and the NAND flash memory 4 is expanded.

[0061] The back-end unit 17 performs processing on the NAND flash memory 4 corresponding to the NAND requests stored in each of the multiple intermediate queues 15. Specifically, the back-end unit 17 acquires the NAND requests from the intermediate queues 15 so that the use of the NAND flash memory 4 is fair among the namespaces. The back-end unit 17 may acquire the NAND requests from the intermediate queues 15 so that the use of the NAND flash memory 4 is fair among the multiple groups associated with one namespace. The back-end unit 17 performs processing on the NAND flash memory 4 corresponding to the acquired NAND requests.

[0062] Here, examples of the configurations of the group management table 51, the group-NAND use time management table 52, and the NS-NAND use time management table 53 used in the memory system 3 will be described.

[0063] 3 shows an example of the configuration of the group management table 51. The group management table 51 includes a plurality of entries corresponding to a plurality of groups, respectively. The number of entries included in the group management table 51 corresponds to, for example, the total number of groups that can be associated with each of a plurality of namespaces. For example, if the memory system 3 provides two namespaces to the host 2 and four groups can be associated with each of the two namespaces, the group management table 51 includes eight entries. Each of the plurality of entries includes, for example, a group field, a namespace field (NS field), an I / O type field, a submission queue field (SQ field), a weight field, and a priority field.

[0064] The group field indicates identification information of the corresponding group.

[0065] The NS field indicates the identification information (namespace ID) of the namespace with which the corresponding group is associated.

[0066] The I / O type field indicates the I / O type of the corresponding group. The I / O type indicates, for example, the type of command stored in the submission queue 25 belonging to the corresponding group. In other words, the I / O type indicates the purpose of the submission queue 25 belonging to the corresponding group. For example, "write" or "read" is set as the I / O type. When "write" is set as the I / O type, the submission queue 25 belonging to the corresponding group is a submission queue 25 used to store a write command (i.e., a submission queue 25 for writing). When "read" is set as the I / O type, the submission queue 25 belonging to the corresponding group is a submission queue 25 used to store a read command (i.e., a submission queue 25 for reading). When the target to be managed as the corresponding group has not yet been determined (for example, the I / O type of the group has not yet been determined), for example, "N / A" is set in the I / O type field.

[0067] The SQ field indicates identification information of the submission queue 25 belonging to the corresponding group. The SQ field indicates, for example, one or more pieces of identification information assigned to one or more submission queues 25. If the target to be managed as the corresponding group has not yet been determined (for example, the identification information of the submission queue 25 belonging to that group has not yet been notified from the host 2), for example, "N / A" is set in the SQ field.

[0068] The weight field indicates the weight W used for the corresponding group. The weight W is a coefficient used to calculate the NAND usage time of the corresponding group. For example, the weight W is set to a larger value for a group that contains a submission queue 25 that stores a command that should be processed with priority. The value set as the weight W is, for example, any value from 1 to 256. If the target to be managed as the corresponding group has not yet been determined (for example, the weight W of the group has not yet been determined), the weight field is set to, for example, "N / A".

[0069] The priority field indicates the priority P of fetching the submission queue 25 belonging to the corresponding group. The higher the priority P of a group, the more frequently the submission queue 25 belonging to that group is selected as a fetch target. The priority field may indicate whether or not it is possible to fetch a command from the submission queue 25 belonging to the corresponding group. If it is possible to fetch a command from the submission queue 25 belonging to the corresponding group, the priority field is set to, for example, "enable". If it is prohibited to fetch a command from the submission queue 25 belonging to the corresponding group, the priority field is set to, for example, "disable". If the target to be managed as the corresponding group has not yet been determined (for example, the priority P of the group has not yet been determined), the priority field is set to, for example, "N / A".

[0070] In the example shown in FIG. 3, for example, group “10” is associated with namespace “1”. The I / O type of group “10” is “write”. The submission queues 25 belonging to group “10” are four submission queues 25 with identification information of “0”, “1”, “2”, and “3”. The weight used for group “10” is W10. The fetch priority of the submission queues 25 belonging to group “10” is P10.

[0071] For example, group "11" is associated with namespace "1". The I / O type of group "11" is "read". The submission queues 25 that belong to group "11" are four submission queues 25 with identification information of "4", "5", "6", and "7". The weight used for group "11" is W11. The fetch priority of the submission queues 25 that belong to group "11" is P11.

[0072] For example, both group "12" and group "13" are associated with namespace "1." Fields other than the NS field of group "12" and group "13" are set to "N / A." Therefore, it has not yet been specified what will be managed as either group "12" or group "13."

[0073] Both group “21” and group “22” are set to namespace “2” and I / O type “read.” In such a case, the controller 6 can manage multiple groups (more specifically, the submission queues 25 belonging to each of these groups) that are set to the same namespace and the same I / O type with different weights W and different priorities P.

[0074] The information managed using the group management table 51 is based on, for example, information notified from the host 2 to the memory system 3. Alternatively, an interface for the host 2 to change the contents of the group management table 51 may be provided.

[0075] 4 shows an example of the configuration of the group-NAND usage time management table 52. The group-NAND usage time management table 52 includes a plurality of entries corresponding to a plurality of groups, respectively. Each of the plurality of entries includes a group field and a NAND usage time field.

[0076] The group field indicates identification information of the corresponding group.

[0077] The NAND usage time field indicates the usage amount of the NAND flash memory 4 by the corresponding group. This usage amount is an index indicating the cumulative amount of processing in the NAND flash memory 4 performed in response to a command fetched from the submission queue 25 belonging to the corresponding group. The NAND usage time field may indicate a value obtained by dividing the usage amount by the weight W used for the corresponding group. The value indicated in the NAND usage time field is updated using the predicted usage amount of the NAND flash memory 4 in response to the command (or the value obtained by dividing the predicted usage amount by the weight W) every time a command is fetched from the submission queue 25 belonging to the corresponding group.

[0078] More specifically, this usage amount is represented by, for example, the usage time (NAND usage time) VT of the NAND flash memory 4 of the corresponding group. The NAND usage time VT is the cumulative total time from a certain point in time that the NAND flash memory 4 has been used in response to a command fetched from the submission queue 25 belonging to the corresponding group. The NAND usage time field may indicate a value obtained by dividing the NAND usage time by the weight W used for the corresponding group. The value indicated in the NAND usage time field is updated using the predicted usage time of the NAND flash memory 4 in response to the command (or the value obtained by dividing the predicted usage time by the weight W) every time a command is fetched from the submission queue 25 belonging to the corresponding group.

[0079] If an object to be managed as a corresponding group in the group management table 51 has not yet been specified, for example, “N / A” is set in the NAND usage time field of the group-NAND usage time management table 52 .

[0080] In the example shown in FIG. 4, for example, the NAND usage time of group “10” is VT10. The NAND usage time of group “11” is VT11. The NAND usage time of group “20” is VT20. The NAND usage time of group “21” is VT21. The NAND usage time of group “22” is VT22. In addition, the NAND usage time of groups “12”, “13”, and “23” is “N / A”, and it has not yet been specified which of group “12”, “13”, and “23” will be managed.

[0081] 5 shows an example of the configuration of the NS-NAND usage time management table 53. The NS-NAND usage time management table 53 includes a plurality of entries corresponding to a plurality of namespaces, respectively. The number of entries included in the NS-NAND usage time management table 53 corresponds to the number of namespaces that the memory system 3 provides to the host 2, for example. For example, if the memory system 3 provides two namespaces to the host 2, the NS-NAND usage time management table 53 includes two entries. Each of the multiple entries includes, for example, a namespace field (NS field) and a NAND usage time field.

[0082] The NS field indicates the identification information (namespace ID) of the corresponding namespace.

[0083] The NAND usage time field indicates the usage amount of the NAND flash memory 4 by the corresponding namespace. This usage amount is an index indicating the cumulative amount of processing in the NAND flash memory 4 performed in response to a command fetched from the submission queue 25 assigned to the corresponding namespace. Every time a command is fetched from the submission queue 25 assigned to the namespace, the value indicated in the NAND usage time field is updated using the predicted usage amount of the NAND flash memory 4 in response to that command (or a value obtained by dividing the predicted usage amount by the weight W).

[0084] More specifically, this usage amount is represented by the usage time (NAND usage time) NVT of the NAND type flash memory 4 of the corresponding namespace. The NAND usage time NVT is the cumulative total time from a certain point in time during which the NAND type flash memory 4 has been used in response to commands fetched from the submission queue 25 assigned to the corresponding namespace. The submission queue 25 assigned to a namespace belongs to one of the groups associated with the namespace. Therefore, the NAND usage time NVT of a namespace is the sum of the NAND usage times VT of all the groups associated with the namespace. The NAND usage time NVT of a namespace is updated, for example, every time the NAND usage time VT of one of the groups associated with the namespace is updated.

[0085] In the following, a case where the usage amount of the NAND flash memory 4 is expressed by usage time will be mainly illustrated, but the usage amount of the NAND flash memory 4 can be replaced with various indices that represent the amount of processing in the NAND flash memory 4.

[0086] In the example shown in Fig. 5, the NAND usage time of namespace "1" is NVT1. When the group management table 51 shown in Fig. 3 and the group-NAND usage time management table 52 shown in Fig. 4 are used, groups "10", "11", "12", and "13" belong to namespace "1". Since "N / A" is set in the NAND usage times VT of groups "12" and "13", the NAND usage time NVT1 of namespace "1" is obtained by calculating the sum of the NAND usage time VT10 of group "10" and the NAND usage time VT11 of group "11".

[0087] Furthermore, the NAND usage time of namespace "2" is NVT2. When the group management table 51 shown in Fig. 3 and the group-NAND usage time management table 52 shown in Fig. 4 are used, groups "20", "21", "22", and "23" belong to namespace "2". Since "N / A" is set as the NAND usage time VT of group "23", the NAND usage time NVT2 of namespace "2" is obtained by calculating the sum of the NAND usage time VT20 of group "20", the NAND usage time VT21 of group "21", and the NAND usage time VT22 of group "22".

[0088] Here, the fairness of use of the NAND flash memory 4 among specific management units will be described. There is a demand for the memory system 3 to make the use of the NAND flash memory 4 fair among specific management units. The specific management unit is, for example, a submission queue 25, a group of submission queues 25, or a namespace.

[0089] A case will be described in which the use of the NAND flash memory is unfair among the submission queues in the memory system according to the comparative example.

[0090] 6 shows an example in which the use of the NAND flash memory is unfair between two submission queues in a memory system according to a comparative example. The two submission queues are a first submission queue 25C-1 and a second submission queue 25C-2. Here, it is assumed that the size of data read in one data read operation from the NAND flash memory (read unit) is 16 KB.

[0091] The first submission queue 25C-1 is used for a workload consisting of read commands requesting the reading of 64 KB of user data (hereinafter referred to as 64 KB read commands). The first submission queue 25C-1 continuously stores 64 KB read commands. Specifically, the first submission queue 25C-1 stores a plurality of 64 KB read commands C11, C12, C13, C14, C15, ... in order.

[0092] The second submission queue 25C-2 is used for a workload consisting of read commands requesting the reading of 16 KB of user data (hereinafter referred to as 16 KB read commands). The second submission queue 25C-2 continuously stores 16 KB read commands. Specifically, the second submission queue 25-2 stores a plurality of 16 KB read commands C21, C22, C23, C24, C25, ... in order.

[0093] In the example shown in FIG. 6, four read requests based on a 64 KB read command fetched from the first submission queue 25C-1 and one read request based on a 16 KB read command fetched from the second submission queue 25C-2 are executed alternately to the NAND flash memory.

[0094] Specifically, first, four read requests R11, R12, R13, and R14 based on the 64 KB read command C11 fetched from the first submission queue 25C-1 are executed to the NAND flash memory. One read request R21 based on the 16 KB read command C21 fetched from the second submission queue 25C-2 is executed to the NAND flash memory. Four read requests R15, R16, R17, and R18 based on the 64 KB read command C12 fetched from the first submission queue 25C-1 are executed to the NAND flash memory. Then, one read request R22 based on the 16 KB read command C22 fetched from the second submission queue 25C-2 is executed to the NAND flash memory.

[0095] The read requests R11 to R18 correspond to read commands fetched from the first submission queue 25C-1. Therefore, the NAND usage time of the first submission queue 25C-1 corresponds to the time required for read operations in the NAND flash memory according to the eight read requests R11 to R18.

[0096] The read requests R21 and R22 correspond to read commands fetched from the second submission queue 25C-2. Therefore, the NAND usage time of the second submission queue 25C-2 corresponds to the time required for read operations in the NAND flash memory according to the two read requests R21 and R22.

[0097] 6, the NAND usage time of the first submission queue 25C-1 is longer than the NAND usage time of the second submission queue 25C-2. Therefore, in the memory system of the comparative example, the usage of the NAND flash memory becomes unfair between the first submission queue 25C-1 and the second submission queue 25C-2.

[0098] Note that, in FIG. 6, a case where a read command is stored in the submission queues 25C-1 and 25C-2 has been described. However, similarly, when a write command is stored in the submission queues 25C-1 and 25C-2, the usage of the NAND flash memory may become unfair between the first submission queue 25C-1 and the second submission queue 25C-2.

[0099] In contrast to this, a case will be described in which the use of the NAND flash memories 4 is fair among the submission queues 25 in the memory system 3 of this embodiment.

[0100] 7 shows an example in which the use of the NAND flash memory 4 is fair between two submission queues 25 in the memory system 3. The two submission queues are a first submission queue 25-1 and a second submission queue 25-2. Here, it is assumed that the size of data read in one data read operation from the NAND flash memory 4 (read unit) is 16 KB.

[0101] The read commands C11, C12, C13, C14, C15, ... stored in the first submission queue 25-1 and the read commands C21, C22, C23, C24, C25, ... stored in the second submission queue 25-2 are the same as those in the comparative example described above with reference to Figure 6.

[0102] In the example shown in FIG. 7, one of four read requests based on a 64 KB read command fetched from the first submission queue 25-1 and one read request based on a 16 KB read command fetched from the second submission queue 25-2 are executed alternately to the NAND flash memory 4.

[0103] Specifically, first, the first read request R11 of the four read requests R11, R12, R13, and R14 based on the 64 KB read command C11 fetched from the first submission queue 25-1 is executed to the NAND flash memory 4. One read request R21 based on the 16 KB read command C21 fetched from the second submission queue 25-2 is executed to the NAND flash memory 4. The second read request R12 of the four read requests R11, R12, R13, and R14 is executed to the NAND flash memory 4. One read request R22 based on the 16 KB read command C22 fetched from the second submission queue 25-2 is executed to the NAND flash memory 4. The third read request R13 of the four read requests R11, R12, R13, and R14 is executed to the NAND flash memory 4. One read request R23 based on the 16 KB read command C23 fetched from the second submission queue 25-2 is executed to the NAND flash memory 4. The fourth read request R14 of the four read requests R11, R12, R13, and R14 is executed to the NAND flash memory 4. One read request R24 based on the 16 KB read command C24 fetched from the second submission queue 25-2 is executed to the NAND flash memory 4. The first read request R15 of the four read requests based on the 64 KB read command C12 fetched from the first submission queue 25-1 is executed to the NAND flash memory 4. Then, one read request R25 based on the 16 KB read command C25 fetched from the second submission queue 25-2 is executed to the NAND flash memory 4.

[0104] The read requests R11, R12, R13, R14, and R15 correspond to read commands fetched from the first submission queue 25-1. Therefore, the NAND usage time of the first submission queue 25-1 corresponds to the time required for read operations in the NAND flash memory 4 according to the five read requests R11, R12, R13, R14, and R15.

[0105] The read requests R21, R22, R23, R24, and R25 correspond to read commands fetched from the second submission queue 25-2. Therefore, the NAND usage time of the second submission queue 25-2 corresponds to the time required for read operations in the NAND flash memory 4 according to the five read requests R21, R22, R23, R24, and R25.

[0106] 7, the NAND usage time of the first submission queue 25-1 is equal to the NAND usage time of the second submission queue 25-2. Therefore, in the memory system 3, the usage of the NAND flash memory 4 can be made fair between the first submission queue 25-1 and the second submission queue 25-2.

[0107] Note that, in FIG. 7, a case where a read command is stored in the submission queues 25-1 and 25-2 has been described, but similarly, in a case where a write command is stored in the submission queues 25-1 and 25-2, the use of the NAND flash memory 4 can be made fair between the first submission queue 25-1 and the second submission queue 25-2.

[0108] With reference to FIGS. 8 to 10, the configuration and operation of the memory system 3C according to the comparative example will be further described below regarding the unfairness of the use of the NAND flash memories among the management units.

[0109] 8 shows the configuration of a memory system 3C of a comparative example. The memory system 3C includes a controller 6C and a NAND flash memory 4C.

[0110] The controller 6C is configured to fetch a command from each of the multiple submission queues 25C, and execute a process according to the fetched command on the NAND flash memory 4C. The controller 6C includes a command processing unit 32C, multiple intermediate queues 15C, and a scheduling unit 33C.

[0111] Here, the multiple intermediate queues 15C are four intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4, which correspond to the four management units, respectively.

[0112] The plurality of submission queues 25C includes four submission queues 25C-1, 25C-2, 25C-3, and 25C-4, which correspond to the four management units, respectively.

[0113] The command processing unit 32C selects a fetch target submission queue 25C from the submission queues 25C-1, 25C-2, 25C-3, and 25C-4. The command processing unit 32C uses round robin as an arbitration mechanism for the submission queues 25C-1, 25C-2, 25C-3, and 25C-4. That is, the command processing unit 32C selects the submission queues 25C-1, 25C-2, 25C-3, and 25C-4 one by one in a specific order.

[0114] The command processing unit 32C fetches a command from the selected submission queue 25C. The command processing unit 32C generates one or more NAND requests for the NAND flash memory 4C based on the fetched command. The command processing unit 32C stores the generated one or more NAND requests in the corresponding intermediate queue 15C.

[0115] The scheduling unit 33C schedules processing according to the NAND requests stored in the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4. Specifically, the scheduling unit 33C acquires NAND requests to be processed from the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4 so that the use of the NAND flash memory 4C is fair among the management units. The scheduling unit 33C performs processing on the NAND flash memory 4C based on the acquired NAND requests. Note that, when the NAND flash memory 4C includes multiple NAND memory chips, the scheduling unit 33C performs scheduling for each NAND memory chip.

[0116] In order to ensure that the use of the NAND flash memory 4C is fair among the management units, a sufficient number of commands must be managed in the controller 6C in order for the scheduling unit 33C to acquire NAND requests from the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4. More specifically, for example, a sufficient number of NAND requests must be stored in each of the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4.

[0117] In order to increase the number of commands that the controller 6C can manage, it is necessary to increase the hardware resources (HW resources) of the controller 6C provided for managing the commands. The HW resources are, for example, a memory (for example, RAM) that stores information about commands such as the intermediate queue 15C. However, increasing the HW resources increases the cost of the memory system 3C. Therefore, for example, if the memory capacity is insufficient for the upper limit of the number of commands that can be managed simultaneously based on the specifications of the controller 6C (for example, the NVMe standard), the controller 6C may not be able to manage a sufficient number of commands.

[0118] 9 shows a controller 6C in a comparative memory system 3C when a sufficient number of commands can be managed to use the NAND flash memory 4C fairly among the management units. In the controller 6C, a sufficient number of NAND requests are stored in the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4 to use the NAND flash memory 4C fairly among the management units. Specifically, four NAND requests are stored in the intermediate queue 15C-1. Two NAND requests are stored in the intermediate queue 15C-2. One NAND request is stored in the intermediate queue 15C-3. Three NAND requests are stored in the intermediate queue 15C-4.

[0119] In this case, the scheduling unit 33C can acquire a NAND request from the intermediate queue 15C corresponding to any one of the four management units. Therefore, the scheduling unit 33C can schedule the execution of processes according to the NAND requests stored in the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4 so that the use of the NAND flash memory 4C is fair among the management units.

[0120] Specifically, the scheduling unit 33C acquires NAND requests from the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4 in that order, and performs processing on the NAND flash memory 4C based on the acquired NAND requests. This allows the memory system 3C to make the use of the NAND flash memory 4C fair among the management units.

[0121] On the other hand, FIG. 10 shows a controller 6C in a comparative memory system 3C when a sufficient number of commands cannot be managed to use the NAND flash memory 4C fairly among the management units. In the controller 6C, a sufficient number of NAND requests to use the NAND flash memory 4C fairly among the management units are not stored in the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4. Specifically, four NAND requests are stored in the intermediate queue 15C-1. Two NAND requests are stored in the intermediate queue 15C-2. No NAND requests are stored in either the intermediate queues 15C-3 or 15C-4.

[0122] In this case, the scheduling unit 33C can acquire NAND requests from the intermediate queues 15C-1 and 15C-2, but cannot acquire NAND requests from the intermediate queues 15C-3 or 15C-4. Therefore, the scheduling unit 33C cannot schedule the execution of processes according to the NAND requests stored in the intermediate queues 15C-1, 15C-2, 15C-3, and 15C-4 so that the use of the NAND flash memory 4C is fair among the management units.

[0123] Specifically, the scheduling unit 33C acquires NAND requests from the intermediate queues 15C-1 and 15C-2 in order, for example, and performs processing on the NAND flash memory 4C based on the acquired NAND requests. On the other hand, the scheduling unit 33C cannot acquire NAND requests from the intermediate queues 15C-3 and 15C-4, and therefore cannot perform processing on the corresponding NAND flash memory 4C. Therefore, the NAND flash memory 4C is used for two management units corresponding to the intermediate queues 15C-1 and 15C-2, respectively, but the NAND flash memory 4C is not used for two management units corresponding to the intermediate queues 15C-3 and 15C-4, respectively. Therefore, in the memory system 3C, the use of the NAND flash memory 4C becomes unfair between the management units.

[0124] In this way, the controller 6C of the memory system 3C according to the comparative example may not be able to manage a sufficient number of commands to use the NAND flash memory 4C fairly among the management units. Therefore, in the memory system 3C according to the comparative example, the use of the NAND flash memory 4C may become unfair among the management units.

[0125] In contrast, in the memory system 3 according to the present embodiment, the controller 6 is configured to manage a sufficient number of commands to use the NAND flash memory 4 fairly among the management units. Specifically, the controller 6 manages, for example, a plurality of usage amounts (for example, a plurality of NAND usage times) of the NAND flash memory 4 corresponding to a plurality of namespaces, respectively. When the controller 6 acquires a command from the submission queue 25, it calculates a predicted usage amount (hereinafter, referred to as a predicted usage amount) of the NAND flash memory 4 according to the acquired command. The controller 6 updates the usage amount corresponding to the namespace to which the submission queue 25 is assigned, using the calculated predicted usage amount. Then, the controller 6 selects a submission queue 25 from which a command should be acquired from the plurality of submission queues 25, using a plurality of usage amounts corresponding to a plurality of namespaces, respectively.

[0126] The controller 6, for example, selects (or increases the frequency of selection of) a submission queue 25 assigned to a less used namespace as the submission queue 25 from which a command should be acquired. This allows the controller 6 to manage a sufficient number of commands for that namespace to use the NAND flash memory 4 fairly among the namespaces. This allows the controller 6 to schedule the execution of commands (more specifically, NAND requests corresponding to commands) so that the use of the NAND flash memory 4 is fair among the namespaces. Therefore, in the memory system 3, it is possible to improve the fairness of the use of the NAND flash memory 4 among multiple namespaces.

[0127] Furthermore, the controller 6 does not select (or reduces the frequency of selection of) a submission queue 25 assigned to a namespace with high usage as a submission queue 25 from which a command should be acquired. This allows the controller 6 to prevent excessive acquisition of commands for that namespace and the waste of resources for managing the commands. Therefore, in the memory system 3, the resources for managing commands can be reduced more than, for example, the memory system 3C of the comparative example.

[0128] FIG. 11 shows a specific example of the configuration of the controller 6 in the memory system 3.

[0129] The controller 6 is configured to fetch a command from each of the multiple submission queues 25, and execute a process according to the fetched command on the NAND flash memory 4. The controller 6 also controls the fetching of commands from the multiple submission queues 25 so that the use of the NAND flash memory 4 is fair among the namespaces.

[0130] In the controller 6, the front-end unit 16 includes a fetch scheduling unit 31 and a command processing unit 32. The back-end unit 17 includes a NAND scheduling unit 33.

[0131] Here, an example is shown in which the multiple submission queues 25 include submission queues 25-0, 25-1, 25-4, 25-5, 25-8, 25-9, 25-12, and 25-13, and the multiple intermediate queues 15 include intermediate queues 15-1, 15-2, 15-3, 15-4, 15-5, and 15-6. Note that the number of submission queues 25 and the number of intermediate queues 15 are arbitrary.

[0132] The submission queues 25-0 and 25-1 are submission queues 25 used to store write commands. The submission queues 25-0 and 25-1 belong to group G10. In other words, the I / O type of group G10 is "write."

[0133] The submission queues 25-4 and 25-5 are submission queues 25 used to store read commands. The submission queues 25-4 and 25-5 belong to the group G11. In other words, the I / O type of the group G11 is "read".

[0134] The submission queues 25-0, 25-1, 25-4, and 25-5 are assigned to a first namespace NS1, that is, the first namespace NS1 is associated with groups G10 and G11.

[0135] The submission queues 25-8 and 25-9 are submission queues 25 used to store write commands. The submission queues 25-8 and 25-9 belong to the group G20. In other words, the I / O type of the group G20 is "write".

[0136] The submission queues 25-12 and 25-13 are submission queues 25 used to store read commands. The submission queues 25-12 and 25-13 belong to the group G21. In other words, the I / O type of the group G21 is "read".

[0137] The submission queues 25-8, 25-9, 25-12, and 25-13 are assigned to a second namespace NS2, i.e., the second namespace NS2 is associated with the groups G20 and G21.

[0138] The groups G10, G11, G20, and G21 correspond to the entries of the four groups "10," "11," "20," and "21," respectively, in the group management table 51 described above with reference to FIG.

[0139] The intermediate queues 15-1, 15-2, 15-3, 15-4, 15-5, and 15-6 correspond to six management units, respectively. The management units are, for example, groups. Specifically, for example, the intermediate queue 15-1 corresponds to group G10. The intermediate queue 15-2 corresponds to group G11. The intermediate queue 15-3 corresponds to group G20. The intermediate queue 15-4 corresponds to group G21. Similarly, each of the intermediate queues 15-5 and 15-6 also corresponds to one group (not shown).

[0140] Because the I / O type of group G10 is "write," intermediate queue 15-1 is used to store write requests. Because the I / O type of group G11 is "read," intermediate queue 15-2 is used to store read requests. Because the I / O type of group G20 is "write," intermediate queue 15-3 is used to store write requests. Because the I / O type of group G21 is "read," intermediate queue 15-4 is used to store read requests.

[0141] The fetch scheduling unit 31 schedules the fetching of commands from the multiple submission queues 25. Specifically, the fetch scheduling unit 31 manages, for example, a priority P at which each of the multiple submission queues 25 is selected as a fetch target submission queue 25. The fetch scheduling unit 31 manages the priority P of each submission queue 25, for example, for each management unit. When the management unit is a group, a priority P at which each of one or more submission queues 25 belonging to the group is selected as a fetch target submission queue 25 is set for the group. For example, a group management table 51 is used to manage the priority P.

[0142] The fetch scheduling unit 31 selects a submission queue 25 having a higher priority P as a fetch target submission queue 25 more frequently based on the priority P corresponding to each of the multiple submission queues 25 (for example, the priority P set for the group to which each submission queue 25 belongs). The fetch scheduling unit 31 fetches a command from the fetch target submission queue 25. The fetch scheduling unit 31 sends the fetched command to the command processing unit 32.

[0143] The fetch scheduling unit 31 also manages the NAND usage time VT of each of the multiple groups G10, G11, G20, and G22, and the NAND usage time NVT of each of the multiple namespaces NS1 and NS2. For example, a group-NAND usage time management table 52 is used to manage the NAND usage time VT of each of the multiple groups G10, G11, G20, and G22. For example, an NS-NAND usage time management table 53 is used to manage the NAND usage time NVT of each of the multiple namespaces NS1 and NS2.

[0144] The management of the group's NAND usage time VT will now be specifically explained.

[0145] Based on the fetched command, the fetch scheduling unit 31 updates the NAND usage time VT of the group to which the submission queue 25 from which the command was fetched belongs (hereinafter referred to as the belonging group).

[0146] Specifically, the fetch scheduling unit 31 calculates a predicted usage time of the NAND flash memory 4 according to the fetched command. The predicted usage time of the NAND flash memory 4 according to the command is also referred to as a predicted NAND usage time.

[0147] The fetch scheduling unit 31 uses the calculated predicted NAND usage time to update the NAND usage time VT of the belonging group in the group-NAND usage time management table 52. For example, the fetch scheduling unit 31 adds the calculated predicted NAND usage time to the NAND usage time VT of the belonging group in the group-NAND usage time management table 52. Alternatively, the fetch scheduling unit 31 may add a quotient obtained by dividing the calculated predicted NAND usage time by the weight W used for the belonging group to the NAND usage time VT of the belonging group in the group-NAND usage time management table 52.

[0148] An example of a method for calculating a predicted NAND usage time will be described with reference to Fig. 12 and Fig. 13. Here, it is assumed that the write method shown in Fig. 12 is used.

[0149] 12 shows an example of a write method for the NAND flash memory 4. A data write operation for one NAND memory chip 41 may be performed for a single block, or may be performed for multiple blocks included in multiple planes 42 in one NAND memory chip 41. Performing one data write operation for multiple blocks included in multiple planes 42 is also called a multi-plane program. When the NAND memory chip 41 includes multiple planes 42, for example, a multi-plane program is used with emphasis on program performance.

[0150] 12 illustrates a method of writing data in the TLC mode to four blocks 70, 71, 72, and 73 included in four planes 42-0, 42-1, 42-2, and 42-3, respectively, in one data write operation to the NAND memory chip 41. When data is programmed in the TLC mode to each of the four blocks 70, 71, 72, and 73, three pages of data (i.e., lower page data, middle page data, and upper page data) are transferred to each of the four planes 42-0, 42-1, 42-2, and 42-3. The transferred three pages of data are written to the corresponding blocks in the TLC mode. Here, it is assumed that the size of one page of data is 16 KB.

[0151] In this case, 192 KB (= 16 KB × 3 pages × 4 blocks) of data is written in one data write operation to the NAND memory chip 41. In other words, the size of data (write unit) that can be written to the NAND memory chip 41 in one data write operation is 192 KB.

[0152] Furthermore, 16 KB of data (i.e., one page of data) is read in one data read operation from the NAND memory chip 41. In other words, the size of data that can be read from the NAND memory chip 41 in one data read operation (read unit) is 16 KB.

[0153] When the fetch scheduling unit 31 fetches a command from the submission queue 25, it calculates the number of NAND requests to be executed for the NAND memory chip 41 in response to the command.

[0154] For example, when a read command is fetched from the submission queue 25, the fetch scheduling unit 31 calculates the number Nr of read requests to be executed for the NAND memory chip 41 in response to the read command. The size of the user data requested to be read in response to the read command may be smaller than the read unit, or larger than the read unit. The fetch scheduling unit 31 estimates the number Nr of read requests to be executed for the NAND memory chip 41 based on the size of the user data requested to be read in response to the read command and the read unit. The fetch scheduling unit 31 determines the predicted NAND usage time corresponding to the read command based on the estimated number Nr of read requests. Specifically, the fetch scheduling unit 31 calculates, for example, the product of the estimated number Nr of read requests and the read time tR as the predicted NAND usage time corresponding to the read command. The read time tR is the time required for a read operation in response to one read request in the NAND flash memory 4. The read operation is an operation of reading data from the NAND flash memory 4 (more specifically, the memory cell array 421).

[0155] Also, for example, when a write command is fetched from the submission queue 25, the fetch scheduling unit 31 calculates the number Nw of write requests to be executed for the NAND memory chip 41 in response to the write command. The size of user data requested to be written in response to the write command may be smaller than the write unit or larger than the write unit. The fetch scheduling unit 31 estimates the number Nw of write requests to be executed for the NAND memory chip 41 based on the size of user data requested to be written in response to the write command and the write unit. The fetch scheduling unit 31 determines the predicted NAND usage time corresponding to the write command based on the estimated number Nw of write requests. Specifically, the fetch scheduling unit 31 calculates, for example, the product of the estimated number Nw of write requests and the program time tProg as the predicted NAND usage time corresponding to the write command. The program time tProg is the time required for a program operation in the NAND flash memory 4 in response to one write request. The program operation is an operation of writing (programming) data to the NAND flash memory 4. The program time tProg is, for example, longer than the read time tR.

[0156] Fig. 13 shows an example of the relationship between a command and a predicted NAND usage time. More specifically, Fig. 13 shows an example of a NAND access size, a NAND request count, and a predicted NAND usage time corresponding to a command.

[0157] The NAND access size is the size of data in the NAND flash memory 4 that is accessed in response to the corresponding command.

[0158] When the command is a read command, the NAND access size is the size of user data read from the NAND flash memory 4 in response to the read command. Data read from the NAND flash memory 4 in one data read operation is data in a read unit. Therefore, the NAND access size in response to the read command is Nr times the read unit. Nr corresponds to the number of read requests generated based on the read command. Nr is an integer equal to or greater than 1.

[0159] When the command is a write command, the NAND access size is the size of the user data to be written to the NAND flash memory 4 in response to the write command. The data written to the NAND flash memory 4 in one data write operation is data of a write unit. When the size of the user data to be written in response to the write command is smaller than the write unit, the user data is written to the NAND flash memory 4 as data of a write unit including user data to be written in response to one or more other write commands. Therefore, when the user data to be written in response to one or more write commands reaches the write unit, one write request is generated to write the user data of the write unit to the NAND flash memory 4.

[0160] The NAND request count is the number of NAND requests generated based on the corresponding command.

[0161] When the command is a read command, the NAND request number indicates the number Nr of read requests generated based on the read command. One read request requests the NAND flash memory 4 to read user data of a read unit.

[0162] If the command is a write command, the NAND request count indicates the number Nw of write requests generated based on the write command. One write request requests the NAND flash memory 4 to write user data of a write unit. The number Nw of write requests corresponding to a write command is expressed as a ratio of the size of user data to be written in response to the write command to the write unit.

[0163] The predicted NAND usage time is the time that the NAND flash memory 4 is predicted to be used in response to a corresponding command. When the command is a read command, the predicted NAND usage time is calculated as, for example, the product of the number of NAND requests corresponding to the read command (i.e., the number of read requests Nr) and the read time tR. When the command is a write command, the predicted NAND usage time is calculated as, for example, the product of the number of NAND requests corresponding to the write command (i.e., the number of write requests Nw) and the program time tProg.

[0164] The command example shown in Fig. 13 will be specifically described. Here, it is assumed that the read time tR is 50 microseconds (μs) and the program time tProg is 1 millisecond (ms). Also, as in the example shown in Fig. 12, the read unit is 16 KB and the write unit is 192 KB.

[0165] In the case of a read command requesting the reading of 4 KB of user data, the 4 KB of user data requested to be read is smaller than the read unit (16 KB). Therefore, the NAND access size is 16 KB. Since the NAND flash memory 4 is requested to read the read unit of data, the NAND request number Nr is 1. Therefore, the predicted NAND usage time is 50 μs (= tR × Nr = 50 μs × 1).

[0166] In the case of a read command requesting the reading of 16 KB of user data, the 16 KB of user data requested to be read is equal to the read unit (16 KB). Therefore, the NAND access size is 16 KB. Since the NAND flash memory 4 is requested to read the read unit of data, the NAND request count Nr is 1. Therefore, the predicted NAND usage time is 50 μs (= 50 μs × 1).

[0167] In the case of a read command requesting the reading of 128 KB of user data, the 128 KB of user data requested to be read is 8 times the read unit (16 KB). Therefore, the NAND access size is 16 KB x 8. Since the NAND flash memory 4 is requested to read 8 times the read unit of data, the NAND request number Nr is 8. Therefore, the predicted NAND usage time is 400 μs (= 50 μs x 8).

[0168] In the case of a write command requesting the writing of 16 KB of user data, the 16 KB of user data requested to be written is smaller than the write unit (192 KB). Therefore, the NAND access size is 16 KB. This means that the 16 KB of user data is written to the NAND flash memory 4 as 192 KB (write unit) of user data, including 176 KB of user data written in response to one or more other write commands. Therefore, a write request corresponding to this write command corresponds to 1 / 12 (=16 / 192) of one write request requesting the writing of a write unit of data. In other words, the number of NAND requests Nw is 1 / 12. Therefore, the predicted NAND usage time is 84 μs (=tProg×Nw=1000 μs×1 / 12).

[0169] In the case of a write command requesting the writing of 128 KB of user data, the 128 KB of user data requested to be written is smaller than the write unit (192 KB). Therefore, the NAND access size is 128 KB. This means that the 128 KB of user data is written to the NAND flash memory 4 as 192 KB (write unit) of user data combined with 64 KB of user data written in response to one or more other write commands. Therefore, the write request corresponding to this write command corresponds to 2 / 3 (=128 / 192) of one write request requesting the writing of data of the write unit. In other words, the number of NAND requests Nw is 2 / 3. Therefore, the predicted NAND usage time is 667 μs (=1000 μs×2 / 3).

[0170] In the case of a write command requesting the writing of 192 KB of user data, the 192 KB of user data requested to be written is equal to the write unit (192 KB). Therefore, the NAND access size is 192 KB. The write request corresponding to this write command is one write request requesting the writing of the write unit of data. In other words, the NAND request count Nw is 1. Therefore, the predicted NAND usage time is 1000 μs (= 1000 μs × 1).

[0171] In this way, the fetch scheduling unit 31 can estimate the number of NAND requests to be executed to the NAND memory chip 41 in response to a fetched command, and calculate the predicted NAND usage time corresponding to the command. The fetch scheduling unit 31 can manage the NAND usage time VT for each group by updating the NAND usage time VT of the group to which the fetch scheduling unit 31 belongs using the predicted NAND usage time.

[0172] Returning to FIG. 11, management of the NAND usage time NVT of the namespace will be specifically described.

[0173] In response to the update of the NAND usage time VT of the group, the fetch scheduling unit 31 updates the NAND usage time NVT of the namespace associated with the group. Specifically, for example, the fetch scheduling unit 31 uses the group management table 51 to identify the namespace associated with the group (hereinafter referred to as the first target namespace) and identifies all groups associated with the first target namespace. The fetch scheduling unit 31 acquires the NAND usage time VT of all the identified groups from the group-NAND usage time management table 52. The fetch scheduling unit 31 replaces the NAND usage time NVT of the first target namespace in the NS-NAND usage time management table 53 with the sum of the acquired NAND usage times VT of all the groups. This allows the fetch scheduling unit 31 to manage the NAND usage time NVT for each namespace.

[0174] The fetch scheduling unit 31 uses at least one of the NAND usage time VT for each group and the NAND usage time NVT for each namespace to select a fetch target submission queue 25 from the multiple submission queues 25. Specifically, the fetch scheduling unit 31 uses at least one of the NAND usage time VT for each group and the NAND usage time NVT for each namespace to control the priority P at which a command is fetched from each of the multiple submission queues 25. Then, the fetch scheduling unit 31 selects a fetch target submission queue 25 from the multiple submission queues 25 based on the priority P of each of the multiple submission queues 25.

[0175] For example, the fetch scheduling unit 31 sets the same priority P to one or more submission queues 25 assigned to a namespace. The fetch scheduling unit 31 may further set the same priority P to one or more submission queues 25 belonging to a group. For example, the fetch scheduling unit 31 updates the priority P set for each of the multiple groups in response to an update of the NAND usage time NVT of any of the namespaces.

[0176] Two specific examples of the method for controlling the priority P will be described.

[0177] (Method for fair use of NAND flash memory4 among namespaces) For example, when the NAND usage time NVT of a certain namespace is relatively long compared to a plurality of NAND usage times NVT corresponding to a plurality of namespaces, the fetch scheduling unit 31 lowers the priority P of at least one of the groups associated with the namespace by a first value. Note that, when the NAND usage time NVT of a certain namespace is relatively short, the fetch scheduling unit 31 may raise the priority P of at least one of the groups associated with the namespace by a second value. The second value may be equal to or different from the first value.

[0178] Specifically, the fetch scheduling unit 31 calculates the average of the NAND usage times NVT of all namespaces (hereinafter also referred to as the NS average usage time). When the value obtained by subtracting the NS average usage time from the NAND usage time NVT of a certain namespace is greater than a first threshold, the fetch scheduling unit 31 determines that the namespace is one with a relatively long NAND usage time NVT. In this case, the fetch scheduling unit 31 may determine that the namespaces other than the namespace with the relatively long NAND usage time NVT are one with a relatively short NAND usage time NVT.

[0179] Alternatively, if the value obtained by subtracting the NAND usage time NVT of a certain namespace from the NS average usage time is greater than a second threshold, the fetch scheduling unit 31 determines that the namespace is one in which the NAND usage time NVT is relatively short. The second threshold may be equal to or different from the first threshold. In this case, the fetch scheduling unit 31 may determine that the namespaces other than the namespaces in which the NAND usage time NVT is relatively short are one in which the NAND usage time NVT is relatively long.

[0180] For example, the fetch scheduling unit 31 may prohibit fetching of commands from at least one of the submission queues 25 assigned to a namespace having a relatively long NAND usage time NVT. Also, the fetch scheduling unit 31 may enable fetching of commands from at least one of the submission queues 25 assigned to a namespace having a relatively short NAND usage time NVT. Note that the submission queues 25 assigned to a certain namespace are submission queues 25 that belong to a group associated with that namespace.

[0181] In this way, the fetch scheduling unit 31 can reduce the frequency at which commands are fetched from the submission queue 25 assigned to a namespace with a relatively long NAND usage time NVT. Also, the fetch scheduling unit 31 can increase the frequency at which commands are fetched from the submission queue 25 assigned to a namespace with a relatively short NAND usage time NVT. This allows the controller 6 to manage a sufficient number of commands (more specifically, NAND requests based on commands) for each namespace to make the usage of the NAND flash memory 4 fair among the namespaces. Therefore, the controller 6 can improve the fairness of the usage of the NAND flash memory 4 among a plurality of namespaces. Also, the controller 6 can prevent the commands corresponding to a specific namespace from being excessively managed, resulting in the waste of resources of the memory system 3.

[0182] (Method for ensuring fair use of NAND flash memory4 among groups) For example, when the NAND usage time VT of a certain group is relatively long among a plurality of NAND usage times VT corresponding to a plurality of groups associated with a certain namespace, the fetch scheduling unit 31 lowers the priority P of the group by a first value. This namespace is, for example, a namespace with a relatively long NAND usage time NVT.

[0183] For example, when the NAND usage time VT of a certain group is relatively short with respect to a plurality of NAND usage times VT corresponding to a plurality of groups associated with a certain namespace, the fetch scheduling unit 31 may increase the priority P of the group by a second value. This namespace is, for example, a namespace with a relatively long or short NAND usage time NVT.

[0184] Specifically, the fetch scheduling unit 31 calculates the average of the NAND usage times VT of all groups associated with a certain namespace (hereinafter also referred to as the group average usage time). If the value obtained by subtracting the group average usage time from the NAND usage time VT of a certain group is greater than a third threshold, the fetch scheduling unit 31 determines that the group is a group with a relatively long NAND usage time VT. In this case, the fetch scheduling unit 31 may determine that the groups other than the group with the relatively long NAND usage time VT are groups with relatively short NAND usage times VT.

[0185] Alternatively, if the value obtained by subtracting the NAND usage time VT of a certain group from the group average usage time is greater than the fourth threshold, the fetch scheduling unit 31 determines that the group is a group with a relatively short NAND usage time VT. The fourth threshold may be equal to or different from the third threshold. In this case, the fetch scheduling unit 31 may determine that the groups other than the group with the relatively short NAND usage time VT are groups with relatively long NAND usage times VT.

[0186] The fetch scheduling unit 31 may, for example, identify a group having a relatively long NAND usage time VT from among the groups associated with one namespace, and prohibit fetching of commands from the submission queue 25 belonging to the identified group. Also, the fetch scheduling unit 31 may, for example, identify a group having a relatively short NAND usage time VT, and enable fetching of commands from the submission queue 25 belonging to the identified group.

[0187] In this way, the fetch scheduling unit 31 can reduce the frequency at which commands are fetched from the submission queue 25 belonging to a group with a relatively long NAND usage time VT. Also, the fetch scheduling unit 31 can increase the frequency at which commands are fetched from the submission queue 25 belonging to a group with a relatively short NAND usage time VT. This allows the controller 6 to manage a sufficient number of commands for any group associated with a namespace to make the use of the NAND flash memory 4 fair among the groups. Therefore, the controller 6 can improve the fairness of the use of the NAND flash memory 4 among a plurality of groups associated with a namespace. Also, the controller 6 can prevent commands corresponding to a specific group from being excessively managed, resulting in a waste of resources of the memory system 3.

[0188] The command processing unit 32 generates one or more NAND requests based on the command received from the fetch scheduling unit 31 , and stores the requests in the intermediate queue 15 .

[0189] Specifically, for example, when the received command is a read command, the command processing unit 32 converts the logical address specified in the read command into a physical address using the logical-physical address conversion table 50. The command processing unit 32 generates one or more NAND requests (read requests) based on the size of the user data to be read in response to the read command and the read unit of the NAND flash memory 4.

[0190] Furthermore, for example, if the received command is a write command, the command processing unit 32 generates one NAND request (write request) in response to the size of user data to be written in response to one or more write commands including the write command reaching the write unit of the NAND flash memory 4. The size of the user data to be written in response to one or more write commands is, for example, the size of the user data specified in the one or more write commands.

[0191] The command processing unit 32 stores the one or more generated NAND requests in the corresponding intermediate queue 15. The corresponding intermediate queue 15 is the intermediate queue 15 corresponding to the group to which the submission queue 25 from which the command is fetched belongs. For example, a NAND request based on a command fetched from the submission queue 25-0 is stored in the intermediate queue 15-1 corresponding to the group G10 to which the submission queue 25-0 belongs. Also, for example, a NAND request based on a command fetched from the submission queue 25-13 is stored in the intermediate queue 15-4 corresponding to the group G21 to which the submission queue 25-13 belongs.

[0192] Note that the actual NAND usage time corresponding to the command may differ from the NAND usage time corresponding to the command calculated by the fetch scheduling unit 31. In this case, the command processing unit 32 may feed back information for correcting the NAND usage time to the fetch scheduling unit 31. The information for correcting the NAND usage time is also referred to as correction information. A specific example of the correction information will be described below.

[0193] When user data to be read in response to a read command is cached in the read buffer 55 (cache hit), the command processing unit 32 does not need to read the user data from the NAND flash memory 4. In this case, the command processing unit 32 does not generate a NAND request based on the read command. The command processing unit 32 sends, for example, correction information (hereinafter referred to as first correction information) indicating the number of NAND requests that were not generated due to a cache hit to the fetch scheduling unit 31.

[0194] For example, the fetch scheduling unit 31 subtracts the NAND usage time based on the number of NAND requests indicated in the first correction information (=number of NAND requests×read time tR) from the NAND usage time VT of the corresponding group. Alternatively, the fetch scheduling unit 31 may subtract a value obtained by dividing the NAND usage time based on the number of NAND requests indicated in the first correction information by the weight W of the corresponding group from the NAND usage time VT of the group.

[0195] If the logical address specified in the read command is not associated with any physical address in the logical-physical address conversion table 50 (i.e., if the specified logical address corresponds to an unmapped area), the command processing unit 32 does not generate a NAND request based on the read command. The command processing unit 32 sends, for example, correction information (hereinafter referred to as second correction information) indicating the number of NAND requests that were not generated because the specified logical address corresponds to an unmapped area to the fetch scheduling unit 31.

[0196] For example, the fetch scheduling unit 31 subtracts the NAND usage time based on the number of NAND requests indicated in the second correction information (=number of NAND requests×read time tR) from the NAND usage time VT of the corresponding group. Alternatively, the fetch scheduling unit 31 may subtract a value obtained by dividing the NAND usage time based on the number of NAND requests indicated in the second correction information by the weight W of the corresponding group from the NAND usage time VT of the group.

[0197] The fetch scheduling unit 31 may further update the NAND usage time NVT of the namespace to which the group is associated, by using the NAND usage time VT subtracted based on the first correction information or the second correction information.

[0198] When the command received from the fetch scheduling unit 31 is a flash command, the command processing unit 32 generates a NAND request for writing user data corresponding to the accepted write command with padding to the NAND flash memory 4. Writing user data with padding means writing data of a write unit composed of user data stored in the write buffer 54 and data for padding. The command processing unit 32 sends, for example, correction information (hereinafter referred to as third correction information) indicating the number of NAND requests equivalent to the data for padding to the fetch scheduling unit 31.

[0199] For example, the fetch scheduling unit 31 adds the NAND usage time based on the number of NAND requests indicated in the third correction information (=number of NAND requests×program time tProg) to the NAND usage time VT of the corresponding group. Alternatively, the fetch scheduling unit 31 may add a value obtained by dividing the NAND usage time based on the number of NAND requests indicated in the third correction information by the weight W of the corresponding group to the NAND usage time VT of the group.

[0200] The fetch scheduling unit 31 may further update the NAND usage time NVT of the namespace to which the group is associated, by using the NAND usage time VT added based on the third correction information.

[0201] In this way, the fetch scheduling unit 31 can use the correction information provided by the command processing unit 32 to correct the NAND usage time VT of the group or the NAND usage time NVT of the namespace.

[0202] The NAND scheduling unit 33 schedules processing according to the NAND requests stored in the multiple intermediate queues 15. Specifically, the NAND scheduling unit 33 acquires the NAND requests to be processed from the intermediate queue 15 so that the use of the NAND flash memory 4 is fair between the namespaces. Alternatively, the NAND scheduling unit 33 may acquire the NAND requests to be processed from the intermediate queue 15 so that the use of the NAND flash memory 4 is fair between the namespaces and between the groups. The NAND scheduling unit 33 performs processing on the NAND flash memory 4 based on the acquired NAND requests. Note that, when the NAND flash memory 4 includes multiple NAND memory chips 41, the NAND scheduling unit 33 may perform scheduling for each NAND memory chip 41.

[0203] The NAND scheduling unit 33 may feed back information indicating the usage status of the NAND flash memory 4 (hereinafter referred to as usage status information) to the fetch scheduling unit 31. The NAND scheduling unit 33 periodically sends the usage status information based on the number of NAND requests acquired from each intermediate queue 15 within a specific period, for example, to the fetch scheduling unit 31. The specific period is, for example, 50 ms.

[0204] Alternatively, the NAND scheduling unit 33 may send, in response to acquiring L read requests from the intermediate queue 15, usage status information indicating that the L read requests of the group corresponding to the intermediate queue 15 have been processed to the fetch scheduling unit 31. In addition, in response to acquiring M write requests from the intermediate queue 15, the NAND scheduling unit 33 may send, in response to acquiring M write requests from the intermediate queue 15, usage status information indicating that the M write requests of the group corresponding to the intermediate queue 15 have been processed to the fetch scheduling unit 31. L is, for example, greater than M. M is, for example, 1. This is because the program time tProg corresponding to the write request is long, and therefore the processing overhead for feedback of the usage status information indicating that the M write requests have been processed is unlikely to affect the processing of the NAND request by the NAND scheduling unit 33.

[0205] The fetch scheduling unit 31 may correct the NAND usage time VT of the group and the NAND usage time NVT of the namespace, using the usage status information received from the NAND scheduling unit 33. For example, the fetch scheduling unit 31 may subtract the NAND usage time calculated based on the usage status information from the NAND usage time VT of the group.

[0206] The process executed in the memory system 3 will be described with reference to FIGS.

[0207] 14 is a flowchart showing an example of the procedure of the usage time update process executed by the fetch scheduling unit 31. The usage time update process is a process for updating the NAND usage time of the namespace and group corresponding to a submission queue 25 based on a command fetched from the submission queue 25. For example, the fetch scheduling unit 31 executes the usage time update process in response to a command being fetched from any of the submission queues 25. Here, a case is illustrated in which the command fetched from the submission queue 25 is either a write command or a read command. Also, the submission queue 25 from which the command is fetched is referred to as the target submission queue 25.

[0208] First, the fetch scheduling unit 31 determines whether the fetched command is a read command (step S101).

[0209] If the fetched command is a read command (step S101: yes), the fetch scheduling unit 31 calculates the number of NAND requests Nr (i.e., the number of read requests Nr) corresponding to the read command (step S102). The fetch scheduling unit 31 acquires the weight W associated with the group (belonging group) to which the target submission queue 25 belongs from the group management table 51 (step S103).

[0210] The fetch scheduling unit 31 updates the NAND usage time VT of the belonging group by adding the read time × the number of read requests / weight (i.e., tR × Nr / W) to the current NAND usage time VT of the belonging group in the group-NAND usage time management table 52 (step S104), and proceeds to step S105. Specifically, for example, the fetch scheduling unit 31 acquires the current NAND usage time VT of the belonging group from the group-NAND usage time management table 52. The fetch scheduling unit 31 calculates a value by adding the read time × the number of read requests / weight to the acquired current NAND usage time VT. Then, the fetch scheduling unit 31 sets the calculated value as the NAND usage time VT of the belonging group in the group-NAND usage time management table 52.

[0211] If the fetched command is a write command (step S101: no), the fetch scheduling unit 31 calculates the number of NAND requests Nw (i.e., the number of write requests Nw) corresponding to the write command (step S106). The fetch scheduling unit 31 acquires the weight W associated with the group to which the target submission queue 25 belongs (belonging group) from the group management table 51 (step S107).

[0212] The fetch scheduling unit 31 updates the NAND usage time VT of the belonging group by adding the program time × the number of write requests / weight (i.e., tProg × Nw / W) to the current NAND usage time VT of the belonging group in the group-NAND usage time management table 52 (step S108), and proceeds to step S105. Specifically, for example, the fetch scheduling unit 31 acquires the current NAND usage time VT of the belonging group from the group-NAND usage time management table 52. The fetch scheduling unit 31 calculates a value by adding the program time × the number of write requests / weight to the acquired current NAND usage time VT. Then, the fetch scheduling unit 31 sets the calculated value as the NAND usage time VT of the belonging group in the group-NAND usage time management table 52.

[0213] Next, the fetch scheduling unit 31 updates the NAND usage time NVT of the namespace (first target namespace) to which the target submission queue 25 is assigned (step S105), and ends the usage time update process. Specifically, for example, the fetch scheduling unit 31 uses the group management table 51 to identify all groups associated with the first target namespace. The fetch scheduling unit 31 acquires the NAND usage times VT of all the identified groups from the group-NAND usage time management table 52. The fetch scheduling unit 31 calculates the sum of the acquired NAND usage times VT. Then, the fetch scheduling unit 31 sets the calculated sum of the NAND usage times VT as the NAND usage time NVT of the first target namespace in the NS-NAND usage time management table 53.

[0214] Through the above usage time update process, the fetch scheduling unit 31 can update the NAND usage time VT of the group to which the target submission queue 25 belongs and the NAND usage time NVT of the namespace to which the target submission queue 25 is assigned, based on the command fetched from the target submission queue 25.

[0215] Fig. 15 is a flowchart showing an example of the procedure of the priority control process executed by the fetch scheduling unit 31. The priority control process is a process for controlling the fetch priority P of the submission queue 25 based on the NAND usage time NVT for each namespace and the NAND usage time VT for each group. The fetch scheduling unit 31 executes the priority control process, for example, in response to the completion of the usage time update process described above with reference to Fig. 14.

[0216] First, the fetch scheduling unit 31 calculates the average of the NAND usage times NVT of all namespaces (NS average usage time) using the NS-NAND usage time management table 53 (step S201).

[0217] Next, the fetch scheduling unit 31 selects one namespace from the multiple namespaces (step S202). The selected namespace is referred to as a second target namespace. The fetch scheduling unit 31 determines whether the difference between the NAND usage time NVT of the second target namespace and the NS average usage time is greater than a first threshold (step S203).

[0218] If the difference obtained by subtracting the NS average usage time from the NAND usage time NVT of the second target namespace is equal to or less than the first threshold (no in step S203), the fetch scheduling unit 31 increases the priority P of the submission queue 25 assigned to the second target namespace (step S204), and proceeds to step S211. Specifically, the fetch scheduling unit 31 increases the priority P corresponding to each group associated with the second target namespace by a second value in the group management table 51, for example. The group associated with the second target namespace is a group to which the submission queue 25 assigned to the second target namespace belongs. Alternatively, the fetch scheduling unit 31 may enable fetching from the submission queue 25 assigned to the second target namespace, for example.

[0219] If the difference between the NAND usage time NVT of the second target namespace and the NS average usage time is greater than the first threshold (yes in step S203), the fetch scheduling unit 31 calculates the average (group average usage time) of the NAND usage times VT of all groups associated with the second target namespace (step S205).

[0220] Next, the fetch scheduling unit 31 selects one group from one or more groups associated with the second target namespace (step S206). The selected group is referred to as a target group. The fetch scheduling unit 31 determines whether the difference between the NAND usage time VT of the target group and the group average usage time is greater than a third threshold (step S207).

[0221] If the difference obtained by subtracting the group average usage time from the NAND usage time VT of the target group is greater than the third threshold (yes in step S207), the fetch scheduling unit 31 lowers the priority P of the submission queue 25 belonging to the target group (step S208). Specifically, the fetch scheduling unit 31 lowers the priority P corresponding to the target group by a first value in the group management table 51, for example. Alternatively, the fetch scheduling unit 31 may prohibit fetching from the submission queue 25 belonging to the target group.

[0222] If the difference obtained by subtracting the group average usage time from the NAND usage time VT of the target group is equal to or less than the third threshold (no in step S207), the fetch scheduling unit 31 increases the priority P of the submission queue 25 belonging to the target group (step S209). Specifically, the fetch scheduling unit 31 increases the priority P corresponding to the target group by a second value in the group management table 51, for example. Alternatively, the fetch scheduling unit 31 may enable fetching from the submission queue 25 belonging to the target group.

[0223] Next, the fetch scheduling unit 31 determines whether there is another group associated with the second target namespace that has not yet been selected (step S210). If there is another group that has not yet been selected (yes in step S210), the process by the fetch scheduling unit 31 returns to step S206. That is, the fetch scheduling unit 31 further performs a process for controlling the priority P for the another group associated with the second target namespace.

[0224] If all groups associated with the second target namespace have been selected (no in step S210), the process by the fetch scheduling unit 31 proceeds to step S211.

[0225] Next, the fetch scheduling unit 31 determines whether there is another namespace that has not yet been selected (step S211).

[0226] If there is another namespace that has not yet been selected (yes in step S211), the process by the fetch scheduling unit 31 returns to step S202. That is, the fetch scheduling unit 31 further performs a process for controlling the priority P for each group for the submission queues 25 assigned to another namespace.

[0227] If all namespaces have been selected (No in step S211), the fetch scheduling unit 31 ends the priority control process.

[0228] By the above priority control process, the fetch scheduling unit 31 can control the fetch priority P of the submission queue 25 based on the NAND usage time NVT for each namespace and the NAND usage time VT for each group. Specifically, when the condition that the NAND usage time NVT of the namespace to which the submission queue 25 is assigned is longer than the NS average usage time by more than a first threshold value and the NAND usage time VT of the group to which the submission queue 25 belongs is longer than the group average usage time by more than a third threshold value is satisfied, the fetch scheduling unit 31 lowers the priority P of the submission queue 25 belonging to that group, or prohibits fetching from the submission queue 25 belonging to that group. In addition, the fetch scheduling unit 31 raises the priority P of the submission queue 25 belonging to a group that does not satisfy this condition, or enables fetching from the submission queue 25 belonging to that group.

[0229] This allows the fetch scheduling unit 31 to make the usage time of the NAND flash memory 4 fair among the namespaces. Also, the fetch scheduling unit 31 can make the usage time of the NAND flash memory 4 fair among multiple groups associated with one namespace.

[0230] The fetch scheduling unit 31 may be configured to balance the usage of the NAND flash memory 4 between the read operation and the program operation for each namespace. In this case, the fetch scheduling unit 31 manages an index indicating the relationship between the usage of the NAND flash memory 4 in the read operation and the usage of the NAND flash memory 4 in the program operation for each namespace. Hereinafter, this index is referred to as the read-write usage. The fetch scheduling unit 31 calculates, as the read-write usage, a value obtained by, for example, (1) subtracting the processing amount in the NAND flash memory 4 performed in response to a read command fetched from the submission queue 25 assigned to one namespace, and (2) adding the processing amount in the NAND flash memory 4 performed in response to a write command fetched from the submission queue 25 assigned to that namespace. The fetch scheduling unit 31 manages the read-write usage by, for example, using the NS-NAND usage time management table 53.

[0231] Fig. 16 shows another example of the configuration of the NS-NAND usage time management table 53. Each entry of the NS-NAND usage time management table 53 shown in Fig. 16 further includes a read-write usage time field in addition to the NS field and the NAND usage time field described above with reference to Fig. 5.

[0232] The read-write usage time field indicates the read-write usage in the corresponding namespace. Every time a command is fetched from the submission queue 25 assigned to the namespace, the value indicated in the read-write usage time field is updated using the predicted usage of the NAND flash memory 4 according to the command (or the value obtained by dividing the predicted usage by the weight W).

[0233] More specifically, the read-write utilization amount is represented by an index (hereinafter referred to as read-write utilization time RWVT) indicating the relationship between the utilization time of the NAND flash memory 4 in the read operation and the utilization time of the NAND flash memory 4 in the program operation of the corresponding namespace. The read-write utilization time RWVT is represented by a value obtained by, for example, (1) subtracting the utilization time of the NAND flash memory 4 according to the read command fetched from the submission queue 25 assigned to the corresponding namespace from a certain point in time, and (2) adding the utilization time of the NAND flash memory 4 according to the write command fetched from the submission queue 25 assigned to the namespace. Specifically, when a read command is fetched from the submission queue 25 assigned to a namespace, the predicted utilization time of the NAND flash memory 4 according to the read command (or the value obtained by dividing the predicted utilization time by the weight W) is subtracted from the read-write utilization time RWVT corresponding to the namespace. When a write command is fetched from the submission queue 25 assigned to a namespace, the predicted usage time of the NAND flash memory 4 corresponding to the write command (or the value obtained by dividing the predicted usage time by the weight W) is added to the read-write usage time RWVT corresponding to that namespace.

[0234] In the example shown in FIG. 16, the NAND usage time of namespace "1" is NVT1. The read-write usage time of namespace "1" is RWVT1. The NAND usage time of namespace "2" is NVT2. The read-write usage time of namespace "2" is RWVT2.

[0235] 16, the fetch scheduling unit 31 may not use the group-NAND usage time management table 52. In this case, every time a command is fetched from the submission queue 25 assigned to a namespace, the fetch scheduling unit 31 updates the NAND usage time NVT corresponding to the namespace using the predicted NAND usage time corresponding to the command (or a value obtained by dividing the predicted NAND usage time by the weight W). In other words, when the group-NAND usage time management table 52 is not used, the fetch scheduling unit 31 updates the NAND usage time NVT of the corresponding namespace using the predicted NAND usage time corresponding to the fetched command instead of calculating the sum of the NAND usage times VT of all groups associated with the namespace as the NAND usage time NVT of the namespace.

[0236] A process for balancing the use of the NAND flash memory 4 between read operations and program operations in a certain namespace will be described with reference to FIGS.

[0237] 17 is a flowchart showing another example of the usage time update process executed by the fetch scheduling unit 31. The usage time update process is a process for updating the NAND usage time NVT and the read-write usage time RWVT of the namespace corresponding to the submission queue 25 based on a command fetched from the submission queue 25. For example, the fetch scheduling unit 31 executes the usage time update process in response to a command being fetched from any of the submission queues 25. Here, a case is illustrated in which the command fetched from the submission queue 25 is either a write command or a read command.

[0238] First, the fetch scheduling unit 31 determines whether the fetched command is a read command (step S301).

[0239] If the fetched command is a read command (step S301: yes), the fetch scheduling unit 31 calculates the NAND request number Nr (read request number Nr) corresponding to the read command (step S302). The fetch scheduling unit 31 acquires the weight W associated with the group to which the target submission queue 25 belongs from the group management table 51 (step S303).

[0240] The fetch scheduling unit 31 updates the read-write usage time RWVT of the first target namespace by subtracting the read time×number of read requests / weight (i.e., tR×Nr / W) from the current read-write usage time RWVT of the namespace (first target namespace) to which the target submission queue 25 is assigned in the NS-NAND usage time management table 53 (step S304). Specifically, for example, the fetch scheduling unit 31 acquires the current read-write usage time RWVT of the first target namespace from the NS-NAND usage time management table 53. The fetch scheduling unit 31 calculates a value by subtracting the read time×number of read requests / weight from the acquired current read-write usage time RWVT. Then, the fetch scheduling unit 31 sets the calculated value as the read-write usage time RWVT of the first target namespace in the NS-NAND usage time management table 53.

[0241] Next, the fetch scheduling unit 31 updates the NAND usage time NVT of the first target namespace by adding the read time×number of read requests / weight (i.e., tR×Nr / W) to the current NAND usage time NVT of the first target namespace in the NS-NAND usage time management table 53 (step S305), and ends the usage time update process. Specifically, for example, the fetch scheduling unit 31 acquires the current NAND usage time NVT of the first target namespace from the NS-NAND usage time management table 53. The fetch scheduling unit 31 calculates a value by adding the read time×number of read requests / weight to the acquired current NAND usage time NVT. Then, the fetch scheduling unit 31 sets the calculated value as the NAND usage time NVT of the first target namespace in the NS-NAND usage time management table 53.

[0242] If the fetched command is a write command (step S301: no), the fetch scheduling unit 31 calculates the NAND request count Nw (write request count Nw) corresponding to the write command (step S306). The fetch scheduling unit 31 acquires the weight W associated with the group to which the target submission queue 25 belongs from the group management table 51 (step S307).

[0243] The fetch scheduling unit 31 updates the read-write usage time RWVT of the first target namespace by adding the program time × number of write requests / weight (i.e., tProg × Nw / W) to the current read-write usage time RWVT of the first target namespace in the NS-NAND usage time management table 53 (step S308). Specifically, for example, the fetch scheduling unit 31 acquires the current read-write usage time RWVT of the first target namespace from the NS-NAND usage time management table 53. The fetch scheduling unit 31 calculates a value by adding the program time × number of write requests / weight to the acquired current read-write usage time RWVT. Then, the fetch scheduling unit 31 sets the calculated value as the read-write usage time RWVT of the first target namespace in the NS-NAND usage time management table 53.

[0244] Next, the fetch scheduling unit 31 updates the NAND usage time NVT of the first target namespace by adding the program time × number of write requests / weight (i.e., tProg × Nw / W) to the current NAND usage time NVT of the first target namespace in the NS-NAND usage time management table 53 (step S309), and ends the usage time update process. Specifically, for example, the fetch scheduling unit 31 acquires the current NAND usage time NVT of the first target namespace from the NS-NAND usage time management table 53. The fetch scheduling unit 31 calculates a value by adding the program time × number of write requests / weight to the acquired current NAND usage time NVT. Then, the fetch scheduling unit 31 sets the calculated value as the NAND usage time NVT of the first target namespace in the NS-NAND usage time management table 53.

[0245] Through the above utilization time update process, the fetch scheduling unit 31 can update the NAND utilization time NVT and the read-write utilization time RWVT of the namespace to which the target submission queue 25 is assigned, based on the command fetched from the target submission queue 25 .

[0246] In the above utilization time update process, the fetch scheduling unit 31 updates the read-write utilization time RWVT by subtracting read time x number of read requests / weight (step S304) or adding program time x number of write requests / weight (step S308). However, the fetch scheduling unit 31 may update the read-write utilization time RWVT by a first calculation (e.g., addition, multiplication, or division) of read time x number of read requests / weight, or a second calculation (e.g., subtraction, division, or multiplication) of program time x number of write requests / weight. The second calculation is, for example, an inverse calculation of the first calculation.

[0247] Fig. 18 is a flowchart showing an example of the procedure of the priority control process executed by the fetch scheduling unit 31. The priority control process is a process for controlling the fetch priority P of the submission queue 25 based on the NAND usage time NVT and the read-write usage time RWVT for each namespace. The fetch scheduling unit 31 executes the priority control process, for example, in response to the completion of the usage time update process described above with reference to Fig. 17.

[0248] The procedure from step S401 to step S404 is the same as the procedure from step S201 to step S204 of the priority control process described above with reference to Fig. 15. That is, the fetch scheduling unit 31 judges whether the NAND usage time NVT of the selected namespace (second target namespace) is relatively long or not. Then, if the NAND usage time NVT of the second target namespace is relatively short, the fetch scheduling unit 31 increases the priority P of the submission queue 25 assigned to the second target namespace.

[0249] If the NAND usage time NVT of the second target namespace is relatively long, that is, if the difference obtained by subtracting the NS average usage time from the NAND usage time NVT of the second target namespace is greater than the first threshold (yes in step S403), the fetch scheduling unit 31 lowers the priority P of the submission queue 25 assigned to the second target namespace (step S405). Alternatively, the fetch scheduling unit 31 may prohibit the fetching of commands from the submission queue 25 assigned to the second target namespace. Then, the fetch scheduling unit 31 determines whether the read-write usage time RWVT of the second target namespace is greater than a fifth threshold (step S406). The fifth threshold is a value equal to or greater than 0, for example, 0. The read-write usage time RWVT of the second target namespace being greater than the fifth threshold indicates that the NAND usage time by the program operation is longer than the NAND usage time by the read operation in the second target namespace.

[0250] If the read-write usage time RWVT of the second target namespace is greater than the fifth threshold (yes in step S406), the fetch scheduling unit 31 increases the priority P of the read submission queue 25 assigned to the second target namespace (step S407).Then, the fetch scheduling unit 31 decreases the priority P of the write submission queue 25 assigned to the second target namespace (step S408), and proceeds to step S412.

[0251] If the read-write usage time RWVT of the second target namespace is equal to or less than the fifth threshold (no in step S406), the fetch scheduling unit 31 determines whether the read-write usage time RWVT of the second target namespace is less than the sixth threshold (step S409). The sixth threshold is a value equal to or less than 0, for example, 0. The sixth threshold is a value equal to or less than the fifth threshold. For example, the sixth threshold is set to a smaller value in a use case that places importance on reducing the latency regarding a read command. The read-write usage time RWVT of the second target namespace being less than the sixth threshold indicates that the NAND usage time due to a read operation is longer than the NAND usage time due to a program operation in the second target namespace.

[0252] If the read-write usage time RWVT of the second target namespace is less than the sixth threshold (yes in step S409), the fetch scheduling unit 31 increases the priority P of the write submission queue 25 assigned to the second target namespace (step S410).Then, the fetch scheduling unit 31 decreases the priority P of the read submission queue 25 assigned to the second target namespace (step S411), and proceeds to step S412.

[0253] If the read-write utilization time RWVT of the second target namespace is equal to or greater than the sixth threshold value (No in step S409), the process by the fetch scheduling unit 31 proceeds to step S412.

[0254] Next, the fetch scheduling unit 31 determines whether there is another namespace that has not yet been selected (step S412).

[0255] If there is another namespace that has not yet been selected (yes in step S412), the process by the fetch scheduling unit 31 returns to step S402. That is, the fetch scheduling unit 31 further performs a process for controlling the priority P for the submission queue 25 assigned to another namespace.

[0256] If all namespaces have been selected (No in step S412), the fetch scheduling unit 31 ends the priority control process.

[0257] In the above priority control process, the determination of whether the program operation or the read operation has a longer NAND utilization time (steps S406 and S409) can be changed as appropriate depending on the types of first and second operations used to update the read-write utilization time RWVT.

[0258] By the above priority control process, the fetch scheduling unit 31 can make the usage time of the NAND type flash memory 4 fair among the namespaces, and can balance the usage of the NAND type flash memory 4 between the read operation and the program operation in the second target namespace where the NAND usage time NVT is relatively long. Specifically, when the NAND usage time by the program operation is longer than the NAND usage time by the read operation in the second target namespace, the fetch scheduling unit 31 increases the priority P of the read submission queue 25 assigned to the second target namespace, and decreases the priority P of the write submission queue 25. When the NAND usage time by the read operation is longer than the NAND usage time by the program operation in the second target namespace, the fetch scheduling unit 31 increases the priority P of the write submission queue 25 assigned to the second target namespace, and decreases the priority P of the read submission queue 25.

[0259] As described above, the memory system 3 of this embodiment can improve the fairness of use of the non-volatile memory corresponding to a plurality of logical address spaces. The fetch scheduling unit 31 communicates with the host 2 having a plurality of submission queues 25 each capable of storing one or more commands. The fetch scheduling unit 31 provides the host 2 with a plurality of name spaces to which one or more of the plurality of submission queues 25 are respectively assigned. The fetch scheduling unit 31 calculates a plurality of first usage amounts of the NAND flash memory 4 corresponding to the plurality of name spaces, respectively. The fetch scheduling unit 31 selects a first submission queue 25 from which a command should be acquired from the plurality of submission queues 25 based on the plurality of first usage amounts. The fetch scheduling unit 31 acquires the first command from the first submission queue 25. The fetch scheduling unit 31 calculates a predicted usage amount (predicted usage amount) of the NAND flash memory 4 according to the first command. The fetch scheduling unit 31 updates, among the multiple first utilization amounts, the second utilization amount corresponding to the first namespace to which the first submission queue 25 is assigned, using the calculated predicted utilization amount.

[0260] For example, the fetch scheduling unit 31 can store a sufficient number of NAND requests corresponding to the namespace in the intermediate queue 15 by selecting, as the fetch target submission queue 25, a submission queue 25 assigned to a namespace with low usage of the NAND flash memory 4 (or by increasing the frequency of selection as the fetch target submission queue 25). This allows the NAND scheduling unit 33 to schedule the execution of the NAND requests stored in the intermediate queue 15 so that the usage of the NAND flash memory 4 is fair among the namespaces. Therefore, in the memory system 3, the fairness of the usage of the NAND flash memory 4 among multiple namespaces can be improved.

[0261] Furthermore, the fetch scheduling unit 31 can prevent NAND requests corresponding to a namespace that is heavily used in the NAND flash memory 4 from being excessively stored in the intermediate queue 15 and the memory system 3 resources for managing fetched commands from being wasted by not selecting the submission queue 25 assigned to the namespace that is heavily used in the NAND flash memory 4 as the fetch target submission queue 25 (or by reducing the frequency of selecting the submission queue 25 as the fetch target submission queue 25). Therefore, in the memory system 3, the resources for managing commands (for example, the size of the storage area assigned as the intermediate queue 15) can be reduced more than, for example, the memory system 3C of the comparative example.

[0262] Each of the various functions described in this embodiment may be realized by a circuit (processing circuit). An example of a processing circuit includes a programmed processor, such as a central processing unit (CPU). The processor executes each of the described functions by executing a computer program (a set of instructions) stored in a memory. The processor may be a microprocessor including an electric circuit. Examples of the processing circuit include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microcontroller, a controller, and other electric circuit components. Each of the components other than the CPU described in this embodiment may also be realized by a processing circuit.

[0263] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0264] 1...information processing system, 2...host, 3...memory system, 4...NAND flash memory, 5...DRAM, 6...controller, 11...DRAM I / F, 12...SRAM, 13...memory controller, 15...intermediate queue, 16...front-end section, 17...back-end section, 21...CPU, 22...RAM, 25...submission queue, 31...fetch scheduling section, 32...command processing section, 33...NAND scheduling section, 41...NAND memory chip, 42...plane, 421...memory cell array, 50...logical-physical address conversion table, 51...group management table, 52...group-NAND usage time management table, 53...NS-NAND usage time management table, 54...write buffer, 55...read buffer.

Claims

1. A non-volatile memory; communicating with a host having a plurality of queues, each capable of storing one or more commands; a controller configured to provide the host with a plurality of logical address spaces, each of which is assigned to one or more of the plurality of queues; The controller: Calculating a plurality of first usage amounts of the non-volatile memory corresponding to the plurality of logical address spaces, respectively; selecting a first queue from the plurality of queues from which a command should be retrieved based on the plurality of first utilization rates; Obtaining a first command from the first queue; Calculating a predicted usage of the non-volatile memory in response to the first command; a second utilization amount corresponding to a first logical address space to which the first queue is assigned, among the plurality of first utilization amounts, is updated using the predicted utilization amount; Memory system.

2. The controller: controlling a priority for retrieving commands from each of the plurality of queues based on the plurality of first usage amounts; configured to select, from the plurality of queues, a queue from which a command is to be retrieved based on the priority of each of the plurality of queues.

2. The memory system of claim 1.

3. The controller: Calculating a first average usage amount indicating an average of the plurality of first usage amounts; when a difference between the second usage amount and the first average usage amount is greater than a first threshold, a priority of a command to be acquired from at least one of the one or more queues assigned to the first logical address space is lowered.

3. The memory system of claim 2.

4. The controller: Calculating a first average usage amount indicating an average of the plurality of first usage amounts; when a difference between the second usage amount and the first average usage amount is greater than a first threshold, acquisition of a command from at least any of the one or more queues assigned to the first logical address space is prohibited; 2. The memory system of claim 1.

5. The controller: Calculating a number of requests made to the non-volatile memory in response to the first command; and calculating the projected usage based on the calculated number of requests.

2. The memory system of claim 1.

6. If the first command is a read command, the controller: Calculating the number of read requests executed to the non-volatile memory in response to the first command; and calculating the predicted usage amount based on a time required for a read operation in the non-volatile memory in response to the read request and the calculated number of read requests.

6. The memory system of claim 5.

7. If the first command is a write command, the controller: Calculating the number of write requests to be executed to the non-volatile memory in response to the first command; and calculating the predicted usage amount based on a time required for a program operation in the nonvolatile memory in response to the write request and the calculated number of write requests.

6. The memory system of claim 5.

8. The controller further comprises: managing one or more groups to which at least one of the one or more queues assigned to the first logical address space belongs, and one or more third usage amounts of the non-volatile memory corresponding to the one or more groups, respectively; obtaining the first command from the first queue that belongs to a first group of the one or more groups; Calculating the predicted utilization of the non-volatile memory in response to the first command; updating a fourth usage amount corresponding to the first group among the one or more third usage amounts of the non-volatile memory using the predicted usage amount; configured to update the second utilization amount using the fourth utilization amount; 2. The memory system of claim 1.

9. The controller: controlling a priority for retrieving commands from each of the plurality of queues based on the one or more third usage amounts; configured to select, from the plurality of queues, a queue from which a command is to be retrieved based on the priority of each of the plurality of queues.

9. The memory system of claim 8.

10. The controller: Calculating a first average usage amount indicating an average of the plurality of first usage amounts; If a difference between the second usage amount and the first average usage amount is greater than a first threshold, a second average usage amount indicating an average of the one or more third usage amounts is calculated; When a difference between the fourth usage amount and the second average usage amount is greater than a second threshold, a priority for retrieving commands from the at least one queue belonging to the first group is reduced.

10. The memory system of claim 9.

11. The controller: Calculating a first average usage amount indicating an average of the plurality of first usage amounts; If a difference between the second usage amount and the first average usage amount is greater than a first threshold, a second average usage amount indicating an average of the one or more third usage amounts is calculated; when a difference between the fourth usage amount and the second average usage amount is greater than a second threshold, acquisition of a command from the at least one queue belonging to the first group is prohibited.

9. The memory system of claim 8.

12. The controller further comprises: Managing one or more weights corresponding to the one or more groups, respectively; Calculating a number of requests made to the non-volatile memory in response to the first command; calculating the projected usage based on the calculated number of requests and a first weight corresponding to the first group.

9. The memory system of claim 8.

13. If the first command is a read command, the controller: Calculating the number of read requests executed to the non-volatile memory in response to the first command; and calculating the predicted usage amount based on a time required for a read operation in the non-volatile memory in response to the read request, the calculated number of read requests, and the first weight.

13. The memory system of claim 12.

14. If the first command is a write command, the controller: Calculating the number of write requests to be executed to the non-volatile memory in response to the first command; and calculating the predicted usage amount based on a time required for a program operation in the nonvolatile memory in response to the write request, the calculated number of write requests, and the first weight.

13. The memory system of claim 12.

15. the controller is configured to update the fourth usage amount by adding the predicted usage amount to the fourth usage amount.

15. A memory system according to any one of claims 8 to 14.

16. a volatile memory including one or more storage areas each corresponding to one or more groups; The controller further comprises: generating one or more requests to be performed on the non-volatile memory in response to the first command; configured to store the one or more requests in a first storage area of ​​the one or more storage areas, the first storage area corresponding to the first group; 9. The memory system of claim 8.

17. The controller further comprises: Obtaining a request from the one or more storage areas; configured to execute a process corresponding to the acquired request on the non-volatile memory; 17. The memory system of claim 16.

18. each of the plurality of queues is used for either storing a read command or storing a write command; The controller further comprises: managing a read-write utilization amount that indicates a relationship between a utilization amount of the nonvolatile memory in response to a read command and a utilization amount of the nonvolatile memory in response to a write command, the read-write utilization amount corresponding to the first logical address space; if the first command is a read command, calculate a number of read requests to be executed with respect to the non-volatile memory in response to the first command, and calculate the predicted utilization amount based on a time required for a read operation in the non-volatile memory in response to the read requests and the calculated number of read requests; If the first command is a write command, calculate a number of write requests to be executed with respect to the non-volatile memory in response to the first command, and calculate the predicted utilization amount based on a time required for a program operation in the non-volatile memory in response to the write requests and the calculated number of write requests; updating the read-write utilization with the calculated predicted utilization; and controlling, based on the updated read-write utilization amount, a priority for obtaining a command from a queue used for storing read commands and a priority for obtaining a command from a queue used for storing write commands, among the one or more queues assigned to the first logical address space.

3. The memory system of claim 2.

19. each of the plurality of queues is used for either storing a read command or storing a write command; The controller further comprises: managing a read-write utilization amount that indicates a relationship between a utilization amount of the nonvolatile memory in response to a read command and a utilization amount of the nonvolatile memory in response to a write command, the read-write utilization amount corresponding to the first logical address space; if the first command is a read command, calculate a number of read requests to be executed for the non-volatile memory in response to the first command, calculate the predicted utilization amount based on a time required for a read operation in the non-volatile memory in response to the read requests and the calculated number of read requests, and subtract the predicted utilization amount from the read-write utilization amount; if the first command is a write command, calculate a number of write requests to be executed for the non-volatile memory in response to the first command, calculate the predicted utilization amount based on a time required for a program operation in the non-volatile memory in response to the write requests and the calculated number of write requests, and add the predicted utilization amount to the read-write utilization amount; if the read-write utilization is greater than a third threshold, increasing a first priority for commands to be obtained from a queue used to store read commands among the one or more queues assigned to the first logical address space and decreasing a second priority for commands to be obtained from a queue used to store write commands; if the read-write utilization is less than a fourth threshold, the fourth threshold being less than or equal to the third threshold, decreasing the first priority and increasing the second priority.

3. The memory system of claim 2.

20. each of the plurality of queues is used for either storing a read command or storing a write command; The controller further comprises: managing a read-write utilization amount that indicates a relationship between a utilization amount of the nonvolatile memory in response to a read command and a utilization amount of the nonvolatile memory in response to a write command, the read-write utilization amount corresponding to the first logical address space; if the first command is a read command, calculate a number of read requests to be executed for the non-volatile memory in response to the first command, calculate the predicted utilization amount based on a time required for a read operation in the non-volatile memory in response to the read requests and the calculated number of read requests, and subtract the predicted utilization amount from the read-write utilization amount; if the first command is a write command, calculate a number of write requests to be executed for the non-volatile memory in response to the first command, calculate the predicted utilization amount based on a time required for a program operation in the non-volatile memory in response to the write requests and the calculated number of write requests, and add the predicted utilization amount to the read-write utilization amount; if the read-write utilization is greater than a third threshold, increasing a first priority for commands to be obtained from a queue used to store read commands among the one or more queues assigned to the first logical address space and decreasing a second priority for commands to be obtained from a queue used to store write commands; if the read-write utilization is less than a fourth threshold, the fourth threshold being less than or equal to the third threshold, decreasing the first priority and increasing the second priority.

4. The memory system of claim 3.

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