Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device with increased reliability, in which the variation in damage tolerance under a condition with large current flow is reduced.SOLUTION: A semiconductor device includes a transistor formed on a semiconductor substrate having a first main surface and a second main surface. A transistor region of the semiconductor substrate includes a first semiconductor layer of an n-type, a second semiconductor layer of a p-type provided on a first main surface side relative to the first semiconductor layer, a third semiconductor layer of the n-type provided on the first main surface side relative to the second semiconductor layer, a trench gate that reaches the inside of the first semiconductor layer while penetrating the third semiconductor layer and the second semiconductor layer from the first main surface in a thickness direction, and an interlayer insulating film provided on the trench gate. The interlayer insulating film includes at least one narrow part, which is a part whose length in a width direction intersecting with an extending direction of the trench gate in a plan view is partially narrow.SELECTED DRAWING: Figure 23

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a trench gate. [Background technology]

[0002] Patent Document 1 discloses, as an example of a switching device having a trench gate, an insulated gate bipolar transistor (IGBT) in which, in FIG. 1, an emitter layer connected to an emitter electrode is formed in a stripe shape in a direction intersecting the extension direction of the trench gate.

[0003] An interlayer insulating film is formed on the upper portion of the trench gate, and a plurality of contact regions are formed between adjacent trench gates along the extension direction of the trench gate.

[0004] The length in the left-right direction of the interlayer insulating film, i.e., the width, is formed so that it is larger in the area where the emitter layer is provided than in the area where the emitter layer is not provided, and the planar shape of the interlayer insulating film has repeated unevenness on the left and right along the trench gate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2008-91491 A Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, in the conventional technology, the width of the interlayer insulating film where the emitter layer is provided is increased to narrow the contact portion between the emitter electrode and the emitter layer, thereby suppressing the current even when a large current flows during a short circuit, thereby improving reliability.

[0007] In such conventional semiconductor devices, the contact portion between the emitter electrode and the emitter layer is narrow, which narrows the current path when the IGBT is on, resulting in an increase in on-resistance and therefore an increase in transistor loss.

[0008] The present disclosure has been made to solve the above problems, and aims to provide a semiconductor device with improved reliability by reducing variations in gate insulation breakdown resistance, reverse bias safe operating area (RBSOA), and breakdown resistance under conditions where a large current flows, such as in short circuit tests, without narrowing the current path when the IGBT is on. [Means for solving the problem]

[0009] a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first main surface side of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on the first main surface side of the second semiconductor layer and electrically connected to the first main electrode; a trench gate extending from the first main surface through the third semiconductor layer and the second semiconductor layer in a thickness direction to reach inside the first semiconductor layer; and an interlayer insulating film provided on the trench gate, the interlayer insulating film having at least one narrow portion whose length in a width direction intersecting an extension direction of the trench gate in a plan view is partially narrowed, and the width direction length of the narrow portion is longer than the width direction length of the trench gate. Effect of the Invention

[0010] According to the semiconductor device of the present disclosure, the interlayer insulating film has at least one narrow width portion, thereby making it possible to provide a semiconductor device with improved reliability by reducing the variation in breakdown resistance under conditions in which a large current flows without narrowing the current path when the transistor is on. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a semiconductor device which is an RC-IGBT. [Diagram 2] FIG. 1 is a plan view showing a semiconductor device which is an RC-IGBT. [Diagram 3] FIG. 2 is a partial plan view of an IGBT region in the RC-IGBT. [Figure 4] FIG. 2 is a partial cross-sectional view of an IGBT region in an RC-IGBT. [Diagram 5] FIG. 2 is a partial cross-sectional view of an IGBT region in an RC-IGBT. [Figure 6] FIG. 2 is a partial plan view of a diode region in the RC-IGBT. [Figure 7] FIG. 2 is a partial cross-sectional view of a diode region in an RC-IGBT. [Figure 8] FIG. 2 is a partial cross-sectional view of a diode region in an RC-IGBT. [Figure 9] FIG. 2 is a cross-sectional view of a boundary between an IGBT region and a diode region of an RC-IGBT. [Figure 10] FIG. 2 is a cross-sectional view of a boundary between an IGBT region and a termination region of an RC-IGBT. [Figure 11] FIG. 2 is a cross-sectional view of a boundary between an IGBT region and a termination region of an RC-IGBT. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 13] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 14] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 15] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 18] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 20] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 21] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 22] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 23] 1 is a partial plan view showing a configuration of an RC-IGBT according to a first embodiment. [Figure 24] 10 is an overall plan view showing the configuration of an RC-IGBT according to a second embodiment. FIG. [Diagram 25] FIG. 11 is a cross-sectional view showing a configuration of an RC-IGBT according to a second embodiment. [Figure 26] FIG. 11 is a cross-sectional view showing a configuration of an RC-IGBT according to a second embodiment. [Figure 27] FIG. 11 is a diagram illustrating a configuration of an RC-IGBT according to a second embodiment. [Figure 28] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Figure 29] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 30] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 31] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 32] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 33] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 34]10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 35] 10A to 10C are cross-sectional views showing a manufacturing process of the RC-IGBT according to the second embodiment. [Diagram 36] FIG. 11 is a partial plan view showing the configuration of an RC-IGBT according to a third embodiment. [Figure 37] 13 is an enlarged view of a narrow width portion of the RC-IGBT according to the third embodiment. FIG. [Figure 38] FIG. 11 is a cross-sectional view of a narrow width portion of an RC-IGBT according to a third embodiment. [Figure 39] FIG. 11 is a partial plan view showing the configuration of an RC-IGBT according to a fourth embodiment. [Diagram 40] 13 is a flowchart illustrating a manufacturing method of an RC-IGBT according to the fifth embodiment. [Diagram 41] 13A to 13C are diagrams illustrating a manufacturing method of an RC-IGBT according to the fifth embodiment. [Diagram 42] 13A to 13C are diagrams illustrating a manufacturing method of an RC-IGBT according to the fifth embodiment. [Diagram 43] 13A to 13C are diagrams illustrating a manufacturing method of an RC-IGBT according to the fifth embodiment. [Diagram 44] 13A to 13C are diagrams illustrating a manufacturing method of an RC-IGBT according to the fifth embodiment. [Diagram 45] 13A to 13C are diagrams illustrating a manufacturing method of an RC-IGBT according to the fifth embodiment. [Figure 46] 13 is a flowchart illustrating another manufacturing method of the RC-IGBT according to the fifth embodiment. [Figure 47] FIG. 13 is a diagram showing an exposure pattern when the resist material is a positive type. [Figure 48] FIG. 2 is a diagram showing a resist mask pattern obtained by exposing a positive resist material. [Figure 49] 10A to 10C are cross-sectional views showing another method for manufacturing the step portion. [Figure 50] 10A to 10C are cross-sectional views showing another method for manufacturing the step portion. [Figure 51] 10A to 10C are cross-sectional views showing another method for manufacturing the step portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors. In this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - The n-type impurity concentration is lower than that of the n-type. + The term p-type indicates that the impurity concentration is higher than that of n-type. - The impurity concentration is lower than that of p-type, and p + The n-type indicates that the impurity concentration is higher than that of the p-type.

[0013] In addition, the drawings are shown diagrammatically, and the size and positional relationship of the images shown in different drawings are not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description thereof may be omitted.

[0014] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used; however, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not relate to the directions in which the embodiments are actually implemented.

[0015] Prior to describing the embodiments, a reverse conducting IGBT (RC-IGBT) in which an IGBT and a free wheeling diode (FWD) are provided on a common semiconductor substrate will be described below.

[0016] Fig. 1 is a plan view showing a semiconductor device that is an RC-IGBT. Fig. 2 is a plan view showing a semiconductor device that is an RC-IGBT with another configuration. The semiconductor device 100 shown in Fig. 1 has IGBT regions 10 and diode regions 20 arranged in a stripe pattern, and may be simply called a "striped type." The semiconductor device 101 shown in Fig. 2 has a plurality of diode regions 20 arranged vertically and horizontally, and the IGBT regions 10 are arranged around the diode regions 20, and may be simply called an "island type."

[0017] (1) Stripe-type overall planar structure In FIG. 1, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 in one semiconductor device. The IGBT region 10 and the diode region 20 extend from one end side to the other end side of the semiconductor device 100, and are alternately provided in stripes in a direction perpendicular to the extending direction of the IGBT region 10 and the diode region 20. In FIG. 1, three IGBT regions 10 and two diode regions are shown, and all the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of the IGBT regions 10 and the diode regions 20 is not limited to this, and the number of the IGBT regions 10 may be three or more or less, and the number of the diode regions 20 may be two or more or less. In addition, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 1 may be interchanged, and all the IGBT regions 10 may be sandwiched between the diode regions 20. In addition, the IGBT regions 10 and the diode regions 20 may be provided adjacent to each other.

[0018] As shown in FIG. 1, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the page. The pad region 40 is a region where a control pad 410 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing an FLR (Field Limiting Ring) that surrounds the cell region with a p-type termination well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer with a concentration gradient on the first main surface side, which is the front surface side of the semiconductor device 100, and the number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell and a diode cell may be provided in the pad region 40.

[0019] The control pad 410 may be, for example, a current sense pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, or temperature sense diode pads 410d and 410e. The current sense pad 410a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a part of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is a fraction to a fraction of a few ten thousandths of the current flowing in the entire cell region flows.

[0020] The Kelvin emitter pad 410b and the gate pad 410c are control pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 100. The Kelvin emitter pad 410b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 410c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 410b and the p-type base layer are +The temperature sensing diode pads 410d and 410e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0021] (2) Island-type overall plan structure In Fig. 2, the semiconductor device 101 includes an IGBT region 10 and a diode region 20 within one semiconductor device. A plurality of diode regions 20 are arranged in the vertical and horizontal directions within the semiconductor device, and the diode regions 20 are surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are provided in an island shape within the IGBT region 10. In Fig. 2, the diode regions 20 are shown in a configuration in which they are provided in a matrix shape with four columns in the left-right direction of the paper and two rows in the upper-right direction of the paper, but the number and arrangement of the diode regions 20 are not limited thereto, and it is sufficient that one or a plurality of diode regions 20 are provided in a scattered manner within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0022] As shown in FIG. 2, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 410 for controlling the semiconductor device 101 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 101. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing an FLR (Field Limiting Ring) that surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer with a concentration gradient on the first main surface side, which is the front surface side of the semiconductor device 101, and the number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 101. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell and a diode cell may be provided in the pad region 40.

[0023] The control pad 410 may be, for example, a current sense pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, or temperature sense diode pads 410d and 410e. The current sense pad 410a is a control pad for detecting a current flowing in a cell region of the semiconductor device 101, and is electrically connected to a part of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 101, a current that is a fraction to a fraction of a few ten thousandths of the current flowing in the entire cell region flows.

[0024] The Kelvin emitter pad 410b and the gate pad 410c are control pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 101. The Kelvin emitter pad 410b is connected to the p-type base layer and n-type base layer of the IGBT cell. +The Kelvin emitter pad 410b and the p-type base layer are electrically connected to the p-type source layer, and the gate pad 410c is electrically connected to the gate trench electrode of the IGBT cell. + The temperature sensing diode pads 410d and 410e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0025] (3) General structure of IGBT region 10 Fig. 3 is a partially enlarged plan view showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Fig. 4 and Fig. 5 are cross-sectional views showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Fig. 3 is an enlarged view of a region 82 surrounded by a dashed line in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. Fig. 4 is a cross-sectional view of the semiconductor device 100 shown in Fig. 3 or the semiconductor device 101 shown in Fig. 2 in the direction indicated by the arrows taken along dashed line AA, and Fig. 5 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 3 in the direction indicated by the arrows taken along dashed line BB.

[0026] 3, the active trench gates 11 and the dummy trench gates 12 are provided in a stripe pattern in the IGBT region 10. In the semiconductor device 100, the active trench gates 11 and the dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to the longitudinal direction of the active trench gates 11 and the dummy trench gates 12. On the other hand, in the semiconductor device 101, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, but the longitudinal direction of the active trench gates 11 and the dummy trench gates 12 may be the left-right direction of the paper, or the vertical direction of the paper may be the longitudinal direction of the active trench gates 11 and the dummy trench gates 12.

[0027] The active trench gate 11 is configured by providing a gate trench electrode 11a through a gate trench insulating film 11b in a trench formed in a semiconductor substrate. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a through a dummy trench insulating film 12b in a trench formed in a semiconductor substrate. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 410c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0028] n + The n-type source layer 13 is provided on both sides of the active trench gate 11 in the width direction in contact with the gate trench insulating film 11b. + The source layer 13 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 n + The p-type source layer 13 is arranged along the extension direction of the active trench gate 11. + The contact layers 14 are alternately arranged. + The contact layer 14 is also provided between two adjacent dummy trench gates 12. + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 It is.

[0029] As shown in FIG. 3, in the IGBT region 10 of the semiconductor device 100 or the semiconductor device 101, three active trench gates 11 are arranged next to three dummy trench gates 12, and three active trench gates 11 are arranged next to three dummy trench gates 12. In this way, the IGBT region 10 is configured such that a set of active trench gates 11 and a set of dummy trench gates 12 are arranged alternately. In FIG. 3, the number of active trench gates 11 included in one set of active trench gates 11 is three, but it may be one or more. In addition, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be one or more, and the number of dummy trench gates 12 may be zero. In other words, all of the trenches provided in the IGBT region 10 may be active trench gates 11.

[0030] 4 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dashed line AA in FIG. 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 includes a second semiconductor layer made of a semiconductor substrate, i.e., a n-type semiconductor layer. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 In FIG. 4, the semiconductor substrate is + The source layer 13 and the p + The n-type contact layer 14 extends from the p-type collector layer 16. + The source layer 13 and the p + The upper end of p-type contact layer 14 on the page is called the first main surface of the semiconductor substrate, and the lower end of p-type collector layer 16 on the page is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of semiconductor device 100. In IGBT region 10, which is the cell region, semiconductor device 100 has an n-type interlayer insulating film between the first main surface and the second main surface facing the first main surface. -The semiconductor device has a type drift layer 1.

[0031] As shown in FIG. 4, in the IGBT region 10, - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 13 / cm 3 ~1.0×10 17 / cm 3 In the semiconductor device 100 or the semiconductor device 101, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 region shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The above-mentioned layer and the type drift layer 1 may be collectively referred to as a drift layer.

[0032] The n-type carrier accumulation layer 2 is - The n-type impurity is ion-implanted into the semiconductor substrate constituting the n-type drift layer 1, and then annealed to convert the implanted n-type impurity into n - The doped region is formed by diffusing the doped region into the semiconductor substrate, which is the doped drift layer 1.

[0033] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, an n-type + A p-type source layer 13 is provided in the remaining region. +A contact layer 14 is provided. + The source layer 13 and the p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0034] In addition, the semiconductor device 100 or the semiconductor device 101 has n - On the second main surface side of the n-type drift layer 1, - An n-type buffer layer 3 having a higher concentration of n-type impurities than the p-type drift layer 1 is provided. The n-type buffer layer 3 is provided to suppress punch-through of a depletion layer extending from the p-type base layer 15 to the second main surface side when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) may be injected to form phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both n-type impurities. 12 / cm 3 ~1.0×10 18 / cm 3 It is.

[0035] In the semiconductor device 100 or 101, the n-type buffer layer 3 is not provided, and the n-type buffer layer 3 shown in FIG. - The n-type drift layer 1 may be provided. - The above-mentioned layer and the type drift layer 1 may be collectively referred to as a drift layer.

[0036] In the semiconductor device 100 or 101, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. -A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 constitutes a p-type termination collector layer 16a. The p-type collector layer 16 may be provided so that a portion of it protrudes from the IGBT region 10 into the diode region 20.

[0037] As shown in FIG. 4, the semiconductor device 100 or the semiconductor device 101 has an n-type semiconductor layer extending from a first main surface of a semiconductor substrate through a p-type base layer 15. - A trench is formed so as to reach the n-type drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming an active trench gate 11. The gate trench electrode 11a is connected to the n-type drift layer 1 through the gate trench insulating film 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. A dummy trench electrode 12a is provided in the trench via a dummy trench insulating film 12b, thereby forming a dummy trench gate 12. The dummy trench electrode 12a is connected to the n-type drift layer 1 by the dummy trench insulating film 12b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0038] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), and may be, for example, titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is a n + Type source layer 13, p + ohmic contact with the contact layer 14 and the dummy trench electrode 12a, + Type source layer 13, p + The barrier metal 5 is electrically connected to the contact layer 14 and the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. In addition, when there is a fine region between adjacent interlayer insulating films 4 where the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, may be disposed in the fine region, and the emitter electrode 6 may be provided on the tungsten. Note that, in the case where the barrier metal 5 is not provided and n + Type source layer 13, p + An emitter electrode 6 may be provided on the contact layer 14 and the dummy trench electrode 12a. +The barrier metal 5 may be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode. Note that, although FIG. 4 shows a diagram in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0039] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 6. The collector electrode 7 may have a different configuration from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0040] 5 is a cross-sectional view of the semiconductor device 100 or 101 taken along the dashed line BB in FIG. 3, and is a cross-sectional view of the IGBT region 10. The cross-sectional view taken along the dashed line AA in FIG. 4 is a cross-sectional view of the n-type IGBT region 10 provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11. + 5. The difference is that the n-type source layer 13 is not seen in the cross section taken along the dashed line BB in FIG. + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as the p-type base layer.

[0041] (4) General structure of diode region 20 Fig. 6 is a partially enlarged plan view showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Figs. 7 and 8 are cross-sectional views showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Fig. 6 is an enlarged view of a region 83 surrounded by a dashed line in the semiconductor device 100 or the semiconductor device 101 shown in Fig. 1. Fig. 7 is a cross-sectional view in the direction indicated by the arrow at dashed line CC of the semiconductor device 100 shown in Fig. 6. Fig. 8 is a cross-sectional view in the direction indicated by the arrow at dashed line DD of the semiconductor device 100 shown in Fig. 6.

[0042] The diode trench gate 21 extends from one end side of the diode region 20, which is a cell region, to the opposing other end side along the first main surface of the semiconductor device 100 or the semiconductor device 101. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The p-type drift layer 1 is opposed to the p-type drift layer 1. + A p-type contact layer 24 and a p-type anode layer 25, which is a third semiconductor layer, are provided. + The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 It is. + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0043] 7 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dashed line CC in FIG. 6, and is a cross-sectional view of the diode region 20. In the semiconductor device 100 or the semiconductor device 101, the diode region 20 is also an n-type semiconductor substrate, similar to the IGBT region 10. - The n-type drift layer 1 of the diode region 20 - n-type drift layer 1 and IGBT region 10 - The p-type drift layer 1 is integrally formed and is made of the same semiconductor substrate. + The first semiconductor layer is a + The area is the area up to the cathode layer 26. + The upper end of the n-type contact layer 24 in the drawing corresponds to the first main surface of the semiconductor substrate. + The lower end of the type cathode layer 26 on the page is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0044] As shown in FIG. 7, in the diode region 20, similarly to the IGBT region 10, - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. It is not necessarily required to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the diode region 20 may not be provided with the n-type carrier accumulation layer 2. As with the IGBT region 10, - The n-type drift layer 1, the n-type carrier accumulation layer 2 and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0045] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is - The p-type anode layer 25 is provided between the first main surface and the drift layer 1. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. The p-type anode layer 25 may have a lower p-type impurity concentration than the p-type base layer 15 of the IGBT region 10, so as to reduce the amount of holes injected into the diode region 20 during diode operation. Reducing the amount of holes injected during diode operation can reduce recovery loss during diode operation.

[0046] The first main surface side of the p-type anode layer 25 is + A contact layer 24 is provided. + The concentration of the p-type impurity in the contact layer 24 is + The concentration of the p-type impurity in the p-type contact layer 14 may be the same as or different from the p-type impurity in the p-type contact layer 14. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. + When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be referred to individually. + The p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0047] In the diode region 20, on the second main surface side of the n-type buffer layer 3, + A cathode layer 26 is provided. + The cathode layer 26 is an n-type - The n-type drift layer 1 and the n-type drift layer 2 are disposed between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm3 As shown in Figure 2, n + The cathode layer 26 is provided on a part or the whole of the diode region 20. + The n-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. + The p-type impurity is further selectively implanted into the region where the n-type cathode layer 26 is formed. + A part of the region where the cathode layer 26 is formed is made into a p-type semiconductor. + A type cathode layer may be provided. + Type cathode layer and p + A diode in which the first and second cathode layers are alternately arranged along the second main surface of the semiconductor substrate is called an RFC (Relaxed Field of Cathode) diode.

[0048] As shown in FIG. 7, in the diode region 20 of the semiconductor device 100 or the semiconductor device 101, a semiconductor device having an n-type anode layer 25 is formed. - A trench is formed so as to reach the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor device 1 faces the drift layer 1 .

[0049] As shown in FIG. 7, the diode trench electrodes 21a and p + A barrier metal 5 is provided on the contact layer 24. The barrier metal 5 is a metal that covers the diode trench electrode 21a and the p + The diode trench electrode and the p-type contact layer 24 are in ohmic contact with each other. +The diode trench electrodes 21a and p-type contact layer 24 are electrically connected to the barrier metal 5. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the barrier metal 5 is not provided and the diode trench electrodes 21a and p-type contact layer 24 are electrically connected to the barrier metal 5. + The contact layer 24 and the emitter electrode 6 may be in ohmic contact with each other. Although FIG. 7 shows a diagram in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0050] n + A collector electrode 7 is provided on the second principal surface side of the n-type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is + ohmic contact to the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 and also functions as a cathode electrode.

[0051] 8 is a cross-sectional view of the semiconductor device 100 or 101 taken along the dashed line DD in FIG. 6, and is a cross-sectional view of the diode region 20 taken along the dashed line CC in FIG. 7. + The difference is that the p-type contact layer 24 is not provided, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. + The type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25 .

[0052] (5) Boundary region between IGBT region 10 and diode region 20 9 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT, taken along the arrow direction of dashed line GG in the semiconductor device 100 or 101 shown in FIG.

[0053] 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to protrude into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type collector layer 16 so as to protrude into the diode region 20, + The distance between the type cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during the freewheeling diode operation, n-type + This can suppress current from flowing through the type cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or 101 that is an RC-IGBT, the distance U1 may be zero or less than 100 μm.

[0054] (6) General Structure of Termination Region 30 Fig. 10 and Fig. 11 are cross-sectional views showing the configuration of a termination region of a semiconductor device that is an RC-IGBT. Fig. 10 is a cross-sectional view in the direction indicated by the arrows taken along dashed line EE in Fig. 1 or 2, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 11 is a cross-sectional view in the direction indicated by the arrows taken along dashed line FF in Fig. 1, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0055] As shown in FIGS. 10 and 11, the termination region 30 of the semiconductor device 100 has n-type junctions between the first and second main surfaces of the semiconductor substrate. -The termination region 30 has a n-type drift layer 1. The first and second main surfaces of the termination region 30 are flush with the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. - The n-type drift layer 1 is formed in the IGBT region 10 and the diode region 20. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0056] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate - A p-type termination well layer 31 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a plurality of ring shapes, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100 or the semiconductor device 101. In addition, on the outer edge side of the p-type termination well layer 31, + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 .

[0057] n -A p-type termination collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally and continuously with the p-type collector layer 16 provided in the cell region. Therefore, the p-type termination collector layer 16a may be collectively referred to as the p-type collector layer 16. In a configuration in which the diode region 20 is provided adjacent to the termination region 30 as in the semiconductor device 100 shown in FIG. 1, the end of the p-type termination collector layer 16a on the diode region 20 side is provided protruding into the diode region 20 by a distance U2 as shown in FIG. 11. In this way, by providing the p-type termination collector layer 16a protruding into the diode region 20, the n-type collector layer 16a of the diode region 20 can be reduced. + This allows the distance between the type cathode layer 26 and the p-type termination well layer 31 to be increased, thereby preventing the p-type termination well layer 31 from acting as an anode of a diode. The distance U2 may be, for example, 100 μm.

[0058] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is continuously and integrally formed from a cell region including the IGBT region 10 and the diode region 20 to the termination region 30. On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30.

[0059] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. + The emitter electrode 6 is electrically connected to the semiconductor device channel stopper layer 32 via a contact hole formed in an interlayer insulating film 4 provided on the first main surface of the termination region 30. A termination protective film 34 is provided in the termination region 30 to cover the emitter electrode 6, the termination electrode 6a and the semi-insulating film 33. The termination protective film 34 may be made of, for example, polyimide.

[0060] (7) Typical manufacturing method for RC-IGBT Fig. 12 to Fig. 22 are diagrams showing a method for manufacturing a semiconductor device which is an RC-IGBT. Fig. 12 to Fig. 19 are diagrams showing steps for forming the front surface side of the semiconductor device 100 or the semiconductor device 101, and Fig. 20 to Fig. 22 are diagrams showing steps for forming the back surface side of the semiconductor device 100 or the semiconductor device 101.

[0061] First, as shown in Figure 12, - A semiconductor substrate constituting the n-type drift layer 1 is prepared. The semiconductor substrate may be, for example, a so-called FZ wafer produced by the FZ (Floating Zone) method or a so-called MCZ wafer produced by the MCZ (Magnetic field applied Czochralski) method, and may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the withstand voltage of the semiconductor device to be produced. For example, in a semiconductor device with a withstand voltage of 1200 V, the n-type impurities constituting the semiconductor substrate may be selected from the n-type impurities. - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is about 40 to 120 Ω·cm. As shown in FIG. 12, in the step of preparing a semiconductor substrate, the entire semiconductor substrate is - In the semiconductor device 100 or 101, a p-type or n-type semiconductor layer is formed by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of the semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like, thereby manufacturing the semiconductor device 100 or 101.

[0062] As shown in Figure 12, n -The semiconductor substrate constituting the drift layer 1 includes a region that will become the IGBT region 10 and the diode region 20. Although not shown, a region that will become the termination region 30 is provided around the region that will become the IGBT region 10 and the diode region 20. In the following, a manufacturing method for the configuration of the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101 will be mainly described, but the termination region 30 of the semiconductor device 100 or the semiconductor device 101 may be manufactured by a known manufacturing method. For example, when an FLR having a p-type termination well layer 31 as a breakdown voltage holding structure is formed in the termination region 30, it may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, or it may be formed by implanting p-type impurity ions at the same time as implanting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0063] Next, as shown in FIG. 13, an n-type impurity such as phosphorus (P) is implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Also, a p-type impurity such as boron (B) is implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, the p-type base layer 15 and the p-type anode layer 25 are formed by injecting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurity and the p-type impurity are selectively formed on the first main surface side of the semiconductor substrate because they are ion-implanted after a mask process is applied to the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15 and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type termination well layer 31 in the termination region 30. The mask process refers to a process of forming a mask on a semiconductor substrate by applying a resist onto the semiconductor substrate, forming openings in predetermined regions of the resist using photolithography technology, and then performing ion implantation or etching on the predetermined regions of the semiconductor substrate through the openings.

[0064] The p-type base layer 15 and the p-type anode layer 25 may be formed by simultaneously implanting p-type impurities. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration, resulting in the same configuration. Alternatively, the p-type base layer 15 and the p-type anode layer 25 may have different depths and p-type impurity concentrations by implanting p-type impurities into them separately using a mask process.

[0065] Also, the p-type termination well layer 31 formed in another cross section may be formed by ion implanting p-type impurities at the same time as the p-type anode layer 25. In this case, the p-type termination well layer 31 and the p-type anode layer 25 have the same depth and p-type impurity concentration, and can be configured to be the same. Also, the p-type termination well layer 31 and the p-type anode layer 25 can be formed by ion implanting p-type impurities at the same time, so that the p-type termination well layer 31 and the p-type anode layer 25 have different p-type impurity concentrations. In this case, the aperture ratio can be changed by using a mesh-shaped mask for one or both of the masks.

[0066] In addition, the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted with p-type impurities separately using a mask process, thereby making the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 different. The p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed simultaneously by ion-implanting p-type impurities.

[0067] Next, as shown in FIG. 14, a mask process is used to selectively inject n-type impurities into the first main surface side of the p-type base layer 15 in the IGBT region 10 to form an n + The n-type source layer 13 is formed. The implanted n-type impurity may be, for example, arsenic (As) or phosphorus (P). In addition, a mask process is used to selectively implant the p-type impurity into the first main surface side of the p-type base layer 15 in the IGBT region 10 to form a p + A p-type contact layer 14 is formed, and a p-type impurity is selectively implanted into the first main surface side of the p-type anode layer 25 in the diode region 20 to form a p +Then, a p-type contact layer 24 is formed. The implanted p-type impurity may be, for example, boron (B) or aluminum (Al).

[0068] Next, as shown in FIG. 15, a semiconductor substrate is formed by passing through the p-type base layer 15 and the p-type anode layer 25 from the first main surface side of the semiconductor substrate. - A trench 8 is formed in the IGBT region 10, reaching the n-type drift layer 1. + The trench 8 penetrating the source layer 13 has n-type sidewalls. + The trench 8 constitutes a part of the type source layer 13. The trench 8 may be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, forming an opening in the oxide film at the portion where the trench 8 is to be formed by mask processing, and etching the semiconductor substrate using the oxide film with the opening formed as a mask. In FIG. 15, the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pattern of the pitch of the trenches 8 in a plan view can be appropriately changed by changing the mask pattern in the mask processing.

[0069] 16, the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner wall of the trench 8 and on the first main surface of the semiconductor substrate. Of the oxide films 9 formed on the inner walls of the trenches 8, the oxide film 9 formed in the trenches 8 in the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. In addition, the oxide film 9 formed in the trenches 8 in the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later process.

[0070] Next, as shown in FIG. 17, polysilicon doped with n-type or p-type impurities is deposited in trench 8 having oxide film 9 formed on its inner wall by CVD (chemical vapor deposition) or the like to form gate trench electrode 11a, dummy trench electrode 12a, and diode trench electrode 21a.

[0071] Next, as shown in FIG. 18, the oxide film 9 formed on the first main surface of the semiconductor substrate after the interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10 is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, a contact hole is formed in the deposited interlayer insulating film 4 by a mask process. The contact hole is an n + On type source layer 13, p + On the contact layer 14, + It is formed on the mold contact layer 24, the dummy trench electrode 12a and the diode trench electrode 21a.

[0072] 19, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by physical vapor deposition (PDV) or CVD.

[0073] The emitter electrode 6 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or vapor deposition. A nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, so that the heat capacity of the emitter electrode 6 can be increased and the heat resistance can be improved. When a nickel alloy is further formed by plating after forming the emitter electrode 6 made of an aluminum silicon alloy by PVD, the plating for forming the nickel alloy may be performed after processing the second main surface side of the semiconductor substrate.

[0074] 20, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0075] 21 , n-type impurities are injected from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are injected from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20 and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0076] The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) ions. + ) may be implanted. Furthermore, both protons and phosphorus may be implanted. Protons can be implanted deep into the second main surface of the semiconductor substrate with a relatively low acceleration energy. Also, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. For this reason, when forming the n-type buffer layer 3 with protons, if protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 that is wider in the thickness direction of the semiconductor substrate than one formed with phosphorus can be formed.

[0077] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity than protons, punch-through of the depletion layer can be more reliably suppressed even in a thinned semiconductor substrate by forming the n-type buffer layer 3 with phosphorus. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0078] The p-type collector layer 16 may be formed by, for example, implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, the second main surface is irradiated with a laser and laser annealed, thereby activating the implanted boron and forming the p-type collector layer 16. At this time, phosphorus for the n-type buffer layer 3 implanted at a position relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken not to raise the temperature of the entire semiconductor substrate to a temperature higher than 350°C to 500°C after the protons are implanted, except in the process for activating the protons. Since laser annealing can raise the temperature only near the second main surface of the semiconductor substrate, it can be used to activate n-type impurities and p-type impurities even after the protons are implanted.

[0079] Next, as shown in FIG. + A cathode layer 26 is formed. + The p-type cathode layer 26 may be formed by implanting phosphorus (P), for example. As shown in FIG. 22, the p-type collector layer 16 and the n-type collector layer 17 are disposed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + Phosphorus is selectively implanted from the second main surface side by mask processing so that the boundary with the cathode layer 26 is located. + The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. In FIG. + The depth of the n-type cathode layer 26 is shown to be the same. + The depth of the n-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. + The region in which the cathode layer 26 is to be formed must be made into an n-type semiconductor by implanting n-type impurities into the region implanted with p-type impurities. + In the entire region where the cathode layer 26 is to be formed, the concentration of the implanted p-type impurities is made higher than the concentration of the n-type impurities.

[0080] Next, the collector electrode 7 is formed on the second main surface of the semiconductor substrate, thereby obtaining the cross-sectional configuration shown in FIG. 9. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, and the termination region 30 on the second main surface. The collector electrode 7 may be formed over the entire surface of the second main surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or vapor deposition, or may be formed by laminating a plurality of metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 7 may be formed by forming a metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0081] The above-mentioned steps are used to manufacture the semiconductor device 100 or the semiconductor device 101. Since a plurality of semiconductor devices 100 or semiconductor devices 101 are manufactured in a matrix on one n-type wafer, the semiconductor device 100 or semiconductor device 101 is completed by cutting the wafer into individual semiconductor devices 100 or semiconductor devices 101 by laser dicing or blade dicing.

[0082] <Embodiment 1> Fig. 23 is a partial plan view showing the configuration of the RC-IGBT1000 according to the first embodiment, and is a plan view of an area 91 surrounded by a dashed line in Fig. 3. Therefore, the entire planar structure of the RC-IGBT1000 is the same as that of the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2.

[0083] Fig. 23 shows the interlayer insulating film 4 on the active trench gate 11, which is omitted in Fig. 3. The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate so as to overlap with the active trench gate 11.

[0084] As shown in FIG. 23, the RC-IGBT 1000 has a structure in which the width of the interlayer insulating film 4 on the active trench gate 11 is partially narrowed. Hereinafter, this structure is referred to as a narrow width portion 35. In the narrow width portion 35, a recess CP is partially provided on each of two side surfaces of the interlayer insulating film 4 in the width direction, which is the Y direction intersecting with the X direction, which is the extension direction of the active trench gate 11, in a plan view. In the portion where the recess CP is provided, the width of the interlayer insulating film 4 is narrowed and is approximately the same as the width of the active trench gate 11. Therefore, when the emitter electrode 6 (FIG. 4) is provided on the first main surface of the semiconductor substrate, the distance between the gate trench electrode 11a and the emitter electrode 6 is shorter in the narrow width portion 35 than in the portion where the interlayer insulating film 4 has a normal width. This may increase the concentration of the electric field and the leakage current.

[0085] Here, if an abnormality occurs such as a decrease in the thickness of the gate trench insulating film 11b during manufacturing, or if the mask during patterning of the interlayer insulating film 4 shifts and the interlayer insulating film 4 shifts in the width direction of the active trench gate 11, the distance between the gate trench electrode 11a and the emitter electrode 6 may become even shorter, making it a point that is prone to breakdown when a voltage is applied between the gate and emitter. When a voltage is applied between the gate and emitter at such a point, the narrow width portion 35 undergoes dielectric breakdown, and it is possible to provide an effect equivalent to that of screening the dielectric breakdown resistance of the gate, that is, a screening effect.

[0086] In addition, in the RC-IGBT1000, the narrow width portion 35 is provided in the interlayer insulating film 4, but the width of the interlayer insulating film 4 other than the portion where the narrow width portion 35 is provided is not increased, so the contact region with the emitter electrode 6 is not narrowed. Therefore, the current path does not narrow when the IGBT is on, the on-resistance does not increase, and the transistor loss does not increase.

[0087] The narrow width portion 35 can be provided in the interlayer insulating film 4 by simultaneously patterning the same mask when forming the contact hole in the interlayer insulating film 4 by mask processing as described with reference to Fig. 18, but it can also be provided by forming only the recess CP using another mask after forming the contact hole. It is desirable that the recess CP is large enough not to reach at least above the gate trench electrode 11a.

[0088] In addition, Figure 23 shows an example in which a narrow width portion 35 is provided at one location in the interlayer insulating film 4 above one gate trench electrode 11a, but this is not limited to this. Narrow width portions 35 can also be provided in the interlayer insulating film 4 above multiple gate trench electrodes 11a, and the number of narrow width portions 35 provided is not limited.

[0089] Needless to say, even if the narrow portion 35 is provided, the product functions normally under normal conditions of use, and the product life is guaranteed.

[0090] <Embodiment 2> <Device configuration> Fig. 24 is an overall plan view showing the configuration of an RC-IGBT2000 according to the second embodiment, and its appearance is the same as that of the semiconductor device 100 shown in Fig. 1. Note that it may also have the same appearance as that of the semiconductor device 101 shown in Fig. 2, and there is no distinctive feature in appearance.

[0091] The RC-IGBT 2000 according to the second embodiment is characterized in that a step portion is provided between the IGBT region 10 and the termination region 30, and the interlayer insulating film above the step portion is recessed.

[0092] Fig. 25 is a cross-sectional view in the direction indicated by the arrows at dashed line EE in Fig. 24, a cross-sectional view from the IGBT region 10 to the termination region 30, and a cross-sectional view in a direction intersecting the extension direction of the active trench gate 11. Fig. 26 is a cross-sectional view in the direction indicated by the arrows at dashed line HH in Fig. 24, a cross-sectional view from the IGBT region 10 to the termination region 30, and a cross-sectional view in the extension direction of the active trench gate 11.

[0093] Figures 25 and 26 are basically the same as the cross-sectional views shown in Figures 10 and 11, but a step portion 37 with a height difference of approximately 50 nm is formed in which the first main surface of the semiconductor substrate on the termination region 30 side relative to the boundary between the IGBT region 10 and the termination region 30 is recessed toward the collector electrode 7 side.

[0094] Due to the presence of the step portion 37, the interlayer insulating film 4 above the step portion 37 is recessed as shown in FIG.

[0095] FIG. 27 shows a partial cross-sectional view of the region 94 surrounded by a dashed line in FIG. 26 and a partial plan view including the narrow width portion 35. The upper view of FIG. 27 is a partial enlarged view, and the lower view is a partial plan view, and for convenience, the configuration below the interlayer insulating film 4 is shown. As shown in the upper view of FIG. 27, a step portion 37 of the semiconductor substrate exists on the termination region 30 side from the boundary between the IGBT region 10 and the termination region 30, that is, at a position corresponding to the end of the p-type termination well layer 31 closest to the IGBT region 10, and the interlayer insulating film 4 thereon is recessed. When the interlayer insulating film 4 is recessed, a narrow width portion 35 is formed in the recessed portion when the interlayer insulating film 4 is patterned on the active trench gate 11, as shown in the lower view of FIG. 27. As a result, a screening effect can be imparted in the same manner as the RC-IGBT 1000 of the first embodiment.

[0096] 27 also shows an active region 38 and a non-active region 39 in termination region 30. Active region 38 is a region in which p-type termination well layer 31 is formed, and non-active region 39 is a region from the boundary between IGBT region 10 and termination region 30 to step portion 37.

[0097] 27, in the active region 38, a gate wiring 42 is provided adjacent to the non-active region 39, and the gate wiring 42 is connected to the gate trench electrode 11a via a gate pull-up portion 43 that penetrates the interlayer insulating film 4. Although the upper diagram of FIG. 27 discloses a configuration in which the gate wiring 42 is connected to the gate trench electrode 11a via a barrier metal 5, the arrangement of the barrier metal 5 is arbitrary.

[0098] The gate wiring 42 is electrically connected to the gate pad 410c (FIG. 24) and is electrically isolated from the emitter electrode 6. As shown in the upper diagram of FIG. 27, a termination protective film 34 is disposed between the gate wiring 42 and the emitter electrode 6, and the gate wiring 42 and the emitter electrode 6 are insulated from each other.

[0099] <Manufacturing method> Next, a method for manufacturing the RC-IGBT 2000 will be described with reference to cross-sectional views of Figs. 28 to 35 showing the manufacturing steps in sequence. Figs. 28 to 35 correspond to the cross-sectional view shown in Fig. 26.

[0100] 28, a resist mask RM1 having an opening OP is formed in a region where the p-type termination well layer 31 is to be formed, and p-type impurities are ion-implanted using the resist mask RM1 as an ion implantation mask to form the p-type termination well layer 31. The p-type termination well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 It is.

[0101] Next, in the step shown in FIG. 29, the region where the p-type termination well layer 31 is formed is covered with a resist mask RM2, and polysilicon doped with n-type or p-type impurities is deposited by CVD or the like in the trench with the gate trench insulating film 11b formed on the inner wall to form the gate trench electrode 11a, and the active trench gate 11 is formed. FIG. 29 is a diagram corresponding to the step shown in FIG. 17, and FIGS. 29 to 35 show the manufacturing steps after the step shown in FIG. 17. As shown in FIG. 29, polysilicon doped with n-type or p-type impurities is deposited by CVD or the like in the trench with the gate trench insulating film 11b formed on the inner wall to form the gate trench electrode 11a, and the active trench gate 11 is formed. Thereafter, the resist mask RM2 is removed as shown in FIG. 30.

[0102] 31, the first main surface of the semiconductor substrate is recessed to form a resist mask RM21 on the first main surface of the semiconductor substrate excluding a region where the step portion 37 is to be provided. The region where the step portion 37 is to be provided serves as an opening OP1.

[0103] Thereafter, the first main surface of the semiconductor substrate is etched using the resist mask RM21 as an etching mask, and the first main surface of the semiconductor substrate that is not covered by the resist mask RM21 is removed by about 50 nm to form a step portion 37.

[0104] Next, in the process shown in FIG. + A resist mask RM3 having an opening OP2 is formed in a region where the n-type channel stopper layer 32 is to be formed, and n-type impurities are ion-implanted using the resist mask RM3 as an ion implantation mask. + A type channel stopper layer 32 is formed.

[0105] Next, in the step shown in FIG. 33, an interlayer insulating film 4 is formed entirely over the first main surface of the semiconductor substrate.

[0106] Then, in the process shown in FIG. 34, a resist mask RM4 is formed, which has an opening for patterning the interlayer insulating film 4 onto the active trench gate 11, an opening OP3 as a portion in the interlayer insulating film 4 where the gate pull-up portion 43 is to be formed, and an opening OP4 as a portion where a contact hole is to be formed.

[0107] Next, in the process shown in FIG. 35, the interlayer insulating film 4 is patterned using the resist mask RM4 as an etching mask, so that the interlayer insulating film 4 covers the active trench gate 11, an opening OP11 is formed in the gate pull-up portion 43, and an opening OP12 is formed in the portion where the contact hole is to be formed.

[0108] When the resist mask RM4 is patterned, the shape of the resist mask RM4 on the step portion 37 changes due to focus deviation during exposure, and a narrow portion 35 where the width of the interlayer insulating film 4 is narrowed is formed.

[0109] In FIG. 35, a plan view taken along line XX in the vicinity of the boundary between the IGBT region 10 and the termination region 30 in the direction indicated by the arrows corresponds to the lower diagram in FIG.

[0110] In this way, by providing step portion 37 at the position where narrow portion 35 is desired to be formed, narrow portion 35 can be formed by using an existing resist mask for patterning interlayer insulating film 4, thereby simplifying the manufacturing process.

[0111] <Embodiment 3> Fig. 36 is a partial plan view showing the configuration of an RC-IGBT3000 according to the third embodiment, and is a plan view of an area 92 surrounded by a dashed line in Fig. 3. Therefore, the entire planar structure of the RC-IGBT3000 is the same as that of the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2.

[0112] Fig. 36 illustrates the interlayer insulating film 4 on the active trench gate 11, which is omitted in Fig. 3. The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate so as to overlap with the active trench gate 11.

[0113] As shown in FIG. 36, in the RC-IGBT 3000, the narrow portion 35 of the interlayer insulating film 4 is + adjacent to the p-type source layer 13 + It is formed in the portion where the mold contact layer 14 is provided.

[0114] Fig. 37 is an enlarged view of the narrow portion 35, and Fig. 38 is a cross-sectional view taken along the arrow direction of the broken line II in Fig. 37. In tests in which a large current flows, such as RBSOA and short circuit tests, when the IGBT cuts off the current, holes present inside the IGBT are p + The current is discharged from the mold contact layer 14. At this time, in the narrow width portion 35, the current is concentrated along a path as shown by the arrows in Fig. 38. This results in a narrow width effect in which a large amount of heat is generated in the narrow width portion 35 compared to other portions, making the portion more likely to be destroyed.

[0115] In the RBSOA and short circuit tests, the measurement conditions are gradually made stricter, such as by increasing the amount of current flowing, and measurements are taken until breakdown occurs. Therefore, by providing the narrow width portion 35, the narrow width effect can determine the measurement conditions at which the IGBT under test is broken, and the variation in breakdown resistance can be reduced. Here, the variation in breakdown resistance refers to the variation in the conditions under which IGBTs can operate non-destructively in destructive tests such as the RBSOA and short circuit tests, even if they are manufactured under similar process conditions.

[0116] In addition, in Figure 36, an example is shown in which narrow width portions 35 are provided in the interlayer insulating film 4 above two gate trench electrodes 11a, but this is not limited to this. A narrow width portion 35 may be provided in the interlayer insulating film 4 only above one gate trench electrode 11a, and the number of narrow width portions 35 provided is not limited.

[0117] Even when the narrow width portion 35 is provided, the RC-IGBT3000 functions normally under normal usage conditions and the product life is guaranteed, but the provision of the narrow width portion 35 provides a screening effect on the insulation breakdown resistance of the gate, as in embodiment 1.

[0118] <Fourth embodiment> Fig. 39 is a partial plan view showing the configuration of an RC-IGBT4000 according to the fourth embodiment, and is a plan view of an area 93 surrounded by a dashed line in Fig. 3. Therefore, the entire planar structure of the RC-IGBT4000 is the same as that of the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2.

[0119] 39, similarly to the RC-IGBT 3000 shown in FIG. 36, the narrow portion 35 of the interlayer insulating film 4 is adjacent to the n+ type source layer 13. + The p-type contact layer 14 is formed in the region where the p-type contact layer 14 is provided. + The n-type contact layer 14 is adjacent to + The interlayer insulating films 40a and 40b are also formed on the type source layer 13, and the interlayer insulating film 4 in which the narrow width portion 35 is formed and a region 41 surrounded by the interlayer insulating films 40a and 40b are formed.

[0120] In tests involving large currents such as RBSOA and short circuit tests, when an IGBT cuts off current, holes present inside the IGBT are converted into p + The current is discharged from the contact layer 14. At this time, by providing the region 41, the current flows from the periphery of the region 41 into the inside of the region 41, so that the current is concentrated more in the narrow width portion 35 than in the case of the third embodiment. This enhances the narrow width effect, and the variation in the breakdown resistance can be further reduced.

[0121] Even when the region 41 including the narrow width portion 35 is provided, the RC-IGBT4000 functions normally under normal usage conditions and the product life is guaranteed. However, the provision of the region 41 including the narrow width portion 35 provides a screening effect on the dielectric breakdown resistance of the gate, as in the first embodiment.

[0122] <Embodiment 5> Next, a method for manufacturing the RC-IGBT according to the first, third and fourth embodiments will be described. Fig. 40 is a flow chart for explaining the method for manufacturing the RC-IGBT, and Figs. 41 to 45 are diagrams for explaining the manufacturing process. In the following description, a method for forming a narrow width portion by providing a step portion on the first main surface of a semiconductor substrate will be described.

[0123] As shown in Fig. 40, first, a step is formed on a first main surface, which is the surface of a semiconductor substrate (step S1). Fig. 41 shows this process in a schematic manner, with the upper figure showing a plan view and the lower figure showing a cross-sectional view in the direction indicated by the arrow at dashed line JJ in the upper figure.

[0124] 41, a resist mask RM5 for forming a step portion 37 is formed on the first main surface of the semiconductor substrate on which the n-type carrier accumulation layer 2 and the p-type base layer 15 are formed, and the first main surface of the semiconductor substrate is removed by about 50 nm by dry etching or wet etching using the resist mask RM5 as an etching mask to form the step portion 37. In this case, the step portion 37 is provided so as to intersect with the extending direction of the active trench gate 11.

[0125] After that, through the steps described with reference to FIGS. 14 to 17, n + Type source layer 13, p + A contact layer 14, a gate trench insulating film 11b, and a gate trench electrode 11a are formed. In FIG. 42, the upper figure shows a plan view, and the lower figure shows a cross-sectional view in the direction indicated by the arrow at the dashed line KK in the upper figure. In the example of FIG. 42, adjacent n + Although the step portion 37 is formed so as to cross between the mold source layers 13, the position where the step portion 37 is provided is not limited to this.

[0126] Returning to the explanation of Fig. 40, an interlayer insulating film 4 is formed over the entire first main surface of the semiconductor substrate (step S2). The interlayer insulating film 4 can be SiO2 formed by CVD, for example. Fig. 43 shows this process in a schematic manner, with the upper drawing showing a plan view and the lower drawing showing a cross-sectional view taken along the dashed line LL in the upper drawing.

[0127] As shown in the lower diagram of FIG. 43, by providing a step portion 37 in the semiconductor substrate, the interlayer insulating film 4 above the step portion 37 is recessed.

[0128] Returning to the explanation of FIG. 40, an n-type semiconductor layer is formed on the upper portion of the interlayer insulating film 4 as a contact region with the emitter electrode, which is a surface electrode. + The p-type source layer 13 and + A resist mask RM6 is formed, with an opening OP5 located on the mold contact layer 14 (step S3).

[0129] FIG. 44 shows this process in a schematic manner, with the upper drawing in FIG. 44 showing a plan view and the lower drawing showing a cross-sectional view taken along the broken line MM in the upper drawing.

[0130] As shown in the upper diagram of Figure 44, due to the recession in the interlayer insulating film 4 above the step portion 37, a focus shift occurs in the resist mask RM6 on the interlayer insulating film 4 when exposed to light, and the shape of the resist mask RM6 changes between the step portion 37 and other portions, resulting in the width of the resist mask RM6 being narrow in some parts.

[0131] Returning to the explanation of FIG. 40, the resist mask RM6 is used as an etching mask to remove the interlayer insulating film 4 in the contact region with the emitter electrode, which is the front surface electrode, by etching (step S4).

[0132] FIG. 45 is a plan view showing this step in schematic form, and the interlayer insulating film 4 above the active trench gate 11 has a narrow width portion 35 in a portion corresponding to the step portion 37.

[0133] In this way, by providing step portion 37 at the position where narrow portion 35 is desired to be formed, narrow portion 35 can be formed by using an existing resist mask for patterning interlayer insulating film 4, thereby simplifying the manufacturing process.

[0134] <Other manufacturing methods> In the manufacturing method of the fifth embodiment, a method of forming a narrow width portion by providing a step portion in the first main surface of the semiconductor substrate has been described, but it is also possible to form a narrow width portion without providing a step portion.

[0135] FIG. 46 is a flowchart illustrating a method for manufacturing an RC-IGBT in the case where a narrow width portion is formed without providing a step portion.

[0136] As shown in Fig. 46, an interlayer insulating film 4 is formed on the entire first main surface of a semiconductor substrate (step S11). The semiconductor substrate at this stage undergoes the steps described with reference to Figs. 14 to 17, and n-type ions are formed in the semiconductor substrate as shown in Fig. 42. + Type source layer 13, p + The semiconductor substrate has a contact layer 14, a gate trench insulating film 11b, and a gate trench electrode 11a formed thereon, and the interlayer insulating film 4 can be, for example, SiO2 formed by CVD.

[0137] Next, an n-type electrode, which is a contact region for an emitter electrode, is formed on the upper portion of the interlayer insulating film 4. + The source layer 13 and the p + A resist mask is formed with an opening on the mold contact layer 14 (step S12).

[0138] In this step, the resist mask used in the masking process is formed so that the width of the resist at the portion where the narrow width portion 35 is to be provided in the interlayer insulating film 4 is as narrow as the narrow width portion 35. This makes it possible to form the narrow width portion without providing a step portion, and the provision of the step portion can suppress an increase in the number of steps.

[0139] Here, the exposure pattern when the resist material is a positive type is shown in Fig. 47. As shown in Fig. 47, when the resist material is a positive type, the non-exposed region NEX has a pattern similar to that of the interlayer insulating film 4 having the narrow width portion 35, and the exposed region EX has a pattern similar to that of the contact region with the emitter electrode.

[0140] By exposing a positive resist material with such an exposure pattern, a resist mask RM7 as shown in Fig. 48 can be obtained. If the resist material is a negative resist, the exposure pattern will be one in which the unexposed area NEX and the exposed area EX in Fig. 47 are reversed.

[0141] Returning to the explanation of FIG. 46, the resist mask RM7 is used as an etching mask to remove the interlayer insulating film 4 in the contact region with the emitter electrode, which is the front surface electrode, by etching (step S13).

[0142] <Other manufacturing methods for step portion> In the second embodiment, the manufacturing method of the step portion 37 has been described with reference to FIGS. 28 to 32. However, in order to reduce the number of resist masks, a manufacturing method shown in FIGS. 49 to 51 may be used.

[0143] 49, a resist mask RM1 having an opening OP is formed in a region where the p-type termination well layer 31 is to be formed, and p-type impurities are ion-implanted using the resist mask RM1 as an ion implantation mask to form the p-type termination well layer 31. This process is the same as the process described with reference to FIG.

[0144] 50, the resist mask RM1 is used as an etching mask to recess the first main surface of the semiconductor substrate to form the stepped portion 37. In this case, the outermost surface of the p-type termination well layer 31 is also recessed.

[0145] 51, the region where the p-type termination well layer 31 is formed is covered with a resist mask RM8, and polysilicon doped with n-type or p-type impurities is deposited by CVD or the like in the trench with the gate trench insulating film 11b formed on its inner wall to form the gate trench electrode 11a and the active trench gate 11. FIG. 29 is a diagram corresponding to the process shown in FIG.

[0146] In this way, by using the resist mask for forming the p-type termination well layer 31 as an etching mask for forming the stepped portion 37, the number of resist masks can be reduced, leading to a reduction in manufacturing costs.

[0147] <Other application examples> In the above-described first to fifth embodiments, examples have been shown in which the present disclosure is applied to an RC-IGBT. However, the present disclosure is not limited to application to RC-IGBTs, and may also be applied to IGBTs and MOSFETs (MOS Field Effect Transistors), and in such cases, the same effects as when applied to an RC-IGBT can be obtained.

[0148] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments.

[0149] The present disclosure described above will now be summarized as an appendix.

[0150] (Appendix 1) A semiconductor device including a transistor formed on a semiconductor substrate having a first main surface and a second main surface, The semiconductor substrate is a transistor region in which the transistor is formed; The transistor region is a first main electrode electrically connected to the first main surface; a second main electrode electrically connected to the second main surface; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided closer to the first main surface than the first semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to the first main surface than the second semiconductor layer and electrically connected to the first main electrode; a trench gate extending from the first main surface through the third semiconductor layer and the second semiconductor layer in a thickness direction to reach the first semiconductor layer; an interlayer insulating film provided on the trench gate; The interlayer insulating film is The trench gate has at least one narrow width portion in which the length in a width direction intersecting with the extending direction of the trench gate in a plan view is partially narrowed, a length in the width direction of the narrow portion is longer than a length in the width direction of the trench gate.

[0151] (Appendix 2) The narrow width portion is 2. The semiconductor device according to claim 1, wherein the semiconductor substrate is formed above a step portion formed in the first main surface of the semiconductor substrate in a direction intersecting the extending direction of the trench gate in a plan view.

[0152] (Appendix 3) The semiconductor substrate is a termination region surrounding a cell region including at least the transistor region; The step portion is 3. The semiconductor device according to claim 2, wherein the transistor region is formed closer to the termination region than a boundary between the transistor region and the termination region.

[0153] (Appendix 4) The step portion is 3. The semiconductor device of claim 2, having a height of at least 50 nm.

[0154] (Appendix 5) The transistor region is a fourth semiconductor layer of a second conductivity type provided adjacent to the third semiconductor layer and in the same layer as the third semiconductor layer, and electrically connected to the first main electrode; The narrow width portion is 2. The semiconductor device according to claim 1, wherein the interlayer insulating film is formed in a portion adjacent to the fourth semiconductor layer in a plan view.

[0155] (Appendix 6) The fourth semiconductor layer adjacent to the narrow width portion of the interlayer insulating film is 6. The semiconductor device according to claim 5, wherein the interlayer insulating film is surrounded by an inter-direction interlayer insulating film provided on the adjacent third semiconductor layer and extending in a direction intersecting the extension direction of the trench gate.

[0156] (Appendix 7) The narrow width portion is the interlayer insulating film has recesses on two side surfaces in the width direction intersecting the extension direction of the trench gate; 2. The semiconductor device according to claim 1, wherein the length of the interlayer insulating film in the width direction is partially narrowed in the portion where the recess is provided.

[0157] (Appendix 8) The semiconductor substrate is 2. The semiconductor device of claim 1, having a diode region in which a diode is formed.

[0158] (Appendix 9) (a) having a first major surface and a second major surface; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided closer to the first main surface than the first semiconductor layer; preparing a semiconductor substrate having a third semiconductor layer of a first conductivity type provided closer to the first main surface than the second semiconductor layer; (b) forming a trench gate extending from the first main surface through the third semiconductor layer and the second semiconductor layer in a thickness direction to reach the first semiconductor layer; (c) forming an interlayer insulating film on the trench gate; The step (c) forming, in the interlayer insulating film, at least one narrow width portion in which a length in a width direction intersecting an extension direction of the trench gate in a plan view is partially narrowed; a length in the width direction of the narrow width portion being longer than a length in the width direction of the trench gate;

[0159] (Appendix 10) Before the step (c), 10. The method for manufacturing a semiconductor device according to claim 9, further comprising forming a step portion in the first main surface of the semiconductor substrate in a direction intersecting with an extension direction of the trench gate in a plan view. [Explanation of symbols]

[0160] 1n - 6 emitter electrode; 7 collector electrode; 10 IGBT region; 11 active trench gate; 13 n-type drift layer; + Mold source layer, 14 p + 15 p-type base layer; 20 diode region; 30 termination region; 35 narrow width portion; 37 step portion; 40a, 40b interlayer insulating films in the cross direction.

Claims

1. A semiconductor device including a transistor formed on a semiconductor substrate having a first main surface and a second main surface, The semiconductor substrate is a transistor region in which the transistor is formed; The transistor region is a first main electrode electrically connected to the first main surface; a second main electrode electrically connected to the second main surface; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided closer to the first major surface than the first semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to the first main surface than the second semiconductor layer and electrically connected to the first main electrode; a trench gate extending from the first major surface through the third semiconductor layer and the second semiconductor layer in a thickness direction to reach the first semiconductor layer; an interlayer insulating film provided on the trench gate; The interlayer insulating film is The trench gate has at least one narrow width portion in which the length in a width direction intersecting with an extension direction of the trench gate in a plan view is partially narrowed, a length in the width direction of the narrow portion is longer than a length in the width direction of the trench gate.

2. The narrow width portion is 2 . The semiconductor device according to claim 1 , wherein the trench gate is formed above a step portion formed in the first main surface of the semiconductor substrate in a direction intersecting with the extending direction of the trench gate in a plan view.

3. The semiconductor substrate is a termination region surrounding a cell region including at least the transistor region; The step portion is 3. The semiconductor device according to claim 2, which is formed on the termination region side of a boundary between said transistor region and said termination region.

4. The step portion is The semiconductor device of claim 2 having a height of at least 50 nm.

5. The transistor region is a fourth semiconductor layer of a second conductivity type provided adjacent to the third semiconductor layer and in the same layer as the third semiconductor layer, and electrically connected to the first main electrode; The narrow width portion is The semiconductor device according to claim 1 , wherein said interlayer insulating film is formed in a portion adjacent to said fourth semiconductor layer in a plan view.

6. The fourth semiconductor layer adjacent to the narrow width portion of the interlayer insulating film is 6. The semiconductor device according to claim 5, wherein the semiconductor device is surrounded by said interlayer insulating film and an intersecting interlayer insulating film provided on an adjacent one of said third semiconductor layers and extending in a direction intersecting said extending direction of said trench gate.

7. The narrow width portion is the interlayer insulating film has recesses on two side surfaces in the width direction intersecting the extension direction of the trench gate; 2. The semiconductor device according to claim 1, wherein the length in the width direction of the interlayer insulating film is partially narrowed in the portion where the recess is provided.

8. The semiconductor substrate is 2. The semiconductor device according to claim 1, further comprising a diode region in which a diode is formed.

9. (a) having a first major surface and a second major surface; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided closer to the first major surface than the first semiconductor layer; preparing a semiconductor substrate having a third semiconductor layer of a first conductivity type provided closer to the first main surface than the second semiconductor layer; (b) forming a trench gate extending from the first major surface through the third semiconductor layer and the second semiconductor layer in a thickness direction to reach the first semiconductor layer; (c) forming an interlayer insulating film on the trench gate; The step (c) forming, in the interlayer insulating film, at least one narrow width portion in which a length in a width direction intersecting an extension direction of the trench gate in a plan view is partially narrowed; a length in the width direction of the narrow width portion being longer than a length in the width direction of the trench gate;

10. Prior to the step (c), 10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming a step portion in the first main surface of the semiconductor substrate in a direction intersecting the extending direction of the trench gate in a plan view.

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