Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device including a transistor in a minute size.SOLUTION: A semiconductor device includes a transistor and first to third insulating layers. The transistor includes a semiconductor layer, first to fourth conductive layers, and fourth to sixth insulating layers. The first conductive layer, the first insulating layer, the third conductive layer, the fifth insulating layer, the second insulating layer, the third insulating layer, and the second conductive layer are overlapped on each other in this order. The first insulating layer, the third conductive layer, the second insulating layer, the third insulating layer, and the second conductive layer have an opening that reaches the first conductive layer. The first insulating layer includes a part projecting into the opening. The fifth insulating layer is in contact with an upper surface and a side surface of the third conductive layer. The fourth insulating layer is within the opening in contact with an upper surface of the first insulating layer, a side surface of the fifth insulating layer, and a side surface of the second insulating layer. The semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the fourth insulating layer, and an upper surface of the second conductive layer. The sixth insulating layer is in contact with an upper surface of the semiconductor layer. The fourth conductive layer is on and in contact with the sixth insulating layer so as to overlap with the opening. The fifth insulating layer is an oxide of the third conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), an electronic device including the device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for semiconductor devices with higher integration and faster speeds. For example, when a semiconductor device is applied to a high-definition display device, a highly integrated semiconductor device is required. As one of the means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there is a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are also collectively referred to as extended reality (XR). Display devices for XR are desired to have high definition and high color reproducibility in order to enhance the sense of reality and immersion. Examples of display devices that can be applied include a liquid crystal display device, an organic electroluminescence (EL) device, or a light emitting device including a light emitting device (also referred to as a light emitting element) such as a light emitting diode (LED).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2018 / 087625 Summary of the Invention [Problem to be solved by the invention]

[0007] Further miniaturization of a transistor included in a semiconductor device is required for further integration of the semiconductor device. In addition, when the semiconductor device is applied to a display device, an electronic device, or the like, further speedup of the semiconductor device is required. Thus, an object of one embodiment of the present invention is to provide a semiconductor device having a fine-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device having a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0008] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0009] One embodiment of the present invention includes a transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, the fourth insulating layer, a fifth insulating layer, and a sixth insulating layer. The first conductive layer, the first insulating layer, the third conductive layer, the fifth insulating layer, the second insulating layer, the third insulating layer, and the second conductive layer are provided in this order to be stacked one on top of the other. The first insulating layer, the third conductive layer, the second insulating layer, the third insulating layer, and the second conductive layer each have an opening that reaches the first conductive layer. In the opening, the first insulating layer has a side surface of the third conductive layer, a side surface of the second insulating layer, and a side surface of the third insulating layer. a fifth insulating layer is provided in contact with an upper surface and a side surface of the third conductive layer; a fourth insulating layer is provided within the opening in contact with an upper surface of the first insulating layer, a side surface of the fifth insulating layer, and a side surface of the second insulating layer; a semiconductor layer is provided in contact with an upper surface of the first conductive layer within the opening, a side surface of the fourth insulating layer within the opening, and an upper surface of the second conductive layer; a sixth insulating layer is provided in contact with an upper surface of the semiconductor layer; the fourth conductive layer is provided on the sixth insulating layer so as to overlap with the opening in a planar view; the third conductive layer has a first element; and the fifth insulating layer has an oxide of the first element.

[0010] In the above, it is preferable that the semiconductor layer has a metal oxide, the metal oxide has two or three selected from indium, an element M, and zinc, the element M has one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and the fourth insulating layer has silicon oxide or silicon oxynitride.

[0011] In the above, it is preferable that the third conductive layer contains aluminum, and the fifth insulating layer contains aluminum oxide.

[0012] In the above, it is preferable that the first insulating layer and the third insulating layer each contain silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the second insulating layer contains silicon oxide or silicon oxynitride.

[0013] Another embodiment of the present invention includes a transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer. The first conductive layer, the first insulating layer, the second conductive layer, the fifth insulating layer, the second insulating layer, and the third insulating layer are provided in this order to be stacked. The first insulating layer, the second conductive layer, the second insulating layer, and the third insulating layer each have an opening that reaches the first conductive layer. In the opening, the first insulating layer has a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third insulating layer. a fifth insulating layer is provided in contact with an upper surface and a side surface of the second conductive layer; a fourth insulating layer is provided within the opening in contact with an upper surface of the first insulating layer, a side surface of the fifth insulating layer, and a side surface of the second insulating layer; a semiconductor layer is provided in contact with an upper surface of the first conductive layer within the opening, a side surface of the fourth insulating layer within the opening, and an upper surface of the third insulating layer; a sixth insulating layer is provided in contact with an upper surface of the semiconductor layer; the third conductive layer is provided on the sixth insulating layer so as to overlap with the opening in a planar view; the second conductive layer has a first element; and the fifth insulating layer has an oxide of the first element.

[0014] In the above, it is preferable that the semiconductor layer has a metal oxide, the metal oxide has two or three selected from indium, an element M, and zinc, the element M has one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and the fourth insulating layer has silicon oxide or silicon oxynitride.

[0015] In the above, it is preferable that the second conductive layer contains aluminum, and the fifth insulating layer contains aluminum oxide.

[0016] In the above, it is preferable that the first insulating layer and the third insulating layer each contain silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the second insulating layer contains silicon oxide or silicon oxynitride.

[0017] Another embodiment of the present invention includes forming a first conductive layer, forming a first insulating film on the first conductive layer, forming a second conductive layer on the first insulating film so as to have a region overlapping with the first conductive layer, oxidizing a surface of the second conductive layer to form a first insulating layer on an upper surface and a side surface of the second conductive layer, forming a second insulating film, a third insulating film, and a third conductive layer in this order on the first insulating film and the first insulating layer, forming a first opening by removing parts of the third conductive layer, the third insulating film, the second insulating film, the first insulating layer, and the second conductive layer, and forming a fourth conductive layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth conductive layer, and oxidizing a side surface of the fifth conductive layer exposed in the first opening to form a fourth insulating layer on a side surface of the fifth conductive layer, and forming a fourth insulating layer on the upper surface of the fourth conductive layer, the side surface of the fourth conductive layer in each of the first opening, and the second insulating layer. a fourth insulating film in contact with a side surface of the fourth conductive layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and an upper surface of the first insulating film; removing a part of the fourth insulating film and a part of the first insulating film to form a second opening reaching the first conductive layer; forming a fifth insulating layer having a protruding portion in the second opening, and a sixth insulating layer in contact with the side surface of the fourth conductive layer, the side surface of the second insulating layer, the side surface of the third insulating layer, the side surface of the fourth insulating layer, and an upper surface of the protruding portion, respectively, in the second opening; forming a semiconductor layer in contact with the upper surface of the fourth conductive layer, the side surface of the sixth insulating layer in the second opening, and an upper surface of the first conductive layer; forming a seventh insulating layer in contact with the upper surface and side surface of the semiconductor layer, the upper surface of the fourth conductive layer, and the upper surface of the second insulating layer;

[0018] In the above, when the first opening is formed, it is preferable to remove a part of the first insulating film to form an eighth insulating layer having a recess in a region overlapping with the first opening. Effect of the Invention

[0019] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a small-sized semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0021] [Figure 1] Fig. 1(A) is a plan view showing an example of a semiconductor device, and Fig. 1(B) is a cross-sectional view showing the example of the semiconductor device. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of a semiconductor device. [Diagram 3] 3A to 3D are cross-sectional views showing an example of a semiconductor device. [Figure 4] 4(A) and 4(B) are cross-sectional views showing an example of a semiconductor device. [Diagram 5] 5(A) and 5(B) are cross-sectional views showing an example of a semiconductor device. [Figure 6] 6(A) and 6(B) are cross-sectional views showing an example of a semiconductor device. [Figure 7] 7A to 7D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 8]8A to 8C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] 9A to 9D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 10] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 11] FIG. 11 is a perspective view showing an example of a display device. [Figure 12] FIG. 12 is a cross-sectional view showing an example of a display device. [Figure 13] FIG. 13 is a cross-sectional view showing an example of a display device. [Figure 14] FIG. 14 is a cross-sectional view showing an example of a display device. [Figure 15] FIG. 15 is a cross-sectional view showing an example of a display device. [Figure 16] FIG. 16 is a cross-sectional view showing an example of a display device. [Figure 17] 17(A) and 17(B) are diagrams showing configuration examples of a display device. [Figure 18] FIG. 18 is a diagram showing a configuration example of a display device. [Figure 19] FIG. 19 is a diagram showing a configuration example of a display device. [Figure 20] FIG. 20 is a diagram showing a configuration example of a display device. [Figure 21] FIG. 21 is a block diagram of a display device. [Figure 22] 22A to 22D are circuit diagrams of pixel circuits. [Figure 23] 23A to 23D are circuit diagrams of pixel circuits. [Figure 24] 24(A) and 24(B) are circuit diagrams of a pixel circuit. [Diagram 25] 25A to 25D are diagrams illustrating examples of electronic devices. [Figure 26] 26A to 26F are diagrams showing examples of electronic devices. [Figure 27]27A to 27G are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0024] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0025] In addition, the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0026] A transistor is a type of semiconductor element and can realize a function of amplifying a current or voltage, a switching operation of controlling conduction or non-conduction, etc. In this specification and the like, the transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

[0027] The functions of "source" and "drain" may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification and the like, the terms "source" and "drain" may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as a source terminal and a drain terminal, or a source electrode and a drain electrode, etc., depending on the situation.

[0028] The terms "gate" and "backgate" can be interchanged. For this reason, in this specification and the like, the terms "gate" and "backgate" can be used interchangeably. Note that the gate and backgate of a transistor can be appropriately rephrased as a gate electrode and a backgate electrode, etc., depending on the situation.

[0029] In this specification, the term "connection" includes "electrical connection".

[0030] "A and B are electrically connected" means that, among A and B connected without an insulator (A and B connected via a conductor or semiconductor, or A and B in contact), there is a time when an exchange of electrical signals or an interaction of electrical potential occurs between A and B during circuit operation. In other words, even if there is a time when an exchange of electrical signals or an interaction of electrical potential does not occur between A and B during circuit operation, if there is a time when an exchange of electrical signals or an interaction of electrical potential occurs between A and B, it can be said that "A and B are electrically connected."

[0031] An "electrical connection" includes a connection that does not involve a circuit element (for example, a transistor, but excluding wiring) (direct connection) and a connection that involves one or more circuit elements (indirect connection).

[0032] Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, when A and B are connected via the source and drain of one or more transistors, etc. However, this is subject to the premise that there is a timing when an electrical signal is exchanged or potential interaction occurs between A and B.

[0033] An example of a case where A and B are connected via an insulator and therefore it cannot be said that "A and B are electrically connected" is when there is a dielectric of a capacitive element or a gate insulating film of a transistor between A and B.

[0034] Examples of cases where A and B are connected without an insulator, but there is no timing at which an electrical signal is exchanged or there is no potential interaction between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power source, signal source, etc. (however, this does not include the case where potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, but there is no timing at which both transistor TrP and transistor TrQ are on at the same time.

[0035] In this specification, a structure in which at least light-emitting layers are separately prepared for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the optimization of materials and configurations for each light-emitting device, which increases the freedom of material and configuration selection and facilitates the improvement of brightness and reliability.

[0036] In this specification and the like, holes or electrons may be referred to as "carriers". Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer", a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer", and a hole block layer or an electron block layer may be referred to as a "carrier block layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics. In addition, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0037] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, layers (also called functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0038] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0039] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, the term refers to a shape having an area in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with a slight unevenness.

[0040] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (for example, a step or the like).

[0041] In this specification, the phrase "top surface shapes generally match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in these cases, the phrase "top surface shapes generally match" may also be used.

[0042] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Also, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0043] In addition, in this specification, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are approximately the same in a cross-sectional view. For example, the heights of the processed surfaces when a planarization process (typically, a chemical mechanical polishing (CMP) process) is performed are approximately the same. However, even when a planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification, the heights are also considered to be "approximately the same" in this case.

[0044] (Embodiment 1) In this embodiment, a transistor of one embodiment of the present invention and a manufacturing method of the transistor will be described.

[0045] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, a second insulating layer, and a third insulating layer.

[0046] The transistor is a vertical transistor in which a source electrode and a drain electrode are provided overlapping each other at different heights with respect to the substrate surface, and a drain current flows in the height direction (vertical direction). Therefore, it is possible to miniaturize the transistor and reduce the occupied area compared to a planar transistor in which a source electrode and a drain electrode are provided on the same plane. By providing the transistor with the above-mentioned structure, it is possible to miniaturize and highly integrate a semiconductor device.

[0047] The transistor has a first gate electrode and a second gate electrode (also referred to as a backgate electrode) provided to sandwich a semiconductor layer functioning as a channel formation region. Specifically, the first gate electrode is provided to be surrounded by the semiconductor layer in a plan view, and the second gate electrode is provided to surround the semiconductor layer in a plan view. This allows a gate electric field to be applied to carriers in the channel formation region from both surfaces of the semiconductor layer. Therefore, a larger on-current can be realized than a transistor having only one gate electrode. Also, a smaller off-current can be realized. Also, the threshold voltage can be shifted to the normally-off side. Also, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with an increase in the drain voltage).

[0048] The first insulating layer, the second insulating layer, and the third insulating layer are provided in this order when viewed from the substrate side. The first insulating layer, the second insulating layer, and the third insulating layer have regions overlapping with the source electrode, the drain electrode, and the second gate electrode of the transistor, respectively.

[0049] Specifically, in the region, a first insulating layer is provided on one of a source electrode or a drain electrode of the transistor. A second gate electrode of the transistor is provided on the first insulating layer. A second insulating layer is provided on the second gate electrode of the transistor. A third insulating layer is provided on the second insulating layer. The other of the source electrode or the drain electrode of the transistor is provided on the third insulating layer.

[0050] The second insulating layer is formed of a material that contains oxygen and releases oxygen by heat treatment or the like. On the other hand, the first insulating layer and the third insulating layer are each formed of a material that has blocking properties against gases such as oxygen and hydrogen. Therefore, it is possible to prevent the oxygen contained in the second insulating layer from diffusing downward (to the substrate side) of the second insulating layer through the first insulating layer. In addition, it is possible to prevent the oxygen contained in the second insulating layer from diffusing upward of the second insulating layer through the third insulating layer.

[0051] The second gate electrode of the transistor has an insulating layer (fourth insulating layer) made of an oxide of an element contained in the second gate electrode along the top surface and side surface. The fourth insulating layer has blocking properties against gases such as oxygen and hydrogen, similar to the first insulating layer and the third insulating layer. The fourth insulating layer can be formed, for example, by performing a plasma treatment in an oxygen-containing atmosphere on the surface of a conductive layer to be the second gate electrode, and oxidizing a part of the conductive layer. This makes it possible to form an insulating layer having the same function as the first insulating layer and the third insulating layer without using a film formation method such as a plasma CVD method or a sputtering method, thereby reducing the number of times the film formation method is applied. As described above, the second insulating layer is provided on the second gate electrode of the transistor. Therefore, it is possible to suppress the oxygen contained in the second insulating layer from diffusing into the inside of the second gate electrode through the fourth insulating layer.

[0052] The first insulating layer, the second gate electrode, the second insulating layer, the third insulating layer, and the other of the source electrode or the drain electrode of the transistor have an opening that reaches one of the source electrode or the drain electrode in a region overlapping with one of the source electrode or the drain electrode. In the opening, the first insulating layer preferably has a portion that protrudes beyond a side surface of the second gate electrode, a side surface of the second insulating layer, a side surface of the third insulating layer, and a side surface of the other of the source electrode or the drain electrode.

[0053] A gate insulating layer of the transistor (which is also referred to as a back gate insulating layer because it is a gate insulating layer corresponding to the first gate insulating layer or the second gate electrode) is provided in contact with the top surface of the first insulating layer (the top surface of the protruding portion), the side surface of the second gate electrode of the transistor, the side surface of the second insulating layer, the side surface of the third insulating layer, and the other side surface of the source electrode or drain electrode of the transistor in each of the openings. The first gate insulating layer of the transistor is formed of a material that contains oxygen and releases oxygen by heat treatment or the like, similar to the second insulating layer.

[0054] In addition, a semiconductor layer having a channel formation region of the transistor is provided in contact with an upper surface of one of the source electrode or drain electrode of the transistor in the opening, a side surface of the first insulating layer in the opening, a side surface of the first gate insulating layer of the transistor in the opening, and an upper surface of the other of the source electrode or drain electrode of the transistor. As described above, in the transistor of one embodiment of the present invention, the first gate insulating layer is formed of a material that releases oxygen. Therefore, for example, when a metal oxide is used as a material for the semiconductor layer, oxygen contained in the second insulating layer and oxygen contained in the first gate insulating layer can be supplied to the metal oxide through the first gate insulating layer, and oxygen vacancies in the metal oxide can be repaired. Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0055] As described above, the first insulating layer has a protruding portion in the opening, and the first gate insulating layer of the transistor is provided in contact with the upper surface of the protruding portion. That is, the first gate insulating layer of the transistor is provided on one of the source electrode or drain electrode of the transistor through the first insulating layer. Therefore, oxygen released from the first gate insulating layer is blocked by the first insulating layer, and it is possible to suppress diffusion to one of the source electrode or drain electrode. Therefore, even if a low-resistance conductive material such as a metal is used for one of the source electrode or drain electrode, it is possible to suppress the material from being oxidized by the above-mentioned oxygen and becoming highly resistive. This can further improve the electrical characteristics and reliability of the transistor.

[0056] Below, specific configuration examples of the transistor of one embodiment of the present invention will be described with reference to drawings.

[0057] <Configuration example 1> FIG 1A shows a plan view (also referred to as a top view) of a transistor 100. FIG 1B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG 1A, and FIG 2 shows a cross-sectional view taken along dashed dotted line B1-B2 in FIG 1A. Note that some of the components of the transistor 100 (such as an insulating layer) are omitted in FIG 1A. As with FIG 1A, some of the components are omitted in plan views of the transistor and the like in the following drawings.

[0058] The transistor 100 is provided over a substrate 102. The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 114, an insulating layer 116, an insulating layer 110s, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a first gate electrode. The conductive layer 114 functions as a second gate electrode (also referred to as a back gate electrode). A part of the insulating layer 106 functions as a first gate insulating layer. The insulating layer 110s functions as a second gate insulating layer (also referred to as a back gate insulating layer). A part of the insulating layer 116 can function as a second gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode. The conductive layer 112b functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108, between the source electrode and the drain electrode, the entire region overlapping with the gate electrode via the gate insulating layer functions as a channel formation region. In addition, in the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0059] The detailed configuration of the transistor 100 will be described.

[0060] A conductive layer 112a is provided on the substrate 102. An insulating layer 110a is provided on the conductive layer 112a and on the substrate 102. A conductive layer 114 is provided on the insulating layer 110a. An insulating layer 116 is provided on the conductive layer 114. An insulating layer 110b is provided on the insulating layer 110a and on the insulating layer 116. An insulating layer 110c is provided on the insulating layer 110b. A conductive layer 112b is provided on the insulating layer 110c. Note that the insulating layers 110a, 110b, and 110c may be collectively referred to as the insulating layer 110.

[0061] The conductive layer 112a, the conductive layer 114, the insulating layer 116, the insulating layer 110, and the conductive layer 112b have a region where they overlap with each other. In this region, the conductive layer 114 is provided to be sandwiched between the conductive layer 112a and the conductive layer 112b. In this region, the conductive layer 112a overlaps with the conductive layer 114 with the insulating layer 110a interposed therebetween, and the conductive layer 112b overlaps with the conductive layer 114 with the insulating layer 116, the insulating layer 110b, and the insulating layer 110c interposed therebetween. The insulating layer 116 is provided in contact with the side surface and the top surface of the conductive layer 114.

[0062] The insulating layer 110a, the conductive layer 114, the insulating layer 110b, the insulating layer 110c, and the conductive layer 112b each have an opening 143 that reaches the conductive layer 112a. The opening 143 is provided in a region overlapping with the conductive layer 112a, the conductive layer 114, and the conductive layer 112b.

[0063] The insulating layer 110a is provided so as to have a protruding portion in the opening 143. That is, in a cross-sectional view (FIGS. 1(B) and 2), the side surface of the insulating layer 110a on the opening 143 side is provided so as to be located more inward of the opening 143 than the side surfaces of the conductive layer 114, the insulating layer 116, the insulating layer 110b, the insulating layer 110c, and the conductive layer 112b on the opening 143 side. In other words, the opening 143 can be said to have a configuration combining openings provided in the conductive layer 114, the insulating layer 110b, the insulating layer 110c, and the conductive layer 112b and an opening with a smaller opening diameter provided in the insulating layer 110a.

[0064] Insulating layer 110s is provided in contact with the upper surface of insulating layer 110a (the upper surface of the protruding portion described above), the side surface of insulating layer 116, the side surface of insulating layer 110b, the side surface of insulating layer 110c, and the side surface of conductive layer 112b in each opening 143. Insulating layer 110s has a curved upper end. Insulating layer 110s may be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0065] 1B and 2 show a configuration in which the film thickness of the insulating layer 110a in the region overlapping with the opening 143 is thinner than the film thickness of the region not overlapping with the opening 143, but this is not limited thereto. The film thickness of the insulating layer 110a in the region overlapping with the opening 143 may be the same as the film thickness of the region not overlapping with the opening 143.

[0066] A semiconductor layer 108 is provided in contact with the upper surface of the conductive layer 112a in the opening 143, the side surface of the insulating layer 110a in the opening 143, the side surface of the insulating layer 110s in the opening 143, the curved portion of the insulating layer 110s, and the upper surface of the conductive layer 112b.

[0067] The semiconductor layer 108 has a region facing a side surface of the conductive layer 114 in the opening 143 with the insulating layer 110s and the insulating layer 116 interposed therebetween. This region functions as a channel formation region (also referred to as a back channel formation region). A region of the insulating layer 110s and the insulating layer 116 facing a side surface of the conductive layer 114 in the opening 143 functions as a second gate insulating layer.

[0068] Here, the insulating layer 110b and the insulating layer 110s are preferably insulating layers containing oxygen. In addition, the insulating layers are preferably insulating layers that release oxygen by heating. As a result, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layer 110s can be supplied to the metal oxide. Alternatively, oxygen contained in the insulating layer 110b can be supplied to the metal oxide through the insulating layer 110s. As a result, oxygen vacancies in the metal oxide can be repaired, and the electrical characteristics and reliability of the transistor 100 can be improved. That is, in the transistor 100, the insulating layer 110s functions as a second gate insulating layer and also has a function of supplying oxygen to the semiconductor layer 108 (mainly a channel formation region).

[0069] On the other hand, the insulating layers 110a and 110c are preferably insulating layers that have a blocking property against gases such as oxygen and hydrogen, etc. This can prevent oxygen contained in the insulating layer 110b from being released to the outside through the insulating layer 110a or the insulating layer 110c.

[0070] As described above, the insulating layer 110a has a protruding portion within the opening 143, and the protruding portion prevents the conductive layer 112a and the insulating layer 110s from directly contacting each other. This makes it possible to prevent the oxygen released from the insulating layer 110s from diffusing to the conductive layer 112a side, causing the conductive layer 112a to become oxidized and increase in resistance, and thus preventing problems such as the on-current of the transistor hitting a plateau (i.e., in the drain current (Id)-gate voltage (Vg) characteristics, Id becomes difficult to increase with an increase in Vg).

[0071] As described above, the insulating layer 116 is provided in contact with the side and top surfaces of the conductive layer 114. The insulating layer 116 is preferably an insulating layer made of an oxide of an element contained in the conductive layer 114. The material of the conductive layer 114 is preferably a conductive material that is easily oxidized. As a result, for example, the insulating layer 116 in contact with the side and top surfaces of the conductive layer 114 can be formed by performing plasma treatment or the like in an oxygen atmosphere on the surface of the conductive layer 114. Note that the insulating layer 116 is preferably an insulating layer having blocking properties against gases such as oxygen and hydrogen, similar to the insulating layers 110a and 110c. As a result, oxygen released from the insulating layers 110s and 110b can be suppressed from diffusing to the conductive layer 114 side through the insulating layer 116. Furthermore, by having the above-mentioned configuration, an insulating layer having the same function as the insulating layer 110a and the insulating layer 110c can be formed without using a film formation method such as a plasma CVD method or a sputtering method, so that the number of times the above-mentioned film formation method is applied can be reduced, and productivity can be increased in some cases.

[0072] The insulating layer 106 is provided over the semiconductor layer 108. The insulating layer 106 has a region in contact with an upper surface and side surfaces of the semiconductor layer 108, an upper surface and side surfaces of the conductive layer 112b, and an upper surface of the insulating layer 110c.

[0073] The conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 is provided to have a region overlapping with the opening 143 in a plan view. The conductive layer 104 has a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween. Furthermore, the conductive layer 104 has a region facing a side surface of the conductive layer 114 in the opening 143 with the insulating layer 106, the semiconductor layer 108, the insulating layer 110s, and the insulating layer 116 interposed therebetween.

[0074] Within the opening 143, one surface of the semiconductor layer 108 has an area facing the conductive layer 104 via the insulating layer 106, and the other surface of the semiconductor layer 108 has an area facing the conductive layer 114 via the insulating layer 110s and the insulating layer 116.

[0075] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface on which the transistor 100 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows in the vertical direction or approximately vertical direction in the transistor 100. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a vertical field effect transistor (VFET).

[0076] Since the source electrode and drain electrode of the transistor 100 can be overlapped, the transistor can be made smaller and the area occupied by the transistor on the substrate can be significantly reduced compared to a so-called planar type transistor in which the source electrode and drain electrode are arranged in a plane.

[0077] An insulating layer 195 is provided to cover the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, the insulating layer 106, the conductive layer 104, and the like included in the transistor 100. The insulating layer 195 functions as a protective layer for the transistor 100.

[0078] One of the conductive layer 104 and the conductive layer 114 can function as a gate electrode (first gate electrode), and the other can function as a backgate electrode (second gate electrode). The conductive layer 104 and the conductive layer 114 are preferably arranged to sandwich a channel formation region of the semiconductor layer 108. This allows a gate voltage to be applied to the channel formation region from both sides thereof, thereby strengthening the effect of the gate voltage on carriers in the region. As a result, the on-current of the transistor 100 can be increased. In addition, the off-current can be reduced. In addition, the threshold voltage can be shifted to the normally-off side.

[0079] By applying a potential to the back gate electrode (second gate electrode) that turns on the transistor, the field effect mobility of the transistor can be increased. Furthermore, by changing the potential of the back gate electrode, the threshold voltage of the transistor can be changed. The potential of the back gate electrode can be set to the same potential as that of the gate electrode (first gate electrode). Alternatively, the potential of the back gate electrode can be set to the ground potential or an arbitrary potential. The potential of the back gate electrode can also be set to the same potential as that of the source electrode or drain electrode. This allows the potential of the region of the semiconductor layer facing the back gate electrode to be fixed, thereby suppressing variations in the electrical characteristics of the transistor.

[0080] When the back gate electrode is applied with the same potential as the gate electrode, the back gate electrode and the gate electrode may be connected to each other to provide electrical continuity. When the back gate electrode is applied with the same potential as the source electrode or the drain electrode, the back gate electrode and the source electrode or the drain electrode may be connected to each other to provide electrical continuity. By connecting the gate electrode or the back gate electrode to the source electrode, for example, the reliability of the transistor can be improved.

[0081] In the case where the potential of the backgate electrode is set to the ground potential or an arbitrary potential, a common wiring connected to the backgate electrodes of a plurality of transistors may be provided and the potential may be applied to the common wiring.

[0082] When a transistor has a backgate electrode, variation in electrical characteristics among a plurality of transistors can be reduced in some cases, for example, variation in threshold voltage among a plurality of transistors can be reduced in some cases.

[0083] The upper surface shape of the opening 143 may be, for example, circular or elliptical. The upper surface shape of the opening 143 may be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or a shape with rounded corners of these polygons. As shown in FIG. 1(A), the upper surface shape of the opening 143 is preferably circular. By making the upper surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and the opening 143 of a fine size can be formed. Note that in this specification and the like, a circle is not limited to a perfect circle.

[0084] The channel length and channel width of the transistor 100 will be described.

[0085] In the semiconductor layer 108, a region in contact with the conductive layer 112a functions as one of a source region or a drain region, a region in contact with the conductive layer 112b functions as the other of the source region or the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0086] The channel length of the transistor 100 is the distance between the source region and the drain region. In Figures 1(B) and 2, the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. In Figures 1(B) and 2, the distance along the side and curved portion of the insulating layer 110s between the top surface of the conductive layer 112a and the top surface of the conductive layer 112b, and along the side surface of the insulating layer 110a, is indicated as the channel length L100 of the transistor 100.

[0087] Note that the channel length L100 of the transistor 100 may be defined as a total thickness T110 (in Figures 1(B) and 2, the thickness T110 is indicated by a double-headed arrow of a dashed line) of the insulating layer 110a, the conductive layer 114, the insulating layer 116, the insulating layer 110b, and the insulating layer 110c in a region sandwiched between the upper surface of the conductive layer 112a and the lower surface of the conductive layer 112b. Alternatively, the channel length L100 of the transistor 100 may be defined as the sum of the thickness T110 and the thickness of the conductive layer 112b. Alternatively, the channel length L100 of the transistor 100 may be defined as the height of the insulating layer 110s (the distance between the upper end and the lower end of the insulating layer 110s in a direction perpendicular to the substrate surface).

[0088] Here, the channel length L100 of the transistor 100 is determined by the thickness of the insulating layer 110a, the thickness of the conductive layer 114, the thickness of the insulating layer 116, the thickness of the insulating layer 110b, the thickness of the insulating layer 110c, the thickness of the conductive layer 112b, the angle θ110 between the surface on which the insulating layer 110s is formed (here, the side of the insulating layer 110a, the side of the insulating layer 116, the side of the insulating layer 110b, the side of the insulating layer 110c, and the side of the conductive layer 112b) and the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a), and is not affected by the performance of the exposure device used to manufacture the transistor. Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.

[0089] The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L100 can be 100 nm or more and 1 μm or less.

[0090] The thickness T110 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

[0091] The angle θ110 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and less than 85 degrees, 40 degrees or more and less than 80 degrees, 45 degrees or more and less than 80 degrees, 50 degrees or more and less than 80 degrees, 55 degrees or more and less than 80 degrees, 60 degrees or more and less than 80 degrees, 65 degrees or more and less than 80 degrees, or 70 degrees or more and less than 80 degrees. The angle θ110 can also be 90 degrees. The smaller the angle θ110, the higher the coverage of the layers (insulating layer 110s, semiconductor layer 108, etc.) formed along the sidewall of the opening 143 can be, which is preferable. On the other hand, the closer the angle θ110 is to 90 degrees, the more preferable it is because the area occupied by the transistor on the substrate surface can be reduced.

[0092] 3A is an enlarged view of a region 161 shown in FIG. 1B. FIG. 3A shows a configuration (the configuration shown in FIG. 1B, etc.) in which the height of the upper end of the insulating layer 110s is equal to or approximately equal to the height of the upper surface of the conductive layer 112b. In this configuration, no step is formed between the upper end of the insulating layer 110s and the side surface of the conductive layer 112b. Therefore, compared to a configuration having such a step, the coverage of the semiconductor layer 108 provided in contact with the side surface of the insulating layer 110s and the upper surface of the conductive layer 112b can be improved.

[0093] In the transistor 100, the height of the upper end of the insulating layer 110s is not limited to the configuration in which the height of the upper end of the insulating layer 110s is equal to or approximately equal to the height of the upper surface of the conductive layer 112b as shown in Figure 1(B) etc. The configurations shown in Figures 3(B) to 3(D) are examples of configurations in which the height of the upper end of the insulating layer 110s, etc. are different from that of Figure 3(A).

[0094] 3B shows a configuration in which the height of the upper end of the insulating layer 110s is lower than the height of the upper surface of the conductive layer 112b and higher than the height of the upper surface of the insulating layer 110c located under the conductive layer 112b. In the configuration shown in FIG. 3B, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108. When the semiconductor layer 108 is in contact with the side surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b becomes larger, and the contact resistance between them may be reduced.

[0095] 3C shows a configuration in which the height of an upper end of the insulating layer 110s is lower than the height of an upper surface of the insulating layer 110c. In the configuration shown in FIG. 3C, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108, and the side surface of the insulating layer 110c has a region in contact with the semiconductor layer 108. In this configuration, the semiconductor layer 108 is in contact with the entire side surface of the conductive layer 112b, so that the contact resistance between the semiconductor layer 108 and the conductive layer 112b may be reduced more than in the configuration shown in FIG. 3B.

[0096] 3(D) shows a configuration in which the height of the upper end of the insulating layer 110s is lower than the height of the upper surface of the insulating layer 110b. In the configuration shown in FIG. 3(D), the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108, the side surface of the insulating layer 110c has a region in contact with the semiconductor layer 108, and the side surface of the insulating layer 110b has a region in contact with the semiconductor layer 108. In the case of this configuration, the same effect as that obtained in the configuration shown in FIG. 3(C) described above may be obtained.

[0097] In the etching for forming the insulating layer 110s, the height of the insulating layer 110s (the distance between the upper end and the lower end of the insulating layer 110s in the direction perpendicular to the substrate surface) may be reduced by increasing the etching time. When the etching time is increased, the height of the upper end of the insulating layer 110s may become lower than the height of the upper surface of the conductive layer 112b. The height of the upper end of the insulating layer 110s is preferably higher than at least the height of the upper surface of the conductive layer 114. That is, the insulating layer 110s is preferably opposed to the entire side surface of the conductive layer 114 via the insulating layer 116 in the opening 143. As described above, the insulating layer 110s is an insulating layer that functions as a second gate insulating layer (back gate insulating layer) of the transistor 100. Therefore, since the insulating layer 110s has a region facing the entire side surface of the conductive layer 114, the entire region of the semiconductor layer 108 facing the conductive layer 114 via the insulating layer 110s within the opening 143 can function as a channel formation region (back channel formation region).

[0098] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, when the transistor of one embodiment of the present invention is used in a semiconductor device, the semiconductor device can be miniaturized.

[0099] For example, by applying the transistor of one embodiment of the present invention to a display device, the frame of the display device can be narrowed. For example, when the transistor of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, a signal delay in each wiring can be reduced, and display unevenness can be suppressed.

[0100] The channel width of the transistor 100 is the length of the source region or the length of the drain region in a plan view ( FIG. 1(A)). That is, the channel width of the transistor 100 is the length of a region where the semiconductor layer 108 and the conductive layer 112a are in contact with each other or the length of a region where the semiconductor layer 108 and the conductive layer 112b are in contact with each other in a plan view. Alternatively, the channel width of the transistor 100 may be the perimeter of a side surface of the insulating layer 110s in a plan view. Alternatively, the channel width of the transistor 100 may be the perimeter of a region where the insulating layer 110s and the conductive layer 112b are in contact with each other in a plan view.

[0101] Here, the channel width of the transistor 100 is described as the perimeter of a region where the insulating layer 110s and the conductive layer 112b are in contact with each other in a plan view. In Figures 1A, 1B, and 2, the channel width W100 of the transistor 100 is indicated by a solid double-headed arrow. The channel width W100 can also be referred to as the perimeter of the opening 143 in a plan view.

[0102] The channel width W100 is determined by the top surface shape of the opening 143, etc. In FIG. 1(A), FIG. 1(B), and FIG. 2, the width D143 of the opening 143 is indicated by a double-arrowed two-dot chain line. The width D143 refers to the short side of the smallest rectangle circumscribing the opening 143 in a plan view. When the opening 143 is formed using a photolithography method, the width D143 of the opening 143 is equal to or greater than the limit resolution of the exposure device. The width D143 is, for example, 0.20 μm or more and less than 5.0 μm. When the top surface shape of the opening 143 is circular, the width D143 corresponds to the diameter of the opening 143, and the channel width W100 can be calculated as "D143×π".

[0103] [Semiconductor layer 108] The semiconductor material that can be used for the semiconductor layer 108 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0104] The crystallinity of a semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0105] Silicon can be used for the semiconductor layer 108. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0106] A transistor using amorphous silicon for the semiconductor layer 108 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 108 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 108 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0107] The semiconductor layer 108 preferably has a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably has one or more selected from indium, element M, and zinc. The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. The element M is more preferably gallium.

[0108] For example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used for the semiconductor layer 108. Alternatively, indium tin oxide containing silicon, etc. can be used.

[0109] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.

[0110] Specific examples of the ALD method for forming the semiconductor layer 108 include thermal ALD and PEALD (Plasma Enhanced ALD) methods. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is preferable because it exhibits high step coverage and allows low-temperature film formation.

[0111] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100.

[0112] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. In addition, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. In addition, by using a metal oxide that has a low content of element M in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. In addition, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0113] The composition of the metal oxide in the semiconductor layer 108 will be described later in detail.

[0114] It is preferable to use a metal oxide layer having crystallinity for the semiconductor layer 108. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a poly-crystal structure, a nano-crystal (nc) structure, or the like can be used. By using a metal oxide layer having crystallinity for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of IGZO microcrystals) have a c-axis orientation, and the above-mentioned plurality of microcrystals are connected without being oriented in the ab plane. In the CAAC structure, crystal grain boundaries (grains) are not clearly visible in the ab plane compared to the poly-crystal structure, and therefore a highly reliable transistor can be realized.

[0115] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 108, the more the density of defect states in the semiconductor layer 108 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0116] The semiconductor layer 108 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer may be used, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, which can reduce manufacturing costs. For example, the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as oxygen flow rate ratio) can be changed using the same sputtering target to form a stacked structure of two or more metal oxide layers with different crystallinity. Note that the two or more metal oxide layers included in the semiconductor layer 108 may have different compositions.

[0117] The thickness of the semiconductor layer 108 (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, more preferably 20 nm or more and 40 nm or less, and more preferably 25 nm or more and 40 nm or less.

[0118] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0119] When an oxide semiconductor is used for the semiconductor layer 108, hydrogen contained in the oxide semiconductor may react with oxygen bonded to a metal atom to form water, and an oxygen vacancy (VO) may be formed in the oxide semiconductor. Furthermore, a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as VOH) may function as a donor and generate an electron that serves as a carrier. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that serves as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.

[0120] VOH can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, in an oxide semiconductor, it may be evaluated by the carrier concentration instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0121] From the above, when an oxide semiconductor is used for the semiconductor layer 108, it is preferable to reduce VOH in the semiconductor layer 108 as much as possible and make the semiconductor layer 108 highly intrinsic or substantially highly intrinsic. In order to obtain an oxide semiconductor with a sufficiently reduced VOH, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies (VO). Stable electrical characteristics can be imparted by using an oxide semiconductor with sufficiently reduced defects such as VOH for the channel formation region of a transistor. Note that supplying oxygen to an oxide semiconductor to repair oxygen vacancies (VO) is sometimes referred to as oxygen addition treatment.

[0122] When an oxide semiconductor is used for the semiconductor layer 108, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is preferably 1×1018 cm-3 or less, more preferably less than 1×1017 cm-3, further preferably less than 1×1016 cm-3, further preferably less than 1×1013 cm-3, and further preferably less than 1×1012 cm-3. Note that the lower limit of the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is not particularly limited, and can be, for example, 1×10-9 cm-3.

[0123] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has an extremely high field-effect mobility compared to a transistor using amorphous silicon. In addition, the OS transistor has an extremely small source-drain leakage current in an off state (hereinafter also referred to as an off-current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor in a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0124] The OS transistor can be applied to a display device. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a drive transistor included in the pixel circuit. Since an OS transistor has a higher source-drain withstand voltage than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by applying an OS transistor to a drive transistor of a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0125] When the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting device can be precisely controlled. This allows the pixel circuit to have a larger number of gray levels.

[0126] In terms of the saturation characteristics of the current that flows when the transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a drive transistor, for example, a stable current can be passed through a light-emitting device even when the current-voltage characteristics of the light-emitting device vary. In other words, when the OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is increased, so the light emission luminance of the light-emitting device can be stabilized.

[0127] As described above, by using an OS transistor for the driving transistor included in the pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," and "suppression of variation in light-emitting devices."

[0128] OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., have high resistance to radiation, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of flat panel detectors for X-rays. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0129] [Insulation layer] In the transistor of one embodiment of the present invention and a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for an insulating layer (the insulating layer 110, the insulating layer 106, the insulating layer 110s, the insulating layer 116, and the insulating layer 195). Alternatively, a stacked structure of an inorganic insulating material and an organic insulating material may be used for the insulating layer.

[0130] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0131] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0132] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0133] In addition, for example, Rutherford Backscattering Spectrometry (RBS) or X-Ray Reflection (XRR) can be used to evaluate the film density of an insulating layer. In addition, the difference in film density may be evaluated by a cross-sectional transmission electron microscopy (TEM) image. In TEM observation, if the film density is high, the transmission electron (TE) image is dense (dark), and if the film density is low, the transmission electron (TE) image is light (bright). Even if the same material is applied to the insulating layer, if the film densities are different, the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0134] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to a point where the count number of the element is a maximum value in a spectrum in which the horizontal axis indicates the energy of characteristic X-rays and the vertical axis indicates the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in the nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0135] The hydrogen concentration in the insulating layer can be evaluated by, for example, SIMS.

[0136] When hydrogen diffuses into the semiconductor layer 108, it reacts with oxygen atoms contained in the oxide semiconductor to form water, which may cause oxygen vacancies (VO) in the semiconductor layer 108. Furthermore, VOH may be formed in the semiconductor layer 108, which may increase the carrier concentration in the semiconductor layer 108. By using a blocking film that suppresses the diffusion of hydrogen as an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, it is possible to reduce oxygen vacancies (VO) and VOH in the semiconductor layer 108, and a transistor with good electrical characteristics and high reliability can be obtained.

[0137] It is preferable that the oxygen vacancies (VO) and VOH in the channel formation region of the transistor 100 are small. In particular, when the channel length L100 is short, the oxygen vacancies (VO) and VOH in the channel formation region have a large effect on the electrical characteristics and reliability of the transistor 100. For example, the diffusion of VOH from the source region or drain region to the channel formation region increases the carrier concentration in the channel formation region, which may cause a change in the threshold voltage of the transistor 100 or a decrease in reliability. The shorter the channel length L100 of the transistor 100, the larger the effect of such diffusion of VOH on the electrical characteristics and reliability of the transistor 100. By reducing the oxygen vacancies (VO) and VOH in the semiconductor layer 108, particularly in the channel formation region of the semiconductor layer 108, a transistor having a short channel length with good electrical characteristics and high reliability can be realized.

[0138] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108 (for example, the insulating layer 106 or the insulating layer 110s) or an insulating layer located around the semiconductor layer 108 (for example, the insulating layer 110), oxygen can be supplied from the insulating layer to the semiconductor layer 108. By supplying oxygen to the channel formation region of the semiconductor layer 108, oxygen vacancies (VO) and VOH in the semiconductor layer 108 can be reduced, and a transistor having good electrical characteristics and high reliability can be obtained. Note that other treatments for supplying oxygen to the semiconductor layer 108 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0139] It is preferable that an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108 releases little impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here refer to substances that may adversely affect the electrical characteristics of a transistor by diffusing into the semiconductor layer 108 and causing oxygen vacancies (VO) and VOH in the semiconductor layer 108. By reducing the release of impurities, the diffusion of the impurities into the semiconductor layer 108 is suppressed, and a transistor that exhibits good electrical characteristics and is highly reliable can be obtained.

[0140] Heat applied in a process after the formation of the semiconductor layer 108 may cause oxygen to be desorbed from the semiconductor layer 108. However, oxygen is supplied to the semiconductor layer 108 from an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, so that an increase in oxygen vacancies (VO) and VOH in the semiconductor layer 108 can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the process after the formation of the semiconductor layer 108. Specifically, the process temperature can be increased in the process after the formation of the semiconductor layer 108. Therefore, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be formed.

[0141] [Insulating layer 110] An inorganic insulating material or an organic insulating material can be used for the insulating layer 110 (the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c). The insulating layer 110 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0142] An inorganic insulating material can be suitably used for the insulating layer 110. As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used. As the insulating layer 110, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride can be used.

[0143] The insulating layer 110 may have a stacked structure of two or more layers. In FIG. 1B and other drawings, the insulating layer 110 has a stacked structure of an insulating layer 110a, an insulating layer 110b over the insulating layer 110a, and an insulating layer 110c over the insulating layer 110b. Note that the insulating layers 110a, 110b, and 110c may be made of the same material or different materials.

[0144] It is preferable that the insulating layer 110 releases little impurities (for example, water and hydrogen) from itself.

[0145] The insulating layer 110b may have a thickness greater than that of the insulating layer 110a and that of the insulating layer 110c. As described above, the insulating layer 110b is an insulating layer that contains oxygen to be supplied to the semiconductor layer 108. Therefore, by making the insulating layer 110b the thickest among the three insulating layers (insulating layer 110a, insulating layer 110b, and insulating layer 110c) that constitute the insulating layer 110, the amount of oxygen that can be contained in the insulating layer 110 as a whole can be increased. The deposition rate of the insulating layer 110b is preferably faster than that of the insulating layer 110a and that of the insulating layer 110c. By increasing the deposition rate of a thick film, productivity can be increased.

[0146] The insulating layer 110a and the insulating layer 110c each function as a blocking film that suppresses desorption of gas from the insulating layer 110b. The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for gas to diffuse into. The insulating layer 110a and the insulating layer 110c each preferably have a region with a higher film density than the insulating layer 110b. By increasing the film density of the insulating layer, the blocking ability against gas can be improved. By decreasing the film formation speed of the insulating layer, the film density increases, and the blocking ability against gas can be improved.

[0147] The insulating layer 110b is preferably formed using an oxide or an oxynitride. The insulating layer 110b is preferably formed using a film that releases oxygen when heated. The insulating layer 110b can be formed using, for example, silicon oxide or silicon oxynitride.

[0148] When the insulating layer 110b releases oxygen, oxygen can be supplied from the insulating layer 110b to the semiconductor layer 108 via the insulating layer 110s. The insulating layer 110b preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient, oxygen can be easily diffused in the insulating layer 110b, and oxygen can be efficiently supplied to the semiconductor layer 108. Furthermore, as described above, by making the insulating layer 110b thicker than the insulating layer 110a and the insulating layer 110c, more oxygen can be supplied to the semiconductor layer 108.

[0149] The insulating layer 110 is preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD method.

[0150] In particular, by forming the film by a sputtering method without using a gas containing hydrogen in the film formation gas, a film containing an extremely small amount of hydrogen can be obtained. Therefore, hydrogen can be prevented from being supplied to the semiconductor layer 108, and the electrical characteristics of the transistor 100 can be stabilized. When forming silicon oxide by a sputtering method, the film can be formed, for example, using a silicon target in an atmosphere containing an oxidizing gas. When forming silicon nitride by a sputtering method, the film can be formed, for example, using a silicon target in an atmosphere containing nitrogen gas. When forming aluminum oxide by a sputtering method, the film can be formed, for example, using an aluminum target in an atmosphere containing an oxidizing gas.

[0151] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0152] The insulating layer 110a and the insulating layer 110c can be formed using a material that contains more nitrogen than the insulating layer 110b. By increasing the nitrogen content of the insulating layer, the blocking property against oxygen and hydrogen can be improved.

[0153] The insulating layer 110a and the insulating layer 110c may have a region with a lower hydrogen concentration than the insulating layer 110b.

[0154] The insulating layer 110a and the insulating layer 110c are preferably impermeable to oxygen. Furthermore, the insulating layer 110a and the insulating layer 110c are preferably impermeable to hydrogen. The insulating layer 110a and the insulating layer 110c function as blocking films that suppress diffusion of hydrogen from the outside of the transistor to the semiconductor layer 108 through the insulating layer 110a and the insulating layer 110c. The film density of the insulating layer 110a and the insulating layer 110c is preferably higher than that of the insulating layer 110b. By increasing the film density of the insulating layer, the blocking property of oxygen and hydrogen can be improved. When silicon oxide or silicon oxynitride is used for the insulating layer 110b, silicon nitride or silicon nitride oxide can be used for the insulating layer 110a and the insulating layer 110c, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layer 110a and the insulating layer 110c.

[0155] Furthermore, each of the insulating layer 110a and the insulating layer 110c can have a stacked structure of two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide.

[0156] When oxygen contained in the insulating layer 110b diffuses downward (toward the substrate 102) from the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease. By providing the insulating layer 110a below the insulating layer 110b, it is possible to suppress the oxygen contained in the insulating layer 110b from diffusing downward from the insulating layer 110b. Furthermore, by providing the insulating layer 110c on the insulating layer 110b, it is possible to suppress the oxygen contained in the insulating layer 110b from diffusing upward from the insulating layer 110b. Therefore, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 increases, and the oxygen vacancy (VO) and VOH in the semiconductor layer 108 can be reduced.

[0157] Furthermore, by providing the insulating layers 110a and 110c, the diffusion of hydrogen into the semiconductor layer 108 can be suppressed, and oxygen vacancies (VO) and VOH in the semiconductor layer 108 can be reduced.

[0158] The insulating layer 110a and the insulating layer 110c each preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layer 110a and the insulating layer 110c are too thin, the function as a blocking film may be reduced. On the other hand, if the insulating layer 110b and the insulating layer 110c are too thick, the region of the semiconductor layer 108 facing the insulating layer 110b may be narrowed, and the amount of oxygen supplied to the semiconductor layer 108 may be reduced. The insulating layer 110a and the insulating layer 110c each preferably have a thickness (film thickness with respect to the surface on which the insulating layer 110a and the insulating layer 110c) of 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm.

[0159] [Insulating layer 106, insulating layer 110s] The insulating layer 106 and the insulating layer 110s, which function as gate insulating layers, preferably have a low defect density. The low defect density of the insulating layer 106 and the insulating layer 110s enables a transistor to have favorable electrical characteristics. Furthermore, the insulating layer 106 and the insulating layer 110s preferably have a high withstand voltage. The high withstand voltage of the insulating layer 106 and the insulating layer 110s enables a transistor to have high reliability.

[0160] Each of the insulating layers 106 and 110s is preferably an insulating layer containing oxygen. Furthermore, each of the insulating layers 106 and 110s is preferably an insulating layer that releases oxygen by heating. As a result, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layers 106 and 110s can be supplied to the metal oxide. As a result, oxygen vacancies in the metal oxide can be repaired, and the electrical characteristics and reliability of the transistor 100 can be improved.

[0161] For the insulating layer 106 and the insulating layer 110s, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties can be used. For the insulating layer 106 and the insulating layer 110s, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. For example, the insulating layer 106 and the insulating layer 110s may be a single layer or a stacked layer. For example, the insulating layer 106 and the insulating layer 110s may have a stacked structure of an oxide and a nitride.

[0162] In a miniaturized transistor, when the thickness of the gate insulating layer is thin, the leakage current may become large. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, and nitride containing silicon and hafnium.

[0163] The insulating layers 106 and 110s preferably release little impurities (for example, water and hydrogen) from themselves. When the insulating layers 106 and 110s release little impurities, the impurities are prevented from diffusing into the semiconductor layer 108, and the transistor can have favorable electrical characteristics and high reliability.

[0164] Since the insulating layer 106 is formed over the semiconductor layer 108, it is preferable that the insulating layer 106 is formed under conditions that cause little damage to the semiconductor layer 108. For example, it is preferable that the insulating layer 106 is formed under conditions that cause a sufficiently slow film formation speed (also referred to as a film formation rate). For example, when the insulating layer 106 is formed by a plasma CVD method, damage to the semiconductor layer 108 can be reduced by forming the insulating layer 106 under low power conditions.

[0165] Here, the insulating layer 106 and the insulating layer 110s will be specifically described using a structure in which the semiconductor layer 108 is made of a metal oxide as an example.

[0166] In order to improve interface characteristics with the semiconductor layer 108, at least one of an oxide and an oxynitride is preferably used for the insulating layer 106 and the insulating layer 110s on the side in contact with the semiconductor layer 108. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106 and the insulating layer 110s. More preferably, a film that releases oxygen by heating is used for the insulating layer 106 and the insulating layer 110s.

[0167] Note that the insulating layer 106 and the insulating layer 110s may have a stacked structure. The insulating layer 106 can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 108 and a nitride film in contact with the conductive layer 104. Similarly, the insulating layer 110s can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 108 and a nitride film facing the conductive layer 114. As the oxide film or oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, silicon nitride can be preferably used.

[0168] It is more preferable that the thickness of the insulating layer 106 and the insulating layer 110s (film thickness relative to the surface on which the insulating layer 106 and the insulating layer 110s are formed) is 1 nm or more and 100 nm or less. It is sufficient that at least a part of the insulating layer 106 and the insulating layer 110s has a region with the above-mentioned thickness.

[0169] [Conductive layer 112a, conductive layer 112b] The conductive layer 112a and the conductive layer 112b functioning as a source electrode and a drain electrode can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. A low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be preferably used for the conductive layer 112a and the conductive layer 112b. Copper or aluminum is particularly preferable because of its excellent mass productivity.

[0170] The conductive layer 112a and the conductive layer 112b can each be formed using a metal oxide film (also referred to as an oxide conductor). Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0171] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

[0172] Each of the conductive layers 112a and 112b may have a stacked structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0173] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used for each of the conductive layers 112a and 112b. By using the Cu-X alloy film, it is possible to process it by a wet etching method, so that it is possible to reduce manufacturing costs.

[0174] Note that the conductive layers 112a and 112b may be formed using the same material or different materials.

[0175] Here, the conductive layers 112a and 112b will be specifically described using an example in which the semiconductor layer 108 is formed using a metal oxide.

[0176] When an oxide semiconductor is used for the semiconductor layer 108, the conductive layer 112a and the conductive layer 112b may be oxidized by oxygen contained in the semiconductor layer 108, resulting in an increase in resistance. The conductive layer 112a and the conductive layer 112b may be oxidized by oxygen contained in the insulating layer 110 and the insulating layer 110s, resulting in an increase in resistance. In addition, the conductive layer 112a and the conductive layer 112b may be oxidized by oxygen contained in the semiconductor layer 108, resulting in an increase in oxygen vacancies (VO) in the semiconductor layer 108. The conductive layer 112a and the conductive layer 112b may be oxidized by oxygen contained in the insulating layer 110 and the insulating layer 110s, resulting in a decrease in the amount of oxygen supplied to the semiconductor layer 108 from the insulating layer 110 and the insulating layer 110s.

[0177] The conductive layer 112a and the conductive layer 112b are preferably made of a material that is not easily oxidized. The conductive layer 112a and the conductive layer 112b are preferably made of an oxide conductor. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be suitably used. The conductive layer 112a and the conductive layer 112b may be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 112a and the conductive layer 112b may have a stacked structure of the above-mentioned materials.

[0178] By using a material that is not easily oxidized for the conductive layer 112a and the conductive layer 112b, it is possible to suppress an increase in resistance due to oxidation caused by oxygen contained in the semiconductor layer 108 or oxygen contained in the insulating layer 110 and the insulating layer 110s. In addition, an increase in oxygen vacancies (VO) in the semiconductor layer 108 is suppressed, and the amount of oxygen supplied to the semiconductor layer 108 from the insulating layer 110 and the insulating layer 110s can be increased.

[0179] [Conductive layer 104, conductive layer 114] The conductive layer 104 and the conductive layer 114 functioning as a gate electrode and a back gate electrode can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. The conductive layer 104 and the conductive layer 114 may be formed using the materials that can be used for the conductive layer 112a and the conductive layer 112b. As described above, the conductive layer 114 is preferably made of a conductive material that is easily oxidized in order to provide the insulating layer 116 that can be formed by plasma treatment or the like in an oxygen atmosphere on the side and upper surfaces of the conductive layer 114. For example, the conductive layer 114 is preferably made of aluminum.

[0180] 1B and the like, the conductive layer 104 is shown as having a single-layer structure, but this is not the only possible embodiment. For example, the conductive layer 104 may have a stacked structure of two or more layers. For example, when the conductive layer 104 has a two-layer stacked structure, a nitride or an oxide can be used as a first conductive layer (conductive layer on the insulating layer 106 side), and a second conductive layer can be made of one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. Furthermore, for example, when the conductive layer 104 has a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 106 side) can be an alloy containing one or more of the above-mentioned metals or a nitride of the metal or the alloy, the second conductive layer can be an alloy containing one or more of the above-mentioned metals, and the third conductive layer can be an alloy containing one or more of the above-mentioned metals or a nitride of the metal or the alloy.

[0181] [Insulating layer 116] The insulating layer 116 is an oxide containing the elements contained in the conductive layer 114. The insulating layer 116 can be an oxide of the conductive layer 114, specifically, a metal oxide such as aluminum oxide or tantalum oxide. For example, when aluminum is used for the conductive layer 114, the insulating layer 116 becomes aluminum oxide. The insulating layer 116 is preferably an insulating layer that can be formed by performing plasma treatment on the conductive layer 114 in an oxygen atmosphere, or the like.

[0182] The insulating layer 116 is preferably an insulating layer having blocking properties against oxygen, similar to the insulating layer 110a and the insulating layer 110c. This can prevent oxygen released from the insulating layer 110s and the insulating layer 110b from diffusing to the conductive layer 114 side through the insulating layer 116. Furthermore, since an insulating layer having the same function as the insulating layer 110a and the insulating layer 110c can be formed without using a film formation method such as a plasma CVD method or a sputtering method, the number of times the above film formation method is applied can be reduced, and productivity can be increased in some cases. An example of the insulating layer 116 that satisfies the above conditions is aluminum oxide.

[0183] [Insulating layer 195] The insulating layer 195, which functions as a protective layer for the transistor 100, is preferably made of a material that is difficult for impurities to diffuse into. By providing the insulating layer 195, it is possible to effectively suppress the diffusion of impurities from the outside into the transistor, and the reliability of the transistor can be improved. Examples of impurities include water and hydrogen. The insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material. For example, an inorganic material such as an oxide, an oxynitride, a nitride oxide, or a nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of an acrylic resin and a polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 195 may have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.

[0184] [Substrate 102] There are no significant limitations on the material of the substrate 102, but the material must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which a semiconductor element is provided may be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0185] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device that is partially or entirely completed thereon from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0186] [Composition of Metal Oxide in Semiconductor Layer 108] The composition of the metal oxide contained in the semiconductor layer 108 will be described below.

[0187] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100.

[0188] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0189] When an In-Zn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these can be used.

[0190] When an In-Sn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these can be used.

[0191] When an In-M-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108 can use metal oxides having an atomic ratio of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or a metal oxide having an atomic ratio close to these.

[0192] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of the element M. In addition, it is preferable that the atomic ratios of indium, the element M, and zinc are in the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be the atomic ratio of the element M. In addition, it is preferable that the atomic ratios of indium, the element M, and zinc are in the above-mentioned range.

[0193] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic %, preferably 30 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 90 atomic %, more preferably 40 atomic % or more and 90 atomic %, more preferably 45 atomic % or more and 90 atomic %, more preferably 50 atomic % or more and 80 atomic %, more preferably 60 atomic % or more and 80 atomic %, more preferably 70 atomic % or more and 80 atomic %. For example, when an In-Ga-Zn oxide is used for the semiconductor layer 108, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is in the above-mentioned range.

[0194] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0195] By increasing the content of indium in the metal oxide, a transistor with a large on-state current can be obtained. When the transistor is used as a transistor that is required to have a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0196] For example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used to analyze the composition of the metal oxide. Alternatively, a combination of these techniques may be used to perform the analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, quantification may be difficult, or element M may not be detected.

[0197] In the present specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when the atomic ratio is described as In:M:Zn=4:2:3 or a composition in the vicinity thereof, it includes the case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. When the atomic ratio is described as In:M:Zn=5:1:6 or a composition in the vicinity thereof, it includes the case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. When the atomic ratio is described as In:M:Zn=1:1:1 or a composition in the vicinity thereof, it includes the case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0198] Here, the reliability of transistors will be described. One of the indicators for evaluating the reliability of transistors is the GBT (Gate Bias Temperature) stress test, in which the gate is held at high temperature while an electric field is applied to the gate. Among them, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and drain potential and the gate is held at high temperature is called the PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential (negative bias) is applied to the gate and the gate is held at high temperature is called the NBTS (Negative Bias Temperature Stress) test. The PBTS and NBTS tests, which are performed under light irradiation, are called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0199] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (current passing state), so the amount of variation in threshold voltage in the PBTS test is one of the important items to note as an indicator of the reliability of the transistor.

[0200] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be obtained. That is, a transistor with a small variation in threshold voltage in a PBTS test can be obtained. When a metal oxide that contains gallium is used, the gallium content is preferably lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0201] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the amount of carrier trapping into the defect levels, and the more significant the degradation in the PBTS test. The generation of the defect levels can be suppressed by lowering the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0202] The reason why the use of a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer can suppress the variation in threshold voltage in the PBTS test is, for example, as follows. Gallium contained in the metal oxide has a property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium bonds with excess oxygen in the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, it is considered that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing the threshold voltage to vary.

[0203] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be applied to the semiconductor layer 108. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga to the semiconductor layer 108.

[0204] The semiconductor layer 108 is preferably made of a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is higher than 0 atomic % and not more than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By lowering the content of gallium in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. In addition, by including gallium in the metal oxide, an effect is achieved in that oxygen vacancies (VO) are less likely to occur in the metal oxide.

[0205] Metal oxides not containing gallium may be applied to the semiconductor layer 108. For example, In-Zn oxide may be applied to the semiconductor layer 108. In this case, the field effect mobility of the transistor can be increased by increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide. On the other hand, by increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, so that the fluctuation of the electrical characteristics of the transistor is suppressed and the reliability can be increased. In addition, metal oxides not containing gallium and zinc, such as indium oxide, may be applied to the semiconductor layer 108. By using a metal oxide not containing gallium, the fluctuation of the threshold voltage in the PBTS test can be made extremely small.

[0206] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide in which the atomic ratio of metal elements is, for example, In:Zn=2:3 or a ratio close thereto can be used.

[0207] Although gallium has been described as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0208] A transistor with high reliability against application of a positive bias can be obtained by using a metal oxide with a low content of element M for the semiconductor layer 108. By using the transistor as a transistor that is required to have high reliability against application of a positive bias, a highly reliable semiconductor device can be obtained.

[0209] Next, the reliability of the transistor against light will be described.

[0210] When light is incident on a transistor, the electrical characteristics of the transistor may vary. In particular, it is preferable that a transistor applied to a region where light can be incident has small variations in electrical characteristics under light irradiation and high reliability against light. The reliability against light can be evaluated, for example, by the amount of variation in threshold voltage in an NBTIS test.

[0211] By increasing the content of element M in the metal oxide, a transistor with high reliability against light can be obtained. That is, a transistor with a small variation in threshold voltage in the NBTIS test can be obtained. Specifically, a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and the variation in threshold voltage of the transistor in the NBTIS test can be reduced. The band gap of the metal oxide in the semiconductor layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more, more preferably 3.0 eV or more, more preferably 3.2 eV or more, more preferably 3.3 eV or more, more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0212] For example, the semiconductor layer 108 can use metal element atomic ratios of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or metal oxides close to these.

[0213] For the semiconductor layer 108, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0214] When an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the atomic number of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0215] For the semiconductor layer 108, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0216] A transistor with high reliability against light can be obtained by using a metal oxide with a high content of element M for the semiconductor layer 108. By using the transistor as a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be obtained.

[0217] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the semiconductor layer 108. Thus, by varying the composition of the metal oxide in accordance with the electrical characteristics and reliability required for a transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be provided.

[0218] The semiconductor layer 108 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs.

[0219] The two or more metal oxide layers in the semiconductor layer 108 may have different compositions. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer, may be preferably used. In addition, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0220] <Configuration example 2> Fig. 4A shows a structural example of a transistor 100A having a different structure from the transistor 100 shown in Fig. 1A to Fig. 2. Fig. 4A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in Fig. 1A.

[0221] A transistor 100A illustrated in FIG. 4A differs from the transistor 100 illustrated in FIG. 1B mainly in that a bottom end of an insulating layer 110s is in contact with an upper surface of a conductive layer 112a.

[0222] In the transistor 100A, the side surfaces of the insulating layer 110a, the side surfaces of the insulating layer 116, the side surfaces of the insulating layer 110b, the side surfaces of the insulating layer 110c, and the side surfaces of the conductive layer 112b are aligned or approximately aligned in the opening 143. That is, unlike the transistor 100, in the transistor 100A, the insulating layer 110a does not have a protruding portion in the opening 143. Also, the insulating layer 110s is provided in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the insulating layer 116, the side surface of the insulating layer 110b, the side surface of the insulating layer 110c, and the side surface of the conductive layer 112b, respectively, in the opening 143.

[0223] The above-described structure of the transistor 100A may cause oxygen in the insulating layer 110s to diffuse into the conductive layer 112a. However, when the conductive layer 112a is made of a material that is not easily oxidized, as described above, it is not necessary to leave a part of the insulating layer 110a between the insulating layer 110s and the conductive layer 112a. The introduction of the structure of the transistor 100A may provide more freedom in fabrication than the transistor 100, making it easier to fabricate the transistor.

[0224] With respect to the transistor 100A, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0225] <Configuration example 3> Fig. 4B shows a structural example of a transistor 100B, which has a different structure from the transistor 100 shown in Fig. 1A to Fig. 2. Fig. 4B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in Fig. 1A.

[0226] 4B is different from the transistor 100 shown in FIG 1B mainly in that the insulating layer 110s has a stacked structure of an insulating layer 110s1 and an insulating layer 110s2 over the insulating layer 110s1. In addition, in the transistor 100B, the insulating layer 116 is not provided on the side surface of the conductive layer 114 on the opening 143 side. The insulating layer 110s1 is provided in contact with a top surface of the conductive layer 112a, a side surface of the insulating layer 110a, a side surface of the conductive layer 114, a side surface of the insulating layer 116, a side surface of the insulating layer 110b, a side surface of the insulating layer 110c, and a side surface of the conductive layer 112b. The insulating layer 110s2 is arranged to face, via the insulating layer 110s1, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the conductive layer 114, the side surface of the insulating layer 116, the side surface of the insulating layer 110b, the side surface of the insulating layer 110c, and the side surface of the conductive layer 112b.

[0227] For example, the material, the manufacturing method, etc. used for the insulating layer 110a and the insulating layer 110c can be applied to the insulating layer 110s1. For example, the material, the manufacturing method, etc. used for the insulating layer 110b can be applied to the insulating layer 110s2.

[0228] In the case where the insulating layer 110s2 having a function of supplying oxygen is in contact with the conductive layer 114, there is a concern that the conductive layer 114 is oxidized, the amount of oxygen contained in the insulating layer 110s2 is reduced, and the amount of oxygen supplied from the insulating layer 110s2 to the semiconductor layer 108 is reduced. By forming the insulating layer 110s as a stacked structure of the insulating layer 110s1 and the insulating layer 110s2, the insulating layer 110s2 and the conductive layer 114 can be prevented from being in contact with each other. This can prevent the conductive layer 114 from being oxidized by the oxygen contained in the insulating layer 110s2. In addition, a decrease in the amount of oxygen supplied from the insulating layer 110s2 to the semiconductor layer 108 can be prevented.

[0229] Furthermore, by providing the insulating layer 110s1, it is possible to eliminate the step of providing the insulating layer 116 on the side surface of the conductive layer 114 on the opening 143 side. Furthermore, since the insulating layer 110s2 can be configured not to be in contact with either the conductive layer 112a or the conductive layer 112b, it is possible to prevent oxygen contained in the insulating layer 110s2 from diffusing not only to the conductive layer 112a side but also to the conductive layer 112b side. Therefore, it is possible to apply a conductive material that is easily oxidized and has low resistance to both the conductive layer 112a and the conductive layer 112b, thereby expanding the range of material options.

[0230] With respect to the transistor 100B, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0231] <Configuration Example 4> Fig. 5A illustrates a configuration example of a transistor 100C that is different from the transistor 100 illustrated in Fig. 1A to Fig. 2. Fig. 5A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in Fig. 1A.

[0232] The transistor 100C shown in FIG. 5(A) differs from the transistor 100 shown in FIG. 1(B) mainly in that the transistor 100C does not have a conductive layer 112b and that the end portion of the semiconductor layer 108 extends to the outside of the conductive layer 114 and the conductive layer 112a in a planar view.

[0233] In the transistor 100C, the semiconductor layer 108 has a region in contact with a top surface of the conductive layer 112a, a side surface of the insulating layer 110s, and a top surface of the insulating layer 110c. In the transistor 100C, the semiconductor layer 108 can function as a semiconductor layer having a channel formation region and as the other of the source electrode and the drain electrode. For example, a region of the semiconductor layer 108 facing the insulating layer 110s in the opening 143 can function as a channel formation region. In addition, a region located outside the channel formation region (a region in contact with the top surface of the insulating layer 110c) can function as the other of the source electrode and the drain electrode.

[0234] By reducing the resistance of a part of the semiconductor layer 108, the part can be used as a source region and a drain region of a transistor. For example, the semiconductor layer 108 can be reduced in resistance by supplying an impurity functioning as a dopant, such as boron, to the semiconductor layer 108 from a direction perpendicular to the substrate surface by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. Alternatively, when an oxide semiconductor is used for the semiconductor layer 108, a silicon nitride film or the like can be formed on a region of the semiconductor layer 108 that does not overlap with the opening 143 to make the region an oxide conductor (OC), thereby forming a low-resistance region in the semiconductor layer 108. In this manner, the region corresponding to the source region and the drain region of the semiconductor layer 108 can be made lower in resistance than the channel formation region. Therefore, the channel formation region and the source region and the drain region having a lower resistance than the channel formation region can be separately formed in the semiconductor layer 108. As a result, in the transistor 100C, the region corresponding to the source electrode and the drain electrode can be formed in the semiconductor layer 108 without providing the conductive layer 112b. Therefore, in the transistor 100C, the conductive layer 112b is not provided, and therefore the number of steps required for manufacturing the transistor can be reduced.

[0235] With respect to the transistor 100C, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0236] <Configuration Example 5> Fig. 5B illustrates a structural example of a transistor 100D, which has a different structure from the transistor 100 illustrated in Fig. 1A to Fig. 2. Fig. 5B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in Fig. 1A.

[0237] The transistor 100D shown in FIG. 5B differs from the transistor 100C shown in FIG. 5A mainly in that the insulating layers corresponding to the insulating layers 110b and 110c in the transistor 100 are replaced with an insulating layer 110d having a single-layer structure.

[0238] In the transistor 100D, the insulating layer 110d is preferably made of a material that can be used for the insulating layer 110a and the insulating layer 110c. For example, the insulating layer 110d is preferably made of silicon nitride or silicon nitride oxide. That is, it is preferable to use a material that has high blocking properties against oxygen and hydrogen. This can suppress the conductive layer 114 from being oxidized due to the diffusion of oxygen from the outside of the insulating layer 110a and the insulating layer 110d. In addition, it can suppress the diffusion of oxygen in the semiconductor layer 108 to the insulating layer 110a and the insulating layer 110d side, and the formation of oxygen vacancies (VO) in the semiconductor layer 108. In addition, by providing the insulating layer 110d, it is possible to reduce the step of forming the insulating layer 116 at the interface between the conductive layer 114 and the insulating layer 110d. In addition, since the insulating layer 110d has a single-layer structure, the number of steps related to the formation of the insulating layer 110 can be reduced compared to the transistor 100 and the like.

[0239] With respect to the transistor 100D, the same description as given for the transistor 100C can be referred to except for the points mentioned above.

[0240] <Configuration Example 6> Fig. 6A illustrates a configuration example of a transistor 100E that has a different configuration from the transistor 100 illustrated in Fig. 1A to Fig. 2. Fig. 6A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in Fig. 1A.

[0241] A transistor 100E illustrated in FIG. 6A differs from the transistor 100 illustrated in FIG. 1B mainly in that the conductive layer 112a has a layered structure.

[0242] In the transistor 100E, the conductive layer 112a has a stacked structure of a conductive layer 112a_1 and a conductive layer 112a_2 on the conductive layer 112a_1. The conductive layer 112a_1 is provided to be embedded in an opening formed in an insulating layer 115 on the substrate 102, and the upper surfaces of the conductive layer 112a_1 and the insulating layer 115 are planarized. The conductive layer 112a_2 is located on the conductive layer 112a_1 and the insulating layer 115. The transistor 100E has a configuration in which the height of the upper surface of the insulating layer 115 and the height of the upper surface of the conductive layer 112a_1 are the same or approximately the same.

[0243] In the transistor 100E, the height of the upper surface of the insulating layer 115 and the height of the upper surface of the conductive layer 112a_1 are made equal or approximately equal to each other, so that the steps on the surfaces on which the insulating layer 110 and the conductive layer 112b are formed can be reduced. This makes it possible to reduce the steps that may be formed on the upper surface of the conductive layer 112b and the upper surface of the insulating layer 110. Therefore, in the step of forming the insulating layer 110s (e.g., an etch-back step or the like), it is possible to suppress the insulating layer from remaining on the upper surface of the conductive layer 112b and the upper surface of the insulating layer 110, and it is possible to selectively form the insulating layer only on the side surface of the insulating layer 116, the side surface of the insulating layer 110b, the side surface of the insulating layer 110c, and the side surface of the conductive layer 112b in the opening 143.

[0244] In addition, the process of forming a planarizing film on an uneven film surface and performing highly anisotropic etching (e.g., dry etching) on ​​the uneven film together with the planarizing film to reduce the unevenness of the film is sometimes called an "etch-back process."

[0245] In the transistor 100E, an example is shown in which the end of the conductive layer 112a_2 is located outside the end of the conductive layer 112a_1, but the end of the conductive layer 112a_2 may be located inside the end of the conductive layer 112a_1. When a plug is provided to connect the conductive layer 112a to an upper conductive layer, the conductive layer 112a_2 may be extended outside the conductive layer 112a_1, and the upper surface of the conductive layer 112a_2 may be in contact with the plug in the extended region. The plug is provided to fill the opening of the insulating layer 110, the insulating layer 195, etc.

[0246] As described above, the conductive layer 112a and the conductive layer 112b in contact with the semiconductor layer 108 are preferably made of a material that is not easily oxidized. However, when a material that is not easily oxidized is used, the resistance of the conductive layer 112a and the conductive layer 112b may become high. Since the conductive layer 112a and the conductive layer 112b function as wirings, their resistance is preferably low. Thus, by using a material that is not easily oxidized for the conductive layer 112a_2 having a region in contact with the semiconductor layer 108 and using a material with low resistance for the conductive layer 112a_1 not having a region in contact with the semiconductor layer 108, the resistance of the conductive layer 112a as a whole can be reduced.

[0247] As described above, oxygen vacancies (VO) and VOH in the channel formation region have a large effect on the electrical characteristics and reliability of the transistor, particularly when the channel length is short. By using a material that is not easily oxidized for the conductive layer 112a_2, it is possible to suppress an increase in oxygen vacancies (VO) and VOH in the semiconductor layer 108. Therefore, a transistor having a short channel length and excellent electrical characteristics and high reliability can be realized.

[0248] The conductive layer 112a_2 can be preferably made of one or more of an oxide conductor and a nitride conductor. The conductive layer 112a_1 can be preferably made of a material having a lower resistance than the conductive layer 112a_2. The conductive layer 112a_1 can be preferably made of, for example, one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above-mentioned metals. Specifically, the conductive layer 112a_2 can be preferably made of In-Sn-Si oxide (ITSO), and the conductive layer 112a_1 can be preferably made of tungsten.

[0249] An inorganic insulating material or an organic insulating material can be used for the insulating layer 115. The insulating layer 115 may have a stacked structure of an inorganic insulating material and an organic insulating material. For example, the insulating layer 115 can be preferably made of any of the materials and structures given for the insulating layer 110a, the insulating layer 110c, the insulating layer 195, and the like.

[0250] With respect to the transistor 100E, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0251] <Configuration Example 7> Fig. 6B shows a structural example of a transistor 100F that is different from the transistor 100 shown in Fig. 1A to Fig. 2. Fig. 6B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in Fig. 1A.

[0252] A transistor 100F illustrated in FIG. 6B is different from the transistor 100 illustrated in FIG. 1B mainly in the structure of the conductive layer 104 and the structure of the insulating layer 195.

[0253] In the transistor 100F, the conductive layer 104 is provided to fill a recess formed on the semiconductor layer 108 and the insulating layer 106 that reflects the shape of the opening 143, and the insulating layer 195 is provided to fill the conductive layer 104. In the transistor 100F, the upper surface of the conductive layer 104 and the upper surface of the insulating layer 195 are flattened and have the same or approximately the same height.

[0254] When the transistor 100F has the above structure, the coverage of films provided over the conductive layer 104 and the insulating layer 195 can be improved.

[0255] With respect to the transistor 100F, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0256] <Production method example> A method for manufacturing a transistor of one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100 illustrated in FIG. 1B and the like will be used as an example.

[0257] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0258] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when forming an insulating film, and DC sputtering is mainly used when forming a metal conductive film. Pulsed DC sputtering is mainly used when forming a compound such as an oxide, nitride, or carbide by reactive sputtering.

[0259] CVD methods can be classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD: Thermal CVD) methods that use heat, and photo CVD (Photo CVD) methods that use light, etc. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal Organic CVD) methods.

[0260] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0261] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0262] The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable, for example, for covering the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0263] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0264] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0265] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0266] When processing the thin film constituting the semiconductor device, it can be processed using a photolithography method or the like. In addition, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like. Also, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0267] There are two typical photolithography methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0268] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0269] The thin film can be etched by, for example, dry etching, wet etching, or sandblasting.

[0270] As a representative example of the planarization treatment of the thin film, a polishing treatment method such as a CMP method can be preferably used. A reflow method in which a conductive layer is subjected to a heat treatment and fluidized can be preferably used. A combination of the reflow method and the CMP method can also be used. In addition, a dry etching treatment or a plasma treatment can also be used. The polishing treatment, the dry etching treatment, and the plasma treatment can be performed multiple times, or they can be performed in combination. In the case of performing the combined treatment, the order of the steps is not particularly limited, and can be appropriately set according to the unevenness of the surface to be treated.

[0271] In order to precisely process the thin film to a desired thickness, for example, a CMP method is used. In this case, the thin film is first polished at a constant processing speed until a part of the upper surface of the thin film is exposed. Then, the thin film is polished at a slower processing speed until the thin film has a desired thickness, thereby enabling highly precise processing.

[0272] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and the change in the reflected light is detected, a physical method in which the polishing resistance experienced by the processing device from the surface to be treated is detected, and a method in which magnetic lines are applied to the surface to be treated and the change in the magnetic lines due to the generated eddy currents is used.

[0273] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process under conditions of a slow processing speed while monitoring the thickness of the thin film by an optical method using a laser interferometer, etc. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0274] 7A to 10C illustrate a method for manufacturing the transistor 100. Each of the drawings illustrates a cross-sectional view taken along dashed line A1-A2 in the plan view illustrated in FIG.

[0275] First, a conductive film to be the conductive layer 112a is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layer 112a (FIG. 7A). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0276] Subsequently, an insulating film 110a_f is formed on the conductive layer 112a and the substrate 102.

[0277] For the insulating film 110a_f, any of the materials that can be used for the insulating layer 110a described above can be used as appropriate.

[0278] As the insulating film 110a_f, for example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be suitably used.

[0279] Specifically, as the insulating film 110a_f, for example, a silicon nitride film can be formed by a sputtering method, or a silicon nitride film can be formed by a PEALD method, or an aluminum oxide film can be formed by a sputtering method.

[0280] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used. For example, a structure in which aluminum oxide formed by a sputtering method and silicon nitride formed by a PEALD method are stacked can be used.

[0281] Subsequently, a conductive film 114_f is formed on the insulating film 110a_f (FIG. 7(B)).

[0282] The conductive film 114_f can be formed using any of the above-described materials that can be used for the conductive layer 114. Note that the conductive film 114_f is preferably formed using a material that is easily oxidized because a surface of the conductive film 114_f is oxidized in a later step to form an insulating layer that becomes the insulating layer 116. For example, the conductive layer 114 can be preferably formed using aluminum.

[0283] The conductive film 114_f can be formed by, for example, a sputtering method.

[0284] Next, the conductive film 114_f is processed to form a conductive layer 114_e (FIG. 7C). The conductive layer 114_e is formed to have a region overlapping with the conductive layer 112a.

[0285] Next, the conductive layer 114_e is subjected to a plasma treatment in an atmosphere containing oxygen to oxidize the surface of the conductive layer 114_e, thereby forming an insulating layer 116_e on the upper and side surfaces of the conductive layer 114_e (FIG. 7(D)). For example, when aluminum is used as the material of the conductive layer 114_e, the surface of the conductive layer 114_e is oxidized by the plasma treatment, so that aluminum oxide is formed on the upper and side surfaces of the conductive layer 114_e, which becomes the insulating layer 116_e.

[0286] Subsequently, an insulating film 110b_f is formed on the insulating film 110a_f and the insulating layer 116_e, and an insulating film 110c_f is formed on the insulating film 110b_f.

[0287] For the insulating film 110b_f, any of the materials that can be used for the insulating layer 110b described above can be used as appropriate.

[0288] As the insulating film 110b_f, for example, silicon oxide, silicon oxynitride, or the like can be suitably used.

[0289] Specifically, as the insulating film 110b_f, for example, a silicon oxide film can be formed by using a sputtering method. Alternatively, for example, a silicon oxide film can be formed by using a PECVD method. Alternatively, for example, a silicon oxynitride film can be formed by using a PECVD method.

[0290] Also, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked together.

[0291] After the insulating film 110b_f is formed, heat treatment may be performed, which can release water and hydrogen from the surface and inside of the insulating film 110b_f.

[0292] The temperature of the heat treatment is preferably 150° C. or higher and lower than the distortion point of the substrate, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, dry air (CDA: Clean Dry Air) may be used. It is preferable that the content of hydrogen, water, and the like in the atmosphere is as small as possible. As the atmosphere, it is preferable to use a high purity gas having a dew point of −60° C. or lower, preferably −100° C. or lower. By using an atmosphere containing as little hydrogen, water, and the like as possible, it is possible to prevent hydrogen, water, and the like from being taken into the insulating film 110b_f as much as possible. For the heat treatment, for example, an oven or a rapid heating (RTA: Rapid Thermal Annealing) device can be used. By using an RTA device, the heat treatment time can be shortened.

[0293] After the heat treatment, a step of supplying oxygen to the insulating film 110b_f may be performed. For example, after the insulating film 110b_f is formed, a metal oxide layer may be formed on the insulating film 110b_f to supply oxygen to the insulating film 110b_f. Alternatively, a heat treatment may be performed after the metal oxide layer is formed. By performing a heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b_f, and oxygen can be contained in the insulating film 110b_f. The oxygen supplied to the insulating film 110b_f is supplied to the semiconductor layer 108 in a later step, whereby oxygen vacancies (VO) and VOH in the semiconductor layer 108 can be reduced.

[0294] After the metal oxide layer is formed or after the above-described heat treatment, oxygen may be further supplied to the insulating film 110b_f through the metal oxide layer. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. As the plasma treatment, an apparatus that turns oxygen gas into plasma by high-frequency power can be preferably used. As an apparatus that turns gas into plasma by high-frequency power, for example, a plasma etching apparatus and a plasma ashing apparatus can be used.

[0295] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-doped indium tin oxide (ITSO).

[0296] For the metal oxide layer, it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108. Since the metal oxide layer can be formed using the same sputtering target as that for the semiconductor layer 108, manufacturing costs can be reduced.

[0297] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher composition (content) of gallium than the semiconductor layer 108 can be used. By using a material having a higher composition (content) of gallium for the metal oxide layer, blocking properties against oxygen can be further improved. This is preferable because oxygen contained in the insulating film 110b_f can be prevented from being released to the outside.

[0298] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, the metal oxide layer is preferably formed in an atmosphere containing oxygen by a sputtering method. In this way, oxygen can be suitably supplied to the insulating film 110b_f during the formation of the metal oxide layer.

[0299] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0300] The process of supplying oxygen to the insulating film 110b_f is not limited to the above-mentioned method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like is supplied to the insulating film 110b_f by an ion doping method, an ion implantation method, a plasma treatment, or the like. Alternatively, after a film that suppresses oxygen desorption is formed over the insulating film 110b_f, oxygen may be supplied to the insulating film 110b_f through the film. The film is preferably removed after the oxygen is supplied. As the above-mentioned film that suppresses oxygen desorption, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0301] For the insulating film 110c_f, any of the materials that can be used for the insulating layer 110c described above can be used as appropriate.

[0302] For the material and deposition method that can be used for the insulating film 110c_f, the above description regarding the material and deposition method that can be used for the insulating film 110a_f can be referred to.

[0303] Next, a conductive film 112b_f is formed over the insulating film 110c_f. The conductive film 112b_f can be formed using any of the materials that can be used for the conductive layer 112b described above.

[0304] The conductive film 112b_f can be formed by, for example, a sputtering method.

[0305] Next, a resist mask 191 is formed over the conductive film 112b_f by photolithography (FIG. 8A).

[0306] Then, a part of the conductive film 112b_f is removed using the resist mask 191 as a mask to form a conductive layer 112b_e. After the conductive layer 112b_e is formed, the resist mask 191 is removed (FIG. 8B).

[0307] Then, a process is performed to remove a part of each of the conductive layer 112b_e, the insulating film 110c_f, the insulating film 110b_f, the insulating layer 116_e, the conductive layer 114_e, and the insulating film 110a_f to form an opening 141. For example, a dry etching method can be suitably used for this process. By this process, the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, the insulating layer 116, and the conductive layer 114 each having an opening, and the insulating layer 110a_e having a recess are formed (FIG. 8(C)). It can be said that the opening 141 is composed of the openings formed in each of the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, the insulating layer 116, and the conductive layer 114, and the recesses of the insulating layer 110a_e formed in the regions overlapping with the openings.

[0308] 8C shows an example in which a part of the upper surface of the insulating film 110a_f is removed by forming the opening 141, and an insulating layer 110a_e having a recess is formed, but this is not limited thereto. A process may be performed in which a part of the upper surface of the insulating film 110a_f is not removed when the opening 141 is formed. In this case, the opening 141 can be said to be composed of openings formed in each of the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, the insulating layer 116, and the conductive layer 114.

[0309] Next, the side surface of the conductive layer 114 exposed in the opening 141 is subjected to plasma treatment in an atmosphere containing oxygen to oxidize the side surface, thereby forming an insulating layer 116 on the side surface (FIG. 9(A)). For example, when aluminum is used as the material of the conductive layer 114, the exposed side surface of the conductive layer 114 is oxidized by the plasma treatment to form aluminum oxide on the side surface, which becomes the insulating layer 116.

[0310] Next, an insulating film 110s_f is formed in contact with the upper surface of the conductive layer 112b, the side surfaces of the conductive layer 112b in the openings 141, the side surfaces of the insulating layer 110c, the side surfaces of the insulating layer 110b, the side surfaces of the insulating layer 116, and the side surfaces and upper surface of the insulating layer 110a_e (Figure 9(B)).

[0311] For the insulating film 110s_f, any of the materials that can be used for the insulating layer 110s described above can be used as appropriate.

[0312] It is preferable to form the insulating film 110s_f using a CVD method, an ALD method, or the like, since the insulating film 110s_f can be well coated on the side surfaces of the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, the insulating layer 116, and the insulating layer 110a_e within the opening 141.

[0313] Then, a process of removing a part of the insulating film 110s_f by etching is performed. Specifically, a region of the insulating film 110s_f in contact with the upper surface of the conductive layer 112b and a region in contact with the upper surface of the insulating layer 110a_e in the opening 141 are removed. In addition, the insulating layer 110a_e overlapping with a part of the upper surface of the insulating film 110s_f in the opening 141 is also removed. As a result, an opening 143 reaching the conductive layer 112a is formed, and an insulating layer 110a having a part protruding into the opening 143 and an insulating layer 110s in contact with the side of the conductive layer 112b, the side of the insulating layer 110c, the side of the insulating layer 110b, the side of the insulating layer 116, and the upper surface of the protruding part of the insulating layer 110a in the opening 143 are formed (FIG. 9(C)). It can be said that the opening 143 is composed of the opening 141 and an opening (having a smaller diameter than the opening 141) in the insulating layer 110a formed by this treatment.

[0314] The insulating film 110s_f can be etched by, for example, anisotropic etching. More specifically, the insulating layer 110s can be formed by, for example, performing highly anisotropic dry etching.

[0315] The insulating layer 110s has a curved upper end portion. By changing the conditions of the anisotropic etching, the height of the upper end portion of the insulating layer 110s can be adjusted as shown in FIGS. 3(A) to 3(D).

[0316] As shown in Fig. 9(D), depending on the conditions for forming the insulating layer 110s, a sidewall insulating layer 110w may be formed on the side surface of the conductive layer 112b outside the opening 143. Fig. 9(D) corresponds to the region 163 surrounded by a dashed line in Fig. 9(C). Such a sidewall insulating layer 110w may be formed not only on the side surface of the conductive layer 112b, but also in portions having irregularities on the surface on which the insulating film 110s_f is to be formed.

[0317] Next, a semiconductor film that becomes the semiconductor layer 108 is formed in contact with the upper surface of the conductive layer 112a in the opening 143, the side surface of the insulating layer 110s in the opening 143, the curved portion of the insulating layer 110s, and the upper surface of the conductive layer 112b. Then, a part of the semiconductor film is removed by etching to form the semiconductor layer 108 (FIG. 10(A)). The semiconductor layer 108 is provided so as to have a region that overlaps with the opening 143. In addition, the semiconductor layer 108 is provided so as to have a region where an end portion thereof contacts the conductive layer 112b.

[0318] For the semiconductor film that becomes the semiconductor layer 108, the above-described materials that can be used for the semiconductor layer 108 can be used as appropriate.

[0319] A sputtering method, for example, can be used to form a semiconductor film that becomes the semiconductor layer 108. For example, when a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by a sputtering method using a metal oxide target. The sputtering method is preferable because a film with a low hydrogen content can be formed relatively easily.

[0320] When a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0321] For example, when forming an In-Ga-Zn oxide, three precursors, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, a precursor containing indium, and a precursor containing gallium and zinc, can be used.

[0322] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0323] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0324] Furthermore, as a precursor containing zinc, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0325] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0326] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions continuously.

[0327] By using an ALD method for forming a semiconductor film to be the semiconductor layer 108, the semiconductor layer 108 can be formed with a uniform thickness on the side surface of the insulating layer 110s, which is preferable.

[0328] Heat treatment may be performed after the semiconductor film to be the semiconductor layer 108 is formed. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen to the semiconductor film from the insulating layer 110, the insulating layer 110s, or the like. Note that the heat treatment may be performed after the semiconductor film is processed.

[0329] The substrate temperature during the formation of the semiconductor layer 108 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By keeping the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0330] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed. Also, the higher the oxygen flow rate ratio, the higher the crystallinity of the metal oxide layer that can be formed.

[0331] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110c (FIG. 10(B)). The insulating layer 106 has a region in contact with the upper surface and side surfaces of the semiconductor layer 108, the upper surface of the conductive layer 112b, and the upper surface of the insulating layer 110c.

[0332] For the insulating layer 106, the above-mentioned materials can be used as appropriate.

[0333] The insulating layer 106 can be formed by, for example, the ALD method. The ALD method is preferable because it allows the insulating layer 106 to be formed with good coverage over the semiconductor layer 108 formed to cover the opening 143. Note that, if the semiconductor layer 108 can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer 106. For example, a PECVD method, a sputtering method, or the like can be used. This allows the insulating layer 106 to be formed at a higher rate than when the ALD method is used, thereby improving productivity.

[0334] Next, a conductive film to be the conductive layer 104 is formed on the insulating layer 106. The conductive film can be formed using any of the materials that can be used for the conductive layer 104 described above. The conductive film can be formed using any of a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the conductive film is preferably formed in contact with the insulating layer 106 that faces the side surface of the insulating layer 110s in the opening 143. Therefore, the conductive film is preferably formed using a method that has good coverage or embedding properties, and more preferably using a CVD method, an ALD method, or the like.

[0335] Next, the conductive film to be the conductive layer 104 is processed to form the conductive layer 104 (FIG. 10C). The conductive layer 104 is formed to have a region overlapping with the semiconductor layer 108 and the insulating layer 110s in a plan view. The conductive layer 104 may be formed by a photolithography method. A dry etching method or a wet etching method can be used for the above processing. Processing by a dry etching method is suitable for fine processing.

[0336] Subsequently, an insulating layer 195 is formed to cover the conductive layer 104 and the insulating layer 106 (FIG. 1(B)).

[0337] The insulating layer 195 can be formed, for example, using the same material and method as the insulating layers 110a and 110c.

[0338] Through the above steps, a semiconductor device including the transistor 100 can be manufactured.

[0339] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0340] (Embodiment 2) In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0341] The display device of the present embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of the present embodiment can be used for electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0342] The display device of the present embodiment can be a high-definition display device. Therefore, the display device of the present embodiment can be used, for example, as a display unit of a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit of a wearable device that can be worn on the head, such as a VR device such as a head mounted display (HMD) and an AR device such as a glasses-type device.

[0343] The semiconductor device of one embodiment of the present invention can be used for a display device or a module having the display device. Examples of the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip on glass (COG) method, a chip on film (COF) method, or the like.

[0344] [Display device 50A] FIG. 11 shows a perspective view of a display device 50A.

[0345] Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Fig. 11, substrate 152 is indicated by a dashed line.

[0346] The display device 50A has a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Fig. 11 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 11 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0347] The connection unit 140 is provided on the outside of the display unit 168. The connection unit 140 can be provided along one side or multiple sides of the display unit 168. The connection unit 140 may be single or multiple. FIG. 11 shows an example in which the connection unit 140 is provided so as to surround the four sides of the display unit. The connection unit 140 connects a common electrode of the display element and a conductive layer, and can supply a potential to the common electrode.

[0348] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0349] The wiring 165 has a function of supplying signals and power to the display portion 168 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside via the FPC 172, or are input to the wiring 165 from the IC 173.

[0350] 11 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driving circuit and a signal line driving circuit can be used as the IC 173. Note that the display device 50A and the display module may be configured not to include an IC. Also, the IC may be mounted on an FPC by a COF method, or the like.

[0351] A transistor of one embodiment of the present invention can be used in, for example, one or both of the display portion 168 and the circuit portion 164 of the display device 50A.

[0352] For example, when the transistor of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. For example, when the transistor of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the transistor of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using the transistor in the display device.

[0353] The display section 168 is a region in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. An enlarged view of one pixel 210 is shown in FIG.

[0354] The pixel arrangement in the display device of the present embodiment is not particularly limited, and various methods can be applied. Examples of the pixel arrangement include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.

[0355] A pixel 210 shown in FIG. 11 has a sub-pixel 11R that provides red light, a sub-pixel 11G that provides green light, and a sub-pixel 11B that provides blue light.

[0356] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0357] As the display element, various elements can be used, for example, liquid crystal elements and light emitting elements. In addition, a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element, a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used. In addition, a QLED (Quantum-dot LED) using a light source and a color conversion technology using a quantum dot material may be used.

[0358] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0359] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LEDs that can be used include mini LEDs and micro LEDs.

[0360] Examples of light-emitting substances that the light-emitting element has include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0361] The light emitting element may emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light emitting element with a microcavity structure.

[0362] Of a pair of electrodes included in the light-emitting element, one electrode functions as an anode and the other electrode functions as a cathode.

[0363] In this embodiment mode, a case where a light-emitting element is used as a display element will be mainly described as an example.

[0364] Note that the display device of one embodiment of the present invention may be any of a top emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom emission type that emits light toward the substrate on which a light-emitting element is formed, and a dual emission type that emits light to both sides.

[0365] FIG. 12 shows an example of a cross section of the display device 50A, where a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0366] 12 includes transistors 205D, 205R, 205G, and 205B, as well as light-emitting elements 130R, 130G, and 130B, between substrates 151 and 152. The light-emitting element 130R is a display element included in subpixel 11R that emits red light, the light-emitting element 130G is a display element included in subpixel 11G that emits green light, and the light-emitting element 130B is a display element included in subpixel 11B that emits blue light.

[0367] The display device 50A has an SBS structure. The SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.

[0368] The display device 50A is a top emission type, which allows transistors and the like to be arranged so as to overlap the light emitting region of the light emitting element, thereby enabling the aperture ratio of the pixel to be increased compared to the bottom emission type.

[0369] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured using the same material and through the same process.

[0370] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors of one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistors of one embodiment of the present invention in both the display portion 168 and the circuit portion 164. By using the transistors of one embodiment of the present invention in the display portion 168, the pixel size can be reduced, and high definition can be achieved. Furthermore, by using the transistors of one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, and a narrower frame can be achieved. For the transistors of one embodiment of the present invention, the description of the above embodiment can be referred to.

[0371] Specifically, transistor 205D, transistor 205R, transistor 205G, and transistor 205B each have a conductive layer 104 functioning as one of a first gate electrode and a second gate electrode, a conductive layer 114 functioning as the other of the first gate electrode and the second gate electrode, an insulating layer 106 functioning as a gate insulating layer, an insulating layer 110s functioning as a gate insulating layer, a conductive layer 112a functioning as one of a source electrode or a drain electrode, a conductive layer 112b functioning as the other of the source electrode or the drain electrode, and a semiconductor layer 108 having a metal oxide.

[0372] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0373] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0374] The display device of this embodiment may also include a transistor using silicon for a channel formation region (Si transistor).

[0375] Examples of silicon include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor having an LTPS semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and good frequency characteristics.

[0376] In order to increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a drive transistor included in the pixel circuit. Since an OS transistor has a higher source-drain withstand voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the drive transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0377] Furthermore, when the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current with respect to the change in gate-source voltage compared to the Si transistor. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting element can be controlled. This allows the pixel circuit to have a larger number of gray scales.

[0378] In addition, in terms of the saturation characteristics of the current that flows when the transistor operates in the saturation region, the OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a drive transistor, a stable current can be passed to the light-emitting element, for example, even when the current-voltage characteristics of the light-emitting element vary. In other words, when the OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, so that the light emission luminance of the light-emitting element can be stabilized.

[0379] The transistors included in the circuit portion 164 and the transistors included in the display portion 168 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 168 may all have the same structure or may have two or more types.

[0380] All the transistors in the display portion 168 may be OS transistors, all the transistors in the display portion 168 may be Si transistors, or some of the transistors in the display portion 168 may be OS transistors and the rest may be Si transistors.

[0381] For example, by using both an LTPS transistor and an OS transistor in the display unit 168, a display device with low power consumption and high driving capability can be realized. A configuration in which an LTPS transistor and an OS transistor are combined may be referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0382] For example, one of the transistors in the display unit 168 functions as a transistor for controlling a current flowing to a light-emitting element and can be called a driving transistor. One of the source and the drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0383] On the other hand, the other one of the transistors in the display unit 168 functions as a switch for controlling the selection and non-selection of a pixel, and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of a pixel even if the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0384] An insulating layer 195 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B, and an insulating layer 235 is provided over the insulating layer 195.

[0385] The insulating layer 195 preferably functions as a protective layer for the transistor. The insulating layer 195 is preferably made of a material through which impurities such as water and hydrogen are unlikely to diffuse. This allows the insulating layer 195 to function as a barrier layer. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0386] The insulating layer 195 preferably has one or more inorganic insulating films. Examples of the inorganic insulating film include an insulating oxide film, an insulating nitride film, an insulating oxynitride film, and an insulating nitride oxide film. Specific examples of these inorganic insulating films are as described above.

[0387] The insulating layer 235 preferably functions as a planarizing layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This can prevent a recess from being formed in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, and the like. Alternatively, a recess may be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, and the like.

[0388] On the insulating layer 235, the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B are provided.

[0389] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Fig. 12 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0390] The light emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light emitting element 130G shown in Fig. 12 emits green light (G). The EL layer 113G has a light emitting layer that emits green light.

[0391] The light emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light emitting element 130B shown in Fig. 12 emits blue light (B). The EL layer 113B has a light emitting layer that emits blue light.

[0392] In addition, in Fig. 12, the EL layer 113R, the EL layer 113G, and the EL layer 113B are all shown to have the same film thickness, but this is not limited thereto. The film thicknesses of the EL layer 113R, the EL layer 113G, and the EL layer 113B may be different from each other. For example, it is preferable to set the film thicknesses of the EL layer 113R, the EL layer 113G, and the EL layer 113B to a thickness corresponding to the optical path length that strengthens the light emitted by each of them. This realizes a microcavity structure and can increase the color purity of the light emitted from each light-emitting element.

[0393] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0394] Each end of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B is covered with an insulating layer 237. The insulating layer 237 functions as a partition (also referred to as a bank, a spacer). The insulating layer 237 can be provided in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 195 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can insulate the pixel electrode and the common electrode. In addition, the insulating layer 237 can insulate adjacent light-emitting elements from each other.

[0395] The common electrode 135 is a continuous film provided in common to the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B. The common electrode 135 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed of the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0396] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is used for the electrode from which light is extracted, out of a pixel electrode and a common electrode, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0397] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to dispose the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0398] As a material for forming a pair of electrodes of a light-emitting element, a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like can be appropriately used. Specific examples of the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combination. Examples of the material include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) not listed above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0399] It is preferable that a micro-optical resonator (microcavity) structure is applied to the light-emitting element. Therefore, it is preferable that one of a pair of electrodes of the light-emitting element is an electrode having transparency and reflectivity to visible light (semi-transmissive / semi-reflective electrode), and the other is an electrode having reflectivity to visible light (reflective electrode). When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer is resonated between both electrodes, and the light emitted from the light-emitting element can be intensified.

[0400] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light having a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10-2 Ωcm or less.

[0401] The EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape. In FIG. 12, the end of the adjacent EL layer 113R overlaps with the end of the EL layer 113G, the end of the adjacent EL layer 113G overlaps with the end of the EL layer 113B, and the end of the adjacent EL layer 113R overlaps with the end of the EL layer 113B. When forming an island-shaped EL layer using a fine metal mask, the ends of the adjacent EL layers may overlap as shown in FIG. 12, but this is not limited to this. That is, the adjacent EL layers may not overlap with each other and may be separated from each other. In addition, in the display device, there may be both a portion where the adjacent EL layers overlap with each other and a portion where the adjacent EL layers do not overlap with each other and are separated from each other.

[0402] Each of the EL layer 113R, the EL layer 113G, and the EL layer 113B has at least a light-emitting layer. The light-emitting layer has one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. In addition, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0403] The light-emitting material may include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0404] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used. As the one or more organic compounds, a bipolar substance (a substance with high electron transport properties and hole transport properties) or a TADF material may be used.

[0405] The light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. With this configuration, light emission can be efficiently obtained using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from an exciplex to a light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest energy absorption band of the light-emitting material, energy transfer becomes smooth and light emission can be efficiently obtained. With this configuration, high efficiency, low voltage operation, and long life of the light-emitting element can be simultaneously achieved.

[0406] In addition to the light-emitting layer, the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a material with hole transport properties (hole transport layer), a layer containing a substance with high electron blocking properties (electron block layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing a material with electron transport properties (electron transport layer), and a layer containing a substance with high hole blocking properties (hole block layer). In addition, the EL layer may contain one or both of a bipolar material and a TADF material.

[0407] The light-emitting element may be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound. Each of the layers constituting the light-emitting element may be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an ink-jet method, a coating method, or the like.

[0408] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. The charge-generating layer has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. The tandem structure makes it possible to obtain a light-emitting element capable of emitting high-luminance light. Furthermore, the tandem structure can reduce the current required to obtain the same luminance as the single structure, thereby improving reliability. The tandem structure may also be called a stack structure.

[0409] In FIG. 12, when light-emitting elements having a tandem structure are used, it is preferable that EL layer 113R has a structure having a plurality of light-emitting units that emit red light, EL layer 113G has a structure having a plurality of light-emitting units that emit green light, and EL layer 113B has a structure having a plurality of light-emitting units that emit blue light.

[0410] A protective layer 131 is provided on the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 149. The substrate 152 is provided with a light shielding layer 117. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light emitting element. In FIG. 12, the space between the substrate 152 and the substrate 151 is filled with an adhesive layer 149, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 149 may be provided so as not to overlap with the light emitting element. The space may also be filled with a resin different from the adhesive layer 149 provided in a frame shape.

[0411] The protective layer 131 is provided at least on the display unit 168, and is preferably provided so as to cover the entire display unit 168. The protective layer 131 is preferably provided so as to cover not only the display unit 168, but also the connection unit 140 and the circuit unit 164. The protective layer 131 is preferably provided up to the end of the display device 50A. Meanwhile, in the connection unit 204, there is a portion where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 167.

[0412] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0413] The protective layer 131 may have a single-layer structure or a stacked structure of two or more layers. There is no restriction on the conductivity of the protective layer 131. The protective layer 131 can be made of at least one of an insulating film, a semiconductor film, and a conductive film.

[0414] The protective layer 131 having an inorganic film can prevent oxidation of the common electrode 135, and inhibit impurities (e.g., water, oxygen, etc.) that induce deterioration of the light-emitting element from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0415] For the protective layer 131, for example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably has a nitride insulating film or a nitride oxide insulating film, and more preferably has a nitride insulating film.

[0416] Also, an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like can be used for the protective layer 131. The inorganic film preferably has a high resistance, specifically, a higher resistance than the common electrode 135. The inorganic film may further contain nitrogen.

[0417] When light emitted from the light emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials each having high transparency to visible light.

[0418] For example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a laminated structure, it is possible to prevent impurities (e.g., water, oxygen, etc.) that may cause deterioration of the light-emitting element from penetrating into the EL layer side.

[0419] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of the organic film that can be used for the protective layer 131 include an organic insulating film that can be used for the insulating layer 235.

[0420] A connection portion 204 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, the wiring 165 is connected to the FPC 172 via a conductive layer 166, a conductive layer 167, and a connection layer 242. The wiring 165 is an example of a conductive layer having a single layer structure obtained by processing the same conductive film as the conductive layer 112a. The conductive layer 166 is an example of a conductive layer having a single layer structure obtained by processing the same conductive film as the conductive layer 112b. The conductive layer 167 is an example of a conductive layer having a single layer structure obtained by processing the same conductive film as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. On the upper surface of the connection portion 204, the conductive layer 167 is exposed. This allows the connection portion 204 and the FPC 172 to be connected via the connection layer 242.

[0421] The display device 50A is a top emission type. Light emitted by the light emitting elements is emitted to the substrate 152 side. It is preferable to use a material having high transparency to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B include a material that reflects visible light, and the counter electrode (common electrode 135) includes a material that transmits visible light.

[0422] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, the circuit section 164, and the like.

[0423] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be improved.

[0424] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film. On the outside of the substrate 152, a surface protection layer such as an antistatic film that suppresses adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, and an impact absorbing layer may be arranged. For example, by providing a glass layer or a silica layer (SiOx layer) as the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable. Also, DLC (diamond-like carbon), aluminum oxide (AlOx), polyester-based materials, polycarbonate-based materials, etc. may be used as the surface protection layer. Note that it is preferable to use a material with high transmittance for visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0425] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased and a flexible display can be realized. A polarizing plate may be used for at least one of the substrates 151 and 152.

[0426] The substrates 151 and 152 may each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of the substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.

[0427] In addition, when a circularly polarizing plate is laminated on a display device, it is preferable to use a substrate with high optical isotropy as the substrate of the display device. A substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, acrylic film, etc.

[0428] For the adhesive layer 149, various types of curing adhesives can be used, such as a photo-curing adhesive such as an ultraviolet curing adhesive, a reaction curing adhesive, a heat curing adhesive, and an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. A two-liquid mixed resin may also be used. An adhesive sheet or the like may also be used.

[0429] The connection layer 242 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0430] [Display device 50B] 13 is different from display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each color subpixel. In the following description of the display device, the description of the same parts as those of the display device described above may be omitted.

[0431] The display device 50B shown in FIG. 13 has, between the substrate 151 and the substrate 152, a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0432] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0433] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0434] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0435] The light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B each have in common an EL layer 113 and a common electrode 135. The configuration in which the sub-pixels of each color are provided with a common EL layer 113 can reduce the number of manufacturing steps compared to the configuration in which the sub-pixels of each color are provided with different EL layers.

[0436] For example, the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B shown in Fig. 13 each emit white light. The white light emitted by the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B passes through the colored layer 132R, the colored layer 132G, and the colored layer 132B, respectively, to obtain light of a desired color.

[0437] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers may be selected such that the emission colors of the two light-emitting layers are in a complementary color relationship. For example, a configuration in which the light-emitting element as a whole emits white light may be obtained by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer in a complementary color relationship. In addition, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to obtain a configuration in which the light-emitting element as a whole emits white light.

[0438] The EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a wavelength longer than that of blue. The EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0439] For the light-emitting element that emits white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, red light, and a light-emitting unit that emits blue light in this order, etc. can be applied. For example, examples of the number of layers and the order of colors of the light-emitting units include, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and a three-layer structure of B, X, and B. Examples of the number of layers and the order of colors of the light-emitting layers in light-emitting unit X include, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. In addition, another layer may be provided between the two light-emitting layers.

[0440] Alternatively, for example, the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B shown in FIG. 13 emit blue light. In this case, the EL layer 113 has one or more light emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light emitting element 130B can be extracted. In the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer is provided between the light emitting element 130R or the light emitting element 130G and the substrate 152, so that the blue light emitted by the light emitting element 130R or the light emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light emitting element 130G. A part of the light emitted by the light emitting element may be transmitted as it is without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0441] [Display device 50C] A display device 50C shown in FIG. 14 differs from the display device 50B mainly in that the display device 50C is a bottom-emission type display device.

[0442] Light emitted from the light emitting element is emitted to the substrate 151 side. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the material used for the substrate 152 may or may not have light transmitting properties.

[0443] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. Fig. 14 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, the colored layer 132R (not shown), the colored layer 132G, and the colored layer 132B are provided on the insulating layer 195, and the insulating layer 235 is provided on the colored layer 132R (not shown), the colored layer 132G, and the colored layer 132B.

[0444] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 135.

[0445] The light emitting element 130B overlapping with the colored layer 132B includes a pixel electrode 111B, an EL layer 113, and a common electrode 135.

[0446] The pixel electrodes 111G and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 135. In a bottom emission type display device, a low resistance metal or the like can be used for the common electrode 135, so that it is possible to suppress the occurrence of a voltage drop due to the resistance of the common electrode 135, and to realize high display quality.

[0447] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the size of the pixel can be reduced.

[0448] [Display device 50D] A display device 50D shown in FIG. 15 differs from the display device 50A mainly in that a light receiving element 130S is included.

[0449] The display device 50D has a light emitting element and a light receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light emitting element and an organic photodiode as the light receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be built into the display device using the organic EL element.

[0450] In the display device 50D having a light emitting element and a light receiving element in each pixel, the pixels have a light receiving function, and therefore it is possible to detect the contact or proximity of an object while displaying an image. Therefore, the display unit 168 has one or both of an imaging function and a sensing function in addition to an image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50D, some of the sub-pixels can emit light as a light source, some of the sub-pixels can detect light, and the remaining sub-pixels can display an image.

[0451] Therefore, it is not necessary to provide a light receiving unit and a light source separately from the display device 50D, and the number of parts of the electronic device can be reduced. For example, it is not necessary to separately provide a biometric authentication device or a capacitive touch panel for scrolling, etc., which are provided in the electronic device. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0452] When the light receiving element is used as an image sensor, the display device 50D can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.

[0453] The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the display device and the object are in direct contact with each other. A non-contact sensor can detect an object even if the object does not touch the display device.

[0454] The light receiving element 130S has a pixel electrode 111S on the insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 135 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0455] The pixel electrode 111S is connected to a conductive layer 112b included in the transistor 205S through an opening provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.

[0456] The end of the pixel electrode 111S is covered with an insulating layer 237.

[0457] The common electrode 135 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 135 shared by the light emitting element and the light receiving element is connected to the conductive layer 123 provided in the connection portion 140.

[0458] The functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors including organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor of the active layer is shown. By using an organic semiconductor, the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), and a common manufacturing device can be used, which is preferable.

[0459] The functional layer 113S may further include a layer containing a substance having a high hole transporting property, a substance having a high electron transporting property, or a bipolar substance (a substance having high electron transporting property and hole transporting property) as a layer other than the active layer. In addition, without being limited to the above, the functional layer 113S may further include a layer containing a substance having a high hole injection property, a hole blocking material, a substance having a high electron injection property, or an electron blocking material. For example, the materials that can be used in the above-mentioned light-emitting element can be used for the layers other than the active layer of the light-receiving element.

[0460] The light receiving element may be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound. The layers constituting the light receiving element may be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

[0461] [Display device 50E] The display device 50E shown in Fig. 16 is an example of a display device to which the MML (metal maskless) structure is applied. That is, the display device 50E has a light-emitting element manufactured without using a fine metal mask. Note that the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore the description thereof will be omitted.

[0462] In FIG. 16, on an insulating layer 235, a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B are provided.

[0463] The light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 134 on the layer 133R, and a common electrode 135 on the common layer 134. The light-emitting element 130R shown in FIG. 16 emits red light (R). The layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 134 can be collectively referred to as an EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0464] The light-emitting element 130G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 134 on the layer 133G, and a common electrode 135 on the common layer 134. The light-emitting element 130G shown in FIG. 16 emits green light (G). The layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 134 can be collectively referred to as an EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0465] The light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 134 on the layer 133B, and a common electrode 135 on the common layer 134. The light-emitting element 130B shown in FIG. 16 emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 134 can be collectively referred to as an EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0466] In this specification and the like, among the EL layers included in the light-emitting elements, layers provided in an island shape for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 134. Note that in this specification and the like, the layer 133R, layer 133G, and layer 133B may be referred to as an island-shaped EL layer, an EL layer formed in an island shape, or the like, without including the common layer 134.

[0467] The layers 133R, 133G, and 133B are spaced apart from each other. By providing the EL layer in an island shape for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.

[0468] 16, the layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limited thereto.The layers 133R, 133G, and 133B may each have a different thickness.

[0469] The conductive layer 124R is connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 112b of the transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of the transistor 205B.

[0470] Conductive layer 124R, conductive layer 124G, and conductive layer 124B are formed so as to cover openings provided in insulating layer 235. Layer 128 is embedded in the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively.

[0471] The layer 128 has a function of planarizing the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B. The conductive layer 126R, the conductive layer 126G, and the conductive layer 126B connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B are provided on the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, respectively. Therefore, the regions overlapping with the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layer 124R and the conductive layer 126R.

[0472] The layer 128 may be an insulating layer or a conductive layer. For the layer 128, various inorganic insulating materials, organic insulating materials, and conductive materials can be appropriately used. In particular, the layer 128 is preferably formed using an insulating material, and more preferably formed using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 described above can be applied to the layer 128.

[0473] 16 shows an example in which the upper surface of layer 128 has a flat portion, but there is no particular limitation on the shape of layer 128. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0474] Furthermore, the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.

[0475] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R. The end of each of the conductive layers 124R and 126R is preferably tapered. Specifically, the end of each of the conductive layers 124R and 126R is preferably tapered with a taper angle of less than 90 degrees. When the end of the pixel electrode is tapered, the layer 133R provided along the side of the pixel electrode has an inclined portion. By making the side of the pixel electrode tapered, the coverage of the EL layer provided along the side of the pixel electrode can be improved.

[0476] The conductive layers 124G, 126G, 124B, and 126B are similar to the conductive layers 124R and 126R, and therefore will not be described in detail.

[0477] The upper surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the upper surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the upper surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, thereby increasing the aperture ratio of the pixel.

[0478] A portion of the upper surface and the side surfaces of each of the layers 133R, 133G, and 133B are covered with the insulating layer 125 and the insulating layer 127. A common layer 134 is provided on the layers 133R, 133G, and 133B, and the insulating layer 125 and the insulating layer 127, and a common electrode 135 is provided on the common layer 134. The common layer 134 and the common electrode 135 are each a continuous film provided in common to a plurality of light-emitting elements.

[0479] In FIG. 16, the insulating layer 237 shown in FIG. 12 and the like is not provided between the conductive layer 126R and the layer 133R. That is, the display device 50E does not have an insulating layer (also called a partition wall, a bank, a spacer, etc.) that contacts the pixel electrode and covers the upper surface end of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0480] As described above, the layer 133R, the layer 133G, and the layer 133B each have a light-emitting layer. The layer 133R, the layer 133G, and the layer 133B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, the layer 133R, the layer 133G, and the layer 133B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, the layer 133R, the layer 133G, and the layer 133B each preferably have a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layer 133R, the layer 133G, and the layer 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.

[0481] The common layer 134 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 134 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together. The common layer 134 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0482] The respective side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the respective side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0483] By covering the side surfaces (and even parts of the upper surfaces) of the layers 133R, 133G, and 133B with at least one of the insulating layers 125 and 127, the common layer 134 (or the common electrode 135) is prevented from contacting the pixel electrodes and the side surfaces of the layers 133R, 133G, and 133B, and short-circuiting of the light-emitting elements can be prevented, thereby improving the reliability of the light-emitting elements.

[0484] The insulating layer 125 is preferably in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. When the insulating layer 125 is in contact with the layer 133R, the layer 133G, and the layer 133B, peeling of the layer 133R, the layer 133G, and the layer 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0485] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a part of the side surface of the insulating layer 125.

[0486] By providing the insulating layers 125 and 127, the gap between the adjacent island-shaped layers can be filled, and therefore the large unevenness of the surface on which the layer (e.g., the carrier injection layer, the common electrode, etc.) is formed on the island-shaped layers can be reduced and made flatter. Therefore, the coverage of the carrier injection layer, the common electrode, etc. can be improved.

[0487] The common layer 134 and the common electrode 135 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region (a region between light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided. In the display device of one embodiment of the present invention, the step can be flattened by including the insulating layer 125 and the insulating layer 127, and the coverage of the common layer 134 and the common electrode 135 can be improved. Therefore, a connection failure due to a step disconnection of the common layer 134 or the common electrode 135 can be suppressed. In addition, an increase in electrical resistance due to a local thinning of the common electrode 135 caused by the step can be suppressed.

[0488] The upper surface of insulating layer 127 preferably has a shape with high flatness. The upper surface of insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of insulating layer 127 preferably has a smooth convex curved surface shape with high flatness.

[0489] The insulating layer 125 can be an insulating layer containing an inorganic material. For the insulating layer 125, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may have a single layer structure or a laminated structure. In particular, aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 127 described later. In particular, by applying an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method to the insulating layer 125, it is possible to form the insulating layer 125 with few pinholes and excellent function of protecting the EL layer. The insulating layer 125 may also have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. The insulating layer 125 may have a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0490] The insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.

[0491] In this specification and the like, a barrier insulating layer refers to an insulating layer having a barrier property. In addition, in this specification and the like, the barrier property refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing or fixing (also referred to as gettering) a corresponding substance.

[0492] The insulating layer 125 has a function as a barrier insulating layer or a gettering function, and thus can suppress the intrusion of impurities (substances that can induce deterioration of the light-emitting element, typically at least one of water and oxygen) that can diffuse from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and further a highly reliable display device can be provided.

[0493] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. By lowering the impurity concentration in the insulating layer 125, the barrier property against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0494] The insulating layer 127 provided on the insulating layer 125 has a function of flattening the large unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 135 is formed.

[0495] An insulating layer containing an organic material can be suitably used as the insulating layer 127. As the organic material, it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin. In this specification and the like, the acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to the whole acrylic polymer in a broad sense.

[0496] Also, the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, or the like. Also, the insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Also, a photoresist may be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0497] The insulating layer 127 may be made of a material that absorbs visible light. When the insulating layer 127 absorbs light emitted from the light-emitting element, leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light) can be suppressed. This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0498] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide, etc.), and resin materials that can be used for color filters (color filter materials). In particular, it is preferable to use a resin material in which two or more colors of color filter materials are laminated or mixed, since this can enhance the visible light shielding effect. In particular, by mixing three or more colors of color filter materials, it is possible to make a resin layer that is black or close to black.

[0499] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the size of the pixel can be reduced.

[0500] This embodiment mode can be combined with other embodiment modes as appropriate.

[0501] (Embodiment 3) In this embodiment, a structural example of a display device to which a semiconductor device of one embodiment of the present invention can be applied will be described.

[0502] Since the semiconductor device of one embodiment of the present invention can be extremely fine, a display device to which the semiconductor device of one embodiment of the present invention is applied can be a display device with extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), and in a display portion of a head-mounted display (HMD) device such as a VR device or a glasses-type AR device.

[0503] [Display module] 17A shows a perspective view of a display module 280. The display module 280 includes a display device 200A and an FPC 290. Note that the display panel included in the display module 280 is not limited to the display device 200A, and may be a display device 200B or a display device 200C described later.

[0504] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0505] 17(B) shows a perspective view that typically illustrates the configuration on the substrate 291 side. On the substrate 291, a circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are laminated. In addition, a terminal portion 285 for connecting to an FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are connected by a wiring portion 286 that is composed of a plurality of wirings.

[0506] The pixel section 284 has a plurality of pixels 284a arranged periodically. An enlarged view of one pixel 284a is shown on the right side of Fig. 17(B). The pixel 284a has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0507] The pixel circuit section 283 has a plurality of pixel circuits 283a arranged periodically. One pixel circuit 283a is a circuit that controls the light emission of three light emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light emitting device. For example, the pixel circuit 283a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitance element for each light emitting device. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0508] The circuit portion 282 has a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it is preferable to have one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be constituted by a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0509] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, etc. from the outside to the circuit section 282. In addition, an IC may be mounted on the FPC 290.

[0510] The display module 280 can be configured such that one or both of the pixel circuit section 283 and the circuit section 282 are provided in an overlapping manner under the pixel section 284, so that the aperture ratio (effective display area ratio) of the display section 281 can be extremely high. For example, the aperture ratio of the display section 281 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. In addition, the pixels 284a can be arranged at an extremely high density, so that the resolution of the display section 281 can be extremely high. For example, it is preferable that the pixels 284a are arranged in the display section 281 with a resolution of 2000 ppi or more and 30000 ppi or less, preferably 3000 ppi or more and 20000 ppi or less, more preferably 5000 ppi or more and 20000 ppi or less, and even more preferably 6000 ppi or more and 20000 ppi or less.

[0511] Such a display module 280 is extremely high-definition and can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through a lens, the display module 280 has an extremely high-definition display unit 281, so that even if the display unit is enlarged with a lens, pixels are not visible, and a highly immersive display can be performed. In addition, the display module 280 is not limited to this, and can be suitably used in electronic devices having a relatively small display unit. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0512] [Display device 200A] 18 includes a substrate 331, a light emitting element 130R, a light emitting element 130G, a light emitting element 130B, a capacitor 240, and a transistor 320. The light emitting element 130R is a display element included in the subpixel 11R that emits red light, the light emitting element 130G is a display element included in the subpixel 11G that emits green light, and the light emitting element 130B is a display element included in the subpixel 11B that emits blue light.

[0513] The substrate 331 corresponds to the substrate 291 in FIG.

[0514] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Any of the transistors described in Embodiment 1 can be used as the transistor 320.

[0515] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 108 to the insulating layer 332 side. As the insulating layer 332, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0516] A conductive layer 112a is provided on the insulating layer 332. An insulating layer 110a, a conductive layer 114 on the insulating layer 110a, an insulating layer 110b on the conductive layer 114, and a conductive layer 112b on the insulating layer 110b are provided on the conductive layer 112a. Openings are provided in the insulating layer 110a, the conductive layer 114, the insulating layer 110b, and the conductive layer 112b, and an insulating layer 110s is provided along the sidewall of each opening. A semiconductor layer 108 is provided so as to cover the top surface of the conductive layer 112a, the sidewall of the insulating layer 110s, and the top surface of the conductive layer 112b, an insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. An insulating layer 195 is provided on the insulating layer 106 and the conductive layer 104. An insulating layer 196 is provided on the insulating layer 195. The upper surface of the insulating layer 196 is planarized, and an insulating layer 266 is provided on the insulating layer 196 .

[0517] The insulating layer 196 and the insulating layer 266 function as interlayer insulating layers. A barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor, from diffusing from the insulating layer 266 or the like to the transistor 320 may be provided between the insulating layer 266 and the insulating layer 196. An insulating film similar to the insulating layer 332 can be used as the barrier layer.

[0518] The plug 274 connected to the conductive layer 112b is provided so as to be embedded in the insulating layer 266, the insulating layer 196, the insulating layer 195, and the insulating layer 106. Here, the plug 274 preferably has a conductive layer 274a covering side surfaces of the openings of the insulating layer 266, the insulating layer 196, the insulating layer 195, and the insulating layer 106 and a part of the upper surface of the conductive layer 112b, and a conductive layer 274b in contact with the upper surface of the conductive layer 274a. In this case, it is preferable to use a conductive material through which hydrogen and oxygen are unlikely to diffuse as the conductive layer 274a.

[0519] Furthermore, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0520] The conductive layer 241 is provided over the insulating layer 266 and is embedded in the insulating layer 254. The conductive layer 241 is connected to the conductive layer 112b of the transistor 320 by a plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0521] An insulating layer 255a is provided covering the capacitor 240, an insulating layer 255b is provided on the insulating layer 255a, and an insulating layer 255c is provided on the insulating layer 255b.

[0522] For the insulating layer 255a, the insulating layer 255b, and the insulating layer 255c, an inorganic insulating film can be suitably used. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which a part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0523] The light emitting elements 130R, 130G, and 130B are provided on the insulating layer 255c. For details of the light emitting elements 130R, 130G, and 130B, the above-described embodiments can be referred to.

[0524] The light-emitting element 130R has a pixel electrode 111R, a layer 133R, a common layer 134, and a common electrode 135. The light-emitting element 130G has a pixel electrode 111G, a layer 133G, a common layer 134, and a common electrode 135. The light-emitting element 130B has a pixel electrode 111B, a layer 133B, a common layer 134, and a common electrode 135. The common layer 134 and the common electrode 135 are provided in common to the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0525] The layer 133R of the light emitting element 130R has a light emitting organic compound that emits at least red light. The layer 133G of the light emitting element 130G has a light emitting organic compound that emits at least green light. The layer 133B of the light emitting element 130B has a light emitting organic compound that emits at least blue light. The layer 133R, the layer 133G, and the layer 133B can also be called EL layers, and have at least a layer (light emitting layer) containing a light emitting organic compound.

[0526] In the display device 200A, a different light-emitting device is manufactured for each emitted color, so that the change in chromaticity between low-luminance and high-luminance emission is small. In addition, since the layers 133R, 133G, and 133B are spaced apart from each other, the occurrence of crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. Therefore, a display panel that is high in definition and has high display quality can be realized.

[0527] In the regions between adjacent light emitting elements, an insulating layer 119, an insulating layer 125, and an insulating layer 127 are provided.

[0528] The insulating layer 119 is obtained by leaving a part of an insulating layer (also referred to as a mask layer) provided in contact with the top surfaces of the layers 133R, 133G, and 133B when the layers 133R, 133G, and 133B are processed. In this manner, in the display device of one embodiment of the present invention, a part of a mask layer used to protect the layers 133R, 133G, and 133B during the manufacture of the display device may remain. The insulating layer 119 can be formed using, for example, the same material as that which can be used for the insulating layer 125 described above.

[0529] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B of the light-emitting element are connected to the conductive layer 112b of the transistor 320 by the insulating layer 243, the insulating layer 255a, the insulating layer 255b, and a plug 256 embedded in the insulating layer 255c, the conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0530] A protective layer 131 is provided on the light emitting elements 130R, 130G, and 130B. A substrate 170 is attached to the protective layer 131 with an adhesive layer 171.

[0531] Between two adjacent pixel electrodes 111 (pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B), there is no insulating layer covering the upper surface end of the pixel electrode 111. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. As a result, a high-definition or high-resolution display device can be obtained.

[0532] [Display device 200B] A display device having a configuration partially different from that described above will be described below, but the same configuration as the above will be referred to and the description thereof may be omitted.

[0533] 19 shows an example in which a transistor 320A, which is a planar type transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical channel type transistor, are stacked together. The transistor 320B has a similar configuration to the transistor 320 in the display device 200A.

[0534] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0535] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities, such as water or hydrogen, that may adversely affect the electrical characteristics of the transistor from diffusing from the substrate 331 to the transistor 320A and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. As the insulating layer 352, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0536] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a first gate electrode of the transistor 320A, and a part of the insulating layer 356 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0537] The semiconductor layer 351 is provided over an insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0538] An insulating layer 358 and an insulating layer 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect electrical characteristics of a transistor from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be an insulating film similar to the insulating layer 352.

[0539] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with an upper surface of the semiconductor layer 351 and a conductive layer 354 are embedded in the opening. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0540] The top surface of the conductive layer 354, the top surface of the insulating layer 353, and the top surface of the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities, such as water or hydrogen, that may adversely affect the electrical characteristics of the transistor from diffusing into the transistor 320A. The insulating layer 359 can be an insulating film similar to the insulating layer 352.

[0541] The transistor 320A has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the same signal may be supplied to drive the transistor. Alternatively, the threshold voltage of the transistor may be controlled by supplying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0542] [Display device 200C] A display device 200C shown in FIG. 20 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 320B which is a vertical channel transistor.

[0543] The transistor 310 has a channel formation region in a substrate 301. For example, a semiconductor substrate such as a single crystal silicon substrate can be used as the substrate 301. The transistor 310 has a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with an impurity that functions as a dopant, and functions as a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0544] In addition, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0545] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0546] (Embodiment 4) In this embodiment, a circuit, a layout, and the like that can be applied to a display device of one embodiment of the present invention will be described.

[0547] 21 is a block diagram illustrating the display device 200. The display device 200 has a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0548] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n ​​is an integer of 1 or more).

[0549] 11, and the pixel 230 corresponds to, for example, the subpixel 11R, the subpixel 11G, the subpixel 11B, and the pixel 210 in FIG.

[0550] 17A, and the pixel 230 corresponds to, for example, the subpixel 11R, the subpixel 11G, the subpixel 11B, and the pixel 284a in FIG. 17B.

[0551] 21, the pixel 230 in the first row and nth column is indicated as pixel 230[1,n], the pixel 230 in the mth row and first column is indicated as pixel 230[m,1], and the pixel 230 in the mth row and nth column is indicated as pixel 230[m,n]. Any pixel 230 included in the display unit 435 may be indicated as pixel 230[r,s]. r is an integer between 1 and m, and s is an integer between 1 and n.

[0552] The circuit included in the first driving circuit section 431 functions as, for example, a scanning line driving circuit. The circuit included in the second driving circuit section 432 functions as, for example, a signal line driving circuit. Note that some circuit may be provided at a position facing the first driving circuit section 431 across the display section 435. Note that some circuit may be provided at a position facing the second driving circuit section 432 across the display section 435. Note that the circuits included in the first driving circuit section 431 and the second driving circuit section 432 are collectively referred to as a peripheral driving circuit 433.

[0553] The peripheral driver circuit 433 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. The transistor 100 according to one embodiment of the present invention or the like can be used for the peripheral driver circuit 433. Note that the transistor included in the peripheral driver circuit and the transistor included in the pixel 230 may be formed in the same process.

[0554] The display device 200 also has m wires 436 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the first drive circuit section 431, and n wires 437 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the second drive circuit section 432.

[0555] 21 illustrates an example in which the wiring 436 and the wiring 437 are connected to the pixel 230. However, the wiring 436 and the wiring 437 are just an example, and the wirings connected to the pixel 230 are not limited to the wiring 436 and the wiring 437.

[0556] <Pixel circuit configuration example> 22(A) to 22(D), 23(A) to 23(D), 24(A) and 24(B) show configuration examples of a pixel 230. The pixel 230 has a pixel circuit 51 (a pixel circuit 51A, a pixel circuit 51B, a pixel circuit 51C, a pixel circuit 51D, a pixel circuit 51E, a pixel circuit 51F, a pixel circuit 51G, a pixel circuit 51H, a pixel circuit 51I or a pixel circuit 51J) and a light-emitting element 61.

[0557] The light-emitting element (also called a light-emitting device) described in the present embodiment and the like refers to a self-luminous display element such as an organic electroluminescence element (also called an OLED). Note that the light-emitting element connected to the pixel circuit can be a self-luminous light-emitting element such as an LED, a micro LED, a QLED, or a semiconductor laser.

[0558] A pixel circuit 51A shown in FIG. 22A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.

[0559] One of the source or drain of the transistor 52A is connected to the wiring SL, and the gate of the transistor 52A is connected to the wiring GL. One of the source or drain of the transistor 52A is connected to the gate of the transistor 52B and one terminal of the capacitor 53. One of the source or drain of the transistor 52B is connected to the wiring ANO. The other of the source or drain of the transistor 52B is connected to the other terminal of the capacitor 53 and the anode of the light-emitting element 61. The cathode of the light-emitting element 61 is connected to the wiring VCOM. A region where the other of the source or drain of the transistor 52A, the gate of the transistor 52B, and one terminal of the capacitor 53 are connected functions as a node ND.

[0560] The wiring GL corresponds to the wiring 436, and the wiring SL corresponds to the wiring 437. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting element 61. The transistor 52A has a function of controlling the conductive state or non-conductive state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0561] By turning on the transistor 52A, an image signal is supplied from the wiring SL to the node ND. After that, by turning off the transistor 52A, the image signal is held at the node ND. In order to reliably hold the image signal supplied to the node ND, it is preferable to use a transistor with low off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0562] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting element 61. The capacitor 53 has a function of holding a gate potential of the transistor 52B. The intensity of light emitted by the light-emitting element 61 is controlled in response to an image signal supplied to the gate (node ​​ND) of the transistor 52B.

[0563] In a pixel circuit 51A shown in FIG. 22A, a transistor 52A and a transistor 52B have a backgate. A signal line or a power supply line can be connected to the backgate to apply any potential. The backgate may be connected to a ground potential. The backgate may be connected to a gate. The backgate may be connected to a source or a drain. Note that although an example in which all the transistors have a backgate is shown here, a configuration in which only some of the transistors have a backgate may be used.

[0564] The pixel circuit 51B shown in Fig. 22(B) is a 3Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51B shown in Fig. 22(B) has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Fig. 22(A).

[0565] The other of the source and the drain of the transistor 52C is connected to the other of the source and the drain of the transistor 52B. The other of the source and the drain of the transistor 52C is connected to a wiring V0. For example, a reference potential is supplied to the wiring V0.

[0566] The transistor 52C has a function of controlling the conduction or non-conduction state between the other of the source and the drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL. The wiring V0 is a wiring for applying a reference potential. When an n-channel transistor is used as the transistor 52B, the reference potential of the wiring V0 applied via the transistor 52C can suppress variation in the gate-source voltage of the transistor 52B.

[0567] In addition, a current value that can be used to set pixel parameters can be obtained using the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0568] In a pixel circuit 51B shown in FIG. 22B, the transistor 52A, the transistor 52B, and the transistor 52C have a backgate. A signal line or a power supply line can be connected to the backgate to apply any potential. The backgate may be connected to a ground potential. The backgate may be connected to a gate. The backgate may be connected to a source or a drain. Note that although an example in which all the transistors have a backgate is shown here, a configuration in which only some of the transistors have a backgate may be used.

[0569] A pixel circuit 51C shown in FIG. 22(C) is an example in which a transistor having a back gate and the back gate is connected to the gate is applied to the transistor 52A and the transistor 52B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 22(D) is an example in which the transistor is applied to the pixel circuit 51B. This can increase the current that the transistor can pass. Note that, although transistors having a gate and a back gate connected to each other are applied to all the transistors here, this is not limiting. Also, a transistor having a gate and a back gate and connected to different wirings may be applied. For example, reliability can be improved by using a transistor in which one of the gate or the back gate is connected to the source.

[0570] A pixel circuit 51E shown in Fig. 23A has a configuration in which a transistor 52D is added to the pixel circuit 51B shown in Fig. 22B. The pixel circuit 51E shown in Fig. 23A is a 4Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, and a capacitor 53.

[0571] One of a source and a drain of the transistor 52D is connected to the node ND, and the other is connected to the wiring V0. The transistor 52D has a backgate.

[0572] The pixel circuit 51E is connected to a wiring GL1, a wiring GL2, and a wiring GL3. The wiring GL1 is connected to the gate of the transistor 52A, the wiring GL2 is connected to the gate of the transistor 52C, and the wiring GL3 is connected to the gate of the transistor 52D. Note that in the present embodiment and the like, the wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL. Thus, the number of wirings GL is not limited to one, and may be multiple.

[0573] By simultaneously turning on the transistors 52C and 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through the light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which a display period and an off period are alternately provided.

[0574] The pixel circuit 51F shown in FIG. 23B is an example in which a capacitance 53A is added to the pixel circuit 51E. The capacitance 53A functions as a storage capacitance. The pixel circuit 51E shown in FIG. 23A is a 4Tr1C type pixel circuit. The pixel circuit 51F shown in FIG. 23B is a 4Tr2C type pixel circuit.

[0575] A pixel circuit 51G shown in Figure 23(C) and a pixel circuit 51H shown in Figure 23(D) respectively show a configuration in which, in the pixel circuit 51E or pixel circuit 51F, the back gates of transistor 52A, transistor 52C, and transistor 52D are connected to the gate, and the back gate of transistor 52B is connected to the source.

[0576] 24A is a 6Tr1C pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, a transistor 52E, a transistor 52F, and a capacitor 53. The transistors 52A to 52F each have a back gate.

[0577] One of the source or drain of the transistor 52A is connected to the wiring SL, and the gate of the transistor 52A is connected to the wiring GL1. One of the source or drain of the transistor 52D is connected to the wiring ANO, and the gate of the transistor 52D is connected to the wiring GL2. The other of the source or drain of the transistor 52D is connected to one of the source or drain of the transistor 52B. The other of the source or drain of the transistor 52B is connected to the other of the source or drain of the transistor 52A and one of the source or drain of the transistor 52F. The gate of the transistor 52F is connected to the wiring GL3.

[0578] One of the source or drain of the transistor 52E is connected to the other of the source or drain of the transistor 52D and one of the source or drain of the transistor 52B. The other of the source or drain of the transistor 52E is connected to the gate of the transistor 52B and one terminal of the capacitor 53. The other terminal of the capacitor 53 is connected to the other of the source or drain of the transistor 52F, the anode of the light-emitting element 61, and one of the source or drain of the transistor 52C. The gate of the transistor 52E and the gate of the transistor 52C are connected to a wiring GL4. The other of the source or drain of the transistor 52C is connected to a wiring V0. A region to which the other of the source or drain of the transistor 52E, the gate of the transistor 52B, and one terminal of the capacitor 53 are connected functions as a node ND.

[0579] FIG. 24B shows a configuration in which the backgates of the transistor 52A, the transistor 52C, the transistor 52D, the transistor 52E, and the transistor 52F are connected to the gates, and the backgate of the transistor 52B is connected to the other of the source and the drain.

[0580] By using the transistor 100 or the like according to one embodiment of the present invention in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced. Thus, the resolution of the display device can be improved. For example, a display device having a resolution of 1000 ppi to 10000 ppi, preferably 2000 ppi to 9000 ppi, more preferably 3000 ppi to 8000 ppi, further preferably 4000 ppi to 8000 ppi, further preferably 5000 ppi to 8000 ppi, and further preferably 6000 ppi to 8000 ppi can be realized.

[0581] In addition, by reducing the area occupied by the pixel circuit, the number of pixels of the display device can be increased (resolution can be increased). For example, it is possible to realize a display device with extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0582] Therefore, by using the transistor 100 according to one embodiment of the present invention or the like in a pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission display device using an EL element, the aperture ratio of the pixel can be increased. A pixel with a high aperture ratio can emit light with the same luminance as a pixel with a low aperture ratio, but with a lower current density than a pixel with a low aperture ratio. Thus, the reliability of the display device can be improved.

[0583] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes.

[0584] (Embodiment 5) In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0585] The electronic devices of this embodiment include the display device of one embodiment of the present invention in a display portion. The display device of one embodiment of the present invention can easily have high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portion of various electronic devices.

[0586] Examples of electronic devices include electronic devices with relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0587] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, and glasses-type AR and MR devices.

[0588] The display device according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), or 8K (7680×4320 pixels). In particular, a resolution of 4K, 8K, or more is preferable. The pixel density (resolution) of the display device according to one embodiment of the present invention is preferably 100 ppi or more, more preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having one or both of such high resolution and high resolution, it is possible to further enhance the sense of realism and depth. The screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0589] The electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0590] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, etc.

[0591] An example of a wearable device that can be worn on the head will be described with reference to Figures 25(A) to 25(D). These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device have the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0592] Electronic device 700A shown in FIG. 25(A) and electronic device 700B shown in FIG. 25(B) each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0593] The display device of one embodiment of the present invention can be applied to the display panel 751. Thus, the electronic device can provide an extremely high-definition display.

[0594] Each of the electronic devices 700A and 700B can project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Since the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, each of the electronic devices 700A and 700B is an electronic device capable of AR display.

[0595] The electronic device 700A and the electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. In addition, the electronic device 700A and the electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to the orientation in the display area 756.

[0596] The communication unit has a wireless communication device and can supply a video signal, etc., via the wireless communication device. Note that instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential can be connected may be provided.

[0597] The electronic device 700A and the electronic device 700B are provided with a battery (not shown), which can be charged wirelessly and / or wired.

[0598] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting that the outer surface of the housing 721 is touched. The touch sensor module detects a tap operation or a slide operation by the user, and can execute various processes. For example, a tap operation can execute a process such as pausing or resuming a video, and a slide operation can execute a process such as fast forwarding or rewinding. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0599] As the touch sensor module, various touch sensors can be applied. For example, various types of touch sensors can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, an optical type, etc. In particular, it is preferable to apply a capacitance type or an optical type sensor to the touch sensor module.

[0600] When an optical touch sensor is used, a photoelectric conversion element can be used as the light receiving element. An active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0601] Electronic device 800A shown in Figure 25 (C) and electronic device 800B shown in Figure 25 (D) each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0602] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0603] Display unit 820 is provided inside housing 821 at a position where it can be viewed through lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0604] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0605] It is preferable that electronic device 800A and electronic device 800B each have a mechanism for adjusting the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism for adjusting the focus by changing the distance between lens 832 and display unit 820.

[0606] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 25(C) and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited thereto. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0607] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. In addition, multiple cameras may be provided so as to be compatible with multiple angles of view, such as telephoto and wide angle.

[0608] Although an example having the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection And Ranging) can be used. By using an image obtained by the camera and an image obtained by the distance image sensor, more information can be obtained, enabling more accurate gesture operation.

[0609] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having the vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without requiring a separate audio device such as headphones, earphones, or speakers.

[0610] Each of the electronic devices 800A and 800B may have an input terminal. A cable for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device can be connected to the input terminal.

[0611] The electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 25A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 25C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0612] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 25(B) has an earphone unit 727. For example, the earphone unit 727 and the control unit may be configured to be connected to each other by wire. A part of the wiring connecting the ear...

Claims

1. a transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer; the first conductive layer, the first insulating layer, the third conductive layer, the fifth insulating layer, the second insulating layer, the third insulating layer, and the second conductive layer are provided in this order in a superimposed manner; the first insulating layer, the third conductive layer, the second insulating layer, the third insulating layer, and the second conductive layer each have an opening reaching the first conductive layer; the first insulating layer has a portion that protrudes in the opening beyond a side surface of the third conductive layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and a side surface of the second conductive layer; the fifth insulating layer is provided in contact with an upper surface and a side surface of the third conductive layer, the fourth insulating layer is provided in the opening in contact with an upper surface of the first insulating layer, a side surface of the fifth insulating layer, and a side surface of the second insulating layer; the semiconductor layer is provided in contact with an upper surface of the first conductive layer in the opening, a side surface of the fourth insulating layer in the opening, and an upper surface of the second conductive layer; the sixth insulating layer is provided in contact with an upper surface of the semiconductor layer, the fourth conductive layer is provided on the sixth insulating layer so as to overlap with the opening in a plan view; the third conductive layer has a first element; the fifth insulating layer comprises an oxide of the first element; Semiconductor device.

2. In claim 1, the semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; the fourth insulating layer comprises silicon oxide or silicon oxynitride; Semiconductor device.

3. In claim 1 or 2, the third conductive layer comprises aluminum; the fifth insulating layer comprises aluminum oxide; Semiconductor device.

4. In claim 1 or 2, the first insulating layer and the third insulating layer each comprise silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device.

5. a transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer; the first conductive layer, the first insulating layer, the second conductive layer, the fifth insulating layer, the second insulating layer, and the third insulating layer are provided in this order in a superimposed manner; the first insulating layer, the second conductive layer, the second insulating layer, and the third insulating layer each have an opening reaching the first conductive layer; the first insulating layer has a portion that protrudes beyond a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third insulating layer within the opening; the fifth insulating layer is provided in contact with an upper surface and a side surface of the second conductive layer, the fourth insulating layer is provided in the opening in contact with an upper surface of the first insulating layer, a side surface of the fifth insulating layer, and a side surface of the second insulating layer; the semiconductor layer is provided in contact with an upper surface of the first conductive layer in the opening, a side surface of the fourth insulating layer in the opening, and an upper surface of the third insulating layer; the sixth insulating layer is provided in contact with an upper surface of the semiconductor layer, the third conductive layer is provided on the sixth insulating layer so as to overlap with the opening in a plan view; the second conductive layer has a first element; the fifth insulating layer comprises an oxide of the first element; Semiconductor device.

6. In claim 5, the semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; the fourth insulating layer comprises silicon oxide or silicon oxynitride; Semiconductor device.

7. In claim 5 or 6, the second conductive layer comprises aluminum; the fifth insulating layer comprises aluminum oxide; Semiconductor device.

8. In claim 5 or 6, the first insulating layer and the third insulating layer each comprise silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device.

9. forming a first conductive layer; forming a first insulating film on the first conductive layer; forming a second conductive layer on the first insulating film so as to have a region overlapping with the first conductive layer; forming a first insulating layer on an upper surface and a side surface of the second conductive layer by oxidizing a surface of the second conductive layer; forming a second insulating film, a third insulating film, and a third conductive layer in this order on the first insulating film and the first insulating layer; removing a portion of each of the third conductive layer, the third insulating film, the second insulating film, the first insulating layer, and the second conductive layer to form a first opening, and forming a fourth conductive layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth conductive layer; forming the fourth insulating layer on a side surface of the fifth conductive layer by oxidizing a side surface of the fifth conductive layer exposed in the first opening; forming a fourth insulating film in contact with an upper surface of the fourth conductive layer, a side surface of the fourth conductive layer in each of the first openings, a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and an upper surface of the first insulating film; removing a part of the fourth insulating film and a part of the first insulating film to form a second opening reaching the first conductive layer, and forming a fifth insulating layer having a protruding portion in the second opening, and a sixth insulating layer in contact with a side surface of the fourth conductive layer, a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and an upper surface of the protruding portion in the second opening, respectively; forming a semiconductor layer in contact with an upper surface of the fourth conductive layer, a side surface of the sixth insulating layer in each of the second openings, and an upper surface of the first conductive layer; forming a seventh insulating layer in contact with an upper surface and a side surface of the semiconductor layer, an upper surface of the fourth conductive layer, and an upper surface of the second insulating layer; forming a sixth conductive layer on the seventh insulating layer, the sixth conductive layer having an area overlapping with the semiconductor layer and the sixth insulating layer in a plan view; A method for manufacturing a semiconductor device.

10. In claim 9, a part of the first insulating film is removed when the first opening is formed, and an eighth insulating layer having a recess in a region overlapping with the first opening is formed. A method for manufacturing a semiconductor device.

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