Wide bandgap semiconductor device

Abstract

To provide a wide bandgap semiconductor device capable of detecting substrate temperature with high accuracy even during operation of the main transistor.SOLUTION: A wide bandgap semiconductor device comprises a substrate made primarily of the wide bandgap semiconductor, a vertical MOSFET as the main transistor in the first region of the substrate, and a horizontal MOSFET for temperature detection in the second region of the substrate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to wide bandgap semiconductor devices. [Background technology]

[0002] There is known a semiconductor device in which a main semiconductor element and a temperature sensor are disposed on the same silicon carbide substrate (see, for example, Patent Document 1). In the semiconductor device disclosed in Patent Document 1, the temperature sensor is, for example, a polysilicon diode made of a p-type polysilicon layer and an n-type polysilicon layer disposed on the front surface of the silicon carbide substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 208734 Summary of the Invention [Problem to be solved by the invention]

[0004] A main transistor provided on a wide bandgap semiconductor substrate may generate light of a short wavelength during its operation. When this light is incident on a polysilicon diode for temperature detection, the polysilicon may generate an erroneous signal due to its narrow bandgap, and the temperature detection accuracy may decrease. In particular, when the wide bandgap semiconductor is gallium nitride (GaN), which is a direct transition semiconductor and has a wider bandgap than silicon carbide (SiC), it emits stronger light of a shorter wavelength than SiC, and the impact is significant. The present disclosure aims to provide a wide bandgap semiconductor device capable of detecting the temperature of the substrate with high accuracy even during the operation of the main transistor. [Means for solving the problem]

[0005] In order to solve the above problems, a wide band gap semiconductor device according to one embodiment of the present disclosure includes a substrate whose main material is a wide band gap semiconductor, a vertical MOSFET that is a main transistor provided in a first region of the substrate, and a lateral MOSFET for temperature detection provided in a second region of the substrate. Effect of the Invention

[0006] According to the present disclosure, it is possible to provide a wide bandgap semiconductor device capable of detecting the temperature of the substrate with high accuracy even while the main transistor is in operation. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a cross-sectional view showing a configuration example of the GaN semiconductor device according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration example of the GaN semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a graph illustrating the temperature dependence of the IV characteristics in the linear region of a lateral MOSFET for temperature detection. [Diagram 5] FIG. 5 is a circuit diagram showing a modification of the GaN semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a graph illustrating the temperature dependence of IV characteristics in the linear and saturated regions of a lateral MOSFET for temperature detection. [Figure 7] FIG. 7 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 2 of the present disclosure. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a GaN semiconductor device according to the second embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view illustrating a modification of the GaN semiconductor device according to the second embodiment of the present disclosure. [Figure 10]FIG. 10 is a circuit diagram showing a modification of the GaN semiconductor device according to the second embodiment of the present disclosure. [Figure 11] FIG. 11 is a cross-sectional view illustrating a configuration example of a GaN semiconductor device according to embodiment 3 of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The following describes an embodiment of the present disclosure. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, and the like are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0009] In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and the Y-axis direction are parallel to the surface 10a of the GaN substrate 10 described below. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10. The Z-axis direction is also the thickness direction of the GaN substrate 10. The X-axis direction, Y-axis direction, and Z-axis direction are mutually orthogonal.

[0010] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0011] In the following description, the case where the first conductivity type is N type and the second conductivity type is P type will be described as an example. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being P type and the second conductivity type being N type. Furthermore, + or - attached to P or N means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions are attached with the same P and P (or N and N), it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0012] <Embodiment 1> (Overall configuration example) Fig. 1 is a plan view showing a configuration example of a GaN (gallium nitride) semiconductor device 100 (an example of a "wide band gap semiconductor device" of the present disclosure) according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view showing a configuration example of the GaN semiconductor device 100 according to the first embodiment of the present disclosure. Fig. 2 shows a cross section taken along line AA' of the plan view of Fig. 1.

[0013] GaN semiconductor device 100 shown in Fig. 1 and Fig. 2 is a power device. As shown in Fig. 1 and Fig. 2, GaN semiconductor device 100 includes a GaN substrate 10 (an example of a "substrate mainly made of a wide band gap semiconductor" in the present disclosure) having a front surface 10a and a back surface 10b, a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 provided in a first region Ar1 of GaN substrate 10, and a lateral MOSFET 2 for temperature detection provided in a second region Ar2 of GaN substrate 10.

[0014] The vertical MOSFETs 1 are repeatedly arranged in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and a plurality of such unit structures are arranged in one direction. The vertical MOSFETs 1 are main transistors of the GaN semiconductor device 100, which is a power device.

[0015] The temperature detection lateral MOSFET 2 is provided on the surface 10a side of the second region Ar2 of the GaN substrate 10. Unlike the vertical MOSFET 1, the temperature detection lateral MOSFET 2 is composed of, for example, one MOSFET. The second region Ar2 is adjacent to the first region Ar1. In a plan view from the thickness direction of the GaN substrate 10 (for example, the Z-axis direction), the second region Ar2 has a smaller area than the first region Ar1.

[0016] 1 and 2, the GaN substrate 10 has an N+ type GaN single crystal substrate 11 and an N type GaN layer 12 provided on the GaN single crystal substrate 11. The GaN single crystal substrate 11 is, for example, an N+ type c-plane GaN single crystal substrate. The N type impurities contained in the GaN single crystal substrate 11 are one or more of Si (silicon), O (oxygen) and Ge (germanium). As an example, the GaN single crystal substrate 11 contains Si as an N type impurity, and the impurity concentration of Si in the GaN single crystal substrate 11 is 5×10 17 cm -3 That's all.

[0017] The GaN single crystal substrate 11 has a dislocation density of 1×10 7 cm -2 The GaN single crystal substrate 11 may be a low dislocation freestanding substrate having a dislocation density of less than 100 nm. When the GaN single crystal substrate 11 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low dislocation freestanding substrate, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN substrate 10. This enables the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations during heat treatment.

[0018] The GaN layer 12 is a single crystal GaN layer epitaxially grown on one surface of the GaN single crystal substrate 11. The GaN layer 12 is formed by doping with an N-type impurity during the epitaxial growth process. The N-type impurity is, for example, Si. The GaN layer 12 is formed by doping with, for example, 1×10 15 cm-3 5×10 or more 16 cm -3 Contains the following concentrations:

[0019] (Example of main transistor configuration) The vertical MOSFET 1 has a P-type well region 13 provided on the front surface 10a of the GaN substrate 10 (i.e., the front surface of the N-type GaN layer 12) and a P+-type contact region 15 having a higher P-type impurity concentration than the well region 13. The vertical MOSFET 1 also has a gate insulating film 21 provided on the front surface 10a of the GaN substrate 10, a gate electrode 22 provided on the gate insulating film 21, a source region 23 provided on the front surface 10a of the GaN substrate 10, a source electrode 25 provided on the front surface 10a of the GaN substrate 10 and in contact with the source region 23 and the contact region 15, an insulating film (e.g., a SiO2 film) 26 provided between the gate electrode 22 and the source electrode 25, and a drain electrode 27 provided on the back surface 10b of the GaN substrate 10 and in contact with the N+-type GaN single crystal substrate 11.

[0020] The well region 13 is a p-type layer formed by ion-implanting a p-type impurity such as Mg on the surface 10a side of the GaN substrate 10 and activating the p-type impurity by heat treatment. The well region 13 is formed by ion-implanting a p-type impurity such as Mg at a concentration of 1×10 17 cm -3 More than 3×10 18 cm -3 The well region 13 faces the surface 10a of the GaN substrate 10. The surface of the well region 13 is in contact with the gate insulating film 21. The channel of the vertical MOSFET 1 is formed on the surface of the well region 13 in contact with the gate insulating film 21 and in the vicinity thereof.

[0021] The source region 23 is an N+ type layer formed by ion-implanting N-type impurities such as Si or O into the surface 10a of the GaN substrate 10 and activating the N-type impurities by heat treatment. For example, Si is implanted into the source region 23 at 1×10 19 cm -3 5×10 or more 20 cm -3The source regions 23 are provided in the well region 13 below both sides of the gate electrode 22, and face the surface 10a of the GaN substrate 10. The source regions 23 are located inside the well region 13 and are in contact with the well region 13.

[0022] The contact region 15 is a P+ type layer formed by ion-implanting a p-type impurity such as Mg into the front surface 10a of the GaN substrate 10 and activating the p-type impurity by heat treatment. The contact region 15 is formed by ion-implanting Mg as a p-type impurity at a concentration of 3×10 18 cm -3 More than 1×10 21 cm -3 More preferably, it is present at a concentration of 1×10 19 cm -3 More than 2×10 20 cm -3 Contains the following concentrations:

[0023] The contact region 15 faces the surface 10a of the GaN substrate 10. The contact region 15 is in contact with the well region 13. The contact region 15 also is in contact with the source region 23. The contact region 15 is formed to a deeper position from the surface 10a of the GaN substrate 10 than the well region 13.

[0024] The well region 13 is connected to the source electrode 25 via the contact region 15. As a result, the potential of the well region 13 is fixed to the potential of the source electrode 25 (for example, a reference potential such as the ground potential (GND)).

[0025] The gate insulating film 21 is, for example, a SiO2 film. The gate insulating film 21 may be a single layer film including any one of an Al2O3 film, a SiON film, an AlSiO film, and an AlON film, or may be a laminated film including any one or more of a SiO2 film, an Al2O3 film, a SiON film, an AlSiO film, and an AlON film. The thickness of the gate insulating film 21 is, for example, 50 nm or more and 150 nm or less, for example, 100 nm.

[0026] The gate electrode 22 is adjacent to a region where a channel is formed (hereinafter, referred to as a channel region) via the gate insulating film 21. The gate electrode 22 is made of a metal or an alloy. For example, the gate electrode 22 is a metal electrode made of titanium nitride (TiN), tungsten nitride (WN), titanium silicide (TiSi), tungsten silicide (WSi), tungsten (W), or the like. The gate electrode 22 is connected to a gate pad (gate terminal) G.

[0027] The source electrode 25 is in ohmic contact with each of the N+ type source region 23 and the P+ type contact region 15. The drain electrode 27 is in ohmic contact with the other surface of the N+ type GaN single crystal substrate 11 (i.e., the surface opposite to the surface in contact with the GaN layer 12).

[0028] The source electrode 25 and the drain electrode 27 are made of Al or an Al-Si alloy, Ni, a Ni alloy, a Ti-Al alloy, a Ni-Au alloy, or the like. The source electrode 25 may have a barrier metal layer between itself and the source region 23. The drain electrode 27 may have a barrier metal layer between itself and the N+ type GaN single crystal substrate 11. The barrier metal layer may be made of Ti (titanium).

[0029] That is, the source electrode 25 and the drain electrode 27 may be a laminate of a Ti layer and an Al layer, or a laminate of a Ti layer and an Al-Si alloy layer. The source electrode 25 may also serve as a source pad (source terminal) S, or may be an electrode provided separately from the source pad S. The drain electrode 27 may also serve as a drain pad (drain terminal) D (not shown), or may be an electrode provided separately from the drain pad D.

[0030] (Temperature detection transistor) The temperature detection lateral MOSFET 2 has a P-type well region 113 provided on the surface 10a of the GaN substrate 10 (i.e., the surface of the N-type GaN layer 12) and a P+-type contact region 115 (an example of the “impurity region” of the present disclosure) having a higher P-type impurity concentration than the well region 113. The temperature detection lateral MOSFET 2 also includes a gate insulating film 121 provided on the surface 10a of the GaN substrate 10, a gate electrode 122 provided on the gate insulating film 121, an N+-type source region 123 and an N+-type drain region 124 provided on the surface 10a of the GaN substrate 10, a source electrode 125 provided on the surface 10a of the GaN substrate 10 and in contact with the source region 123 and the contact region 115, an insulating film (e.g., a SiO2 film) 126 provided between the gate electrode 122 and the source electrode 125 and between the gate electrode 122 and the drain electrode 127, and a drain electrode 127 provided on the surface 10a of the GaN substrate 10 and in contact with the drain region 124.

[0031] The P-type well region 113 is formed, for example, in the same process and simultaneously with the P-type well region 13 of the vertical MOSFET 1 (i.e., the main transistor), and has the same configuration as the P-type well region 13. Similarly, the P+ type contact region 115 is formed, for example, in the same process and simultaneously with the P+ type contact region 15 of the vertical MOSFET 1, and has the same configuration as the P+ type contact region 15.

[0032] The gate insulating film 121 is formed, for example, at the same time as the gate insulating film 21 of the vertical MOSFET 1 in the same process, and has the same configuration as the gate insulating film 21.

[0033] The gate electrode 122 is formed, for example, at the same time and in the same process as the gate electrode 22 of the vertical MOSFET 1, and has the same configuration as the gate electrode 22. That is, the gate electrode 122 is made of a metal, an alloy, etc. For example, the gate electrode 122 is a metal electrode made of titanium nitride (TiN), tungsten nitride (WN), titanium silicide (TiSi), tungsten silicide (WSi), tungsten (W), or the like.

[0034] The source region 123 and the drain region 124 are formed, for example, at the same time as the N+ type source region 23 of the vertical MOSFET 1 in the same process, and have the same configuration as the N+ type source region 23.

[0035] The source electrode 125 is formed, for example, in the same process and at the same time as the source electrode 25 of the vertical MOSFET 1, and has the same configuration as the source electrode 25. The source electrode 125 is in contact with (for example, ohmic-connected to) the N+ type source region 123 and the P+ type contact region 115. The source electrode 125 may be an electrode that also serves as a source pad (source terminal) c for temperature detection, or may be an electrode provided separately from the source pad c.

[0036] The drain electrode 127 is formed simultaneously with the source electrode 125 in the same process, and has the same configuration as the source electrode 125. The drain electrode 127 is in ohmic contact with the N+ type drain region 124. The drain electrode 127 may be an electrode that also serves as a drain pad (drain terminal) a for temperature detection, or may be an electrode provided separately from the drain pad a.

[0037] The P+ type contact region 115 is formed to a position deeper from the surface 10a of the GaN substrate 10 than the P type well region 113. As shown in Fig. 1 and Fig. 2, in a plan view from the thickness direction of the GaN substrate 10 (for example, the Z-axis direction), the P+ type contact region 115 surrounds the P type well region 113. This makes it possible to stop the extension of a depletion layer from the side of the vertical MOSFET 1, which is the main transistor, to the well region 113 by the P+ type contact region 115. In addition, when a transient current caused by the expansion of the depletion layer flows into the P type well region 113, it is possible to prevent a high potential portion from being formed in the P type well region 113 as much as possible.

[0038] 2 and FIGS. 7, 9, and 11 described later show an embodiment in which the P+ type contact region 115 is formed deeper from the surface 10a of the GaN substrate 10 than the P type well region 113, but this embodiment is not necessarily limited to this. The P+ type contact region 115 may be shallower than the P type well region 113. It is preferable to form the P type well region 113 deeper than the P type well region 113, but when forming the P type well region 113 by ion implantation, it may be difficult to form it deeper. In such a case, the P+ type contact region 115 may be formed shallower than the P type well region 113.

[0039] (Temperature detection method) 3 is a circuit diagram showing a configuration example of the GaN semiconductor device 100 according to the first embodiment of the present disclosure. As shown in Fig. 2 and Fig. 3, the gate electrode 122 of the lateral MOSFET 2 for temperature detection is short-circuited (i.e., electrically connected) to the drain electrode 127 of the lateral MOSFET 2 and has the same potential as the drain electrode 127. In the lateral MOSFET 2, a current Iac is caused to flow between the drain pad a and the source pad c (hereinafter also referred to as drain-source ac), and it is possible to measure a drain-source ac voltage Vac when the current Iac reaches a preset value.

[0040] 4 is a graph illustrating the temperature dependence of the current-voltage characteristics (hereinafter also referred to as IV characteristics) in the linear region of the temperature-detection lateral MOSFET 2. In Fig. 4, the horizontal axis represents the drain-source ac voltage Vac, and the vertical axis represents the drain-source ac current Iac.

[0041] As shown in Fig. 4, the IV characteristics in the linear region are linear and have temperature dependence. The slope of the line Lh showing the IV characteristics at high temperature is different from the slope of the line Ll showing the IV characteristics at low temperature. Therefore, as shown by the dashed line parallel to the horizontal axis in Fig. 4, the temperature of the GaN substrate 10 on which the lateral MOSFET 2 is provided can be detected by passing a preset value of current I between the drain and source ac and measuring the drain-source ac voltage Vac.

[0042] For example, when a preset current I flows between the drain and source ac, a voltage Vac between the drain and source is measured as a voltage Vh at high temperatures and as a voltage Vl at low temperatures. In the linear region, when a constant current I flows between the drain and source ac of the lateral MOSFET 2, a 1:1 relationship is established between the value of the drain-source ac voltage Vac and the temperature. Therefore, the temperature of the GaN substrate 10 on which the lateral MOSFET 2 is provided can be detected with high accuracy from the measured value of the voltage Vac.

[0043] It is preferable to set the current Iac flowing when detecting the temperature to a value that makes it easy to detect the temperature. For example, it is preferable to set the current Iac flowing when detecting the temperature to a value that does not pass through the point where the straight lines Lh and Ll intersect as shown in FIG. 4. It is difficult to detect the temperature difference near the point where the straight lines Lh and Ll intersect, that is, the temperature detection sensitivity is low. Therefore, it is better to set the current value of the current Iac so as to avoid the vicinity of the point where the straight lines Lh and Ll intersect.

[0044] 3 shows a case where the source electrode 25 of the vertical MOSFET 1, which is the main transistor, and the source electrode 125 of the lateral MOSFET 2 for temperature detection are short-circuited, but this is merely an example. The source electrodes 25 and 125 do not have to be connected to each other. This is also true in FIGS. 5, 8, and 10, which will be described later, and the source electrodes 25 and 125 do not have to be connected to each other.

[0045] (Effects of the First Embodiment) As described above, the GaN semiconductor device 100 according to the first embodiment of the present disclosure comprises a GaN substrate 10, a vertical MOSFET 1 serving as a main transistor provided in a first region Ar1 of the GaN substrate 10, and a lateral MOSFET 2 for temperature detection provided in a second region Ar2 of the GaN substrate 10.

[0046] According to this, the temperature detection lateral MOSFET 2 is provided on the same GaN substrate 10 as the vertical MOSFET 1 serving as the main transistor (i.e., formed monolithically), and has the same wide band gap. This makes it possible to prevent an erroneous signal from being generated in the temperature detection lateral MOSFET 2 even if short-wavelength light is generated during operation of the vertical MOSFET 1 serving as the main transistor and the short-wavelength light is incident on the temperature detection lateral MOSFET 2. The temperature detection lateral MOSFET 2 can detect the temperature of the GaN substrate 10 with high accuracy even during operation of the vertical MOSFET 1 serving as the main transistor.

[0047] Moreover, it is preferable that the second region Ar2 in which the temperature-detecting lateral MOSFET 2 is provided is adjacent to the first region Ar1 in which the main transistor vertical MOSFET 1 is provided. This makes the temperature of the second region Ar2 the same (or almost the same) as the temperature of the first region Ar1. The temperature-detecting lateral MOSFET 2 can detect the temperature of the first region Ar1 (i.e., the temperature of the main transistor vertical MOSFET 1) with higher accuracy.

[0048] In the GaN semiconductor device 100 according to the first embodiment, the gate electrode 22 of the vertical MOSFET 1 serving as the main transistor and the gate electrode 122 of the lateral MOSFET 2 for temperature detection are preferably made of metal or alloy having the same composition. This allows the vertical MOSFET 1 serving as the main transistor to operate at high speed. In addition, the gate electrode 22 of the vertical MOSFET 1 serving as the main transistor and the gate electrode 122 of the lateral MOSFET 2 for temperature detection can be formed simultaneously in the same process. Since a dedicated process for forming the gate electrode 122 of the lateral MOSFET 2 for temperature detection (e.g., a process for forming a polysilicon film and a doping process thereof) is not required, the manufacturing cost can be reduced.

[0049] As a comparative example, a method of forming a PN diode as a temperature detection element on a GaN substrate is considered. In this comparative example, an N-type impurity layer is formed in a P-type well region to form a PN diode. In this comparative example, when the main transistor is subjected to high-speed switching operation, noise or an erroneous signal may be generated in the PN diode for temperature detection due to the junction charging current. In addition, when a potential higher than that of the source is applied to the P-type well layer, a parasitic current may be generated due to the bipolar effect, causing the PN diode for temperature detection to malfunction. More specifically, the detection current value may contain a large error, and the temperature may not be detected correctly. If noise or an erroneous signal is generated in the PN diode, or if the PN diode malfunctions, the accuracy of temperature detection decreases.

[0050] In contrast, the GaN semiconductor device 100 according to the first embodiment uses a lateral MOSFET 2 for temperature detection instead of a PN diode. As a result, even when the vertical MOSFET 1, which is the main transistor, is subjected to high-speed switching operation, noise or erroneous signals are not generated, and no malfunction occurs, as in the comparative example.

[0051] (Modification of the first embodiment) Figure 5 is a circuit diagram showing a modification of GaN semiconductor device 100 according to embodiment 1 of the present disclosure. The modification of GaN semiconductor device 100 shown in Figure 5 differs from GaN semiconductor device 100 shown in Figure 3 in that gate electrode 122 is not short-circuited to drain electrode 127 (i.e., electrically isolated) and that a gate pad (gate terminal) b connected to gate electrode 122 is provided. Other configurations of the modification of GaN semiconductor device 100 are the same as those of GaN semiconductor device 100 shown in Figures 1 to 3.

[0052] Fig. 6 is a graph illustrating the temperature dependence of the current-voltage characteristics (IV characteristics) in the linear and saturation regions of the lateral MOSFET 2 for temperature detection. In Fig. 6, the horizontal axis indicates the drain-source ac voltage Vac, and the vertical axis indicates the drain-source ac current Iac. In Fig. 6, the voltage applied to the gate electrode 122 of the lateral MOSFET 2 (hereinafter also referred to as the gate voltage) is a constant voltage equal to or higher than the threshold voltage (hereinafter also referred to as the Vth) of the lateral MOSFET 2.

[0053] As shown in FIG. 6, the IV characteristics in the saturation region are constant regardless of the drain-source voltage Vac. In addition, under a condition where the gate voltage is constant, the drain-source ac current Iac is higher at low temperatures than at high temperatures. Therefore, with the gate voltage set to a constant value equal to or higher than Vth, a voltage V of a preset value is applied between the drain and source ac as shown by the dashed line parallel to the vertical axis in FIG. 6, and the current in the saturation region (hereinafter also referred to as the saturation current) Iac flowing between the drain and source ac is measured. This makes it possible to detect the temperature of the GaN substrate 10 on which the lateral MOSFET 2 is provided.

[0054] For example, when a preset voltage V is applied between the drain and source ac with the gate voltage held constant at Vth or higher, the saturation current Iac between the drain and source is measured as a saturation current Ih at high temperatures and as a saturation current Il at low temperatures. Under the condition that the gate voltage is held constant at Vth or higher, a 1:1 relationship is established between the value of the saturation current Iac and the temperature. Therefore, the temperature of the GaN substrate 10 on which the lateral MOSFET 2 is provided can be detected with high accuracy from the measured value of the saturation current Iac.

[0055] This modification provides the same effects as the GaN semiconductor device 100 shown in Figures 1 to 3. For example, the temperature-detecting lateral MOSFET 2 is formed on the same GaN substrate 10 as the main transistor vertical MOSFET 1 (i.e., formed monolithically). This allows the temperature-detecting lateral MOSFET 2 to detect the temperature of the GaN substrate 10 with high accuracy even during operation of the main transistor vertical MOSFET 1.

[0056] <Embodiment 2> In the above-described first embodiment, the temperature detection lateral MOSFET 2 is configured with one transistor. However, the embodiments of the present disclosure are not limited to this. The temperature detection lateral MOSFET 2 may be configured with multiple transistors.

[0057] FIG. 7 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200 according to embodiment 2 of the present disclosure. FIG. 8 is a circuit diagram showing a configuration example of a GaN semiconductor device 200 according to embodiment 2 of the present disclosure. The GaN semiconductor device 200 shown in FIGS. 7 and 8 differs from the GaN semiconductor device 100 shown in FIGS. 1 to 3 in the configuration of the lateral MOSFET 2 for temperature detection. In embodiment 2, the lateral MOSFET 2 for temperature detection has a configuration in which a plurality of lateral MOSFETs are connected in series. Other configurations of the GaN semiconductor device 200 are the same as those of the GaN semiconductor device 100 shown in FIGS. 1 to 3.

[0058] As shown in FIGS. 7 and 8, the temperature detection lateral MOSFET 2 includes, for example, a first lateral MOSFET 2A and a second lateral MOSFET 2B connected in series to the first lateral MOSFET 2A.

[0059] The first lateral MOSFET 2A has an N+ type first drain region 124A provided on the surface 10a side of the GaN substrate 10, a first drain electrode 127A provided on the surface 10a side of the GaN substrate 10 and in contact with the drain region 124, and a first gate electrode 122A provided on the gate insulating film 121.

[0060] The first lateral MOSFET 2A has an N+ type first drain region 124A provided on the front surface 10a of the GaN substrate 10, a first drain electrode 127A provided on the front surface 10a of the GaN substrate 10 and in contact with the first drain region 124A, and a first gate electrode 122A provided on the gate insulating film 121. The first gate electrode 122A is short-circuited to the first drain electrode 127A and has the same potential as the first drain electrode 127A.

[0061] The second lateral MOSFET 2B has an N+ type second drain region 124B provided on the surface 10a of the GaN substrate 10, a second drain electrode 127B provided on the surface 10a of the GaN substrate 10 and in contact with the second drain region 124B, a second gate electrode 122B provided on the gate insulating film 121, an N+ type source region 123 provided on the surface 10a of the GaN substrate 10, and a source electrode 125 provided on the surface 10a of the GaN substrate 10 and in contact with the source region 123 and the P+ type contact region 115. The second gate electrode 122B is short-circuited to the second drain electrode 127B and has the same potential as the second drain electrode 127B.

[0062] The second drain region 124B of the second lateral MOSFET 2B also serves as the source region of the first lateral MOSFET 2A. The second drain electrode 127B of the second lateral MOSFET 2B also serves as the source electrode of the first lateral MOSFET 2A.

[0063] The first lateral MOSFET 2A and the second lateral MOSFET 2B have, for example, the same size. Specifically, the gate length of the first lateral MOSFET 2A and the gate length of the second lateral MOSFET 2B are the same. The gate width of the first lateral MOSFET 2A and the gate width of the second lateral MOSFET 2B are also the same.

[0064] Moreover, the gate electrode 22 of the vertical MOSFET 1 which is the main transistor and the first gate electrode 122A and the second gate electrode 122B of the lateral MOSFET 2 for temperature detection are made of a metal or alloy having the same composition.

[0065] The GaN semiconductor device 200 according to the second embodiment has the same effects as the GaN semiconductor device 100 according to the first embodiment. For example, the temperature-detecting lateral MOSFET 2 is formed on the same GaN substrate 10 as the vertical MOSFET 1 serving as the main transistor (i.e., formed monolithically). This allows the temperature-detecting lateral MOSFET 2 to detect the temperature of the GaN substrate 10 with high accuracy even during operation of the vertical MOSFET 1 serving as the main transistor.

[0066] Furthermore, in the GaN semiconductor device 200, the first lateral MOSFET 2A and the second lateral MOSFET 2B are connected in series. This makes it possible to double the temperature detection voltage Vac compared to, for example, a case in which the temperature detection lateral MOSFET 2 is composed of only the first lateral MOSFET 2A, thereby making it possible to increase the sensitivity of temperature detection.

[0067] (Modification of the second embodiment) FIG. 9 is a cross-sectional view showing a modified example of GaN semiconductor device 200 according to embodiment 2 of the present disclosure. FIG. 10 is a circuit diagram showing a modified example of GaN semiconductor device 200 according to embodiment 2 of the present disclosure. The modified example of GaN semiconductor device 200 shown in FIGS. 9 and 10 is different from GaN semiconductor device 200 shown in FIGS. 7 and 8 in that both the first gate electrode and the second gate electrode are shorted to first drain electrode 127A and second drain electrode 127B is not provided. The configuration of the modified example of GaN semiconductor device 200 is otherwise the same as that of GaN semiconductor device 200 shown in FIGS. 7 and 8.

[0068] This modification has the same effects as the GaN semiconductor device 200 shown in Figures 7 and 8. For example, the temperature-detecting lateral MOSFET 2 is formed on the same GaN substrate 10 as the vertical MOSFET 1 serving as the main transistor (i.e., formed monolithically). This allows the temperature-detecting lateral MOSFET 2 to detect the temperature of the GaN substrate 10 with high accuracy even during operation of the vertical MOSFET 1 serving as the main transistor.

[0069] In addition, there is no need to connect second drain electrode 127B and second gate electrode 122B, and there is no need to form second drain electrode 127B. As a result, the modified example of GaN semiconductor device 200 shown in Figures 9 and 10 has the potential to reduce the chip area compared to GaN semiconductor device 200 shown in Figures 7 and 8.

[0070] <Embodiment 3> In the above-mentioned first and second embodiments, the vertical MOSFET 1 serving as the main transistor has a planar structure. However, in the embodiments of the present disclosure, the vertical MOSFET may have a trench gate structure instead of the planar structure.

[0071] Fig. 11 is a cross-sectional view showing a configuration example of a GaN semiconductor device 300 according to a third embodiment of the present disclosure. The GaN semiconductor device 300 shown in Fig. 11 differs from the GaN semiconductor device 100 shown in Figs. 1 to 3 in that the vertical MOSFET 1, which is the main transistor, has a trench gate structure. Other configurations of the GaN semiconductor device 300 are the same as those of the GaN semiconductor device 100 shown in Figs. 1 to 3.

[0072] 11, the vertical MOSFET 1 according to the third embodiment has a trench H provided in a GaN substrate 10. The trench H opens to the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the P-type well region 13, and the bottom of the trench H reaches the N-type GaN layer 12.

[0073] A gate insulating film 21 and a gate electrode 22 are disposed inside the trench H. The gate insulating film 21 covers the inner side and bottom surface of the trench H. The gate electrode 22 is embedded in the trench H via the gate insulating film 21. In the vertical MOSFET 1, a region of the P-type well region 13 facing the gate electrode 22 via the gate insulating film 21 provided on the inner side surface of the trench H serves as a channel region.

[0074] The GaN semiconductor device 300 according to the third embodiment has the same effects as the GaN semiconductor device 100 according to the first embodiment. For example, the temperature-detecting lateral MOSFET 2 is formed on the same GaN substrate 10 as the vertical MOSFET 1 serving as the main transistor (i.e., formed monolithically). This allows the temperature-detecting lateral MOSFET 2 to detect the temperature of the GaN substrate 10 with high accuracy even during operation of the vertical MOSFET 1 serving as the main transistor.

[0075] <Other embodiments> As described above, the present disclosure has been described by the first to third embodiments and their modifications, but the descriptions and drawings forming part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure. For example, the "wide band gap semiconductor" of the present disclosure is not limited to gallium nitride (GaN) and may be, for example, silicon carbide (SiC). That is, a SiC substrate may be used instead of the GaN substrate 10.

[0076] Thus, the present disclosure naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments 1 to 3 and their modifications. Furthermore, the effects described in this specification are merely examples and are not limited thereto, and other effects may also be present. The technical scope of the present disclosure is defined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description.

[0077] The present disclosure can also be configured as follows. (1) A substrate mainly made of a wide band gap semiconductor; a vertical MOSFET as a main transistor provided in a first region of the substrate; a lateral MOSFET for detecting temperature provided in a second region of the substrate. (2) The wide band gap semiconductor device according to (1), wherein the gate electrode of the vertical MOSFET and the gate electrode of the lateral MOSFET are made of a metal or alloy having the same composition. (3) 3. The wide bandgap semiconductor device according to claim 1, wherein a gate electrode of the lateral MOSFET is short-circuited to a drain electrode of the lateral MOSFET. (4) The lateral MOSFET is a first lateral MOSFET; and a second lateral MOSFET connected in series to the first lateral MOSFET. (5) the first lateral MOSFET has a first drain electrode and a first gate electrode; the second lateral MOSFET has a second drain electrode and a second gate electrode; the first gate electrode is shorted to the first drain electrode; The wide bandgap semiconductor device according to (4), wherein the second gate electrode is short-circuited to the second drain electrode. (6) the first lateral MOSFET has a first drain electrode and a first gate electrode; the second lateral MOSFET has a second gate electrode; The wide band gap semiconductor device according to (4), wherein the first gate electrode and the second gate electrode are each short-circuited to the first drain electrode. (7) 7. The wide band gap semiconductor device according to claim 1, wherein the second region has a smaller area than the first region when viewed in a plan view in a thickness direction of the substrate. (8) The wide band gap semiconductor device according to any one of (1) to (7), wherein the second region is adjacent to the first region. (9) the substrate has a first conductivity type; The lateral MOSFET is a second conductivity type well region provided in the substrate; a first conductivity type source region provided in the well region; a second conductivity type impurity region provided in the substrate and in contact with the well region; the impurity region has a higher concentration of the second conductivity type than the well region; 9. The wide bandgap semiconductor device according to any one of (1) to (8), wherein a source electrode of the lateral MOSFET is in contact with the source region and the impurity region. (10) the impurity region is formed to a position deeper from the surface of the substrate than the well region; 10. The wide band gap semiconductor device according to claim 9, wherein the impurity region surrounds the well region in a plan view in a thickness direction of the substrate. (11) 11. The wide band gap semiconductor device according to any one of (1) to (10), wherein the wide band gap semiconductor is silicon carbide (SiC) or gallium nitride (GaN). [Explanation of symbols]

[0078] 1 Vertical MOSFET (the main transistor) 2 Lateral MOSFET (for temperature sensing) 2A 1st lateral MOSFET 2B Second lateral MOSFET 10 GaN substrate 10a surface 10b back side 11 GaN single crystal substrate 12 GaN layers 13, 113 well area 15, 115 Contact Area 21, 121 Gate insulating film 22, 122 Gate electrode 23, 123 Source region 25, 125 Source electrode 26, 126 Insulating film 27, 127 Drain electrode 100 GaN semiconductor device 122A First gate electrode 122B Second gate electrode 124 Drain Region 124A First drain region 124B Second drain region 127A First drain electrode 127B Second drain electrode a Drain pad (drain terminal) Ar1 1st area Ar2 2nd area b, G Gate pad (gate terminal) D Drain pad (drain terminal) c, S Source pad (source terminal) H Trench

Claims

1. A substrate mainly made of a wide band gap semiconductor; a vertical MOSFET as a main transistor provided in a first region of the substrate; a temperature sensing lateral MOSFET provided in a second region of the substrate.

2. 2. The wide band gap semiconductor device according to claim 1, wherein the gate electrode of said vertical MOSFET and the gate electrode of said lateral MOSFET are made of a metal or alloy having the same composition.

3. 3. The wide bandgap semiconductor device according to claim 1, wherein a gate electrode of said lateral MOSFET is short-circuited to a drain electrode of said lateral MOSFET.

4. The lateral MOSFET is a first lateral MOSFET; 3. The wide bandgap semiconductor device according to claim 1, further comprising: a second lateral MOSFET connected in series to the first lateral MOSFET.

5. the first lateral MOSFET has a first drain electrode and a first gate electrode; the second lateral MOSFET has a second drain electrode and a second gate electrode; the first gate electrode is shorted to the first drain electrode; 5. The wide bandgap semiconductor device of claim 4, wherein said second gate electrode is shorted to said second drain electrode.

6. the first lateral MOSFET has a first drain electrode and a first gate electrode; the second lateral MOSFET has a second gate electrode; 5. The wide bandgap semiconductor device according to claim 4, wherein said first gate electrode and said second gate electrode are each shorted to said first drain electrode.

7. 3. The wide bandgap semiconductor device according to claim 1, wherein the second region has an area smaller than that of the first region in a plan view in a thickness direction of the substrate.

8. 3. The wide bandgap semiconductor device according to claim 1, wherein the second region is adjacent to the first region.

9. the substrate has a first conductivity type; The lateral MOSFET is a second conductivity type well region provided in the substrate; a first conductivity type source region provided in the well region; a second conductivity type impurity region provided in the substrate and in contact with the well region; the impurity region has a higher concentration of the second conductivity type than the well region; 3. The wide bandgap semiconductor device according to claim 1, wherein a source electrode of said lateral MOSFET is in contact with said source region and said impurity region.

10. the impurity region is formed to a position deeper from the surface of the substrate than the well region; 10. The wide bandgap semiconductor device according to claim 9, wherein the impurity region surrounds the well region in a plan view in a thickness direction of the substrate.

11. 3. The wide band gap semiconductor device according to claim 1, wherein the wide band gap semiconductor is silicon carbide (SiC) or gallium nitride (GaN).

Images