Semiconductor integrated circuit and semiconductor device

Abstract

To provide a semiconductor integrated circuit and a semiconductor device capable of suitably generating a gray code.SOLUTION: A clock signal is input to clock terminals of a first FF and a second FF. A first signal output from a Q terminal of the first FF is input to a D terminal of the second FF. A first inverter performs an inversion operation on a second signal output from the Q terminal of the second FF. The signal output from the first inverter is input to the D terminal of the first FF. A second inverter performs an inversion operation on the first signal. Each of (L-1) adders calculates a different bit of the gray code by addition based on a carry signal. A circuit block generates the carry signal of a first adder on the basis of an AND operation of the first signal and the second signal. The circuit block generates the carry signals of a second adder to an (L-1)th adder on the basis of the second signal and the signal output by the second inverter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor integrated circuit and a semiconductor device. [Background technology]

[0002] A Gray code counter is a semiconductor integrated circuit that outputs a Gray code corresponding to the count value of a clock. The Gray code is a code in which only one bit changes for each change in the count value of 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-131071 A [Non-patent literature]

[0004] [Non-Patent Document 1] M. Cohen, and S. Even, "A Gray code counter," IEEE Transactions on Computers, vol. C-18, no.7, pp. 662-664, Jul. 1969. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor integrated circuit and a semiconductor device that can suitably generate a Gray code. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor integrated circuit generates an L-bit (where L is an integer equal to or greater than 3) Gray code according to a count value of a first clock signal. The semiconductor integrated circuit includes a first flip-flop, a second flip-flop, a first inverter, a second inverter, (L-1) adders, a circuit block, a first terminal, and (L-1) second terminals. The first clock signal is input to the clock terminal of the first flip-flop and the clock terminal of the second flip-flop. The first signal output from the Q terminal of the first flip-flop is input to the D terminal of the second flip-flop. The first inverter performs an inversion operation on the second signal output from the Q terminal of the second flip-flop. The signal output from the first inverter is input to the D terminal of the first flip-flop. The second inverter performs an inversion operation on the first signal. Each of the (L-1) adders calculates a different bit of the Gray code by addition based on the input carry signal. The circuit block generates a carry signal input to a first adder of the (L-1) adders based on a logical AND operation between a first signal and a second signal. The circuit block generates carry signals input to each of the second adders through the (L-1)th adder of the (L-1) adders based on the second signal and a signal output by the second inverter. The first terminal outputs the second signal. The (L-1) second terminals each output a signal output from a corresponding one of the (L-1) adders. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram showing an example of a circuit configuration of a Gray code counter according to the first embodiment. [Diagram 2] 4 is a timing chart showing an example of transition of various signals in the Gray code counter of the first embodiment. [Diagram 3] Truth table corresponding to the timing chart shown in Figure 2. [Figure 4] FIG. 13 is a diagram illustrating an example of a circuit configuration of a Gray code counter according to a second embodiment. [Diagram 5]10 is a timing chart showing an example of transition of various signals in the Gray code counter of the second embodiment. [Figure 6] FIG. 13 is a diagram illustrating an example of a circuit configuration of a Gray code counter according to a third embodiment. [Figure 7] 13 is a timing chart showing an example of transition of various signals in the Gray code counter of the third embodiment. [Figure 8] FIG. 13 is a diagram showing an example of a circuit configuration of a Gray code counter according to a fourth embodiment. [Figure 9] 13 is a truth table for the Gray code counter according to the fourth embodiment when a selection signal SEL is set to "0." [Figure 10] 13 is a timing chart showing an example of transition of various signals in the Gray code counter of the fourth embodiment. [Figure 11] FIG. 13 is a diagram showing an example of a circuit configuration of a Gray code counter according to a fifth embodiment. [Figure 12] 13 is a timing chart showing an example of transition of various signals in the Gray code counter according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of a circuit configuration of a Gray code counter according to a sixth embodiment. [Figure 14] 13 is a timing chart showing an example of transition of various signals in the Gray code counter according to the sixth embodiment. [Figure 15] FIG. 23 is a diagram showing an example of a circuit configuration of a Gray code counter according to the seventh embodiment. [Figure 16] 13 is a timing chart showing an example of transition of various signals in the Gray code counter of the seventh embodiment. [Figure 17] FIG. 23 is a diagram showing an example of a circuit configuration of a Gray code counter according to the eighth embodiment. [Figure 18] 13 is a timing chart showing an example of transition of various signals in the Gray code counter according to the eighth embodiment. [Figure 19] FIG. 13 is a diagram showing an example of the configuration of a memory system according to a ninth embodiment. [Figure 20] FIG. 23 is a diagram showing an example of the configuration of a portion of a bridge chip according to a ninth embodiment. [Figure 21] FIG. 23 is a diagram showing an example of the configuration of a frequency counter according to the ninth embodiment. [Figure 22] 13 is a timing chart showing an example of waveforms of various signals in the frequency counter of the ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A semiconductor integrated circuit and a semiconductor device according to embodiments will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0009] (First embodiment) 1 is a diagram showing an example of a circuit configuration of a Gray code counter that is a semiconductor integrated circuit according to the first embodiment. In the following description, the logical values ​​corresponding to the signal levels are explained as "H" state representing "1" and "L" state representing "0."

[0010] The Gray code counter 1 outputs an L-bit (where L is an integer of 3 or more) Gray code according to the count value of the clock signal CLK input thereto.

[0011] The Gray code counter 1 includes a clock terminal TCLK to which a clock signal CLK is input, a reset input terminal TRSTN to which a reset signal RSTN is input, and L data output terminals TQ0 to TQ(L-1) that output different bits of an L-bit Gray code.

[0012] In this specification, the least significant bit of the Gray code is denoted as the 0th bit, and the i-th bit from the least significant bit of the Gray code (where i is an integer from 0 to (L-1)) is denoted as the i-th bit. Data output terminal TQi outputs the i-th bit of the Gray code. A signal indicating data of the i-th bit of the Gray code is denoted as data signal Qi. Hereinafter, each of data output terminals TQ0 to TQ(L-1) may be denoted as data output terminal TQ. Furthermore, data signals Q0 to Q(L-1) may be collectively referred to as data signal Q.

[0013] The Gray code counter 1 includes a first circuit block 11, a second circuit block 12, and (L-1) adders AD1 to AD(L-1). Hereinafter, each of the adders AD1 to AD(L-1) may be referred to as an adder AD.

[0014] A carry signal C is input to each adder AD from second circuit block 12. Each adder AD calculates different bits of the Gray code by addition based on the input carry signal C, and outputs the bit data obtained by the calculation as a data signal Q. Hereinafter, the carry signal C input to adder ADj (where j is an integer from 1 to (L-1)) will be represented as carry signal C(j-1).

[0015] The adder ADj includes an XOR circuit XORj that performs an exclusive OR (in other words, XOR) operation, and a flip-flop FFj. The flip-flop FFj is a D flip-flop that includes a Q terminal, a D terminal, a clock terminal, and a reset terminal.

[0016] XOR circuit XORj has two input terminals, one of which is connected to the Q terminal of flip-flop FFj. The other of the two input terminals of XOR circuit XORj is connected to second circuit block 12, and carry signal C(j-1) is input from second circuit block 12 as carry signal C. The output terminal of XOR circuit XORj is connected to the D terminal of flip-flop FFj.

[0017] The data output from the Q terminal of the flip-flop FFj is the data signal Qj. Therefore, when the carry signal C is "1", the XOR circuit XORj inverts and outputs the data signal Qj, and when the carry signal C is "0", it outputs the data signal Qj without inverting it.

[0018] Flip-flop FFj takes in the signal input to the D terminal from XOR circuit XORj at the next clock cycle (more precisely, at the next rising edge of the clock signal CLK) and outputs the taken-in signal from the Q terminal.

[0019] Therefore, when the carry signal C(j-1) is "1", the adder ADj performs a bit operation to add "1" to the value represented by the current data signal Qj, and outputs the signal after the bit operation as the data signal Qj in the next clock cycle. When the carry signal C(j-1) is "0", the adder ADj outputs the value represented by the current data signal Qj as the data signal Qj in the next clock cycle without changing it.

[0020] The Q terminal of the flip-flop FFj is connected to the data output terminal TQj among the data output terminals TQ1 to TQ(L-1). Therefore, the data output terminals TQ1 to TQ(L-1) output the set of data signals Q1 to Q(L-1) output from the adders AD1 to AD(L-1).

[0021] A reset signal RSTN is input to a reset terminal of the flip-flop FFj. In this example, the flip-flop FFj is reset when the reset signal RSTN is "0."

[0022] Based on the reference signal input from the first circuit block 11, the second circuit block 12 calculates the carry signal C input to the adders AD1 to AD(L-1), that is, the carry signals C0 to C(L-2).

[0023] The second circuit block 12 may calculate the carry signals C0 to C(L-2) using the ripple carry method, or may calculate the carry signals C0 to C(L-2) using the carry look-ahead method. In the example shown in Figure 1, the second circuit block 12 has a configuration that calculates the carry signals C0 to C(L-2) using the ripple carry method.

[0024] The second circuit block 12 includes (L-2) element blocks 13_1 to 13_(L-2) connected in series. The element blocks 13_1 to 13_(L-2) may be collectively referred to as element block 13.

[0025] Carry generation signal P, which is a signal used to generate carry signal C, is propagated from element block 13_1 to element block 13_(L-2). Based on the carry generation signal P that has propagated to it, each element block 13 generates carry signal C and carry generation signal P to be propagated to the subsequent element block 13. The carry generation signal P generated by element block 13_m (where m is an integer from 1 to (L-2)) is denoted as carry generation signal Pm.

[0026] The element block 13_1 includes an AND circuit ANp1, and outputs a carry generation signal P1 from the output terminal of the AND circuit ANp1. Before describing the configuration of the element block 13_1 in further detail, the configurations of the element blocks 13_2 to 13_(L-2) will first be described in detail.

[0027] The element blocks 13_2 to 13_(L-2) have a common configuration. Element block 13_k (where k is an integer from 2 to (L-2)) generates a carry signal C(k-1) and a carry generation signal Pk based on a carry generation signal P(k-1) and a data signal Q(k-1).

[0028] The element block 13_k includes two AND circuits ANpk and ANck and an inverter INVk. Each of the AND circuits ANpk and ANck includes two input terminals.

[0029] One of the two input terminals of the AND circuit ANck is connected to the Q terminal of the flip-flop FF(k-1) included in the adder AD(k-1), and receives the data signal Q(k-1) output from the Q terminal of the flip-flop FF(k-1). The other of the two input terminals of the AND circuit ANck is connected to the element block 13_(k-1), more precisely, to the output terminal of the AND circuit ANp(k-1) included in the element block 13_(k-1), and receives the carry generation signal P(k-1). The output terminal of the AND circuit ANck is connected to the other of the two input terminals of the XOR circuit XORk included in the adder ADk.

[0030] The AND circuit ANck calculates the logical product of the data signal Q(k-1) and the carry generation signal P(k-1). The signal obtained by this logical product calculation is input to the XOR circuit XORk as the carry signal C(k-1).

[0031] The input terminal of the inverter INVk is connected to the Q terminal of the flip-flop FF(k-1) in the adder AD(k-1), and receives the data signal Q(k-1) output from the Q terminal of the flip-flop FF(k-1). The inverter INVk performs an inversion operation on the data signal Q(k-1) and outputs the operation result.

[0032] One of the two input terminals of the AND circuit ANpk is connected to the output terminal of the AND circuit ANp(k-1) included in the element block 13_(k-1), and the carry generation signal P(k-1) output from the AND circuit ANp(k-1) is input. The other of the two input terminals of the AND circuit ANpk is connected to the output terminal of the inverter INVk, and the data signal Q(k-1) inverted by the inverter INVk is input. The AND circuit ANpk calculates the logical product of the carry generation signal P(k-1) and the inverted data signal Q(k-1). The signal obtained by this logical product calculation is output from the element block 13_k as the carry generation signal Pk.

[0033] In this manner, the carry generation signal P propagates from element block 13_2 to element block 13_(L-2). Each element block 13_k generates a carry signal C(k-1) based on the carry generation signal P(k-1) propagated from the preceding element block 13_(k-1) and the data signal Q(k-1) output from the adder AD(k-1). Each element block 13_k also generates a new carry generation signal Pk based on the carry generation signal P(k-1) and the data signal Q(k-1). The generated carry generation signal Pk is output to the succeeding element block 13_(k+1).

[0034] In the element block 13_(L-2) corresponding to the last element block 13 among the element blocks 13_2 to 13_(L-2), the output terminal of the AND circuit ANp(L-2) is connected to the other of the two input terminals of the XOR circuit XOR(L-1) included in the adder AD(L-1). The carry generation signal P(L-2) output from the output terminal of the AND circuit ANp(L-2) is input to the XOR circuit XOR(L-1) as the carry signal C(L-2).

[0035] The first circuit block 11 generates a reference signal to be supplied to the second circuit block 12 based on the clock signal CLK.

[0036] Here, a technique compared to the embodiment will be described. The technique compared to the embodiment will be referred to as a comparative example. According to the comparative example, a circuit block for generating a reference signal includes a D flip-flop. The D flip-flop included in the circuit block for generating a reference signal will be referred to as a reference flip-flop.

[0037] In the comparative example, a clock signal is input to a clock terminal of the reference flip-flop, and data held by the reference flip-flop is inverted every clock cycle. A circuit block generates a reference signal based on the data held by the reference flip-flop that is inverted every clock cycle.

[0038] Since the Gray code changes only one bit per clock cycle, the power consumption due to data inversion in flip-flops (such as flip-flops FF1 to FF(L-1) in the configuration shown in FIG. 1) that hold each bit of the Gray code is small. When a flip-flop in which data is inverted every clock cycle to generate a reference signal is provided as a reference flip-flop as in the comparative example, the power consumption due to data inversion in the reference flip-flop is significantly larger than the power consumption due to data inversion in the flip-flops that hold each bit of the Gray code, and the power consumption of the Gray code counter increases.

[0039] Therefore, in the first embodiment, the first circuit block 11 is configured to reduce the frequency of inversion of the data held by the reference flip-flop compared to the comparative example. By reducing the frequency of inversion of the data held by the reference flip-flop, the power consumption caused by the inversion of the data of the reference flip-flop is reduced, and thus the power consumption of the Gray code counter 1 is reduced.

[0040] Specifically, the first circuit block 11 includes two reference flip-flops FFr1 and FFr2 and two inverters INVr1 and INVr2. Each of the reference flip-flops FFr1 and FFr2 is a D flip-flop including a Q terminal, a D terminal, a clock terminal, and a reset terminal.

[0041] The clock signal CLK is input to the clock terminals of the reference flip-flops FFr1 and FFr2, and the reset signal RSTN is input to the reset terminals of the reference flip-flops FFr1 and FFr2. In this example, the reference flip-flops FFr1 and FFr2 are reset when the reset signal RSTN is "0."

[0042] The D terminal of the reference flip-flop FFr2 is connected to the Q terminal of the reference flip-flop FFr1, and receives the signal output from the Q terminal of the reference flip-flop FFr1. The input terminal of the inverter INVr1 is connected to the Q terminal of the reference flip-flop FFr2. The inverter INVr1 performs an inversion operation on the signal output from the Q terminal of the reference flip-flop FFr2. The output terminal of the inverter INVr1 is connected to the D terminal of the reference flip-flop FFr1. The signal output from the inverter INVr1 is input to the D terminal of the reference flip-flop FFr1.

[0043] Therefore, the data held by the reference flip-flops FFr1 and FFr2 is inverted at a time interval that is twice the clock cycle of the clock signal CLK. The frequency of inversion of the data held by the reference flip-flops FFr1 and FFr2 is made smaller than the frequency of inversion of the data held by the reference flip-flop in the comparative example, and the power consumption of the Gray code counter 1 is reduced compared to the comparative example.

[0044] The signal output from the Q terminal of the reference flip-flop FFr2 is set as the data signal Q0. The Q terminal of the reference flip-flop FFr2 is connected to the data terminal TQ0. The data terminal TQ0 outputs the data signal Q0 output from the Q terminal of the reference flip-flop FFr2.

[0045] For convenience, the signal output from the Q terminal of the reference flip-flop FFr1 is referred to as a data signal Q(-1). Note that the data signal Q(-1) is not output from the Gray code counter 1 to the outside.

[0046] The Q terminal of the reference flip-flop FFr1 is connected to the input terminal of the inverter INVr2. The inverter INVr2 performs an inversion operation on the data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1.

[0047] The signal output from the Q terminal of the reference flip-flop FFr2 (i.e., the data signal Q0), the signal output from the Q terminal of the reference flip-flop FFr1 (i.e., the data signal Q(-1)), and the signal output from the output terminal of the inverter INVr2 (i.e., the inverted signal of the data signal Q(-1)) are input to the second circuit block 12 as reference signals.

[0048] For convenience, the signal output from the Q terminal of the reference flip-flop FFr1 and input to the second circuit block 12 is referred to as the carry generation signal P0. In other words, the data signal Q(-1) is input to the second circuit block 12 as the carry generation signal P0.

[0049] In the second circuit block 12, the element block 13_1 generates the carry signal C0 and the carry generation signal P1 based on the data signal Q0, an inverted signal of the data signal Q(-1), and the carry generation signal P0. To achieve this, the element block 13_1 includes two AND circuits ANp1 and ANc1, and an inverter INV1.

[0050] The Q terminal of a reference flip-flop FFr2 included in the first circuit block 11 is connected to one of the two input terminals of the AND circuit ANc1, and a data signal Q0 output from the Q terminal of the reference flip-flop FFr2 is input to the other of the two input terminals of the AND circuit ANc1. The Q terminal of a reference flip-flop FFr1 is connected to the other of the two input terminals of the AND circuit ANc1, and a carry generation signal P0 output from the Q terminal of the reference flip-flop FFr1 is input to the other of the two input terminals.

[0051] The output terminal of the AND circuit ANc1 is connected to the other of the two input terminals of the XOR circuit XOR1 included in the adder AD1. The AND circuit ANc1 calculates the logical product of the data signal Q0 and the carry generation signal P0. The signal obtained by the logical product calculation is input as the carry signal C0 to the XOR circuit XOR1 included in the adder AD1.

[0052] The input terminal of the inverter INV1 is connected to the Q terminal of the reference flip-flop FFr2 included in the first circuit block 11, and receives the data signal Q0 output from the Q terminal of the reference flip-flop FFr2. The inverter INV1 performs an inversion operation on the data signal Q0.

[0053] An output terminal of the inverter INVr2 included in the first circuit block 11 is connected to one of the two input terminals of the AND circuit ANp1, and a data signal Q(-1) inverted by the inverter INVr2 is input to it. An output terminal of the inverter INV1 is connected to the other of the two input terminals of the AND circuit ANp1, and a data signal Q0 inverted by the inverter INV1 is input to it. The AND circuit ANp1 calculates the logical product of the inverted data signal Q(-1) and the inverted data signal Q0. The signal obtained by this logical product calculation is output from the element block 13_1 as a carry generation signal P1.

[0054] 1, second circuit block 12 calculates carry signals C0 to C(L-2) using the ripple carry method. As described above, second circuit block 12 may be configured to calculate carry signals C0 to C(L-2) using the carry look-ahead method. When the carry look-ahead method is applied, second circuit block 12 is configured to have an arithmetic circuit that collectively calculates carry signals C1 to C(L-2) based on carry generation signal P1, instead of element blocks 13_2 to 13_(L-2).

[0055] 2 is a timing chart showing an example of the transition of various signals in the Gray code counter 1 of the first embodiment. In this figure, for ease of understanding, L is set to "4".

[0056] When reset by reset signal RSTN (immediately before timing t0 in FIG. 2), carry generation signal P0, carry signals C0, C1, and data signal Q are "0", and carry generation signals P1, P2, and carry signal C2 are "1".

[0057] Then, when the reset by the reset signal RSTN is released (timing t0), the data signal Q(-1) and carry generation signal P0 output from the Q terminal of the reference flip-flop FFr1 and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2 transition with a waveform obtained by dividing the clock signal CLK by 4. In other words, if the clock cycle of the clock signal CLK is denoted as CC, the data held by the reference flip-flops FFr1 and FFr2 changes periodically with a cycle of 4CC.

[0058] Figure 3 is a truth table corresponding to the timing chart shown in Figure 2. The 4-bit Gray code Q0-Q3 is counted sequentially from top to bottom in the truth table shown in Figure 3 for each clock cycle.

[0059] A data signal Q3 indicating the value of the most significant bit of the 4-bit Gray code Q0-Q3 is "1" in the first half of the count cycle and is "0" in the second half of the count cycle. In other words, the Gray code counter 1 operates as a counter whose count direction is downward, that is, as a down counter.

[0060] Furthermore, one bit of the 4-bit Gray code Q0-Q3 changes every clock cycle, and the data signal Q(-1) from which the 4-bit Gray code Q0-Q3 data is generated is inverted every two clock cycles.

[0061] As described above, the Gray code counter 1 of the first embodiment includes a reference flip-flop FFr1, a reference flip-flop FFr2, an inverter INVr1, an inverter INVr2, (L-1) adders AD1 to AD(L-1), a second circuit block 12, and data output terminals TQ0 to TQ(L-1). A clock signal CLK is input to the clock terminal of the reference flip-flop FFr1 and the clock terminal of the reference flip-flop FFr2. A data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1 is input to the D terminal of the reference flip-flop FFr2. The inverter INVr1 performs an inversion operation on the data signal Q0 output from the Q terminal of the reference flip-flop FFr2. The signal output from the inverter INVr1 is input to the D terminal of the reference flip-flop FFr1. The inverter INVr2 performs an inversion operation on the data signal Q(-1). Each of the (L-1) adders AD1 to AD(L-1) calculates a different bit of the Gray code by addition based on the input carry signal C. The second circuit block 12 generates the carry signal C0 input to the adder AD1 of the (L-1) adders AD1 to AD(L-1) by calculating the logical product of the data signal Q(-1) and the data signal Q0. The second circuit block 12 generates the carry signals C1 to C(L-2) input to each of the (L-1) adders from the adder AD2 to the adder AD(L-1) based on the data signal Q0 and the inverted data signal Q(-1) output from the inverter INVr2.

[0062] This reduces the frequency of inversion of data held by reference flip-flops (e.g., reference flip-flops FFr1 and FFr2) required for the calculation of the reference signal, thereby reducing the power consumption of the Gray code counter 1. In addition, the Gray code counter 1 can operate as a down counter. In other words, the Gray code is generated appropriately.

[0063] According to the first embodiment, each adder AD (expressed as adder ADj) includes a flip-flop FFj and an XOR circuit XORj. The XOR circuit XORj inputs to the D terminal of the flip-flop FFj a signal obtained by exclusive ORing the signal output from the Q terminal of the flip-flop FFj, i.e., the signal Qj, and the carry signal C(j-1).

[0064] Therefore, each adder AD can perform addition based on the input carry signal C.

[0065] Second Embodiment In a Gray code counter having a regular structure, specifically a structure in which circuit blocks such as element blocks 13 and adders AD are regularly arranged, like the Gray code counter 1 of the first embodiment, if a soft error occurs due to high-energy particles or electromagnetic waves, there is a possibility that the counting direction will be reversed.

[0066] For example, in the Gray code counter 1 of the first embodiment, some or all of the stored contents of the flip-flops FFr1, FFr2, and FF1 to FF(L-1) may be rewritten due to a soft error. When such rewriting causes the Gray code counter 1 to enter an illegal state, that is, a state in which the set of values ​​of the data signals Q(-1) to Q(L-1) takes a set of values ​​not included in a truth table (for example, the truth table shown in FIG. 3), the count direction changes from the down direction to the up direction.

[0067] In the second embodiment, a Gray code counter capable of recovering from an illegal state will be described.

[0068] The Gray code counter of the second embodiment is denoted as Gray code counter 1a. In the description of the second embodiment, the description of the same components as those of the first embodiment will be omitted or will be described briefly.

[0069] 4 is a diagram showing an example of a circuit configuration of the Gray code counter 1a of the second embodiment. The circuit configuration of the Gray code counter 1a differs from the circuit configuration of the Gray code counter 1 of the first embodiment in that a recovery circuit 14 is added.

[0070] Restoration circuit 14 invalidates carry signal C input to adder AD(L-1) according to the values ​​of data signals Q(L-1), Q(L-2), which are the values ​​of the most significant two bits of the Gray code. Note that invalidating carry signal C means leaving carry signal C unchanged. In other words, invalidating carry signal C is masking carry signal C.

[0071] In counting down, the carry generation signal P(L-2) used as the carry signal C(L-2) changes from "0" to "1" only when the value of the data signal Q(L-1) is equal to the value of the data signal Q(L-2). For example, referring to FIG. 2, the carry generation signal P2 changes from "0" to "1" only when the data signal Q3 is equal to the data signal Q2. In contrast, in counting up, the carry generation signal P(L-2) changes from "0" to "1" only when the value of the data signal Q(L-1) is different from the value of the data signal Q(L-2).

[0072] Therefore, only when the values ​​of data signals Q(L-1) and Q(L-2) are equal, restoration circuit 14 inputs carry generation signal P(L-2) to adder AD(L-1) as carry signal C. When the values ​​of data signals Q(L-1) and Q(L-2) are not equal, restoration circuit 14 prevents carry signal C to adder AD(L-1) from changing in response to a change in carry generation signal P(L-2). That is, in this case, restoration circuit 14 invalidates carry signal C input to adder AD(L-1).

[0073] Hereinafter, the carry signal C input from the restoration circuit 14 to the adder AD(L-1) will be referred to as a carry signal C'(L-2).

[0074] The recovery circuit 14 includes an XNOR circuit XNORd and an AND circuit ANDd.

[0075] The XNOR circuit XNORd has two input terminals, one of which is connected to the Q terminal of the flip-flop FF(L-1) included in the adder AD(L-1). The other of the two input terminals of the XNOR circuit XNORd is connected to the Q terminal of the flip-flop FF(L-2) included in the adder AD(L-2). The XNOR circuit XNORd performs an exclusive OR operation on the data signal Q(L-1) output from the Q terminal of the flip-flop FF(L-1) and the data signal Q(L-2) output from the Q terminal of the flip-flop FF(L-2). The XNOR circuit XNORd then performs an inversion operation on the signal obtained by the exclusive OR operation.

[0076] Hereinafter, the signal output from the XNOR circuit XNORd is referred to as a disable signal DE.

[0077] One of the two input terminals of the AND circuit ANd is connected to the output terminal of the AND circuit ANp(L-2) included in the element block 13_(L-2), and the carry generation signal P(L-2) output from the AND circuit ANp(L-2) is input. The other of the two input terminals of the AND circuit ANd is connected to the output terminal of the XNOR circuit XNORd, and the disable signal DE output from the XNOR circuit XNORd is input. The AND circuit ANd calculates the logical product of the carry generation signal P(L-2) and the disable signal DE.

[0078] The output terminal of the AND circuit ANd is connected to the adder AD(L-1). The signal output from the AND circuit ANd is input to the adder AD(L-1) as the carry signal C'(L-2).

[0079] If the values ​​of data signals Q(L-1) and Q(L-2) are equal, then disable signal DE is "1" and carry signal C'(L-2) is not negated. If the values ​​of data signals Q(L-1) and Q(L-2) are different, then disable signal DE is "0" and therefore carry signal C'(L-2) is negated.

[0080] The XOR circuit XOR(L-1) provided in the adder AD(L-1) calculates the exclusive OR of the carry signal C'(L-2) output from the AND circuit ANd and the data signal Q(L-1) output from the Q terminal of the flip-flop FF(L-1) provided in the adder AD(L-1).

[0081] 5 is a timing chart showing an example of the transition of various signals in the Gray code counter 1a of the second embodiment. In this diagram, L is also set to "4" for ease of understanding.

[0082] In the example shown in FIG. 5, a soft error causes a change in the value of data signal Q3 during counting in the downward direction, causing the counting direction to change to the upward direction (timing t2).

[0083] After timing t2, the value of data signal Q3 and the value of data signal Q2 differ from each other, so the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is suppressed. In other words, carry signal C'2 is invalidated. This suppresses the change of data signal Q3 from "0" to "1". After timing t2, each signal changes in a waveform similar to that of the counting operation in the downward direction shown in FIG. 2. In other words, the counting direction is corrected from the up direction to the down direction.

[0084] In this way, according to the second embodiment, even if the Gray code counter 1a enters an illegal state, it is possible to recover from the illegal state, i.e., a Gray code is generated appropriately.

[0085] (Third embodiment) In the third embodiment, a Gray code counter that can output a notification of recovery from an illegal state to the outside when recovery from the illegal state has been performed will be described.

[0086] The Gray code counter of the third embodiment is denoted as Gray code counter 1b. In the description of the third embodiment, the description of the same components as those of the second embodiment will be omitted or will be described briefly.

[0087] 6 is a diagram showing an example of a circuit configuration of a Gray code counter 1b according to the third embodiment. The circuit configuration of the Gray code counter 1b differs from the circuit configuration of the Gray code counter 1a according to the second embodiment in that a status generation circuit 15 and a status signal output terminal TEC are added.

[0088] The status generating circuit 15 includes an inverter INVe and an AND circuit ANe.

[0089] The output terminal of the XNOR circuit XNORd is connected to the input terminal of the inverter INVe, and the disable signal DE output from the XNOR circuit XNORd is input to the inverter INVe, which performs an inversion operation on the disable signal DE.

[0090] One of the two input terminals of the AND circuit ANe is connected to the output terminal of the AND circuit ANp(L-2) included in the element block 13_(L-2), and receives the carry generation signal P(L-2) output from the AND circuit ANp(L-2). The other of the input terminals of the AND circuit ANe is connected to the output terminal of the inverter INVe, and receives the inverted disable signal DE. The AND circuit ANe calculates the logical product of the carry generation signal P(L-2) and the inverted disable signal DE.

[0091] If the carry signal C'(L-2) is not disabled (if the disable signal DE is "1"), the AND circuit ANe suppresses output of the input carry generation signal P(L-2). If the carry signal C'(L-2) is disabled (if the disable signal DE is "0"), the AND circuit ANe outputs the input carry generation signal P(L-2).

[0092] Therefore, if the carry signal C'(L-2) is invalidated, when the carry generation signal P(L-2) changes from "0" to "1", that change is output as is from the AND circuit ANe. In other words, when a return from the illegal state has been made, the AND circuit ANe outputs "1".

[0093] An output terminal of the AND circuit ANe is connected to a status signal output terminal TEC. A signal output from the AND circuit ANe is output to the outside from the status signal output terminal TEC as a status signal EC indicating whether or not a recovery from the illegal state has been performed.

[0094] 7 is a timing chart showing an example of the transition of various signals in the Gray code counter 1b according to the third embodiment. In this diagram, L is also set to "4" for ease of understanding.

[0095] In the example shown in FIG. 7, a soft error causes a change in the value of data signal Q3 during counting in the downward direction, causing the counting direction to change to the upward direction (timing t4).

[0096] After timing t4, the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is suppressed, thereby correcting the count direction from up to down.

[0097] When the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is suppressed, status signal EC changes from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1". After changing from "0" to "1", status signal EC returns from "1" to "0" at the next rising edge of clock CLK (timing t5).

[0098] Therefore, the fact that the count direction has been corrected from up to down, in other words, that a return from the illegal state has occurred, is notified to the outside.

[0099] In this way, according to the third embodiment, when the Gray code counter 1b recovers from the illegal state, it is possible to notify the outside that the recovery from the illegal state has been performed. In other words, the Gray code is generated appropriately.

[0100] (Fourth embodiment) In the fourth embodiment, a Gray code counter capable of switching the count direction setting will be described. The Gray code counter of the fourth embodiment will be referred to as Gray code counter 1c. In the description of the fourth embodiment, the description of the same components as those of the first embodiment will be omitted or will be briefly described.

[0101] 8 is a diagram showing an example of a circuit configuration of a Gray code counter 1c according to the fourth embodiment. The circuit configuration of the Gray code counter 1c differs from the circuit configuration of the Gray code counter 1 according to the first embodiment in that a first circuit block 11a is provided instead of the first circuit block 11, and that a selection signal input terminal TSEL is added.

[0102] A selection signal SEL for selecting the count direction is input from the outside to the selection signal input terminal TSEL. As an example, the selection signal SEL being "0" means that the count direction is set to up, and the selection signal SEL being "1" means that the count direction is set to down.

[0103] The first circuit block 11a generates a reference signal to be supplied to the second circuit block 12 based on a clock signal CLK and a selection signal SEL.

[0104] The first circuit block 11a includes two reference flip-flops FFr1 and FFr2, two XOR circuits XORr1 and XORr2, and two XNOR circuits XNORr1 and XNORr2.

[0105] The clock signal CLK is input to the clock terminals of the reference flip-flops FFr1 and FFr2, and the reset signal RSTN is input to the reset terminals of the reference flip-flops FFr1 and FFr2.

[0106] The signal output from the Q terminal of the reference flip-flop FFr1 is denoted as a data signal Q(-1). Note that the data signal Q(-1) is not output from the Gray code counter 1c to the outside.

[0107] The XNOR circuit XNORr1 has two input terminals, one of which is connected to the Q terminal of the reference flip-flop FFr1. The other of the two input terminals of the XNOR circuit XNORr1 is connected to a selection signal input terminal TSEL. The XNOR circuit XNORr1 performs an exclusive OR operation on the data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1 and the selection signal SEL, and performs an inversion operation on the signal obtained by the exclusive OR operation.

[0108] The output terminal of the XNOR circuit XNORr1 is connected to the D terminal of the reference flip-flop FFr2. The signal output from the Q terminal of the reference flip-flop FFr2 is set as the data signal Q0. The Q terminal of the reference flip-flop FFr2 is connected to the data terminal TQ0. The data terminal TQ0 outputs the data signal Q0 output from the Q terminal of the reference flip-flop FFr2.

[0109] The XOR circuit XORr1 has two input terminals, one of which is connected to the Q terminal of the reference flip-flop FFr2. The other of the two input terminals of the XOR circuit XORr1 is connected to a selection signal input terminal TSEL. The XOR circuit XORr1 calculates an exclusive OR of the selection signal SEL and a data signal Q0 output from the Q terminal of the reference flip-flop FFr2. The output terminal of the XOR circuit XORr1 is connected to the D terminal of the reference flip-flop FFr1.

[0110] The data held by the reference flip-flops FFr1 and FFr2 is inverted at a time interval of twice the clock cycle of the clock signal CLK, regardless of the value of the selection signal SEL. Since the frequency of inversion of the data held by the reference flip-flops FFr1 and FFr2 is made smaller than the frequency of inversion of the data held in one clock cycle, the power consumption of the Gray code counter 1c is relatively reduced.

[0111] The Q terminal of the reference flip-flop FFr2 is also connected to the second circuit block 12. That is, the data signal Q0 output from the Q terminal of the reference flip-flop FFr2 is input to the second circuit block 12.

[0112] The XNOR circuit XNORr2 has two input terminals, one of which is connected to the Q terminal of the reference flip-flop FFr1. The other of the two input terminals of the XNOR circuit XNORr2 is connected to a selection signal input terminal TSEL. The XNOR circuit XNORr2 performs an exclusive OR operation on the data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1 and the selection signal SEL, and performs an inversion operation on the signal obtained by the exclusive OR operation. The output terminal of the XNOR circuit XNORr2 is connected to the second circuit block 12.

[0113] In the fourth embodiment, the signal output from the XNOR circuit XNORr2 and input to the second circuit block 12 is the carry generation signal P0.

[0114] The XOR circuit XORr2 has two input terminals, one of which is connected to the Q terminal of the reference flip-flop FFr1. The other of the two input terminals of the XOR circuit XORr2 is connected to a selection signal input terminal TSEL. The XOR circuit XORr2 calculates an exclusive OR of the data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1 and the selection signal SEL. The output terminal of the XOR circuit XORr2 is connected to the second circuit block 12.

[0115] The data signal Q0 output from the Q terminal of the reference flip-flop FFr2, the carry generation signal P0 output from the output terminal of the XNOR circuit XNORr2, and the signal output from the output terminal of the XOR circuit XORr2 are input to the second circuit block 12 as reference signals.

[0116] In the second circuit block 12, the element block 13_1 generates the carry signal C0 and the carry generation signal P1 based on the three input reference signals. To achieve this, the element block 13_1 includes two AND circuits ANp1, ANc1, and an inverter INV1, similar to the first embodiment.

[0117] The Q terminal of the reference flip-flop FFr2 included in the first circuit block 11 is connected to one of the two input terminals of the AND circuit ANc1, and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2 is input. The output terminal of the XNOR circuit XNORr2 is connected to the other of the two input terminals of the AND circuit ANc1, and the carry generation signal P0 output from the output terminal of the XNOR circuit XNORr2 is input. The AND circuit ANc1 calculates the logical AND of the data signal Q0 and the carry generation signal P0, and the signal obtained by the calculation is output as the carry signal C0 from the output terminal of the AND circuit ANc1.

[0118] The Q terminal of the reference flip-flop FFr2 is connected to the input terminal of the inverter INV1, and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2 is input to the input terminal of the inverter INV1. The inverter INV1 performs an inversion operation on the data signal Q0.

[0119] An output terminal of the XOR circuit XORr2 is connected to one of the two input terminals of the AND circuit ANp1. An output terminal of the inverter INV1 is connected to the other of the two input terminals of the AND circuit ANp1, and a data signal Q0 inverted by the inverter INV1 is input to the other input terminal. The AND circuit ANp1 calculates a logical product of the signal output from the output terminal of the XOR circuit XORr2 and the inverted data signal Q0. A signal obtained by the logical product calculation is output from the element block 13_1 as a carry generation signal P1. The (L-3) element blocks 13-2 to 13-(L-2) generate carry signals C1 to C(L-2) based on the carry generation signal P1.

[0120] That is, the second circuit block 12 generates a carry signal C0 by ANDing the carry generation signal P0 output from the output terminal of the XNOR circuit XNORr2 and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2. The second circuit block 12 also generates carry signals C1 to C(L-2) based on the signal output from the XOR circuit XORr2 and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2.

[0121] When the selection signal SEL is set to "1", that is, when the down direction setting is selected, the three reference signals input to the second circuit block 12 are caused to transition in the same manner as the Gray code counter 1 of the first embodiment. Therefore, each signal applied to the Gray code counter 1c is caused to transition in the same manner as the transitions shown in Figures 2 and 3. In other words, the Gray code counter 1c operates as a down counter.

[0122] When the selection signal SEL is set to "0", that is, when the up direction setting is selected, the reference signal input from the XNOR circuit XNORr2 to the second circuit block 12 and the reference signal input from the XOR circuit XORr2 to the second circuit block 12 are each inverted.

[0123] 9 shows a truth table in the case where the selection signal SEL is set to "0." In this figure, for ease of understanding, L is set to "4."

[0124] A data signal Q3 indicating the value of the most significant bit of the 4-bit Gray code Q0-Q3 is "0" in the first half of the count cycle and is "1" in the second half of the count cycle. In other words, the Gray code counter 1c operates as a counter whose count direction is up, that is, as an up-counter.

[0125] 10 is a timing chart showing an example of the transition of various signals in the Gray code counter 1c according to the fourth embodiment. Note that, in this diagram, L is also set to "4."

[0126] 10, during the period when the reset signal RSTN is released (the period from timing t10 ​​to timing t13), the selection signal SEL is set to "0" during the period from timing t10 ​​to timing t11, and the selection signal SEL is set to "1" during the period from timing t11 to timing t12. It can be seen that during the period when the selection signal SEL is set to "0", a Gray code is generated in the counting up direction, and during the period when the selection signal SEL is set to "1", a Gray code is generated in the counting down direction.

[0127] Thus, according to the fourth embodiment, the Gray code counter 1c is configured to be able to switch the count direction setting. Also, similar to the first embodiment, the frequency of inversion of data held by reference flip-flops (e.g., reference flip-flops FFr1, FFr2) required for the calculation of the reference signal is reduced, thereby reducing the power consumption of the Gray code counter 1c. Therefore, Gray codes are generated appropriately.

[0128] Fifth embodiment If a soft error occurs in the Gray code counter 1c of the fourth embodiment, there is a possibility that the count direction will be reversed.

[0129] In the fifth embodiment, a Gray code counter that is configured so that the count direction setting can be switched and that employs a recovery circuit for recovering from an illegal state will be described.

[0130] The Gray code counter of the fifth embodiment is denoted as Gray code counter 1d. In the description of the fifth embodiment, the description of the same components as those of the fourth embodiment will be omitted or will be described briefly.

[0131] 11 is a diagram showing an example of a circuit configuration of a Gray code counter 1d according to the fifth embodiment. The circuit configuration of the Gray code counter 1d differs from the circuit configuration of the Gray code counter 1c according to the fourth embodiment in that a recovery circuit 14a is added.

[0132] The recovery circuit 14a invalidates the carry signal C'(L-2) input to the adder AD(L-1) according to the values ​​of the data signals Q(L-1), Q(L-2), which are the values ​​of the most significant two bits of the Gray code, and the selection signal SEL.

[0133] As described above, when counting down, carry signal C(L-2) changes from "0" to "1" only when the value of data signal Q(L-1) is equal to the value of data signal Q(L-2). On the other hand, when counting up, carry signal C(L-2) changes from "0" to "1" only when the value of data signal Q(L-1) is different from the value of data signal Q(L-2).

[0134] Therefore, the recovery circuit 14a is configured to be able to switch, based on the selection signal SEL, whether to invalidate the carry signal when the value of the data signal Q(L-1) and the value of the data signal Q(L-2) are equal to each other or when these values ​​are different from each other.

[0135] The recovery circuit 14a includes an XOR circuit XORda, an XOR circuit XORdb, and an AND circuit ANd.

[0136] The XOR circuit XORda has two input terminals, one of which is connected to the Q terminal of the flip-flop FF(L-1) in the adder AD(L-1). The other of the two input terminals of the XOR circuit XORda is connected to the Q terminal of the flip-flop FF(L-2) in the adder AD(L-2). The XOR circuit XORda calculates the exclusive OR of the data signal Q(L-1) output from the Q terminal of the flip-flop FF(L-1) and the data signal Q(L-2) output from the Q terminal of the flip-flop FF(L-2).

[0137] The XOR circuit XORdb has two input terminals, one of which is connected to the output terminal of the XOR circuit XORda. The other of the two input terminals of the XOR circuit XORdb is connected to a selection signal input terminal TSEL. The XOR circuit XORdb calculates the exclusive OR of the signal output from the XOR circuit XORda and the selection signal SEL.

[0138] In the fifth embodiment, the signal output from the XOR circuit XORdb is used as the disable signal DE.

[0139] One of the two input terminals of the AND circuit ANd is connected to the output terminal of the AND circuit ANp(L-2) included in the element block 13_(L-2), and the carry generation signal P(L-2) is input thereto. The other of the two input terminals of the AND circuit ANd is connected to the output terminal of the XOR circuit XORdb, and the disable signal DE is input thereto. The AND circuit ANd calculates the logical product of the carry generation signal P(L-2) and the disable signal DE.

[0140] The output terminal of the AND circuit ANd is connected to the adder AD(L-1). The signal output from the AND circuit ANd is input to the adder AD(L-1) as the carry signal C'(L-2).

[0141] During the period when the selection signal SEL is set to "1", i.e., when the down direction setting is selected, the disable signal DE becomes "1" only when the values ​​of the data signals Q(L-1) and Q(L-2) are equal to each other. During the period when the selection signal SEL is set to "0", i.e., when the up direction setting is selected, the disable signal DE becomes "1" only when the values ​​of the data signals Q(L-1) and Q(L-2) are different from each other.

[0142] By using the selection signal SEL, the recovery circuit 14a can set the disable signal DE to "0" when a reversal of the count direction occurs due to an illegal state, regardless of whether the count direction is down or up. Therefore, regardless of whether the count direction is down or up, it is possible to disable the carry signal C'(L-2) in response to a reversal of the count direction due to an illegal state.

[0143] When the carry signal C'(L-2) is disabled, the change of the carry signal C'(L-2) from "0" to "1" in response to the change of the carry generation signal P(L-2) from "0" to "1" is suppressed, and the count direction is restored to the direction before the illegal state occurred. In other words, the Gray code counter 1d recovers from the illegal state.

[0144] 12 is a timing chart showing an example of the transition of various signals in the Gray code counter 1d according to the fifth embodiment. In this diagram, L is also set to "4" for ease of understanding.

[0145] In the example shown in FIG. 12, a soft error causes a change in the value of data signal Q3 during counting in the upward direction, causing the counting direction to change to the downward direction (timing t14).

[0146] After timing t14, the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is suppressed, which in turn suppresses the change of data signal Q3 from "1" to "0." As a result, at timing t15, the count direction is returned to the up direction.

[0147] As described above, according to the fifth embodiment, even if the Gray code counter 1d enters an illegal state, it is possible to recover from the illegal state, i.e., a Gray code is generated appropriately.

[0148] Sixth embodiment In the sixth embodiment, a Gray code counter that can notify an external device of a return from an illegal state when the return from the illegal state has been made will be described.

[0149] The Gray code counter of the sixth embodiment is denoted as Gray code counter 1e. In the explanation of the sixth embodiment, the explanation of the same components as those of the fifth embodiment will be omitted or will be explained briefly.

[0150] 13 is a diagram showing an example of a circuit configuration of a Gray code counter 1e according to the sixth embodiment. The circuit configuration of the Gray code counter 1e differs from the circuit configuration of the Gray code counter 1d according to the fifth embodiment in that a status generation circuit 15 is added and a status signal output terminal TEC is added.

[0151] The status generating circuit 15 includes an inverter INVe and an AND circuit ANe.

[0152] The output terminal of the XOR circuit XORdb is connected to the input terminal of the inverter INVe, and the disable signal DE output from the XOR circuit XORdb is input to the inverter INVe, which performs an inversion operation on the input disable signal DE.

[0153] The connections and operations of the AND circuit ANe are the same as those of the AND circuit ANe described with reference to FIG.

[0154] 14 is a timing chart showing an example of the transition of various signals in the Gray code counter 1e according to the sixth embodiment. In this diagram, L is also set to "4" for ease of understanding.

[0155] During counting in the upward direction, a soft error causes a change in the value of data signal Q3, causing the counting direction to change to the downward direction (timing t16).

[0156] After timing t16, the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is invalidated, and the count direction is corrected from down to up.

[0157] When the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is invalidated, status signal EC changes from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1". After changing from "0" to "1", status signal EC returns from "1" to "0" at the next rising edge of clock CLK (timing t17).

[0158] Therefore, the fact that the count direction has been corrected, in other words, that a return from the illegal state has been made, is notified to the outside.

[0159] In this way, according to the sixth embodiment, when the Gray code counter 1e returns from the illegal state, it is possible to notify the outside that the counter has returned from the illegal state. In other words, the Gray code is generated appropriately.

[0160] Seventh embodiment In the seventh embodiment, a Gray code counter configured to perform up-counting and to which a recovery circuit for recovering from an illegal state is applied will be described.

[0161] The Gray code counter of the seventh embodiment is denoted as Gray code counter 1f. In the description of the seventh embodiment, the description of the same components as those of the second embodiment will be omitted or will be briefly described.

[0162] 15 is a diagram showing an example of a circuit configuration of a Gray code counter 1f according to the seventh embodiment. The circuit configuration of the Gray code counter 1f differs from that of the Gray code counter 1a according to the second embodiment in that the Gray code counter 1f includes a first circuit block 11b instead of the first circuit block 11 and a restoration circuit 14b instead of the restoration circuit 14.

[0163] The first circuit block 11b generates a reference signal to be supplied to the second circuit block 12 based on the clock signal CLK.

[0164] The first circuit block 11b includes two reference flip-flops FFr1 and FFr2 and an inverter INVr3.

[0165] The Q terminal of the reference flip-flop FFr1 is connected to the input terminal of the inverter INVr3. The output terminal of the inverter INVr3 is connected to the D terminal of the reference flip-flop FFr2. The inverter INVr3 performs an inversion operation on the signal output from the reference flip-flop FFr1.

[0166] The Q terminal of the reference flip-flop FFr2 is connected to the D terminal of the reference flip-flop FFr1. The signal output from the Q terminal of the reference flip-flop FFr2 is input to the D terminal of the reference flip-flop FFr1.

[0167] Therefore, the data held by the reference flip-flops FFr1 and FFr2 is inverted at a time interval twice the clock cycle of the clock signal CLK. Since the frequency of inversion of the data held by the reference flip-flops FFr1 and FFr2 is made smaller than the frequency of inversion of the data held in one clock cycle, the power consumption of the Gray code counter 1 is relatively reduced.

[0168] The signal output from the Q terminal of the reference flip-flop FFr2 is set as the data signal Q0. The Q terminal of the reference flip-flop FFr2 is connected to the data terminal TQ0. The data terminal TQ0 outputs the data signal Q0 output from the Q terminal of the reference flip-flop FFr2.

[0169] The signal output from the Q terminal of the reference flip-flop FFr2 (that is, the data signal Q0), the signal output from the Q terminal of the reference flip-flop FFr1, and the signal output from the output terminal of the inverter INVr3 are input to the second circuit block 12 as reference signals.

[0170] In the seventh embodiment, the signal output from the Q terminal of the reference flip-flop FFr1 is regarded as the data signal Q(-1), and the signal output from the output terminal of the inverter INVr3 is regarded as the carry generation signal P0.

[0171] In the second circuit block 12, the element block 13_1 generates a carry signal C0 and a carry generation signal P1 based on the data signals Q0, Q(-1), and the carry generation signal P0. To achieve this, the element block 13_1 includes two AND circuits ANp1, ANc1, and an inverter INV1, similar to the second embodiment.

[0172] One of the two input terminals of the AND circuit ANc1 is connected to the Q terminal of the reference flip-flop FFr2 included in the first circuit block 11b. The other of the two input terminals of the AND circuit ANc1 is connected to the output terminal of the inverter INVr3, and receives the carry generation signal P0 output from the inverter INVr3. The AND circuit ANc1 calculates the logical AND of the data signal Q0 and the carry generation signal P0. The signal obtained by this calculation is output as the carry signal C0 from the output terminal of the AND circuit ANc1.

[0173] The connection and operation of the inverter INV1 are the same as those of the inverter INV1 described with reference to FIG. 1 in the first embodiment.

[0174] One of the two input terminals of the AND circuit ANp1 is connected to the Q terminal of the reference flip-flop FFr1 included in the first circuit block 11b. The other of the two input terminals of the AND circuit ANp1 is connected to the output terminal of the inverter INV1. The AND circuit ANp1 calculates the logical product of the data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1 and the data signal Q0 inverted by the inverter INV1. The signal obtained by the logical product calculation is output from the element block 13_1 as the carry generation signal P1. The (L-3) element blocks 13-2 to 13-(L-2) generate carry signals C1 to C(L-3) and a carry generation signal P(L-2) based on the carry generation signal P1. The carry generation signal P(L-2) is used as the carry signal C'(L-2) via the restoration circuit 14b.

[0175] That is, the second circuit block 12 generates a carry signal C0 by ANDing the carry generation signal P0 output from the inverter INVr3 and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2. The second circuit block 12 also generates carry signals (more precisely, carry signals C1 to C(L-3) and carry generation signal P(L-2)) for the adders AD2 to AD(L-2) based on the data signal Q(-1) output from the Q terminal of the reference flip-flop FFr1 and the data signal Q0 output from the Q terminal of the reference flip-flop FFr2.

[0176] The recovery circuit 14b invalidates the carry signal C'(L-2) input to the adder AD(L-1) according to the values ​​of the data signals Q(L-1), Q(L-2), which are the values ​​of the most significant two bits of the Gray code.

[0177] When counting upward, carry signal C'(L-2) changes from "0" to "1" only at the timing when the value of data signal Q(L-1) and the value of data signal Q(L-2) differ.

[0178] Therefore, the recovery circuit 14b invalidates the carry signal when the value of the data signal Q(L-1) and the value of the data signal Q(L-2) are equal to each other.

[0179] More specifically, the recovery circuit 14b includes an XOR circuit XORda and an AND circuit ANd.

[0180] The XOR circuit XORda has two input terminals, one of which is connected to the Q terminal of the flip-flop FF(L-1) in the adder AD(L-1). The other of the two input terminals of the XOR circuit XORda is connected to the Q terminal of the flip-flop FF(L-2) in the adder AD(L-2). The XOR circuit XORda calculates the exclusive OR of the data signal Q(L-1) output from the Q terminal of the flip-flop FF(L-1) and the data signal Q(L-2) output from the Q terminal of the flip-flop FF(L-2).

[0181] In the seventh embodiment, the signal output from the XOR circuit XORda is used as the disable signal DE.

[0182] One of the two input terminals of the AND circuit ANd is connected to the output terminal of the AND circuit ANp(L-2) included in the element block 13_(L-2), and receives the carry generation signal P(L-2) output from the AND circuit ANp(L-2). The other of the two input terminals of the AND circuit ANd is connected to the output terminal of the XOR circuit XORda, and receives the disable signal DE output from the XOR circuit XORda.

[0183] The output terminal of the AND circuit ANd is connected to the adder AD(L-1). The signal output from the AND circuit ANd is input to the adder AD(L-1) as the carry signal C'(L-2).

[0184] During the period when counting up is being performed, the disable signal DE becomes "1" only when the values ​​of the data signals Q(L-1) and Q(L-2) are different from each other. Therefore, if a reversal of the count direction occurs due to an illegal state during the counting up operation, the disable signal DE becomes "0" from "1", thereby invalidating the carry signal C'(L-2).

[0185] When the carry signal C'(L-2) is disabled, the change of the carry signal C'(L-2) from "0" to "1" in response to the change of the carry generation signal P(L-2) from "0" to "1" is suppressed, and the count direction is restored to the direction before the illegal state occurred. In other words, the Gray code counter 1f recovers from the illegal state.

[0186] 16 is a timing chart showing an example of the transition of various signals in the Gray code counter 1f according to the seventh embodiment. In this figure, L is also set to "4" for ease of understanding.

[0187] In the example shown in FIG. 16, a soft error causes a change in the value of data signal Q3 during counting in the upward direction, causing the counting direction to change to the downward direction (timing t20).

[0188] After timing t20, carry signal C'2 is inhibited from changing from "0" to "1" in response to carry generation signal P2 changing from "0" to "1", which inhibits data signal Q3 from changing from "0" to "1". As a result, from timing t21 onwards, the count direction is corrected from down to up.

[0189] In this way, according to the seventh embodiment, even if the Gray code counter 1f goes into an illegal state, it is possible to recover from the illegal state, that is, a Gray code is generated appropriately.

[0190] Eighth embodiment In the eighth embodiment, a Gray code counter that can notify an external device of a return from an illegal state when the return from the illegal state has been made will be described.

[0191] The Gray code counter of the eighth embodiment is denoted as Gray code counter 1g. In the description of the eighth embodiment, the description of the same components as those of the seventh embodiment will be omitted or will be described briefly.

[0192] 17 is a diagram showing an example of a circuit configuration of a Gray code counter 1g according to the eighth embodiment. The circuit configuration of the Gray code counter 1g differs from the circuit configuration of the Gray code counter 1f according to the seventh embodiment in that a status generation circuit 15 is added and a status signal output terminal TEC is added.

[0193] The status generating circuit 15 includes an inverter INVe and an AND circuit ANe.

[0194] The output terminal of the XOR circuit XORda is connected to the input terminal of the inverter INVe, and the disable signal DE output from the XOR circuit XORda is input to the inverter INVe, which performs an inversion operation on the input disable signal DE.

[0195] The connections and operations of the AND circuit ANe are the same as those of the AND circuit ANe described with reference to FIG.

[0196] Therefore, when the change of the carry signal C'(L-2) from "0" to "1" in response to the change of the carry generation signal P(L-2) from "0" to "1" is suppressed, in other words, when a recovery from the illegal state is performed, the AND circuit ANe outputs "1." The signal output from the AND circuit ANe is output to the outside as the status signal EC from the status signal output terminal TEC.

[0197] 18 is a timing chart showing an example of the transition of various signals in the Gray code counter 1g according to the eighth embodiment. In this figure, L is also set to "4" for ease of understanding.

[0198] In the example shown in FIG. 18, a soft error causes a change in the value of data signal Q3 during counting in the upward direction, causing the counting direction to change to the downward direction (timing t21).

[0199] After timing t21, the change of carry signal C'2 from "0" to "1" in response to the change of carry generation signal P2 from "0" to "1" is suppressed, which in turn suppresses the change of data signal Q3 from "1" to "0." As a result, at timing t22, the count direction is returned to the up direction.

[0200] In this way, according to the eighth embodiment, even if the Gray code counter 1g goes into an illegal state, it is possible to recover from the illegal state. Also, when the Gray code counter 1g recovers from the illegal state, it is possible to notify the outside that the recovery from the illegal state has been performed. In other words, the Gray code is generated appropriately.

[0201] Ninth embodiment Gray code only changes one bit per clock cycle. Therefore, Gray code counters have the advantage of being able to suppress the effects of errors that can occur when the output value of a Gray code counter is acquired asynchronously with the operation of the Gray code counter. Due to this feature, Gray code counters can be used, for example, in devices that handle two different clock signals.

[0202] The Gray code counter of the ninth embodiment is provided in a semiconductor device that receives data in synchronization with a first clock signal and processes the data based on a second clock signal. As an example of a system including such a semiconductor device, a memory system SYS will be described.

[0203] FIG. 19 is a diagram illustrating an example of a configuration of a memory system SYS according to the ninth embodiment.

[0204] The memory system SYS can be connected to a host HS. The communication path connecting the host HS and the memory system SYS and the standard to which the communication via the communication path conforms are not limited to a specific standard. The host HS is, for example, a personal computer, a portable information terminal, or a server. The host HS transmits various commands, including a write command or a read command, to the memory system SYS.

[0205] The memory system SYS includes a semiconductor memory device 100, a memory controller MC, and a RAM (Random Access Memory) 200.

[0206] The memory controller MC is a control circuit that controls the semiconductor memory device 100. As part of the control of the semiconductor memory device 100, the memory controller MC executes data transfer between the host HS and the semiconductor memory device 100 in response to an access command from the host HS.

[0207] The RAM 200 provides the memory controller MC with storage areas such as a buffer area, a cache area, and an area into which programs are loaded. For example, the memory controller MC can buffer transfer data between the host HS and the semiconductor memory device 100 in the RAM 200. The memory controller MC also loads firmware programs into the RAM 200 for use, and buffers or caches various management data in the RAM 200.

[0208] The semiconductor memory device 100 includes an external terminal group T, a bridge chip BC, and a plurality of memory chips CP0-0 to CP0-3, CP1-0 to CP1-3.

[0209] The bridge chip BC is an example of the semiconductor device of the ninth embodiment.

[0210] Each of the multiple memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 is, for example, a non-volatile memory chip such as a NAND type flash memory.

[0211] The semiconductor memory device 100 may be implemented as a multi-chip package (MCP) in which the memory chips CP0-0 to CP0-3 and the memory chips CP1-0 to CP1-3 are stacked. When the semiconductor memory device 100 is implemented as an MCP, the bridge chip BC and the memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 in the semiconductor memory device 100 may be sealed with a molding resin around them.

[0212] The semiconductor memory device 100 also includes a plurality of channels connecting the memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 to the bridge chip BC. Each of the plurality of channels is referred to as a memory channel MCH, meaning that it is a channel connecting a NAND type flash memory.

[0213] 19, the semiconductor memory device 100 includes memory channels MCH0 and MCH1 as the multiple memory channels MCH. Four memory chips CP0-0 to CP0-3 are connected to the bridge chip BC via the memory channel MCH0, and four memory chips CP1-0 to CP1-3 are connected to the bridge chip BC via the memory channel MCH1.

[0214] Each memory channel MCH is configured based on a predetermined standard. When each of the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 is a NAND type flash memory, the predetermined standard is, for example, a toggle DDR standard.

[0215] The number of memory chips CP included in the semiconductor memory device 100 is not limited to eight. The number of memory channels MCH connecting the bridge chip BC and the multiple memory chips CP is not limited to two. Furthermore, the number of memory chips CP connected to one memory channel MCH is not limited to four.

[0216] Hereinafter, each of the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may be referred to as a memory chip CP.

[0217] The semiconductor memory device 100 is connected to the memory controller MC via one channel. This one channel is referred to as a host channel HCH, meaning that it is a channel on the host side as viewed from the bridge chip BC.

[0218] The host channel HCH is configured based on a predetermined standard. When each memory chip CP is a NAND type flash memory, the predetermined standard is, for example, the toggle DDR standard.

[0219] The host channel HCH includes a signal line for transferring a chip enable signal CEn, a signal line for transferring a command latch signal CLE, a signal line for transferring an address latch signal ALE, a signal line for transferring a write enable signal WEn, a signal line for transferring a read enable signal RE / REn, a signal line for transferring a data strobe signal DQS / DQSn, a signal line for transferring a data signal DQ[7:0] having a predetermined bit width (here, 8 bits as an example), a signal line for transferring a ready busy signal R / Bn_1, and a signal line for transferring a ready busy signal R / Bn_2. Note that the "n" at the end of the symbol representing a signal indicates that the signal is operated with negative logic. It can be arbitrarily designed whether each signal is operated with negative logic or positive logic.

[0220] The chip enable signal CEn is a signal for enabling the memory chip CP to be accessed. The data strobe signal DQS / DQSn is a signal for instructing the other device to take in the data transmitted by the data signal DQ[7:0]. The data strobe signal DQS / DQSn is a differential signal composed of the data strobe signal DQS and the data strobe signal DQSn. The command latch enable signal CLE is a signal indicating that the data signal DQ[7:0] is a command. The address latch enable signal ALE is a signal indicating that the data signal DQ[7:0] is an address. The write enable signal WEn is a signal for instructing the other device to take in the command or address transmitted by the data signal DQ[7:0]. The read enable signal RE / REn is a signal for instructing the other device to output the data signal DQ[7:0]. The read enable signal RE / REn is a differential signal composed of the read enable signal RE and the read enable signal REn. The ready-busy signal R / Bn_1 and the ready-busy signal R / Bn_2 are signals indicating whether the device is in a ready state, which is a state in which the device is waiting to receive a command, or in a busy state, which is a state in which the device cannot execute a command even if the device receives the command. The configuration of the signal line for transferring the ready-busy signal R / Bn included in the host channel HCH is not limited to the above example. For example, the host channel HCH may have one signal line for transferring one ready-busy signal R / Bn generated by a wired OR connection or the like from the ready-busy signal R / Bn related to the memory channel MCH0 and the ready-busy signal R / Bn related to the memory channel MCH1.

[0221] Each of the memory channels MCH0 and MCH1 can transmit and receive the same types of signals as the host channel HCH. That is, each of the memory channels MCH0 and MCH1 includes a signal line for transferring a chip enable signal CEn, a signal line for transferring a command latch signal CLE, a signal line for transferring an address latch signal ALE, a signal line for transferring a write enable signal WEn, a signal line for transferring a read enable signal RE / REn, a signal line for transferring a data strobe signal DQS / DQSn, a signal line group for transferring a data signal DQ[7:0], and a signal line for transferring a ready / busy signal R / Bn.

[0222] When the host HS requests writing of data (referred to as write data) by a write command, the memory controller MC temporarily stores the write data in the RAM 200. The memory controller MC then performs various processes, such as error correction coding, on the write data stored in the RAM 200, and transfers the processed write data to the bridge chip BC as a data signal DQ[7:0]. When transferring the data signal DQ[7:0] to the bridge chip BC, the memory controller MC transfers to the bridge chip BC data strobe signals DQS / DQSn that have been toggled to synchronize with the transfer of the data signal DQ[7:0].

[0223] The bridge chip BC sequentially captures write data transferred from the memory controller MC as the data signal DQ[7:0] in response to the toggling of the data strobe signals DQS / DQSn. The bridge chip BC transfers the captured write data to one of the memory chips CP as the data signal DQ[7:0]. When transferring the data signal DQ[7:0] to the memory chip CP, the bridge chip BC transfers to the memory chip CP the data strobe signals DQS / DQSn that have been toggled to synchronize with the transfer of the data signal DQ[7:0].

[0224] When the host HS issues a read command requesting the memory controller MC to read data (referred to as read data), the memory controller MC instructs the memory chip CP in which the read data is stored to perform a read operation via the bridge chip BC. In response to the read operation instruction, the memory chip CP in which the read data is stored transfers the read data to the bridge chip BC as a data signal DQ[7:0]. When transferring the data signal DQ[7:0] to the bridge chip BC, the memory chip CP transfers to the bridge chip BC data strobe signals DQS / DQSn that are toggled to synchronize with the transfer of the data signal DQ[7:0].

[0225] The bridge chip BC sequentially captures the read data transferred from the memory chip CP as the data signal DQ[7:0] in response to the toggling of the data strobe signals DQS / DQSn. The bridge chip BC transfers the captured read data to the memory controller MC as the data signal DQ[7:0]. When transferring the data signal DQ[7:0] to the memory controller MC, the bridge chip BC transfers to the memory controller MC the data strobe signals DQS / DQSn that have been toggled to synchronize with the transfer of the data signal DQ[7:0].

[0226] In this way, the bridge chip BC captures data transferred from an external device (in this case, one of the memory controller MC and the memory chip CP) by the data strobe signal DQS / DQSn toggled to synchronize with the transfer of the data, and then transfers the captured data to another external device (in this case, the other of the memory controller MC and the memory chip CP).

[0227] The bridge chip BC includes an oscillator circuit (oscillating circuit 101 described later) that generates a clock signal used for various processes. The clock signal generated by the oscillator circuit 101 is referred to as a clock signal CLK0. The bridge chip BC performs various processes using the clock signal CLK0 on data captured using the data strobe signals DQS / DQSn.

[0228] The frequency of the clock signal CLK0 varies due to various factors including fluctuations in temperature of the oscillator circuit 101 or fluctuations in the voltage supplied to the oscillator circuit 101. However, in order to process all data captured using the data strobe signals DQS / DQSn, the frequency of the clock signal CLK0 is required to be equal to or higher than the frequency of the data strobe signals DQS / DQSn. Therefore, the bridge chip BC has the following configuration to maintain the frequency of the clock signal CLK0 equal to or higher than the frequency of the data strobe signals DQS / DQSn.

[0229] 20 is a diagram showing an example of a partial configuration of the bridge chip BC of the 9th embodiment. The bridge chip BC includes an oscillator circuit 101, a frequency counter 102, and a control circuit 103.

[0230] The oscillator circuit 101 is an oscillator whose oscillation frequency can be controlled by an input from an external terminal. The oscillator circuit 101 generates a clock signal CLK0. The oscillator circuit 101 is, for example, a voltage-controlled oscillator (VCO).

[0231] Data strobe signals DQS / DQSn transferred from the outside (memory controller MC or memory chip CP) are input to the frequency counter 102. The frequency counter 102 counts the input data strobe signals DQS / DQSn. The count by the frequency counter 102 corresponds to the count of the frequency of the data strobe signals DQS / DQSn.

[0232] For ease of understanding, it is assumed here that the data strobe signal DQS of the data strobe signals DQS / DQSn is input to the frequency counter 102, and the frequency of the data strobe signal DQS is counted. The frequency of the data strobe signal DQS is equal to the frequency of the data strobe signal DQSn.

[0233] Furthermore, the data strobe signal DQS input to the frequency counter 102 may be treated as a signal similar to a clock signal for the sake of convenience, and may be referred to as a clock signal CLK1.

[0234] The control circuit 103 adjusts the frequency of the clock signal CLK0 so that the frequency of the clock signal CLK0 is equal to or higher than the frequency of the data strobe signals DQS / DQSn, based on the count value of the frequency counter 102. The control circuit 103 changes the frequency of the clock signal CLK0 by inputting a control signal to the control terminal of the oscillation circuit 101.

[0235] FIG. 21 is a diagram illustrating an example of the configuration of the frequency counter 102 according to the ninth embodiment.

[0236] The frequency counter 102 includes a Gray code counter 1h, four registers RG1 to RG4, a Gray-binary code converter 111, two multiplexers MX1 and MX2, a timing signal generating circuit 112, and a subtractor 113.

[0237] A reset signal RSTN is input to the Gray code counter 1h, the registers RG1 to RG4, and the reset terminals of the timing signal generating circuit 112. A clock signal CLK0 is input to the clock terminals of the registers RG1 to RG4 and the timing signal generating circuit 112.

[0238] The Gray code counter 1h is a semiconductor integrated circuit having a configuration similar to that of any one of the Gray code counters 1 of the first embodiment to the Gray code counters 1g of the eighth embodiment. A data strobe signal DQS is input as a clock signal CLK1 to a clock terminal (clock terminal TCLK in the first embodiment) of the Gray code counter 1h. The Gray code counter 1h counts the input clock signal CLK1. The Gray code counter 1h outputs an L-bit Gray code Q0 to Q(L-1) corresponding to the count value of the clock signal CLK1 from a data output terminal (a set of data output terminals TQ0 to TQ(L-1) in the first to eighth embodiments).

[0239] The data output terminal of the Gray code counter 1h is connected to the data input terminal of the register RG1. The register RG1 stores the L-bit Gray code output from the data output terminal of the Gray code counter 1h at a timing based on the clock signal CLK0, more specifically, at the timing of the rising edge of the clock signal CLK0.

[0240] The data output terminal of the register RG1 is connected to the data input terminal of the register RG2. The data output terminal of the register RG2 is connected to the Gray-binary code converter 111.

[0241] The Gray-binary code converter 111 converts the L-bit Gray code into L-bit binary data, thereby obtaining L-bit data that represents the count value of the clock signal CLK1 in binary.

[0242] The multiplexer MX1 ​​has two input terminals AI and BI, each of which receives L-bit data, an output terminal ZO which outputs L-bit data, and an input terminal SI which receives a selection signal. The input terminal AI of the multiplexer MX1 ​​is connected to the output terminal of the register RG3. The input terminal BI of the multiplexer MX1 ​​is connected to the output terminal of the Gray-binary code converter 111.

[0243] The input terminal of the register RG3 is connected to the output terminal of the multiplexer MX1.

[0244] The multiplexer MX2 has two input terminals AI and BI, each of which receives L-bit data, an output terminal ZO which outputs L-bit data, and an input terminal SI which receives a selection signal. The input terminal AI of the multiplexer MX2 is connected to the output terminal of the register RG4. The input terminal BI of the multiplexer MX2 is connected to the output terminal of the register RG3.

[0245] The timing signal generating circuit 112 generates a timing pulse TP that becomes "1" during one clock cycle every predetermined number of clock cycles (hereinafter referred to as a count period) based on the clock signal CLK0. The timing pulse TP is input to the multiplexers MX1 and MX2 as a selection signal.

[0246] Each of the multiplexers MX1 and MX2 selects the input from the input terminal AI when the input selection signal (i.e., timing pulse TP) is "0." Each of the multiplexers MX1 and MX2 selects the input from the input terminal BI when the input selection signal (i.e., timing pulse TP) is "1."

[0247] The subtractor 113 has two input terminals XI and YI, each of which receives L-bit data, and an output terminal. The input terminal XI is connected to the output terminal of the register RG3. The input terminal Y1 is connected to the output terminal of the register RG4. The subtractor 113 subtracts the L-bit data input to the input terminal YI from the L-bit data input to the input terminal XI, and outputs the L-bit data obtained by the subtraction as data FO corresponding to the frequency of the clock signal CLK1 (hereinafter, frequency data). The frequency data FO corresponds to the count value of the clock signal CLK1 during the count period.

[0248] 22 is a timing chart showing an example of waveforms of various signals in the frequency counter 102 of the ninth embodiment. As shown in this figure, when the reset by the reset signal RSTN is released (timing t30) and a timing pulse TP that is set to "1" for one clock cycle in each count period is input to the multiplexers MX1 and MX2, the count value of the clock signal CLK1 (i.e., the data strobe signal DQS) obtained in each count period is output as frequency data FO in the next count period.

[0249] The control circuit 103 acquires frequency data F O as a count value by the frequency counter 102. The control circuit 103 adjusts the oscillation frequency of the oscillation circuit 101 based on the frequency data F O acquired from the frequency counter 102.

[0250] For example, when the control circuit 103 determines that the frequency of the clock signal CLK0 is lower than the frequency of the clock signal CLK1 based on the frequency data FO acquired from the frequency counter 102, the control circuit 103 increases the oscillation frequency of the oscillation circuit 101. When the control circuit 103 determines that the frequency of the clock signal CLK0 is not lower than the frequency of the clock signal CLK1, the control circuit 103 does not change the oscillation frequency of the oscillation circuit 101. Note that the method of adjusting the oscillation frequency of the oscillation circuit 101 is not limited to this.

[0251] As described above, according to the ninth embodiment, the bridge chip BC includes a Gray code counter 1h that counts the clock signal CLK1, an oscillator circuit 101 that generates the clock signal CLK0, and a register RG1 that stores the Gray code output from the Gray code counter 1h in itself at a timing based on the clock signal CLK0.

[0252] The Gray code counter 1h of the embodiment can be applied not only to the bridge chip BC but also to any semiconductor device that operates based on a clock signal different from the clock signal that is the target of counting by the Gray code counter 1h.

[0253] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0254] 1, 1a to 1h Gray code counter, 11 first circuit block, 12 second circuit block, 13 element block, 14, 14a, 14b recovery circuit, 15 status generation circuit, 100 semiconductor memory device, 101 oscillator circuit, 102 frequency counter, 103 control circuit, 111 Gray-binary code converter, 112 timing signal generation circuit, 113 subtractor.

Claims

1. A semiconductor integrated circuit that generates an L-bit (where L is an integer equal to or greater than 3) Gray code corresponding to a count value of a first clock signal, a first flip-flop having a clock terminal to which the first clock signal is input; a second flip-flop, the first clock signal being input to a clock terminal thereof, and the first signal output from a Q terminal of the first flip-flop being input to a D terminal of the second flip-flop; a first inverter that performs an inversion operation on a second signal output from a Q terminal of the second flip-flop, the signal output from the first inverter being input to a D terminal of the first flip-flop; a second inverter that performs an inversion operation on the first signal; (L-1) adders, each of which calculates a different bit of the Gray code by addition based on an input carry signal; a circuit block that generates a carry signal input to a first adder of the (L-1) adders based on an AND operation of the first signal and the second signal, and generates carry signals input to each of the second adder to the (L-1)-th adder of the (L-1) adders based on the second signal and a signal output by the second inverter; a first terminal for outputting the second signal; (L-1) second terminals for outputting signals output from corresponding adders among the (L-1) adders; A semiconductor integrated circuit comprising:

2. Each of the (L-1) adders a third flip-flop having a clock terminal to which the first clock signal is input; an exclusive OR circuit that calculates an exclusive OR between an input carry signal and a third signal output from a Q terminal of the third flip-flop, the signal output from the exclusive OR circuit being input to a D terminal of the third flip-flop; Equipped with Each of the (L-1) second terminals outputs a third signal of each of the corresponding (L-1) adders.

2. The semiconductor integrated circuit according to claim 1.

3. an exclusive-NOR circuit that performs an exclusive-OR operation on the third signal output from a Q terminal of the third flip-flop included in the (L-1) adder and the third signal output from a Q terminal of the third flip-flop included in the (L-2) adder of the (L-1) adders, and performs an inversion operation on the signal obtained by the exclusive-OR operation; a first AND circuit that calculates a logical AND between a fourth signal output from the exclusive NOR circuit and a fifth signal output from the circuit block as a carry signal for the (L-1) adder; Further equipped with The exclusive OR circuit included in the (L-1) adder calculates an exclusive OR of the signal output from the first AND circuit and the third signal output from a Q terminal of the third flip-flop included in the (L-1) adder.

3. The semiconductor integrated circuit according to claim 2.

4. a third inverter that performs an inversion operation on the fourth signal; a second AND circuit that calculates a logical AND between the signal output from the third inverter and the fifth signal; a third terminal for outputting a signal output from the second AND circuit; The semiconductor integrated circuit according to claim 3 , further comprising:

5. A semiconductor integrated circuit that generates an L-bit (where L is an integer equal to or greater than 3) Gray code corresponding to a count value of a first clock signal, a first flip-flop having a clock terminal to which the first clock signal is input; a first terminal to which a selection signal is input; a first exclusive-NOR circuit that performs an exclusive-OR operation on a first signal output from a Q terminal of the first flip-flop and the selection signal, and performs an inversion operation on a signal obtained by the exclusive-OR operation; a second flip-flop, the first clock signal being input to a clock terminal thereof, and the signal output from the first exclusive-NOR circuit being input to a D terminal of the second flip-flop; a first exclusive-OR circuit that performs an exclusive-OR operation on a second signal output from a Q terminal of the second flip-flop and the selection signal, the signal output from the first exclusive-OR circuit being input to a D terminal of the first flip-flop; a second exclusive-NOR circuit that performs an exclusive-OR operation on the first signal and the selection signal and performs an inversion operation on the signal obtained by the exclusive-OR operation; a second exclusive-OR circuit that calculates an exclusive-OR between the first signal and the selection signal; (L-1) adders, each of which calculates a different bit of the Gray code by addition based on an input carry signal; a circuit block that generates a carry signal input to a first adder of the (L-1) adders based on a logical AND operation between a signal output from the second exclusive-NOR circuit and the second signal, and generates carry signals input to each of the second adders to the (L-1)th adder of the (L-1) adders based on a signal output from a second exclusive-OR circuit and the second signal; a second terminal for outputting the second signal; (L-1) third terminals for outputting signals output from corresponding adders among the (L-1) adders; A semiconductor integrated circuit comprising:

6. Each of the (L-1) adders a third flip-flop having a clock terminal to which the first clock signal is input; a third exclusive-OR circuit that performs an exclusive-OR operation on an input carry signal and a third signal output from a Q terminal of the third flip-flop, the signal output from the third exclusive-OR circuit being input to a D terminal of the third flip-flop; Equipped with Each of the (L-1) second terminals outputs a third signal of each of the corresponding (L-1) adders.

6. The semiconductor integrated circuit according to claim 5.

7. a fourth exclusive-OR circuit that calculates an exclusive-OR of the third signal output from a Q terminal of the third flip-flop included in the (L-1) adder and the third signal output from a Q terminal of the third flip-flop included in an (L-2)-th adder of the (L-1) adders; a fifth exclusive-OR circuit that calculates an exclusive-OR between a signal output from the fourth exclusive-OR circuit and the selection signal; a first AND circuit that calculates a logical AND of a fourth signal output from the fifth exclusive OR circuit and a fifth signal output from the circuit block as a carry signal for the (L-1) adder; Further equipped with The third exclusive OR circuit included in the (L-1) adder calculates an exclusive OR of the signal output from the first AND circuit and the third signal output from a Q terminal of the third flip-flop included in the (L-1) adder.

7. The semiconductor integrated circuit according to claim 6.

8. an inverter that performs an inversion operation on the fourth signal; a second AND circuit that calculates a logical AND between the signal output from the inverter and the fifth signal; a fourth terminal for outputting a signal output from the second AND circuit; The semiconductor integrated circuit according to claim 7 , further comprising:

9. A semiconductor integrated circuit that generates an L-bit (where L is an integer equal to or greater than 3) Gray code corresponding to a count value of a first clock signal, a first flip-flop having a clock terminal to which the first clock signal is input; a second flip-flop having a clock terminal to which the first clock signal is input, and a first signal output from a Q terminal of the second flip-flop is input to a D terminal of the first flip-flop; a first inverter that performs an inversion operation on a second signal output from a Q terminal of the first flip-flop, the first inverter inverting the second signal output from the first inverter to obtain a third signal that is input to a D terminal of the second flip-flop; (L-1) adders, each of which calculates a different bit of the Gray code by addition based on an input carry signal; a circuit block that generates a carry signal input to a first adder of the (L-1) adders based on an AND operation of the first signal and the third signal, and generates carry signals input to each of the second adder to the (L-1)-th adder of the (L-1) adders based on the first signal and the second signal; a first terminal for outputting the first signal; (L-1) second terminals for outputting signals output from corresponding adders among the (L-1) adders; Equipped with Each of the (L-1) adders a third flip-flop having a clock terminal to which the first clock signal is input; a first exclusive-OR circuit that performs an exclusive-OR operation on an input carry signal and a fourth signal output from a Q terminal of the third flip-flop, and inputs a signal obtained by the exclusive-OR operation to a D terminal of the third flip-flop; Equipped with Each of the (L-1) second terminals outputs a fourth signal of each of the corresponding (L-1) adders; a second exclusive-OR circuit that calculates an exclusive-OR of the fourth signal output from a Q terminal of the third flip-flop included in the (L-1) adder and the fourth signal output from a Q terminal of the third flip-flop included in an (L-2)-th adder of the (L-1) adders; a first AND circuit that calculates a logical AND of a fifth signal output from the second exclusive OR circuit and a sixth signal output from the circuit block as a carry signal for the (L-1) adder; Further equipped with The first exclusive OR circuit included in the (L-1) adder calculates an exclusive OR of the signal output from the first AND circuit and the fourth signal output from a Q terminal of the third flip-flop included in the (L-1) adder. Semiconductor integrated circuit.

10. a second inverter that performs an inversion operation on the fifth signal; a second AND circuit that calculates a logical AND between the signal output from the second inverter and the sixth signal; a third terminal for outputting a signal output from the second AND circuit; The semiconductor integrated circuit according to claim 9 , further comprising:

11. A semiconductor integrated circuit according to any one of claims 1 to 10; an oscillator circuit for generating a second clock signal; a register that stores the Gray codes output from the first terminal and the (L-1) second terminals of the semiconductor integrated circuit at a timing based on the second clock signal; A semiconductor device comprising:

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