Semiconductor memory device

Abstract

To provide a semiconductor memory device to improve processing capacity.SOLUTION: According to the embodiment, a semiconductor memory device includes: a first select transistor ST1, a memory string NS including a first memory cell MC7 and a second memory cell MC6, a bit line BL, a first word line WL7, a second word line WL6, and a control circuit 14 configured to perform a write operation including a program operation and a program verify operation. When the control circuit performs a program verify operation of the first memory cell, a voltage of the second word line is increased to a first voltage VREAD based on a first condition, and when a program verify operation of the second memory cell is performed, a voltage of the first word line is increased to a first voltage based on a second condition different from the first condition.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] A NAND type flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-032169 A Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a semiconductor memory device with improved processing power. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a memory string including a first select transistor, a first memory cell, and a second memory cell connected in series, a bit line connected to the first select transistor, a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a control circuit configured to perform a write operation including a program operation and a program verify operation. When performing a program verify operation of the first memory cell, the control circuit increases a voltage of the second word line to a first voltage based on a first condition, and when performing a program verify operation of the second memory cell, the control circuit increases a voltage of the first word line to the first voltage based on a second condition different from the first condition. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] 1 is a circuit diagram of a memory cell array included in a semiconductor memory device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 4] 4 is a diagram showing threshold voltage distributions and data allocation when the memory cell transistor included in the semiconductor memory device according to the first embodiment is a triple level cell (TLC) capable of storing 3-bit (8-value) data; FIG. [Diagram 5] 4 is a diagram showing a data write order in a NAND string included in the semiconductor memory device according to the first embodiment. [Figure 6] 1 is a diagram showing a write state of memory cell transistors MC when word line group WG0 is selected in the semiconductor memory device according to the first embodiment. [Figure 7] 1 is a diagram showing a write state of memory cell transistors MC when word line group WG1 is selected in the semiconductor memory device according to the first embodiment. [Figure 8] 1 is a diagram showing a write state of memory cell transistors MC when word line group WG2 is selected in the semiconductor memory device according to the first embodiment. [Figure 9] 5 is a timing chart showing voltages of each wiring in a program operation and a program verify operation in the semiconductor memory device according to the first embodiment. [Figure 10] 11A and 11B are timing charts showing the voltage and current of unselected word lines during a program verify operation and a comparative example of the state of a NAND string. [Figure 11] 11A and 11B are timing charts showing the voltage and current of unselected word lines during a program verify operation and a comparative example of the state of a NAND string. [Figure 12] 10 is a diagram showing the voltages and currents of unselected word lines during the period from time t5 to t6 described with reference to FIG. 9 when word line group WG0 is selected in the semiconductor memory device according to the first embodiment. FIG. [Figure 13]10 is a diagram showing the voltages and currents of unselected word lines during the period from time t5 to t6 described with reference to FIG. 9 when word line group WG1 is selected in the semiconductor memory device according to the first embodiment. FIG. [Figure 14] 10 is a diagram showing the voltages and currents of unselected word lines during the period from time t5 to t6 described with reference to FIG. 9 when word line group WG2 is selected in the semiconductor memory device according to the first embodiment. FIG. [Figure 15] 10 is a diagram showing the voltage and current of unselected word lines during the period from time t5 to time t6 described with reference to FIG. 9 when word line group WG0 is selected in the semiconductor memory device according to the second embodiment. FIG. [Figure 16] 10 is a diagram showing the voltages and currents of unselected word lines during the period from time t5 to t6 described with reference to FIG. 9 when word line group WG1 is selected in the semiconductor memory device according to the second embodiment. FIG. [Figure 17] 10 is a diagram showing the voltages and currents of unselected word lines during the period from time t5 to t6 described with reference to FIG. 9 when word line group WG2 is selected in the semiconductor memory device according to the second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given a common reference symbol. When multiple components having a common reference symbol are to be distinguished from one another, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol is added to the multiple components, and no subscript is added. Here, the subscript is not limited to a subscript or a superscript, but includes, for example, a lowercase alphabet added to the end of a reference symbol, and an index indicating an array.

[0008] 1. First embodiment A semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is a NAND type flash memory capable of storing data in a nonvolatile manner. Note that the semiconductor memory device 1 is not limited to a NAND type flash memory. The semiconductor memory device 1 may be another nonvolatile memory.

[0009] 1.1 Configuration 1.1.1 Overall configuration of semiconductor memory device First, an example of the overall configuration of a semiconductor memory device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. Note that, although some of the connections between the components are indicated by arrows in Fig. 1, the connections between the components are not limited to this.

[0010] 1, a semiconductor memory device 1 is configured to be controllable by an external memory controller 2. For example, the semiconductor memory device 1 transmits and receives a signal DQ and timing signals DQS and DQSn to and from the memory controller 2. The signal DQ is, for example, data DAT, an address ADD, or a command CMD. The timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. The timing signal DQSn is an inverted signal of the timing signal DQS.

[0011] Furthermore, the semiconductor memory device 1 receives various control signals from the memory controller 2. Then, the semiconductor memory device 1 transmits a ready / busy signal RBn to the memory controller 2. The ready / busy signal RBn is a signal indicating whether the semiconductor memory device 1 is in a state in which it cannot receive a command CMD from the memory controller 2 (busy state) or in a state in which it can receive a command CMD (ready state).

[0012] The semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, an address register 12, a command register 13, a sequencer 14, a ready / busy circuit 15, a voltage generation circuit 16, a memory cell array 17, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21.

[0013] The input / output circuit 10 is a circuit that inputs and outputs a signal DQ. The input / output circuit 10 is connected to the memory controller 2. The input / output circuit 10 is also connected to a logic control circuit 11, an address register 12, a command register 13, and a data register 20.

[0014] When the input signal DQ is an address ADD, the input / output circuit 10 transmits the address ADD to the address register 12. When the input signal DQ is a command CMD, the input / output circuit 10 transmits the command CMD to the command register 13.

[0015] When the input signal DQ is data DAT, the input / output circuit 10 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input / output circuit 10 transmits the data DAT to the data register 20. In addition, the input / output circuit 10 outputs the data DAT to the memory controller 2 together with the timing signals DQS and DQSn.

[0016] The logic control circuit 11 is a circuit that performs logic control based on control signals. The logic control circuit 11 is connected to the memory controller 2. The logic control circuit 11 is also connected to the input / output circuit 10 and the sequencer 14. The logic control circuit 11 receives a plurality of control signals from the memory controller 2. The logic control circuit 11 controls the input / output circuit 10 and the sequencer 14 based on the received control signals.

[0017] The address register 12 is a register that temporarily stores an address ADD. The address register 12 is connected to the input / output circuit 10, the row decoder 18, and the column decoder 21. The address ADD includes a row address RA and a column address CA. The row address RA is an address for selecting wiring (word lines and select gate lines) arranged in the row direction in the memory cell array 17. The column address CA is an address for selecting wiring (bit lines) arranged in the column direction in the memory cell array 17. For example, the row address RA includes a block address and a word line address. The block address is an address that specifies one of a plurality of blocks BLK included in the memory cell array 17. The word line address is an address that specifies one of a plurality of word lines connected to the block BLK.

[0018] The address register 12 transfers a row address RA to a row decoder 18. The address register 12 also transfers a column address CA to a column decoder 21.

[0019] The command register 13 is a register that temporarily stores the command CMD. The command register 13 is connected to the input / output circuit 10 and the sequencer 14. The command register 13 transfers the command CMD to the sequencer 14.

[0020] The sequencer 14 is a control circuit that controls the semiconductor memory device 1. The sequencer 14 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 14 controls a ready / busy circuit 15, a voltage generating circuit 16, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21. For example, the sequencer 14 executes a write operation, a read operation, an erase operation, etc. based on a command CMD.

[0021] The ready / busy circuit 15 is a circuit that transmits a ready / busy signal RBn to the memory controller 2 under the control of the sequencer 14.

[0022] The voltage generation circuit 16 generates voltages used in write, read, and erase operations under the control of the sequencer 14. The voltage generation circuit 16 supplies the generated voltages to the memory cell array 17, the row decoder 18, the sense amplifier 19, etc. The row decoder 18 and the sense amplifier 19 can apply the voltage supplied from the voltage generation circuit 16 to the memory cell array 17.

[0023] The memory cell array 17 is a collection of multiple memory cell transistors (also simply referred to as "memory cells") arranged in a matrix. The memory cell array 17 includes multiple blocks BLK. In the example shown in FIG. 1, the memory cell array 17 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 17 is arbitrary. The block BLK is, for example, a collection of multiple memory cell transistors from which data is erased collectively. In other words, the block BLK is a unit of data erasure. The configuration of the block BLK will be described in detail later.

[0024] The row decoder 18 is a decode circuit for a row address RA. Based on the decoded result, the row decoder 18 selects one of the blocks BLK in the memory cell array 17. The row decoder 18 applies a voltage to the row-direction wiring (word lines and select gate lines) of the selected block BLK.

[0025] The sense amplifier 19 is a circuit that writes and reads data DAT. The sense amplifier 19 is connected to the memory cell array 17 and a data register 20. During a read operation, the sense amplifier 19 reads data DAT from the memory cell array 17. During a write operation, the sense amplifier 19 supplies the memory cell array 17 with a voltage based on the write data DAT and the threshold voltage of the memory cell transistor.

[0026] The data register 20 is a register that temporarily stores data DAT. The data register 20 is connected to the sense amplifier 19 and the column decoder 21. The data register 20 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0027] The column decoder 21 is a circuit that decodes a column address CA. The column decoder 21 receives the column address CA from the address register 12. The column decoder 21 selects a latch circuit in the data register 20 based on the result of decoding the column address CA.

[0028] 1.1.2 Memory cell array circuit configuration Next, an example of a circuit configuration of the memory cell array 17 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of the memory cell array 17.

[0029] The block BLK includes, for example, four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary. The string unit SU is, for example, a set of multiple NAND strings NS that are collectively selected in a write operation or a read operation.

[0030] Next, the internal configuration of the string unit SU will be described. The string unit SU includes a plurality of NAND strings NS. The NAND string NS is a collection of a plurality of memory cell transistors connected in series. Each of the plurality of NAND strings NS in the string unit SU is connected to one of the bit lines BL0 to BLm (m is an integer equal to or greater than 1).

[0031] Next, the internal configuration of the NAND strings NS will be described. Each NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example shown in Fig. 2, the NAND string NS includes eight memory cell transistors MC0 to MC7.

[0032] The memory cell transistor MC is a memory element that stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that uses an insulator for the charge storage layer, or a FG (Floating Gate) type that uses a conductor for the charge storage layer. The following describes the case where the memory cell transistor MC is a MONOS type.

[0033] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0034] The current paths of the select transistor ST2, the memory cell transistors MC0 to MC7, and the select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0035] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes four string units SU0 to SU3. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for the memory cell transistors MC1 to MC7.

[0036] The gates of the multiple selection transistors ST1 in the string unit SU are commonly connected to one selection gate line SGD. More specifically, the gates of the multiple selection transistors ST1 in the string unit SU0 are commonly connected to a selection gate line SGD0. The gates of the multiple selection transistors ST1 in the string unit SU1 are commonly connected to a selection gate line SGD1. The gates of the multiple selection transistors ST1 in the string unit SU2 are commonly connected to a selection gate line SGD2. The gates of the multiple selection transistors ST1 in the string unit SU3 are commonly connected to a selection gate line SGD3.

[0037] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Note that, like the select gate line SGD, the select gate line SGS may be provided for each string unit SU.

[0038] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3, and the select gate line SGS are each connected to a row decoder 18.

[0039] The bit lines BL are commonly connected to one NAND string NS in each string unit SU of each block BLK. Each bit line BL is connected to a sense amplifier 19.

[0040] The source line SL is shared among, for example, a plurality of blocks BLK.

[0041] A set of multiple memory cell transistors MC connected to a common word line WL in one string unit SU is denoted as, for example, a "cell unit CU." In other words, a cell unit CU is a set of multiple memory cell transistors MC selected collectively in a write operation or a read operation. A page is a unit of data that is collectively written (or collectively read) into a cell unit CU. For example, when a memory cell transistor MC stores 1-bit data, the storage capacity of the cell unit CU is 1 page. Note that the cell unit CU may have a storage capacity of 2 or more pages based on the number of bits of data stored in the memory cell transistor MC.

[0042] 1.1.3 Cross-sectional structure of memory cell array Next, an example of a cross-sectional configuration of the memory cell array 17 will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view of the memory cell array 17. Fig. 3 shows a cross section of one memory pillar MP corresponding to one NAND string NS. Note that some interlayer insulating films are omitted in Fig. 3.

[0043] 3, an insulating layer 31 is formed on a semiconductor substrate 30. The insulating layer 31 is made of, for example, silicon oxide (SiO). Note that circuits such as a row decoder 18 or a sense amplifier 19 may be provided in the region where the insulating layer 31 is formed, i.e., between the semiconductor substrate 30 and the wiring layer 32.

[0044] On the insulating layer 31, a wiring layer 32 that extends in an X direction substantially parallel to the semiconductor substrate 30 and in a Y direction intersecting the X direction and functions as a source line SL is formed. The wiring layer 32 is made of a conductive material, for example, a semiconductor material doped with impurities.

[0045] Above the wiring layer 32, for example, ten wiring layers 33 that function as the select gate lines SGS, the word lines WL0 to WL7, and the select gate lines SGD and extend in the X direction are stacked in sequence with interlayer insulating films (not shown) interposed between them.

[0046] The wiring layer 33 is made of a conductive material, and for example, a semiconductor material or a metal material to which an impurity is added is used. For example, a laminated structure of titanium nitride (TiN) / tungsten (W) is used as the wiring layer 33. Titanium nitride functions as a barrier layer for preventing a reaction between tungsten and silicon oxide when forming a film of tungsten by, for example, CVD (chemical vapor deposition), or as an adhesion layer for improving the adhesion of tungsten. The wiring layer 33 may also include a high-dielectric material such as aluminum oxide (AlO). In this case, the high-dielectric material is formed so as to cover the conductive material. For example, in each of the wiring layers 33, a high-dielectric material is provided so as to contact the upper and lower surfaces of the wiring layer 33 and the side surfaces of the memory pillar MP. Then, titanium nitride is provided so as to contact the high-dielectric material. Then, W is provided so as to contact the titanium nitride and fill the inside of the wiring layer 33. For example, when aluminum oxide is used as the high dielectric constant material, the memory cell transistor MC is also referred to as a MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type.

[0047] A memory pillar MP is formed penetrating the ten wiring layers 33, with its bottom surface reaching the wiring layer 32. The memory pillar MP has, for example, a cylindrical shape extending in the Z direction. One memory pillar MP corresponds to one NAND string NS. The memory pillar MP includes a block insulating film 34, a charge storage layer 35, a tunnel insulating film 36, a semiconductor layer 37, a core layer 38, and a cap layer 39.

[0048] More specifically, a hole corresponding to the memory pillar MP is formed so as to penetrate the wiring layer 33 and reach the wiring layer 32 at its bottom. A block insulating film 34, a charge storage layer 35, and a tunnel insulating film 36 are sequentially stacked on the side of the hole. A semiconductor layer 37 is formed so that its side is in contact with the tunnel insulating film 36 and its bottom is in contact with the wiring layer 32. The semiconductor layer 37 is a region in which the channels of the memory cell transistor MC and the select transistors ST1 and ST2 are formed. Thus, the semiconductor layer 37 functions as a signal line connecting the current paths of the select transistor ST2, the memory cell transistors MC0 to MC7, and the select transistor ST1. A core layer 38 is provided in the semiconductor layer 37. A cap layer 39 is formed on the semiconductor layer 37 and the core layer 38, the side of which is in contact with the tunnel insulating film 36.

[0049] For example, silicon oxide is used for the block insulating film 34, the tunnel insulating film 36, and the core layer 38. For example, silicon nitride (SiN) is used for the charge storage layer 35. For example, polysilicon is used for the semiconductor layer 37 and the cap layer 39.

[0050] A contact plug 40 is formed on the cap layer 39. A wiring layer 41 that functions as a bit line BL and extends in the Y direction is formed on the contact plug 40. The contact plug 40 and the wiring layer 41 are made of a conductive material, such as copper (Cu) wiring.

[0051] In the example of FIG. 3, one layer of each of the wiring layers 33 functioning as the selection gate lines SGD and SGS is provided, but multiple layers may be provided.

[0052] Memory cell transistors MC0 to MC7 are respectively configured by memory pillars MP and eight wiring layers 33 functioning as word lines WL0 to WL7, respectively. Similarly, select transistors ST1 and ST2 are respectively configured by memory pillars MP and two wiring layers 33 functioning as select gate lines SGD and SGS, respectively.

[0053] 1.2 Threshold voltage distribution of memory cell transistors Next, an example of a threshold voltage distribution that the memory cell transistor MC can take will be described with reference to FIG. 4. FIG. 4 is a diagram showing the threshold voltage distribution and data allocation when the memory cell transistor MC is a TLC (Triple Level Cell) capable of storing 3-bit (8-value) data. The number of bits of data that the memory cell transistor MC can store is arbitrary. For example, the memory cell transistor MC may be an SLC (Single Level Cell) capable of storing 1-bit (2-value) data, or an MLC (Multi Level Cell) capable of storing 2-bit (4-value) data. Furthermore, the memory cell transistor MC may be a QLC (Quad Level Cell) capable of storing 4-bit (16-value) data, or a PLC (Penta Level Cell) capable of storing 5-bit (32-value) data.

[0054] 4, when the memory cell transistors MC are TLC, the threshold voltage of each memory cell transistor MC takes a value included in one of, for example, eight discrete distributions. Hereinafter, the eight distributions are referred to as "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state, in order of decreasing threshold voltage.

[0055] The "Er" state corresponds to, for example, the data erased state. The "A" to "G" states correspond to the state where charges are injected into the charge storage layer and data is written. In the write operation, let the verify voltages corresponding to each threshold voltage distribution be VA to VG. Then, these voltage values have the relationship of VA < VB < VC < VD < VE < VF < VG < VREAD. The voltage VREAD is the voltage applied to the non-selected word line WL during the read operation. When the voltage VREAD is applied to the gate of the memory cell transistor MC, it is turned on regardless of the stored data. In the following description, the word line WL selected during the write operation or read operation is denoted as "selected word line WL_s", and the non-selected word line WL is denoted as "non-selected word line WL_u".

[0056] More specifically, the threshold voltage included in the "Er" state is less than the voltage VA. The threshold voltage included in the "A" state is equal to or greater than the voltage VA and less than the voltage VB. The threshold voltage included in the "B" state is equal to or greater than the voltage VB and less than the voltage VC. The threshold voltage included in the "C" state is equal to or greater than the voltage VC and less than the voltage VD. The threshold voltage included in the "D" state is equal to or greater than the voltage VD and less than the voltage VE. The threshold voltage included in the "E" state is equal to or greater than the voltage VE and less than the voltage VF. The threshold voltage included in the "F" state is equal to or greater than the voltage VF and less than the voltage VG. And the threshold voltage included in the "G" state is equal to or greater than the voltage VG and less than the voltage VREAD.

[0057] For example, let the read voltages corresponding to the read operations of the "A" to "G" states be VA to VG respectively. Then, these voltages and the voltage VREAD have the relationship of VA < VB < VC < VD < VE < VF < VG < VREAD.

[0058] Note that the set value of the verify voltage corresponding to each state and the set value of the read voltage may be the same or different. In the following, for the sake of simplicity of explanation, the case where the verify voltage and the read voltage have the same set value will be described.

[0059] Hereinafter, the read operations corresponding to the "A" to "G" states are respectively referred to as the AR read operation, the BR read operation, the CR read operation, the DR read operation, the ER read operation, the FR read operation, and the GR read operation. The AR read operation determines whether the threshold voltage of the memory cell transistor MC is less than the voltage VA. The BR read operation determines whether the threshold voltage of the memory cell transistor MC is less than the voltage VB. The CR read operation determines whether the threshold voltage of the memory cell transistor MC is less than the voltage VC. The same is true for the DR read operation, the ER read operation, the FR read operation, and the GR read operation.

[0060] As described above, each memory cell transistor MC can have one of eight threshold voltage distributions, and can be in eight different states. By assigning these states to binary notation "000" to "111," each memory cell transistor MC can hold three bits of data. Hereinafter, the three bits of data are referred to as the lower bit, the middle bit, and the upper bit. In addition, a set of lower bits that are collectively written (or read) to a cell unit CU is called a lower page, a set of middle bits is called a middle page, and a set of upper bits is called an upper page.

[0061] In the example of FIG. 4, for the memory cell transistors MC included in each threshold voltage distribution, data is assigned to the "Upper bit / Middle bit / Lower bit" as shown below.

[0062] “Er” state: “111” data “A” state: “110” data “B” state: “100” data "C" state: "000" data “D” state: “010” data “E” state: “011” data “F” state: “001” data “G” state: “101” data

[0063] When reading data allocated in this manner, the Lower bit is determined by the AR read operation and the ER read operation. The Middle bit is determined by the BR read operation, the DR read operation, and the FR read operation. The Upper bit is determined by the CR read operation and the GR read operation. In other words, the values ​​of the Lower bit, Middle bit, and Upper bit are determined by two, three, and two read operations, respectively. In what follows, this data allocation is referred to as the "2-3-2 code." Note that the allocation of data to the "Er" to "G" states is not limited to the 2-3-2 code.

[0064] 1.3 Write Operation Next, an example of a write operation will be described. The write operation includes a program operation and a program verify operation. Then, by repeating a combination of the program operation and the program verify operation (hereinafter, referred to as a "program loop"), the threshold voltage of the memory cell transistor MC is raised to a target level.

[0065] A program operation is an operation of increasing the threshold voltage by injecting electrons into the charge storage layer of a memory cell transistor MC to be programmed (or maintaining the threshold voltage by prohibiting the injection of electrons into the charge storage layer of a memory cell transistor MC that is inhibited from being programmed).

[0066] The program verify operation is an operation in which data is read from the memory cell transistor MC after the program operation to determine whether or not the threshold voltage of the memory cell transistor MC has reached a target level. The memory cell transistor MC whose threshold voltage has reached the target level is write-protected in the subsequent program loop.

[0067] 1.3.1 Write Order First, an example of a data write sequence in the NAND string NS will be described with reference to Fig. 5. Fig. 5 is a diagram showing a data write sequence in the NAND string NS.

[0068] 5, when a write operation is performed, the memory cell transistor MC to be written is selected in order starting from the bit line BL side. Hereinafter, the memory cell transistor MC to be written is also referred to as the "selected memory cell transistor MC" or "selected MC." Note that the memory cell transistor MC to be written may be selected in order starting from the source line SL side.

[0069] In the example shown in FIG. 5, the sequencer 14 first selects the word line WL7. Then, the sequencer 14 selects the word lines WL6 to WL1 in order, and finally selects the word line WL0. In other words, the sequencer 14 first selects the memory cell transistor MC7. Then, the sequencer 14 selects the memory cell transistors MC6 to MC1 in order, and finally selects the memory cell transistor MC0. For example, the word line address corresponding to the word line WL7 selected first is also referred to as the "first word line address." Furthermore, the word line address corresponding to the word line WL0 selected last is also referred to as the "last word line address."

[0070] In this embodiment, the word lines WL are divided into a plurality of word line groups WG based on the selection order of the word lines WL. In the example shown in FIG. 5, the word lines WL0 to WL7 are divided into three word line groups WG0 to WG2. For example, the word line WL7 belongs to the word line group WG0. The word lines WL6 to WL1 belong to the word line group WG1. And the word line WL0 belongs to the word line group WG2. That is, the word line WL corresponding to the first word line address belongs to the word line group WG0. The word line group WG1 includes a plurality of word lines WL corresponding to other word line addresses not including the first word line address and the last word line address. The word line group WG2 includes the word line WL corresponding to the last word line address. It should be noted that four or more word line groups WG may be provided. Also, the grouping of the word lines WL can be set arbitrarily. For example, the word lines WL7 and WL6 may belong to the word line group WG0.

[0071] 1.3.2 Relationship between word line group selection and memory cell transistor write state Next, an example of the relationship between the selection of the word line group WG and the write state of the memory cell transistor MC will be described with reference to Figures 6 to 8. Figure 6 is a diagram showing the write state of the memory cell transistor MC when the word line group WG0 is selected. Figure 7 is a diagram showing the write state of the memory cell transistor MC when the word line group WG1 is selected. The example of Figure 7 shows a case where the memory cell transistor MC4 (word line WL4) is selected. Figure 8 is a diagram showing the write state of the memory cell transistor MC when the word line group WG2 is selected.

[0072] 6, when the word line WL7 of the word line group WG0, i.e., the memory cell transistor MC7, is selected, the unselected memory cell transistors MC0 to MC6 are in an unwritten state in which no write operation is being performed, i.e., the unselected memory cell transistors MC0 to MC6 are in the “Er” state.

[0073] 7, for example, when word line WL4 of word line group WG1, i.e., memory cell transistor MC4, is selected, the unselected memory cell transistors MC0 to MC3 are in an unwritten state. That is, the unselected memory cell transistors MC0 to MC3 are in the "Er" state. Random data is written to the unselected memory cell transistors MC5 to MC7. That is, each of the unselected memory cell transistors MC5 to MC7 is in one of the "Er" to "G" states.

[0074] 8, for example, when word line WL0 of word line group WG2, i.e., memory cell transistor MC0, is selected, random data is written to unselected memory cell transistors MC1 to MC7, that is, each of unselected memory cell transistors MC1 to MC7 is in one of the “Er” to “G” states.

[0075] 1.3.3 Voltage of each line during write operation Next, an example of the voltage of each line during a write operation will be described with reference to Fig. 9. Fig. 9 is a timing chart showing the voltage of each line during a program operation and a program verify operation. In the example of Fig. 9, the period from time t0 to t5 shows the program operation, and the period from time t5 to t10 shows the program verify operation.

[0076] In the following description, a string unit SU that is selected during a write operation is referred to as a "selected string unit SU." The select gate line SGD corresponding to the selected string unit SU is referred to as a "select gate line SGD_s." Furthermore, a string unit SU that is not selected during a write operation is referred to as a "non-selected string unit SU." The select gate line SGD corresponding to the non-selected string unit SU is referred to as a "select gate line SGD_u." Among the selected memory cell transistors MC, the bit line BL that corresponds to the memory cell transistor MC to be programmed is referred to as a "bit line BL_p." Furthermore, the bit line BL that corresponds to the memory cell transistor MC that is inhibited from being programmed is referred to as a "bit line BL_i."

[0077] First, the program operation during the period from time t0 to t5 will be described.

[0078] As shown in FIG. 9, at time t0, the row decoder 18 applies a voltage VSG_p1 to the select gate lines SGD_s and SGD_u. The voltage VSG_p1 is a voltage that turns on the select transistor ST1 during a program operation. The sense amplifier 19 applies a voltage VBL_p to the bit line BL_i. The voltage VBL_p is higher than the voltage VSS and lower than the voltage VSG_p1. The voltage VSRC_p is applied to the source line SL. The voltage VSRC_p is a voltage higher than the voltage VSS. The select transistor ST1 of each string unit SU is turned on. The select transistor ST2 is turned off.

[0079] At time t1, the row decoder 18 applies VSS to the select gate line SGS_u. This turns off the select transistor ST1 of the unselected string unit SU. The row decoder 18 also applies a voltage VSG_p2 to the select gate line SGD_s. The voltage VSG_p2 is higher than the voltage VSS and lower than the voltage VBL_p. This turns on the select transistor ST1 corresponding to the memory cell transistor MC to be programmed in the selected string unit SU. The select transistor ST1 corresponding to the program-inhibited memory cell transistor MC is turned off. That is, the NAND string NS corresponding to the program-inhibited memory cell transistor MC is put into a floating state.

[0080] At time t2, the row decoder 18 applies a voltage VPASS to the selected word line WL_s and the unselected word line WL_u. The voltage VPASS is a voltage that turns on the memory cell transistor MC, regardless of the threshold voltage of the memory cell transistor MC.

[0081] At time t3, the row decoder 18 applies the voltage VPGM to the selected word line WL_s. The voltage VPGM is a high voltage for injecting electrons into the charge storage layer of the selected memory cell transistor MC to be programmed. The voltage VPGM is a voltage higher than the voltage VPASS. As a result, in the selected memory cell transistor MC to be programmed, the potential difference (VPGM-VSS) between the selected word line WL_s and the channel becomes large. As a result, electrons are injected into the charge storage layer, and the threshold voltage of the selected memory cell transistor MC increases. On the other hand, in the selected memory cell transistor MC to be inhibited from programming, the potential difference between the selected word line WL_s and the channel is smaller than that of the memory cell transistor MC to be programmed due to channel boosting. As a result, almost no electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MC is maintained (the threshold voltage does not change to such an extent that the threshold voltage transitions to a higher threshold voltage distribution). The voltage VPGM can be stepped up every time the program loop is repeated.

[0082] During the period from time t4 to t5, the row decoder 18 discharges the voltages applied to the selected word line WL_s, the unselected word line WL_u, and the selection gate line SGD_s. In the example shown in FIG. 9, the potentials of the selected word line WL_s, the unselected word line WL_u, and the selection gate line SGD_s are lowered to the voltage VSS. Note that the potentials of the selected word line WL_s and the unselected word line WL_u at time t5 may be a voltage higher than the voltage VSS. In addition, the sense amplifier 19 applies the voltage VSS to the bit line BL_i. In addition, the voltage VSS is applied to the source line SL.

[0083] Next, the program verify operation during the period from time t5 to t10 will be described.

[0084] First, at time t5, the row decoder 18 applies a voltage VREAD to the selected word line WL_s and the unselected word line WL_u. The row decoder 18 also applies a voltage VSG_r to the select gate lines SGD_s, SGD_u, and SGS. The voltage VSG_r is a voltage that turns on the select transistors ST1 and ST2 in the program verify operation.

[0085] In the period from time t5 to t6, the voltage applied to the selected word line WL_s and the unselected word line WL_u reaches the voltage VREAD. The period from time t5 to t6 is also referred to as the "setup time (boost period)" of the voltage VREAD.

[0086] At time t7, the row decoder 18 applies the voltage VSS to the selected word line WL_s and the select gate line SGD_u, thereby turning off the selected memory cell transistor MC and the select transistor ST1 of the selected string unit SU.

[0087] During a period from time t8 to time t9, the row decoder 18 applies a voltage VVFY to the selected word line WL_s. The voltage VVFY is a voltage applied to the selected word line WL during a program verify operation. The voltage VVFY is a voltage lower than the voltage VREAD. The voltage VVFY is based on a target level (a state to be written) of a write operation. In the example shown in FIG. 9, the row decoder 18 applies voltages VA, VB, and VC in order as the voltage VVFY to the selected word line WL_s. In other words, the sequencer 14 executes an AR read operation, a BR read operation, and a CR read operation in succession. The sense amplifier 19 applies a voltage VBL_r to the bit lines BL_p and BL_i. A voltage VSRC_r is applied to the source line SL. The voltage VSRC_r is a voltage higher than the voltage VSS and lower than the voltage VBL_r.

[0088] During the period from time t8 to time t9, the sense amplifier 19 reads data from the selected memory cell transistor MC. If the threshold voltage of the memory cell transistor MC is equal to or higher than the voltage VVFY, the memory cell transistor MC is turned off. In this case, the sequencer 14 determines that the write operation in the memory cell transistor MC is completed. On the other hand, if the threshold voltage of the memory cell transistor MC is lower than the voltage VVFY, the memory cell transistor MC is turned on. In this case, the sequencer 14 determines that the write operation in the memory cell transistor MC is not completed.

[0089] During the period from time t9 to t10, the voltages of the selected word line WL_s, the unselected word line WL_u, the select gate lines SGD_s, SGD_u, and SGS, the bit lines BL_p and BL_i, and the source line SL are discharged, i.e., the voltage VSS is applied to each line.

[0090] 1.3.4 Voltage and current of unselected word lines during program verify operation Next, an example of the voltage and current of the unselected word line WL_u during the program verify operation will be described with reference to FIG. 10 and FIG. 11. FIG. 10 and FIG. 11 are timing charts of the voltage and current I_WL of the unselected word line WL_u during the program verify operation, and are diagrams showing comparative examples of the state of the NAND string NS. FIG. 10 and FIG. 11 show a case where the voltage of the unselected word line WL_u rises (increases) at a constant rate of rise (slew rate) regardless of the selected word line group WG (hereinafter, referred to as the "selected word line group WG"). The example shown in FIG. 10 shows the state of the NAND string NS when the voltage of the unselected word line WL_u is voltage VA. The example shown in FIG. 11 shows the state of the NAND string NS when the voltage of the unselected word line WL_u is higher than voltage VG. In FIG. 10 and FIG. 11, the current I_WL when the word line group WG0 is selected is indicated by a thick solid line. The current I_WL when the word line group WG1 is selected is indicated by a thin solid line. The current I_WL when the word line group WG2 is selected is indicated by a thick dashed line.

[0091] 10 and 11, for example, during a program verify operation, the voltage of the unselected word lines WL_u rises from the voltage VSS to the voltage VREAD during a period from time tSS to tRD (setup time). For example, if the rate of increase in the voltage applied to the unselected word lines WL_u is constant regardless of the selected word line group WG, the peak value of the current I_WL flowing through the unselected word lines WL_u is maximum when the word line group WG0 is selected.

[0092] When the voltage of the unselected word line WL_u rises and becomes higher than the threshold voltage of the unselected memory cell transistor MC, the unselected memory cell transistor MC transitions from an off state to an on state. The timing at which the unselected memory cell transistor MC transitions to the on state differs depending on the threshold voltage (state) of the unselected memory cell transistor MC. When the unselected memory cell transistor MC is turned on and the channel of the memory cell transistor MC is in a conductive state with the source line SL or the bit line BL, charging of the parasitic capacitance between the gate and channel of the memory cell transistor MC is required when raising the voltage of the unselected word line WL_u. For this reason, the amount of current required to raise the voltage of the unselected word line WL_u increases. The more the timing at which the parasitic capacitance starts to be charged is synchronized in the multiple unselected memory cell transistors MC included in the selected string unit SU, the higher the peak value of the current I_WL increases.

[0093] For example, when the memory cell transistor MC7 of the word line group WG0 is selected, the unselected memory cell transistors MC0 to MC6 are all in the "Er" state. At time tA, when the voltage applied to the unselected word line WL_u reaches the voltage VA, the unselected memory cell transistors MC0 to MC6 are all turned on. Since the selected transistors ST1 and ST2 are on, the channels of the unselected memory cell transistors MC0 to MC6 are in a conductive state with the source line SL. Therefore, the unselected memory cell transistors MC0 to MC6 of the selected string unit SU are turned on at approximately the same timing (including a timing shift corresponding to the threshold voltage distribution). That is, the unselected memory cell transistors MC0 to MC6 start charging the parasitic capacitance at approximately the same timing.

[0094] When the word line group WG0 is selected, the charging of the parasitic capacitances of the unselected memory cell transistors MC0 to MC6 in the selected string unit SU starts at approximately the same timing, and therefore the peak value of the current I_WL becomes the largest compared to when the word line groups WG1 and WG2 are selected.

[0095] For example, when the memory cell transistor MC4 of the word line group WG1 is selected, the unselected memory cell transistors MC0 to MC3 are in the “Er” state. The unselected memory cell transistors MC5 to MC7 are in one of the “Er” to “G” states. For example, at time tA, the unselected memory cell transistors MC0 to MC3 are in the on state and in a conductive state with the source line SL. In contrast, the unselected memory cell transistors MC5 to MC7 maintain the off state when they are not in the “Er” state. In most of the NAND strings NS of the selected string unit SU, the unselected memory cell transistors MC5 to MC7 are in a floating state. The timing at which the unselected memory cell transistors MC5 to MC7 are in the on state is distributed depending on the state. Therefore, the timing at which the unselected memory cell transistors MC5 to MC7 are in a conductive state with the bit line BL is distributed. That is, the unselected memory cell transistors MC0 to MC3 start charging the parasitic capacitance at approximately the same timing. In contrast, the timing at which the unselected memory cell transistors MC5 to MC6 start charging the parasitic capacitance is distributed. As shown in FIG. 11, when the voltage of the unselected word line WL_u becomes higher than the voltage VG and the memory cell transistor MC in the "G" state is turned on, the unselected memory cell transistors MC5 to MC7 are turned on and are conductive with the source line SL.

[0096] For example, when the memory cell transistor MC0 of the word line group WG2 is selected, the unselected memory cell transistors MC1 to MC7 are in one of the "Er" to "G" states. For example, at time tA, the unselected memory cell transistors MC1 to MC7 maintain the off state if they are not in the "Er" state. In most of the NAND strings NS of the selected string unit SU, the unselected memory cell transistors MC1 to MC7 are in a floating state. The timing at which the unselected memory cell transistors MC1 to MC7 are turned on and connected to the bit line BL is distributed due to the difference in state. Therefore, the timing at which the unselected memory cell transistors MC1 to MC7 are made conductive to the bit line BL is distributed. That is, the timing at which the unselected memory cell transistors MC1 to MC7 start charging the parasitic capacitance is distributed. As shown in FIG. 11, when the voltage of the unselected word line WL_u becomes higher than the voltage VG and the memory cell transistor MC in the "G" state is turned on, the unselected memory cell transistors MC1 to MC7 are turned on and are conductive with the source line SL.

[0097] 1.3.5 Setup Conditions for Unselected Word Lines During Program Verify Operation Next, an example of the setup condition of the unselected word line WL_u during the program verify operation will be described with reference to Fig. 12 to Fig. 14. Fig. 12 is a diagram showing the voltage and current of the unselected word line WL_u during the period from time t5 to t6 described with reference to Fig. 9 when the word line group WG0 is selected. Fig. 13 is a diagram showing the voltage and current of the unselected word line WL_u during the period from time t5 to t6 described with reference to Fig. 9 when the word line group WG1 is selected. Fig. 14 is a diagram showing the voltage and current of the unselected word line WL_u during the period from time t5 to t6 described with reference to Fig. 9 when the word line group WG2 is selected.

[0098] In this embodiment, the setup conditions (boosting conditions) for raising the voltage of the unselected word lines WL_u to the voltage VREAD differ depending on the selected word line group WG. More specifically, different application conditions for the voltage VREAD are set for each selected word line group WG so that the setup time TS (the length of the period from time t5 to time t6 in FIG. 9) becomes shorter in the order of the word line groups WG0 to WG2.

[0099] 10 and 11, when the rate of rise R of the voltage VREAD is constant, the peak value Ipeak of the current I_WL when the word line group WG1 or WG2 is selected is smaller than the peak value Ipeak of the current I_WL when the word line group WG0 is selected. Therefore, in this embodiment, when the word line group WG1 or WG2 is selected, a step is added in which the rate of rise R of the voltage VREAD is increased until the peak value Ipeak of the current I_WL becomes approximately the same as the peak value Ipeak of the current I_WL when the word line group WG0 is selected, thereby shortening the setup time TS when the word line group WG1 or WG2 is selected.

[0100] First, the setup conditions for the voltage VREAD when the word line group WG0 is selected will be described.

[0101] 12, when the word line group WG0 is selected, the row decoder 18 raises the voltage of the unselected word lines WL_u to the voltage VREAD at a constant rate of increase R0 from time t5 to t6. The setup time (length of the period from time t5 to t6) at this time is set to TS0. For example, the setup time TS0 is set to a time at which the peak value Ipeak0 of the word line current I_WL does not exceed a preset upper limit value.

[0102] Next, the setup conditions for the voltage VREAD when the word line group WG1 is selected will be described.

[0103] As shown in FIG. 13, when the word line group WG1 is selected, the row decoder 18 raises the voltage of the non-selected word line WL to the voltage VREAD in two steps during the period from time t5 to t6. Note that the number of steps may be three or more.

[0104] First, as the first step, during the period from time t5 to t5g1, the row decoder 18 raises the voltage of the non-selected word line WL_u to the voltage V_wg1. For example, at time t5g1, the current I_WL reaches the peak value Ipeak1. The voltage V_wg1 is, for example, a voltage higher than the voltage VA and lower than the voltage VREAD. Let the voltage rise rate at this time be R1a. The rise rates R0 and R1a are in the relationship of R0 < R1a. For example, by changing the voltage rise rate from R0 to R1a, among the non-selected memory cell transistors MC storing random data (in any state from “Er” to “G”) during the period from time t5 to t5g1, the number of non-selected memory cell transistors MC that are turned on increases. That is, during the period from time t5 to t5g1, the number of non-selected memory cell transistors MC that are in conduction with the bit line BL increases. For this reason, the peak value Ipeak1 of the current I_WL increases. The voltage V_wg1 and the rise rate R1a are set such that, for example, the peak value Ipeak1 of the current I_WL is approximately equal to the peak value Ipeak0 of the current I_WL when the word line group WG0 is selected.

[0105] Next, as the second step, during the period from time t5g1 to t6, the row decoder 18 raises the voltage of the non-selected word line WL_u from the voltage V_wg1 to the voltage VREAD. Let the voltage rise rate at this time be R1b. For example, the rise rates R0 and R1b are in the relationship of R0 = R1b. Note that the rise rates R0 and R1b may be in the relationship of R0 > R1b or R0 < R1b.

[0106] The setup time (length of the period from time t5 to t6) when word line group WG1 is selected is defined as TS1. The setup times TS0 and TS1 have a relationship of TS0>TS1. That is, when word line group WG1 is selected, the setup time of voltage VREAD can be made shorter than when word line group WG0 is selected.

[0107] Next, the setup conditions for the voltage VREAD when the word line group WG2 is selected will be described.

[0108] 14, when the word line group WG2 is selected, the row decoder 18 raises the voltage of the unselected word lines WL to the voltage VREAD in two steps during the period from time t5 to time t6, as in the case where the word line group WG1 is selected. The number of steps may be three or more.

[0109] First, as a first step, in a period from time t5 to t5g2, the row decoder 18 raises the unselected word line WL_u to a voltage V_wg2. For example, at time t5g2, the current I_WL reaches a peak value Ipeak2. The length of the period from time t5 to t5g2 may be the same as or different from the length of the period from time t5 to t5g1. The voltage V_wg2 is, for example, a voltage higher than the voltage V_wg1 and lower than the voltage VREAD. The voltage V_wg2 is set so that the peak value Ipeak2 of the current I_WL is approximately equal to the peak value Ipeak0 of the current I_WL when the word line group WG0 is selected. For example, by setting the voltages V_wg1 and V_wg2 and the rise rates R1a and R2a so that the peak value Ipeak0 of the current I_WL when word line group WG0 is selected, the peak value Ipeak1 of the current I_WL when word line group WG1 is selected, and the peak value Ipeak2 of the current I_WL when word line group WG2 is selected are approximately equal, the semiconductor memory device 1 can reduce the variation in the peak value Ipeak of the current I_WL due to the selected word line WL.

[0110] Let the rate of increase of the voltage in the first step be R2a. The rates of increase R0, R1a, and R2a are in the relationship R0 < R1a < R2a. When the word line group WG2 is selected, random data is stored in all non - selected memory cell transistors MC. In the period from time t5 to t5g2, in order to increase the number of non - selected memory cell transistors MC that are in the on state and conductive with the bit line BL, the rate of increase R2a is made larger than the rate of increase R1a.

[0111] Next, as the second step, in the period from time t5g2 to t6, the row decoder 18 raises the voltage of the non - selected word line WL_u from the voltage V_wg2 to the voltage VREAD. Let the rate of increase of the voltage at this time be R2b. The rates of increase R0 and R2b are in the relationship R0 = R2b. Note that the rates of increase R0 and R2b may be in the relationship R0 > R2b or R0 < R2b.

[0112] Let the setup time (the length of the period from time t5 to t6) when the word line group WG2 is selected be TS2. The setup times TS0, TS1, and TS2 are in the relationship TS0 > TS1 > TS2. That is, when the word line group WG2 is selected, the setup time of the voltage VREAD can be made shorter than when the word line groups WG0 and WG1 are selected.

[0113] 1.4 Effects according to this embodiment In the configuration according to this embodiment, the semiconductor memory device 1 can group a plurality of word lines WL connected to one NAND string NS (block BLK). For example, the semiconductor memory device 1 can classify a plurality of word lines WL into a word line group WG0 to which the word line WL corresponding to the first word line address belongs, a word line group WG1 to which the word lines WL corresponding to other word line addresses not including the first word line address and the last word line address belong, and a word line group WG2 to which the word line WL corresponding to the last word line address belongs. During a program verify operation, the semiconductor memory device 1 can raise the voltage of the unselected word lines WL_u to the voltage VREAD under different setup conditions for each selected word line group WG. For example, when the word line group WG1 or WG2 is selected, the semiconductor memory device 1 can raise the voltage of the unselected word lines WL_u to the voltage VREAD in two steps. More specifically, the semiconductor memory device 1 can make the voltage rise rate R1a of the first step of the setup conditions when the word line group WG1 is selected larger than the rise rate R0 of the voltage setup conditions when the word line group WG0 is selected. As a result, the semiconductor memory device 1 can make the setup time TS1 of the voltage VREAD when the word line group WG1 is selected shorter than the setup time TS0 of the voltage VREAD when the word line group WG0 is selected. Furthermore, the semiconductor memory device 1 can make the voltage rise rate R2a of the first step when the word line group WG2 is selected greater than the rise rate R1a. As a result, the semiconductor memory device 1 can make the setup time TS2 of the voltage VREAD when the word line group WG2 is selected shorter than the setup time TS1. Therefore, the semiconductor memory device 1 can shorten the processing time of the write operation and improve the processing capacity.

[0114] Furthermore, with the configuration according to this embodiment, the semiconductor memory device 1 can suppress variations in the current I_WL for each word line group WG.

[0115] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a case will be described in which the setup conditions for the unselected word lines WL during the program verify operation are different from those in the first embodiment. The following will focus on the differences from the first embodiment.

[0116] 2.1 Setup Conditions for Unselected Word Lines During Program Verify Operation An example of the boost operation of the unselected word line WL_u during the program verify operation in this embodiment will be described with reference to Figs. 15 to 17. Fig. 15 is a diagram showing the voltage and current of the unselected word line WL_u during the period from time t5 to t6 described with reference to Fig. 9 when the word line group WG0 is selected. Fig. 16 is a diagram showing the voltage and current of the unselected word line WL_u during the period from time t5 to t6 described with reference to Fig. 9 when the word line group WG1 is selected. Fig. 17 is a diagram showing the voltage and current of the unselected word line WL_u during the period from time t5 to t6 described with reference to Fig. 9 when the word line group WG2 is selected.

[0117] In this embodiment, the setup time TS of the voltage VREAD is the same regardless of the selected word line group WG. The setup conditions of the voltage VREAD are set differently depending on the selected word line group WG.

[0118] In this embodiment, when the word line group WG0 is selected, a step is added in which the rate of increase R of the voltage VREAD is reduced, thereby reducing the peak value Ipeak of the current I_WL. Also, when the word line group WG2 is selected, a step is added in which the rate of increase R of the voltage VREAD is increased, thereby reducing the variation in the peak value Ipeak of the current I_WL for each word line group WG.

[0119] First, the setup conditions for the voltage VREAD when the word line group WG0 is selected will be described.

[0120] As shown in FIG. 15, when the word line group WG0 is selected, the row decoder 18 raises the voltage of the non-selected word line WL in two steps to the voltage VREAD during the period from time t5 to t6. Note that the number of steps may be three or more.

[0121] First, as the first step, during the period from time t5 to t5g0b, the row decoder 18 raises the voltage of the non-selected word line WL_u to the voltage V_wg0b. For example, at time t5g0b, the current I_WL becomes the peak value Ipeak0b. For example, the voltage V_wg0b is a voltage below the voltage VA. Let the voltage rise rate at this time be R0c. The rise rate R0c is lower than the case where the voltage of the non-selected word line WL_u rises to the voltage VREAD at a constant rise rate during the period from time t5 to t6. By reducing the rise rate, the peak value Ipeak0b of the current I_WL is reduced.

[0122] Next, as the second step, during the period from time t5g0b to t6, the row decoder 18 raises the voltage of the non-selected word line WL_u from the voltage V_wg0b to the voltage VREAD. Let the voltage rise rate at this time be R0d. The rise rates R0c and R0d are in the relationship of R0c < R0d. Also, the rise rate R0d is higher than the case where the voltage of the non-selected word line WL_u rises to the voltage VREAD at a constant rise rate during the period from time t5 to t6.

[0123] Next, the setup conditions for the voltage VREAD when the word line group WG2 is selected will be described.

[0124] 16, when the word line group WG1 is selected, the row decoder 18 increases the voltage of the unselected word lines WL_u to the voltage VREAD at a constant rate of increase R1 during the period from time t5 to time t6. For example, the rate of increase R1 is set so that the peak value Ipeak1b of the word line current I_WL does not exceed a preset upper limit value. The rate of increase R1 is greater than the rate of increase R0c and less than the rate of increase R0d. For example, the rate of increase R0c is set so that the peak value Ipeak0b and the peak value Ipeak1b are approximately equal to each other.

[0125] Next, the setup conditions for the voltage VREAD when the word line group WG2 is selected will be described.

[0126] 17, when the word line group WG2 is selected, the row decoder 18 raises the voltage of the unselected word lines WL to the voltage VREAD in two steps during the period from time t5 to time t6, as in the case where the word line group WG1 is selected. The number of steps may be three or more.

[0127] First, as a first step, in the period from time t5 to t5g2b, the row decoder 18 raises the unselected word line WL_u to a voltage V_wg2b. The length of the period from time t5 to t5g2b may be the same as or different from the length of the period from time t5 to t5g0b. The voltage V_wg2b is, for example, a voltage higher than the voltage V_wg0b and lower than the voltage VREAD. The rate of increase of the voltage at this time is R2c. The rate of increase R2c is, for example, greater than the rate of increase R1.

[0128] Next, as a second step, during the period from time t5g2b to t6, the row decoder 18 raises the voltage of the non-selected word line WL_u from the voltage V_wg2b to the voltage VREAD. Let the rate of voltage increase at this time be R2d. The rate of voltage increase R2d is smaller than the rate of voltage increase R2c in the first step. For example, the rate of voltage increase R2d is set so that the peak value Ipeak2b of the word line current I_WL does not exceed a preset upper limit value. For example, the rate of voltage increase R2d is set so that the peak value Ipeak2b and the peak value Ipeak1b are approximately equal. For example, the rate of voltage increase R2d and the rate of voltage increase R1 are in the relationship of R2d < R1.

[0129] 2.2 Effects according to this embodiment With the configuration according to this embodiment, the semiconductor memory device 1 can group a plurality of word lines WL connected to one NAND string NS (block BLK) in the same manner as in the first embodiment. Further, during the program verification operation, the semiconductor memory device 1 can raise the voltage of the non-selected word line WL_u to the voltage VREAD under different setup conditions for each selected word line group WG. For example, when the word line group WG0 is selected, the semiconductor memory device 1 can reduce the peak value Ipeak0b of the current I_WL by reducing the rate of voltage increase R0c in the first step of the setup conditions. Thereby, the peak value Ipeak of the current consumption in the semiconductor memory device 1 can be reduced. And when the word line group WG0 is selected, the semiconductor memory device 1 can make the rate of voltage increase R0d in the second step of the setup conditions larger than the rate of voltage increase R0c in the first step of the setup conditions. Thereby, the semiconductor memory device 1 can shorten the setup time TS.

[0130] Furthermore, with the configuration according to this embodiment, when the word line group WG2 is selected, the semiconductor memory device 1 can increase the peak value Ipeak2b of the current I_WL by increasing the rate of voltage increase R2c in the first step of the setup conditions. Thereby, the semiconductor memory device 1 can suppress the variation in the current I_WL for each word line group WG.

[0131] Furthermore, with the configuration according to this embodiment, when the word line group WG0 or WG2 is selected, the semiconductor memory device 1 can raise the voltage of the unselected word line WL_u to the voltage VREAD in two steps. This can suppress an increase in the setup time TS. Therefore, the semiconductor memory device 1 can suppress an increase in the processing time of the write operation.

[0132] 3. Modifications, etc. The semiconductor memory device according to the embodiment includes a memory string (NS) including a first selection transistor (ST1), a first memory cell (MC7), and a second memory cell (MC6) connected in series, a bit line (BL) connected to the first selection transistor, a first word line (WL7) connected to the first memory cell, a second word line (WL6) connected to the second memory cell, and a control circuit (14) configured to perform a write operation including a program operation and a program verify operation. When performing a program verify operation of the first memory cell, the control circuit increases the voltage of the second word line to a first voltage (VREAD) based on a first condition, and when performing a program verify operation of the second memory cell, the control circuit increases the voltage of the first word line to the first voltage based on a second condition different from the first condition.

[0133] The configuration according to the above embodiment can improve processing capacity.

[0134] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0135] For example, in the above embodiment, a case has been described in which the setup conditions for unselected word lines differ for each word line group WG in a program verify operation, but similar setup conditions may also be applied in a read operation.

[0136] Furthermore, in the above embodiments, "connection" also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0137] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0138] 1...semiconductor memory device, 2...memory controller, 10...input / output circuit, 11...logic control circuit, 12...address register, 13...command register, 14...sequencer, 15...ready / busy circuit, 16...voltage generation circuit, 17...memory cell array, 18...row decoder, 19...sense amplifier, 20...data register, 21...column decoder, 30...semiconductor substrate, 31...insulating layer, 32, 33, 41...wiring layer, 34...block insulating film, 35...charge storage layer, 36...tunnel insulating film, 37...semiconductor layer, 38...core layer, 39...cap layer, 40...contact plug

Claims

1. a memory string including a first select transistor, a first memory cell, and a second memory cell connected in series; a bit line connected to the first selection transistor; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a control circuit configured to perform write operations, including program operations and program verify operations; Equipped with the control circuit increases a voltage of the second word line to a first voltage based on a first condition when performing the program verify operation of the first memory cell, and increases a voltage of the first word line to the first voltage based on a second condition different from the first condition when performing the program verify operation of the second memory cell. Semiconductor memory device.

2. the control circuit executes the write operation of the second memory cell after the write operation of the first memory cell; 2. The semiconductor memory device according to claim 1.

3. A length of a first period during which the first condition is executed is longer than a length of a second period during which the second condition is executed.

2. The semiconductor memory device according to claim 1.

4. the second condition includes a first step that is executed first and a second step that is executed next to the first step, a first rate of increase of the first voltage in the first step is greater than a second rate of increase of the first voltage under the first condition; 4. The semiconductor memory device according to claim 3.

5. a third rate of increase of the first voltage in the second step is equal to the second rate of increase; 5. The semiconductor memory device according to claim 4.

6. the memory string further includes a third memory cell electrically connected to the second memory cell and a second selection transistor connected in series with the third memory cell; a source line connected to the second selection transistor; a third word line connected to the third memory cell; Further equipped with when executing the program verify operation of the third memory cell, the control circuit increases voltages of the first word line and the second word line to the first voltage based on a third condition different from the first condition and the second condition; 2. The semiconductor memory device according to claim 1.

7. the control circuit executes the write operation on the third memory cell after the write operation on the second memory cell; 7. The semiconductor memory device according to claim 6.

8. a third period during which the third condition is executed is shorter than a second period during which the second condition is executed; 7. The semiconductor memory device according to claim 6.

9. the second condition includes a first step that is executed first and a second step that is executed next to the first step, the third condition includes a third step that is executed first and a fourth step that is executed subsequent to the third step; a first rate of increase of the first voltage in the first step is smaller than a fourth rate of increase of the first voltage in the third step; 7. The semiconductor memory device according to claim 6.

10. a fifth rate of increase of the first voltage in the fourth step is equal to a second rate of increase of the first voltage under the first condition; 10. The semiconductor memory device according to claim 9.

11. a length of a first period during which the first condition is executed is equal to a length of a second period during which the second condition is executed; 2. The semiconductor memory device according to claim 1.

12. the first condition includes a first step that is executed first and a second step that is executed subsequent to the first step; a first rate of increase of the first voltage in the first step is smaller than a second rate of increase of the first voltage under the second condition; The semiconductor memory device according to claim 11.

13. a third rate of increase of the first voltage in the second step is greater than the second rate of increase; The semiconductor memory device according to claim 12.

14. a length of a first period during which the first condition is executed, a length of a second period during which the second condition is executed, and a length of a third period during which the third condition is executed are equal; 7. The semiconductor memory device according to claim 6.

15. the third condition includes a third step that is executed first and a fourth step that is executed subsequent to the third step; a fourth rate of increase of the first voltage in the third step is greater than a second rate of increase of the first voltage under the second condition; 7. The semiconductor memory device according to claim 6.

16. a fifth rate of increase of the first voltage in the fourth step is smaller than the second rate of increase; 16. The semiconductor memory device according to claim 15.

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