Semiconductor device and method for manufacturing the same

Abstract

To improve avalanche resistance without affecting element characteristics.SOLUTION: A semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a gate electrode provided in the second semiconductor region via a gate insulating film, a contact portion having a first portion and a second portion, and a second electrode electrically connected to the contact portion. The first portion is aligned with the third semiconductor region and a part of the second semiconductor region, and the second portion is provided at the lower end of the first portion and has a width larger than the width of the first portion at the upper end of the third semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In a circuit that includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a surge voltage is superimposed on the drain-source voltage when the MOSFET is turned off due to stray inductance within the circuit. As a result, the drain-source voltage may exceed the maximum rating of the semiconductor element, causing a breakdown. However, MOSFETs have a characteristic called avalanche resistance, which means that as long as the condition is below a certain level of energy, the element will not be destroyed even if the drain-source voltage exceeds the rated voltage. For this reason, ensuring sufficient avalanche resistance is important for improving the reliability of MOSFETs.

[0003] In order to improve the avalanche resistance, it is conceivable to increase the width of the trench contact. However, this would reduce the alignment margin for the trench contact, which could lead to misalignment of the trench contact. In that case, it would be difficult to ensure sufficient insulation between the gate and source electrodes, and the threshold voltage of the MOSFET would fluctuate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2023-1343 A [Patent Document 2] JP 2022-16286 A [Patent Document 3] Patent Publication No. 2022-16842 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can improve avalanche resistance without affecting element characteristics. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a gate electrode provided in the second semiconductor region via a gate insulating film, a contact portion having a first portion and a second portion, and a second electrode electrically connected to the contact portion. The first portion is aligned with the third semiconductor region and a part of the second semiconductor region, and the second portion is provided at a lower end of the first portion and has a width larger than a width of the first portion at an upper end of the third semiconductor region. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged view of the contact portion of FIG. 1. [Diagram 3] 5A to 5C are diagrams for explaining the shape of a tip portion of a contact portion according to the embodiment. [Figure 4] 5 is a flowchart showing a first example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5A] 1A to 1C are process cross-sectional views illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5B] 5B is a process cross-sectional view illustrating the first example of the method for manufacturing the semiconductor device according to the embodiment, following FIG. 5A. [Figure 5C] 5C are process cross-sectional views illustrating the first example of the method for manufacturing the semiconductor device according to the embodiment, following FIG. 5B. [Figure 5D]5D are process cross-sectional views illustrating the first example of the method for manufacturing the semiconductor device according to the embodiment, following FIG. 5C. [Figure 5E] 5D, which is a process cross-sectional view illustrating the first example of the method for manufacturing the semiconductor device according to the embodiment. [Figure 6] 5 is a flowchart showing a second example of the method for manufacturing a semiconductor device according to the embodiment. [Figure 7A] 5A to 5C are cross-sectional views illustrating steps in a second example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7B] 7B is a process cross-sectional view illustrating a second example of the method for manufacturing the semiconductor device according to the embodiment, following FIG. 7A. [Figure 7C] 7B, which is a process cross-sectional view illustrating the second example of the method for manufacturing the semiconductor device according to the embodiment. [Figure 7D] 7D are process cross-sectional views illustrating the second example of the method for manufacturing the semiconductor device according to the embodiment, following FIG. 7C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to the drawings. Note that the embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those already described are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] In the following description, n + , n, n - , and p + , p, p - The notation n may be used. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, -indicates that the p-type impurity concentration is relatively lower than that of p. + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The above-mentioned type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. In other words, the first conductivity type may be the p-type and the second conductivity type may be the n-type.

[0010] In the description of the embodiment, the direction from the drain electrode to the source electrode is referred to as “up,” and the opposite direction is referred to as “down.” These directions are based on the relative positional relationship between the drain electrode and the source electrode, and are unrelated to the direction of gravity.

[0011] The impurity concentration of the semiconductor region can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS), and the relative level of the impurity concentration can be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM).

[0012] Furthermore, dimensions such as the width of the contact portion can be measured by, for example, a Transmission Electron Microscope (TEM) or Energy Dispersive X-ray spectroscopy (EDX).

[0013] (Semiconductor Device) A semiconductor device 1 according to an embodiment will be described with reference to Figures 1 to 3. The semiconductor device 1 is configured as a vertical MOSFET.

[0014] The semiconductor device 1 includes a drain electrode 2, a source electrode 3, and a semiconductor layer 10 disposed between the drain electrode 2 and the source electrode 3.

[0015] The drain electrode 2 functions as a drain electrode of the MOSFET. The source electrode 3 functions as a source electrode of the MOSFET. The drain electrode 2 is disposed so as to be in contact with the lower surface of the semiconductor layer 10, and the source electrode 3 is disposed on the semiconductor layer 10 with an interlayer insulating film 6 interposed therebetween.

[0016] The drain electrode 2 and the source electrode 3 contain a metal such as tungsten, aluminum, titanium, etc. The drain electrode 2 is an example of a first electrode in the claims, and the source electrode 3 is an example of a second electrode in the claims.

[0017] In this embodiment, the source electrode 3 has a metal film 21 provided on the interlayer insulating film 6, a metal film 22 provided on the metal film 21, and a metal film 23 provided on the metal film 22. The metal film 21 is made of a silicide such as titanium silicide, the metal film 22 is made of titanium nitride or the like, and the metal film 23 is made of tungsten or the like. In this embodiment, the metal film 21 is provided so as to be in contact with the source region 14 and the base region 13 as well.

[0018] The semiconductor layer 10 is provided with a drain region 11, a drift region 12, a base region 13 and a source region 14.

[0019] The semiconductor layer 10 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 10 is silicon (Si). In this case, arsenic (As), phosphorus (P), antimony (Sb), or the like is used as an n-type impurity. Also, boron (B) or the like is used as a p-type impurity. The semiconductor layer 10 may be a silicon-based compound semiconductor such as silicon carbide (SiC).

[0020] The drain region 11 is a semiconductor region that functions as the drain of the MOSFET. The drain region 11 is provided on the drain electrode 2 and is electrically connected to the drain electrode 2. The drain region 11 is, for example, an n + The n-type impurity concentration is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 11 is an example of a first semiconductor region in the claims.

[0021] The drift region 12 is a semiconductor region that functions as a drift region of the MOSFET. The drift region 12 is provided on the drain region 11. The drift region 12 is, for example, an n - The n-type impurity concentration is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The drift region 12 is an example of a first semiconductor region in the claims. The first semiconductor region may include at least one of the drain region 11 and the drift region 12.

[0022] The base region 13 is a semiconductor region that functions as a base region of the MOSFET. The base region 13 is provided on the drift region 12. The base region 13 is adjacent to the gate electrode 4 via the gate insulating film 5. The base region 13 is, for example, a p-type semiconductor region, and the p-type impurity concentration thereof is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The base region 13 is an example of a second semiconductor region in the claims.

[0023] When a voltage is applied to the gate electrode 4, a channel is formed in the base region 13, and carriers (electrons in this embodiment) flow between the drain region 11 and the source region 14. The region where the channel is formed (channel region) is in the base region 13 near the interface between the base region 13 and the gate insulating film 5.

[0024] The source region 14 is a semiconductor region that functions as a source region of the MOSFET. The source region 14 is provided on the base region 13. The source region 14 is electrically connected to the source electrode 3 via the contact portion 7. The source region 14 is, for example, an n + The n-type impurity concentration is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The source region 14 is an example of a third semiconductor region in the claims.

[0025] The high concentration region 15 is a semiconductor region of the second conductivity type provided in the base region 13. The high concentration region 15 is provided so as to surround the lower end (tip portion 7b) of the contact portion 7. The high concentration region 15 is a region having a higher concentration of impurities of the second conductivity type than the base region 13, and may be, for example, p + The p-type impurity concentration of the high concentration region 15 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The high concentration region 15 is an example of a fourth semiconductor region in the claims.

[0026] The gate insulating film 5 is an insulating film provided so as to penetrate the base region 13 from the source region 14 to the drift region 12. A gate electrode 4 is provided inside the gate insulating film 5. This gate insulating film 5 is an insulating film embedded in a gate trench provided so as to penetrate the source region 14 and the base region 13 and to reach partway through the drift region 12. The gate insulating film 5 is made of an insulating material such as silicon oxide or silicon nitride, for example.

[0027] The gate electrode 4 functions as the gate electrode of the MOSFET. The gate electrode 4 is provided in the base region 13 via a gate insulating film 5. In this embodiment, as shown in Fig. 1, the gate electrode 4 is provided from the source region 14 to the drift region 12. The gate electrode 4 extends in a direction perpendicular to the paper surface of Fig. 1. The gate electrode 4 is made of, for example, conductive polysilicon or the like.

[0028] A field plate electrode (not shown) may be provided in the gate insulating film 5 and located below the gate electrode 4. The field plate electrode is electrically connected to the source electrode 3.

[0029] The interlayer insulating film 6 is provided between the source region 14 and the source electrode 3. The interlayer insulating film 6 is made of an insulating material such as silicon oxide or silicon nitride.

[0030] The contact portion 7 is electrically connected to the source electrode 3, and is provided so as to penetrate the interlayer insulating film 6 and the source region 14 and reach the base region 13. In this embodiment, the contact portion 7 extends in a direction perpendicular to the plane of FIG.

[0031] In detail, the contact portion 7 has a conductive through portion 7a, the upper end of which is connected to the source electrode 3, and a conductive tip portion 7b provided at the lower end of the through portion 7a. The through portion 7a is provided so as to penetrate the interlayer insulating film 6 and the source region 14 and reach the base region 13. The tip portion 7b is provided at the lower end (tip) of the through portion 7a located in the base region 13. The through portion 7a is an example of a first portion in the claims, and the tip portion 7b is an example of a second portion in the claims. In this embodiment, the tip portion 7b is integrally formed with the metal film 21.

[0032] Tip 7b has a shape that bulges toward gate electrode 4. More specifically, tip 7b has a width larger than the width of penetrating portion 7a at the upper end of source region 14 (the opening width of source region 14). That is, as shown in FIG 3, width L1 of tip 7b is larger than width L2 of penetrating portion 7a at the upper end of source region 14.

[0033] The width L1 of the tip portion 7b may be larger than the width of the penetrating portion 7a (the opening width of the interlayer insulating film 6) at the upper end of the interlayer insulating film 6. More generally, the width of the tip portion 7b may be larger than the width of the widest portion of the penetrating portion 7a.

[0034] 3, the thickness T2 in the horizontal direction (second direction) of the tip portion 7b may be greater than the thickness T1 in the vertical direction (first direction). Here, the first direction is the direction from the drain electrode 2 toward the source electrode 3, and the second direction is a direction perpendicular to the first direction. For example, the thickness T2 is defined as the length between the metal film 22 (barrier metal) and the end (left end or right end) of the tip portion 7b in the second direction. The thickness T1 is defined as the length between the metal film 22 and the end (lower end) of the tip portion 7b in the first direction.

[0035] The tip portion 7b includes a metal silicide. For example, at least a portion (a bulging portion) of the tip portion 7b facing the gate electrode 4 includes a metal silicide. Note that the tip portion 7b is not limited to a metal silicide, and may include a metal material such as titanium (Ti).

[0036] The tip portion 7b includes titanium silicide (TiSi). The tip portion 7b may include a silicide of a metal other than titanium. For example, the tip portion 7b may include a silicide of chromium (Cr), zirconium (Zr), molybdenum (Mo), tungsten (W), hafnium (Hf), or the like (i.e., chromium silicide, zirconium silicide, molybdenum silicide, tungsten silicide, hafnium silicide, or the like).

[0037] As described above, in the semiconductor device 1 of this embodiment, the contact portion 7 has the tip portion 7b that bulges toward the gate electrode 4, so that it is possible to shorten the distance between the bottom of the contact portion 7 and the channel region. This allows minority carriers (holes in this embodiment) to be efficiently extracted from the tip portion 7b when the MOSFET is turned off, thereby improving the avalanche resistance of the MOSFET.

[0038] Moreover, according to this embodiment, the distance between the bottom of the contact portion 7 and the channel region can be shortened without increasing the width of the contact portion 7 (the through portion 7a). Therefore, an alignment margin can be secured when forming the contact portion 7, so that sufficient insulation between the gate electrode 4 and the source electrode 3 can be secured and fluctuations in the threshold voltage of the MOSFET can be suppressed.

[0039] Therefore, according to this embodiment, it is possible to provide a semiconductor device capable of improving the avalanche resistance without affecting the element characteristics.

[0040] In the above description, the semiconductor device 1 is a vertical MOSFET, but the semiconductor device 1 may be another semiconductor device having a trench gate structure. For example, when the semiconductor device 1 is an insulated gate bipolar transistor (IGBT), the drain region 11 is p + Alternatively, a p-type collector region may be formed between the drain region 11 and the drain electrode 2. + A collector region of a different shape may be added. Other points are the same as those of the vertical MOSFET described in this embodiment. In this case, the source region 14 becomes the emitter region.

[0041] <Method of Manufacturing Semiconductor Device> A first example of a method for manufacturing the semiconductor device 1 will be described with reference to the flow chart of FIG. 4 and the process cross-sectional views of FIGS. 5A to 5E.

[0042] Step S11: As shown in FIG. 5A, a semiconductor layer 10 is prepared in which a gate electrode 4, a base region 13, and a source region 14 are formed and the upper surface of which is covered with an interlayer insulating film 6, and a contact trench T is formed by reactive ion etching (RIE) or the like. The trench T is formed so as to penetrate the interlayer insulating film 6 and the source region 14 and reach the base region 13. This step may be performed by two-stage etching. That is, the interlayer insulating film 6 made of silicon oxide or the like is removed, and then the source region 14 and the base region 13 made of silicon or the like are removed.

[0043] Step S12: As shown in FIG. 5B, oblique ion implantation is performed on the bottom of the trench T to form an amorphous region AR. In this embodiment, p-type impurities (boron, boron fluoride, aluminum, etc.) are ion-implanted obliquely with respect to the bottom surface of the trench T to form an amorphous region AR that spreads laterally from the bottom of the trench T. In this step, the impurity ions are implanted into the bottom of the trench T with as much of a lateral (horizontal surface) velocity component as possible, thereby forming an amorphous region AR that bulges toward the gate electrode 4. Note that although a high concentration region 15 is illustrated in FIG. 5B, strictly speaking, the ions implanted in this step become the high concentration region 15 by being activated by the heat treatment in step S14.

[0044] Step S13: As shown in FIG. 5C, a metal thin film is formed on the side and bottom of the trench T by sputtering or the like. In this embodiment, a metal film 21A made of titanium (Ti) is formed on the side and bottom of the trench T, and then a metal film 22 made of titanium nitride (TiN) is formed on the metal film 21A. The metal films 21A and 22 are also formed on the interlayer insulating film 6. Note that the formation of titanium nitride may be omitted.

[0045] Step S14: As shown in FIG. 5D, a heat treatment (annealing) is performed to form metal silicide in the amorphous region AR. The heat treatment is performed, for example, at a temperature of about 600° C. for about 30 seconds. This heat treatment converts the metal film 21A into a silicide, and a metal film 21 made of titanium silicide is formed. Furthermore, the conversion of silicon into titanium silicide progresses along the amorphous region AR, forming a tip portion 7b having a shape corresponding to the amorphous region AR.

[0046] Step S15: As shown in FIG. 5E, a metal material such as tungsten (W) is deposited inside the trench T by sputtering or the like. The metal material is also deposited on the metal film 22 on the interlayer insulating film 6, forming the metal film 23 that constitutes the source electrode 3. Note that the metal material in this step is not limited to tungsten, and may be, for example, aluminum or titanium.

[0047] Through the above steps, the semiconductor device 1 according to the embodiment can be manufactured.

[0048] The above steps are merely examples. For example, a heat treatment may be performed between steps S12 and S13 to electrically activate the impurities ion-implanted in step S12. The heat treatment in step S14 may be performed after step S15.

[0049] In the above process, the amorphous region AR is formed by ion implantation of a p-type impurity to form the high concentration region 15, but the width of the amorphous region AR may be increased by implanting an inert element such as argon before or after step S12. Also, instead of step S12, the amorphous region AR may be formed by implanting an inert element.

[0050] Next, a second example of a method for manufacturing the semiconductor device 1 will be described with reference to the flow chart of FIG. 6 and the process cross-sectional views of FIGS. 7A to 7D.

[0051] Step S21: A semiconductor layer 10 is prepared, and a contact trench T is formed on the upper surface of the semiconductor layer 10 by RIE or the like. This step is similar to the above-mentioned step S11, and therefore a detailed description thereof will be omitted.

[0052] Step S22: Oblique ion implantation is performed on the bottom of the trench T to form an amorphous region AR. This step is similar to the above-described step S12, and therefore a detailed description thereof will be omitted.

[0053] Step S23: As shown in FIG. 7A, a heat treatment is performed in an oxygen atmosphere to form an oxide film 31 in the amorphous region AR. Since an amorphous semiconductor layer is easily oxidized, an oxide film is formed along the amorphous region AR in this step. The oxygen atmosphere is, for example, a mixed gas of nitrogen and oxygen, and the oxygen ratio is 10% or more. The upper limit of the oxygen ratio is not particularly limited, but is, for example, about 50%.

[0054] Step S24: As shown in FIG. 7B, selective etching such as wet etching is performed to remove the oxide film 31, thereby forming a cavity C.

[0055] Step S25: As shown in FIG. 7C, a metal thin film is formed on the side surface of the trench T and inside the cavity C by sputtering or the like. In this embodiment, a metal film 21A made of titanium (Ti) is formed on the side surface of the trench T and inside the cavity C. Titanium is deposited in the cavity C to form the tip portion 7b. Thereafter, a metal film 22 made of titanium nitride (TiN) is formed on the metal film 21A. The metal films 21A and 22 are also formed on the interlayer insulating film 6. The formation of titanium nitride may be omitted.

[0056] Step S26: A heat treatment (annealing) is performed. As a result, as shown in Fig. 7D, the metal film 21A is silicided to become the metal film 21 made of titanium silicide. As for the titanium deposited in the cavity C, the titanium in the peripheral portion in contact with the semiconductor layer 10 becomes titanium silicide, but the titanium on the inside does not change.

[0057] Step S27: As shown in FIG. 7D, a metal material is deposited inside the trench T by sputtering or the like. In this embodiment, tungsten (W) is deposited inside the trench T. Note that the metal material in this step is not limited to tungsten, and may be, for example, aluminum or titanium.

[0058] Through the above steps, the semiconductor device 1 according to the embodiment can be manufactured. The metal film 21A formed in step S25 may be a metal film of a metal other than titanium, such as chromium (Cr), zirconium (Zr), molybdenum (Mo), tungsten (W), or hafnium (Hf). In this case, the metal film 21 formed in step S26 is chromium silicide, zirconium silicide, molybdenum silicide, tungsten silicide, or hafnium silicide.

[0059] For example, in step S22, the amorphous region AR may be formed by ion-implanting an inert element such as argon instead of the p-type impurity.

[0060] Although the embodiment of the present invention has been described, the embodiment and examples are presented as examples and are not intended to limit the scope of the invention. The embodiment and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and examples and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention. [Explanation of symbols]

[0061] 1 Semiconductor device 2 Drain electrode 3. Source Electrode 4. Gate electrode 5 Gate insulating film 6 Interlayer insulating film 7 Contact section 7a Penetration 7b Tip 10 Semiconductor layer 11 Drain region 12 Drift Region 13 Base Area 14 Source Area 15 High concentration area 21,21A,22,23 Metal film 31 Oxide film AR Amorphous region C Cavity L1,L2 width T-Trench T1, T2 thickness

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode provided in the second semiconductor region via a gate insulating film; a contact portion having a first portion aligned with the third semiconductor region and a part of the second semiconductor region, and a second portion provided at a lower end of the first portion and having a width larger than a width of the first portion at an upper end of the third semiconductor region; A second electrode electrically connected to the contact portion; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the second portion has a thickness in a second direction perpendicular to a first direction from the first electrode to the second electrode that is larger than a thickness in the first direction.

3. an interlayer insulating film provided between the third semiconductor region and the second electrode; the first portion is aligned with the interlayer insulating film, 2. The semiconductor device according to claim 1, wherein a width of said second portion is larger than a width of said first portion at an upper end of said interlayer insulating film.

4. 4. The semiconductor device according to claim 1, wherein said second portion of said contact portion includes a metal silicide.

5. 5. The semiconductor device according to claim 4, wherein the metal silicide is titanium silicide, chromium silicide, zirconium silicide, molybdenum silicide, tungsten silicide, or hafnium silicide.

6. 4. The semiconductor device according to claim 1, wherein said second portion of said contact portion includes a metallic material.

7. 7. The semiconductor device according to claim 6, wherein the metal material is titanium, chromium, zirconium, molybdenum, tungsten, or hafnium.

8. 2. The semiconductor device according to claim 1, further comprising a fourth semiconductor region provided to surround said second portion, said fourth semiconductor region having a higher impurity concentration of the second conductivity type than said second semiconductor region.

9. 2. The semiconductor device according to claim 1, wherein the first electrode is a drain electrode, the second electrode is a source electrode, the first semiconductor region is a drift region and a drain region, the second semiconductor region is a base region, and the third semiconductor region is a source region.

10. forming a contact trench passing through the source region of the first conductivity type and reaching the base region of the second conductivity type; Implanting impurities of a second conductivity type into the bottom of the trench in a direction oblique to the bottom surface of the trench to form an amorphous region extending laterally from the bottom of the trench; depositing a thin metal film on the side and bottom surfaces of the trench; forming a metal silicide in the amorphous region by performing a heat treatment; depositing a metallic material within the trench; A method for manufacturing a semiconductor device.

11. forming a contact trench passing through the source region of the first conductivity type and reaching the base region of the second conductivity type; Implanting impurities of a second conductivity type into the bottom of the trench in a direction oblique to the bottom surface of the trench to form an amorphous region extending laterally from the bottom of the trench; forming an oxide film in the amorphous region by performing a heat treatment in an oxygen atmosphere; removing the oxide film to form a cavity; depositing a thin metal film on the side of the trench and inside the cavity; Heat treatment is carried out, depositing a metallic material within the trench; A method for manufacturing a semiconductor device.

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