Semiconductor device

Abstract

To reduce a reverse recovery charge.SOLUTION: A semiconductor device according to the present embodiment includes: a semiconductor layer having first and second main surfaces; first and second main electrodes disposed on the first and second main surfaces, respectively; a first semiconductor region of a first conductivity type; a first insulating region reaching the first semiconductor region from the first main surface; a first conductive portion disposed in the first insulating region; a second insulating region adjacent to the first insulating region; a control electrode disposed in the second insulating region; a second semiconductor region of the first conductivity type, located between the first and second insulating regions; a second conductive portion that is located on the opposite side of the control electrode with the second semiconductor region sandwiched therebetween and that forms a Schottky junction with the second semiconductor region; a third semiconductor region of the second conductivity type, disposed on the first semiconductor region; a fourth semiconductor region of the first conductivity type, located between the third semiconductor region and the first main electrode; and a contact portion disposed in the third and fourth semiconductor regions.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used in inverters for driving motors, etc. In power MOSFETs, when the body diode (parasitic diode) built into the MOSFET switches from forward operation to reverse operation, a large loss (recovery loss) occurs due to residual minority carriers.

[0003] One method to suppress the recovery loss is to improve the characteristics of the body diode to reduce the amount of minority carriers injected into the drift region during forward operation, thereby reducing the reverse recovery charge. However, it is difficult to sufficiently reduce the reverse recovery charge using this method. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6003961 [Patent Document 2] JP 2016-225333 A [Patent Document 3] Patent No. 5449094 [Patent Document 4] JP 2019-71314 A [Patent Document 5] JP 2009-27152 A [Patent Document 6] JP 2019-161200 A Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PREFERRED EMBODIMENTS An embodiment of the present invention provides a semiconductor device capable of reducing reverse recovery [Means for solving the problem]

[0006] The semiconductor device according to this embodiment includes a semiconductor layer having a first main surface and a second main surface, a first main electrode provided on the first main surface, a second main electrode provided on the second main surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a first insulating region provided in the semiconductor layer and extending from the first main surface to the first semiconductor region, a first conductive portion provided in the first insulating region and electrically connected to the first main electrode, a second insulating region provided in the semiconductor layer, extending from the first main surface to the first semiconductor region and adjacent to the first insulating region, a control electrode provided in the second insulating region, and a second insulating region provided in the semiconductor layer and connecting the first insulating region and the second insulating region. the control electrode is provided with a second semiconductor region of a first conductivity type located between the edge regions; a second conductive portion located on the opposite side of the control electrode across the second semiconductor region, forming a Schottky junction with the second semiconductor region and electrically connected to the first main electrode; a third semiconductor region of a second conductivity type provided on the first semiconductor region in the semiconductor layer and located on the opposite side of the second semiconductor region across the second insulating region; a fourth semiconductor region of the first conductivity type provided in the semiconductor layer and located between the third semiconductor region and the first main electrode; and a contact portion provided in the third semiconductor region and the fourth semiconductor region and electrically connected to the first main electrode. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view of region A in FIG. [Diagram 3] 2 is an enlarged cross-sectional view of the periphery of a gate electrode in the semiconductor device 1 according to the first [Figure 4] 4 is a cross-sectional view for explaining the operation of the semiconductor device according to the first embodiment. FIG. [Figure 5A]2A to 2C are cross-sectional views illustrating an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 5B] 5B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, subsequent to FIG. 5A. [Figure 5C] 5B, a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 5D] 5D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, subsequent to FIG. 5C. [Figure 5E] 5D, a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 5F] 5F is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, subsequent to FIG. 5E. [Figure 6] FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor device according to a first modified example of the second embodiment. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to Modification 2 of the second embodiment. [Figure 9] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] For convenience of explanation, the source electrode side in the stacking direction (thickness direction) of the semiconductor device is also referred to as the "upper" and the drain electrode side is also referred to as the "lower." However, these expressions are for convenience and have no relation to the direction of gravity.

[0010] In the following description, n + , n, n - , and p + , p, p - In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The n-type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. In other words, the first conductivity type may be the p-type.

[0011] (First embodiment) <Semiconductor device> A semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1 to Fig. 3. Fig. 1 is a cross-sectional view of the semiconductor device 1 according to the first embodiment. Fig. 2 is an enlarged cross-sectional view of a region A in Fig. 1. Fig. 3 is an enlarged cross-sectional view of the periphery of a gate electrode 14 in the semiconductor device 1 according to the first embodiment.

[0012] The semiconductor device 1 according to this embodiment is configured to reduce the amount of minority carriers injected into the drift region during forward operation of the body diode, i.e., when a current flows from the source electrode to the drain electrode, and to reduce the reverse recovery charge Qrr, by incorporating a Schottky barrier diode in the vertical MOSFET. That is, the semiconductor device 1 includes a vertical MOSFET and a Schottky barrier diode. As will be described in detail later, the vertical MOSFET includes a source electrode 11, a drain electrode 12, a gate electrode 14, a drift region 21, a base region 23, a source region 26, and a drain region 27. The Schottky barrier diode includes a Schottky barrier metal 15 and an N-type region 22.

[0013] 1, the semiconductor device 1 includes a semiconductor layer 2, a source electrode 11 provided on an upper surface (first major surface) 2a of the semiconductor layer 2, and a drain electrode 12 provided on a lower surface (second major surface) 2b of the semiconductor layer 2. In the example described below, the upper surface 2a and the lower surface 2b of the semiconductor layer 2 are substantially flat, but this does not limit the shape of the semiconductor layer 2.

[0014] The semiconductor layer 2 is disposed on the drain electrode 12. The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity, and for example, boron (B) is used as the p-type impurity. The semiconductor layer 2 may be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0015] The source electrode 11 is an electrode that functions as a source electrode of the MOSFET. The source electrode 11 is electrically connected to a field plate (FP) electrode 13 and a contact portion 16. The source electrode 11 is also electrically connected to a Schottky barrier metal 15. The source electrode 11 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), or the like. The source electrode 11 is an example of a first main electrode in the claims.

[0016] The drain electrode 12 is an electrode that functions as a drain electrode of the MOSFET. The drain electrode 12 forms an ohmic junction with the drain region 27. The drain electrode 12 is made of a metal such as copper, titanium, tungsten, or aluminum. The drain electrode 12 is an example of a second main electrode in the claims.

[0017] Provided in the semiconductor layer 2 are an FP electrode 13, a gate electrode 14, a Schottky barrier metal 15, a contact portion 16, a drift region 21, an N-type region 22, a base region 23, a source region 26, a drain region 27, an FP insulating film 31, and a gate insulating film 32. An interlayer insulating film 33 is provided on an upper surface 2a of the semiconductor layer 2. Each component provided in the semiconductor layer 2 will be described below.

[0018] The FP electrode 13 is disposed in the FP insulating film 31. That is, the FP electrode 13 is disposed so as to be adjacent (opposite) the drift region 21 via the FP insulating film 31. The FP electrode 13 is electrically connected to the source electrode 11. The FP electrode 13 is provided to improve the breakdown voltage of the semiconductor device 1 by alleviating the concentration of the reverse electric field between the gate electrode 14 and the drain electrode 12 (FP effect). In this embodiment, in order to further improve the breakdown voltage, the upper part of the FP electrode 13 is wider than the lower part of the FP electrode 13 so that the distance between the FP electrode 13 and the base region 23 is shortened. The shape of the FP electrode 13 is not limited to those shown in FIG. 1 and FIG. 2, and is arbitrary. The FP electrode 13 is made of, for example, polysilicon. The FP electrode 13 may contain p-type or n-type impurities. The FP electrode 13 is an example of a first conductive part in the claims.

[0019] In this embodiment, the upper end of the FP electrode 13 is located lower than the lower end of the N-type region 22, as shown in FIG.

[0020] The gate electrode 14 is an electrode that functions as the gate electrode of the MOSFET. The gate electrode 14 is disposed in the gate insulating film 32. The upper end of the gate electrode 14 is located, for example, higher than the upper end of the base region 23, and the lower end of the gate electrode 14 is located, for example, lower than the lower end of the base region 23. The gate electrode 14 is disposed adjacent to (facing) the base region 23 via the gate insulating film 32. The gate electrode 14 is made of, for example, polysilicon. The gate electrode 14 is an example of a control electrode in the claims.

[0021] The gate electrode 14 may contain p-type or n-type impurities. When the gate electrode 14 contains p-type impurities, the operation of the MOSFET included in the semiconductor device 1 can be stabilized. When the gate electrode 14 contains n-type impurities, the operation of the Schottky barrier diode included in the semiconductor device 1 can be stabilized.

[0022] The Schottky barrier metal 15 is an electrode that functions as an anode electrode of a Schottky barrier diode. The Schottky barrier metal 15 contains a metal such as platinum (Pt), cobalt (Co) or nickel (Ni), and forms a Schottky junction with the N-type region 22. The Schottky barrier metal 15 is electrically connected to the source electrode 11. In this embodiment, the Schottky barrier metal 15 and the source electrode 11 are electrically connected in the depth direction of the paper in FIG. 1 and FIG. 2. Note that the Schottky barrier metal 15 may be directly connected to the source electrode 11 in the element region through which a current flows as shown in FIG. 2. The Schottky barrier metal 15 is an example of a second conductive portion in the claims.

[0023] The Schottky barrier metal 15 is located on the opposite side of the gate electrode 14 with the N-type region 22 interposed therebetween. In this embodiment, the Schottky barrier metal 15 is provided in the FP insulating film 31 and contacts the N-type region 22. As shown in Fig. 2, the upper end of the Schottky barrier metal 15 reaches the upper surface 2a of the semiconductor layer 2, and the lower end of the Schottky barrier metal 15 is at a height between the upper end and the lower end of the N-type region 22. The Schottky barrier metal 15 may extend to the lower end of the N-type region 22 or below it.

[0024] The Schottky barrier metal 15 may be provided in the N-type region 22 so as to be in contact with the FP insulating film 31, or may be provided so as to straddle the boundary between the FP insulating film 31 and the N-type region 22.

[0025] Furthermore, when the Schottky barrier metal 15 contains platinum, the Schottky barrier metal 15 may be formed by sputtering, and then heat treatment may be performed to diffuse platinum atoms into the drift region 21. Since platinum acts as a lifetime killer that quickly captures carriers, the reverse recovery charge Qrr of the semiconductor device 1 can be further reduced.

[0026] The contact portion 16 is electrically connected to the source electrode 11, and functions as a source electrode of the MOSFET together with the source electrode 11. As shown in FIG. 2, the contact portion 16 is provided in the base region 23 and the source region 26, and forms an ohmic junction with the base region 23 and the source region 26. The contact portion 16 is made of, for example, copper, titanium, tungsten, aluminum, or the like. In order to reduce the resistance with the contact portion 16, a semiconductor region (not shown) having a higher impurity concentration of the second conductivity type than the base region 23 may be provided to surround the tip of the contact portion 16.

[0027] The drift region 21 is a semiconductor region that functions as a drift region of the MOSFET. The drift region 21 is disposed above the drain region 27 (above the drain electrode 12). The drift region 21 is, for example, an n - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The drift region 21 is an example of a first semiconductor region in the claims.

[0028] The N-type region 22 is a semiconductor region that constitutes a Schottky barrier diode. As shown in Fig. 2, the N-type region 22 is disposed on the drift region 21 in the up-down direction. In addition, the N-type region 22 is disposed between the FP insulating film 31 and the gate insulating film 32 in the left-right direction, and is in contact with the FP insulating film 31 and the gate insulating film 32. The n-type impurity concentration of the N-type region 22 is, for example, equal to or lower than the n-type impurity concentration of the drift region 21, and is 1 × 10 13 cm -3 More than 1×10 15 cm -3 The n-type impurity concentration of the N-type region 22 may be higher than the n-type impurity concentration of the drift region 21, so long as a Schottky junction is formed between the Schottky barrier metal 15 and the N-type region 22. The N-type region 22 is an example of a second semiconductor region in the claims.

[0029] The base region 23 is a semiconductor region that functions as a base region of the MOSFET. In the up-down direction, the base region 23 is disposed on the drift region 21. In the left-right direction, the base region 23 is located on the opposite side of the N-type region 22 with the gate electrode 14 and the gate insulating film 32 interposed therebetween. When a voltage is applied to the gate electrode 14, a channel is formed in the base region 23, and carriers flow between the drift region 21 and the source region 26. The base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the base region 23 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The base region 23 is an example of a third semiconductor region in the claims.

[0030] As shown in FIG. 2, in this embodiment, the width W1 of the N-type region 22 is narrower than the width W2 of the base region 23. More specifically, the semiconductor device 1 further includes a second gate electrode 14A that is provided in the semiconductor layer 2 and is located on the opposite side of the gate electrode 14 with the contact portion 16 interposed therebetween, and the width W1 of the N-type region 22 is narrower than the width W2 of the base region 23 between the gate electrode 14 and the second gate electrode 14A. This can improve the breakdown voltage of the semiconductor device 1. The second gate electrode 14A is an example of a second control electrode in the claims. Since the gate electrode 14 and the second gate electrode 14A are functionally the same, they are both referred to as the gate electrode 14 in the following description.

[0031] The source region 26 is a semiconductor region that functions as a source region of the MOSFET. In the vertical direction, the source region 26 is disposed between the base region 23 and the source electrode 11. In the horizontal direction, the source region 26 is disposed between the gate insulating film 32 and the contact portion 16, and is in contact with the contact portion 16. The source region 26 is, for example, an n + The source region 26 has an n-type impurity concentration of, for example, 1×10 18 cm -3 More than 1×10 22 cm-3 The source region 26 is an example of a fourth semiconductor region in the claims.

[0032] The drain region 27 is a semiconductor region that functions as a drain region of the MOSFET. As shown in FIG. 1, the drain region 27 is disposed on the drain electrode 12. The drain region 27 is disposed between the drain electrode 12 and the drift region 21. The drain region 27 is, for example, an n + The n-type impurity concentration of the drain region 27 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 27 is an example of a first semiconductor region in the claims.

[0033] It should be noted that the first semiconductor region in the claims may include both the drift region 21 and the drain region 27, or may include at least one of the drift region 21 and the drain region 27.

[0034] The FP insulating film 31 is an insulating film for electrically insulating the FP electrode 13 from the semiconductor layer 2. The FP insulating film 31 is provided so as to reach the drift region 21 from the upper surface 2a of the semiconductor layer 2. The FP insulating film 31 is made of an insulating material filled in a field plate trench provided so as to reach the drift region 21 from the upper surface 2a. As shown in FIG. 1 and FIG. 2, the FP insulating film 31 provided so as to fill the field plate trench is in contact with the drift region 21 and the N-type region 22. In this embodiment, the field plate trench is provided on the upper surface 2a of the semiconductor layer 2, but this does not limit the shape of the semiconductor layer 2. The FP insulating film 31 is made of an insulating material such as silicon oxide or silicon nitride. The FP insulating film 31 is an example of a first insulating region in the claims.

[0035] The gate insulating film 32 is an insulating film for electrically insulating the gate electrode 14 from the semiconductor layer 2. The gate insulating film 32 is provided so as to extend from the upper surface 2a of the semiconductor layer 2 to the drift region 21 and to be adjacent to the FP insulating film 31. The gate insulating film 32 is made of an insulating material that fills the gate trench. The gate trench is a trench different from the above-mentioned field plate trench and is provided shallower than the field plate trench. In this embodiment, the gate trench is provided on the upper surface 2a of the semiconductor layer 2, but this does not limit the shape of the semiconductor layer 2.

[0036] The drift region 21, the N-type region 22, the base region 23, and the source region 26 are arranged around the gate insulating film 32. The gate insulating film 32 is made of an insulating material such as silicon oxide or silicon nitride. The gate insulating film 32 is an example of a second insulating region in the claims.

[0037] As shown in FIG. 3, the thickness T1 of the gate insulating film 32 on the N-type region 22 side is thicker than the thickness T2 on the base region 23 side. In this way, the thickness T1 on the N-type region 22 side can be increased without changing the width of the gate electrode 14 or the width of the gate trench, and the breakdown voltage of the Schottky barrier diode included in the semiconductor device 1 can be improved. In detail, even if the gate electrode 14 contains n-type impurities, a sufficient breakdown voltage can be ensured by a depletion layer extending from the Schottky barrier metal 15 by making the thickness T1 thicker than the thickness T2. Note that, when the gate electrode 14 contains p-type impurities, the breakdown voltage can be improved by a depletion layer extending from the gate electrode 14 by making the thickness T2 thicker than the thickness T1. The relationship between the thicknesses T1 and T2 of the gate insulating film 32 is not limited to the above. For example, the thickness T1 may be adjusted in consideration of the breakdown voltage and dielectric strength of the semiconductor device 1, and the thickness T2 may be adjusted in consideration of the gate threshold voltage Vth and dielectric strength of the semiconductor device 1.

[0038] The interlayer insulating film 33 is an insulating film for electrically insulating the source electrode 11 from the N-type region 22. In the example shown in FIG. 2, the interlayer insulating film 33 covers the upper surface 2a of the semiconductor layer 2 except for the upper surface of the contact portion 16. By providing the interlayer insulating film 33, the formation of an ohmic junction between the source electrode 11 and the N-type region 22 is suppressed, and the effect of the Schottky junction is prevented from being reduced. Note that the interlayer insulating film 33 may not cover the Schottky barrier metal 15, and the Schottky barrier metal 15 and the source electrode 11 may be in contact with each other.

[0039] <Operation of Semiconductor Device> Next, the operation of the semiconductor device 1 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view for explaining the operation of the semiconductor device 1 according to the first embodiment.

[0040] 4 shows the flow of current in the semiconductor device 1 when the current flows from the source electrode 11 to the drain electrode 12 of the semiconductor device 1. This current flows when a positive potential is applied to the source electrode 11 with respect to the drain electrode 12 during, for example, a switching operation of the semiconductor device 1.

[0041] 4, the semiconductor device 1 of the present embodiment includes a PIN diode as a body diode, which is configured by a base region 23, a drift region 21, and a drain region 27, and further includes a Schottky barrier diode configured by a Schottky barrier metal 15 and an N-type region 22. Therefore, as shown in FIG. 4, the current flowing from the source electrode 11 to the drain electrode 12 flows through the semiconductor device 1 while being divided into a current passing through the body diode (solid line) and a current passing through the Schottky barrier diode (dotted line).

[0042] In detail, when the current flowing from the source electrode 11 to the drain electrode 12 is small, or when the state in which the current flows from the source electrode 11 to the drain electrode 12 ends in a short time, the current mainly flows through the Schottky barrier diode shown by the dotted line in FIG. 4 in the semiconductor device 1. This is because the forward rise voltage of the Schottky barrier diode is smaller than the forward rise voltage of the body diode. Since minority carriers are not accumulated in the Schottky barrier diode, the amount of minority carriers injected into the drift region 21 can be reduced compared to a semiconductor device not provided with a Schottky barrier diode. As a result, the reverse recovery charge Qrr of the semiconductor device 1 can be reduced.

[0043] On the other hand, when the current flowing from the source electrode 11 to the drain electrode 12 is large, in addition to the current flowing through the Schottky barrier diode shown by the dotted line in Fig. 4, a current flows through the body diode shown by the solid line in Fig. 4. However, even in this case, a part of the current flowing in the semiconductor device 1 flows as a current through the Schottky barrier diode, so that the current through the body diode can be reduced. Therefore, compared to a semiconductor device not provided with a Schottky barrier diode, the amount of minority carriers injected into the drift region 21 can be reduced, and the reverse recovery charge Qrr of the semiconductor device 1 can be reduced.

[0044] In this way, according to the semiconductor device 1 of this embodiment, the amount of minority carriers injected into the drift region 21 when a current flows from the source electrode 11 to the drain electrode 12 can be reduced, and the reverse recovery charge Qrr can be reduced.

[0045] <Method of Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to Figures 5A to 5F. Figures 5A to 5F are cross-sectional views illustrating the steps of the method for manufacturing the semiconductor device 1.

[0046] First, as shown in Fig. 5A, a semiconductor layer 2 having a drift region 21 is prepared. The semiconductor layer 2 has an upper surface 2a.

[0047] 5B, a field plate trench FT and a gate trench GT are formed in the upper surface 2a by reactive ion etching (RIE) etc. The field plate trench FT is formed deeper than the gate trench GT.

[0048] Next, as shown in FIG. 5C, an insulating material is deposited in the field plate trench FT and the gate trench GT by chemical vapor deposition (CVD) or the like to form the FP insulating film 31 and the gate insulating film 32. The insulating material is, for example, silicon oxide or silicon nitride. Next, a part of the FP insulating film 31 and the gate insulating film 32 is removed by RIE or the like. At this time, the upper part of the FP insulating film 31 is removed so as to spread. Next, the FP electrode 13 and the gate electrode 14 are formed in the part where the FP insulating film 31 and the gate insulating film 32 have been removed. The FP electrode 13 and the gate electrode 14 are formed by depositing a conductive material such as polysilicon by CVD or the like, and then etching back the excess conductive material. Next, an insulating material is deposited by CVD or the like so as to bury the FP electrode 13 and the gate electrode 14.

[0049] 5D, impurity ions of the second conductivity type are implanted into a surface of the upper surface 2a between the FP insulating film 31 and the gate insulating film 32 to form an N-type region 22. If the impurity concentration of the N-type region 22 is the same as that of the drift region 21, this step is omitted.

[0050] Thereafter, impurity ions of the second conductivity type are implanted into the surface of the upper surface 2a on which the N-type region 22, the FP insulating film 31, and the gate insulating film 32 are not provided, thereby forming the base region 23. Thereafter, impurity ions of the first conductivity type are implanted into the base region 23 to form the source region 26. It is noted that the formation of the N-type region 22 and the formation of the base region 23 may be performed in any order. Furthermore, when the source region 26 is formed, impurity ions of the first conductivity type are also implanted into the N-type region 22, thereby forming the n-type region located above the N-type region 22. + Shape of semiconductor region (N + This N + The n-type impurity concentration in the doped region is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0051] Next, as shown in FIG. 5E, the FP insulating film 31, the base region 23, and a portion of the source region 26 are removed by RIE or the like. Thereafter, a first metal material is deposited by physical vapor deposition (PVD) or the like so as to fill the removed portion of the FP insulating film 31, thereby forming a Schottky barrier metal 15. The first metal material includes, for example, platinum, cobalt, nickel, or the like. In addition, a second metal material is deposited by PVD or the like so as to fill the removed portion of the base region 23 and the source region 26, thereby forming a contact portion 16. The second metal material includes, for example, copper, titanium, tungsten, aluminum, or the like.

[0052] The formation of the Schottky barrier metal 15 and the formation of the contact portion 16 may be performed in any order.

[0053] Furthermore, when the Schottky barrier metal 15 contains platinum, a heat treatment may be performed after the formation of the Schottky barrier metal 15. By performing the heat treatment, platinum atoms can be diffused and act as a lifetime killer that quickly captures carriers.

[0054] 5F, an interlayer insulating film 33 is provided so as to cover at least the upper surface of the N-type region 22 of the upper surface 2a of the semiconductor layer 2. In this embodiment, the interlayer insulating film 33 is provided so as to cover the entire surface except for the upper surface of the contact portion 16. The interlayer insulating film 33 is made of an insulating material such as silicon oxide or silicon nitride.

[0055] Next, as shown in FIG. 5F, the source electrode 11 is formed on the upper surface 2a of the semiconductor layer 2 so as to bury the interlayer insulating film 33 therein.

[0056] Next, although not shown, impurity ions of the first conductivity type are implanted into the lower surface 2b of the semiconductor layer 2 to form a drain region 27. Next, a drain electrode 12 is formed so as to cover the lower surface 2b of the semiconductor layer 2. Note that the drain region 27 and the drain electrode 12 may be formed before the field plate trench FT and the gate trench GT are formed.

[0057] Through the above steps, the semiconductor device 1 is manufactured.

[0058] As described above, the semiconductor device 1 according to the first embodiment includes the N-type region 22 provided in the semiconductor layer 2 and located between the FP insulating film 31 and the gate insulating film 32, and the Schottky barrier metal 15 located on the opposite side of the gate electrode 14 across the N-type region 22, forming a Schottky junction with the N-type region 22, and electrically connected to the source electrode 11. As a result, when a current flows from the source electrode 11 to the drain electrode 12 of the semiconductor device 1, the current flows through a Schottky barrier diode formed by the Schottky barrier metal 15 and the N-type region 22. As a result, the amount of minority carriers injected into the drift region 21 when a current flows from the source electrode 11 to the drain electrode 12 can be reduced, and the reverse recovery charge Qrr can be reduced.

[0059] Second embodiment A semiconductor device 1A according to the second embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of the semiconductor device 1A according to the second embodiment. One of the differences between the semiconductor device 1A according to this embodiment and the semiconductor device 1 according to the first embodiment described above is the position of the upper end of the FP electrode 13. The following describes the semiconductor device 1A according to this embodiment, focusing on the differences from the first embodiment.

[0060] 6, the upper end of the FP electrode 13 in the semiconductor device 1A according to this embodiment is at approximately the same height as the upper surface 2a of the semiconductor layer 2. In addition, the FP electrode 13 is in contact with the Schottky barrier metal 15. That is, the FP electrode 13 is in direct contact with the Schottky barrier metal 15 without an FP insulating film 31 therebetween.

[0061] In this way, in the second embodiment, the upper end of the FP electrode 13 is set to be at approximately the same height as the upper surface 2a of the semiconductor layer 2. As a result, in reverse operation of the body diode, the depletion layer spreads more easily around the N-type region 22 than in the semiconductor device 1 according to the first embodiment, and the breakdown voltage of the Schottky barrier diode included in the semiconductor device 1A can be improved.

[0062] In addition, since the FP effect is sufficient even when the FP electrode 13 and the base region 23 are located farther apart, the width of the N-type region 22 (width W1 in FIG. 2) can be made wider. As a result, the ratio of the Schottky barrier diode to the body diode in the semiconductor device 1A can be made larger. This makes it possible to increase the ratio of the current flowing to the Schottky barrier diode side when the current flows from the source electrode 11 to the drain electrode 12, and to further reduce the reverse recovery charge Qrr of the semiconductor device 1A.

[0063] Furthermore, when manufacturing the semiconductor device 1A, the process of burying the FP insulating film 31 after forming the FP electrode 13 is not required, so that the manufacturing process of the semiconductor device can be simplified.

[0064] The upper end of the gate electrode 14 may also be at approximately the same height as the upper surface 2a. In this case, the step of forming an insulating film on the gate electrode 14 can be omitted, and the manufacturing process of the semiconductor device 1 can be further simplified.

[0065] (Modification 1 of the second embodiment) A semiconductor device 1B according to a first modification of the second embodiment will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view of the semiconductor device 1B according to the first modification of the second embodiment.

[0066] 7, the upper end of the FP electrode 13 in the semiconductor device 1B according to the modification is located higher than the lower end of the Schottky barrier metal 15, but lower than the upper surface 2a of the semiconductor layer 2. As a result, as in the second embodiment described above, the depletion layer spreads more easily than in the semiconductor device 1 according to the first embodiment, and the breakdown voltage of the Schottky barrier diode included in the semiconductor device 1B can be improved.

[0067] In addition, since the FP effect is effective even when the FP electrode 13 and the base region 23 are located farther apart, the width of the N-type region 22 (width W1 in FIG. 2) can be made wider. As a result, the ratio of the Schottky barrier diode to the body diode in the semiconductor device 1B can be made larger. This makes it possible to increase the ratio of the current flowing to the Schottky barrier diode side when the current flows from the source electrode 11 to the drain electrode 12, and to further reduce the reverse recovery charge Qrr of the semiconductor device 1B.

[0068] Furthermore, in the semiconductor device 1B according to this embodiment, the FP electrode 13 is in contact with the Schottky barrier metal 15. This makes it possible to omit separate wiring for connecting the FP electrode 13 and the source electrode 11, for example.

[0069] (Modification 2 of the second embodiment) A semiconductor device 1C according to a first modification of the second embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view of the semiconductor device 1C according to the first modification of the second embodiment.

[0070] 8, the upper end of FP electrode 13 in semiconductor device 1C according to this modification is located higher than the lower end of N-type region 22. In addition, FP electrode 13 is not in contact with Schottky barrier metal 15.

[0071] Since the upper end of the FP electrode 13 is located higher than the lower end of the N-type region 22, as in the second embodiment described above, the depletion layer spreads more easily than in the semiconductor device 1 according to the first embodiment, and the breakdown voltage of the Schottky barrier diode provided in the semiconductor device 1C can be improved.

[0072] In addition, since the FP effect is effective even when the FP electrode 13 and the base region 23 are located farther apart, the width of the N-type region 22 (width W1 in FIG. 2) can be made wider. As a result, the ratio of the Schottky barrier diode to the body diode in the semiconductor device 1C can be made larger. This makes it possible to increase the ratio of the current flowing to the Schottky barrier diode side when the current flows from the source electrode 11 to the drain electrode 12, and to further reduce the reverse recovery charge Qrr of the semiconductor device 1C.

[0073] (Third embodiment) A semiconductor device 1D according to a third embodiment will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of the semiconductor device 1D according to the third embodiment. The following describes the semiconductor device 1D according to this embodiment, focusing on the differences from the second embodiment.

[0074] As shown in FIG. 9, the FP electrode 13 in the semiconductor device 1 according to this embodiment has, in its upper wide portion, a protruding portion 13a that protrudes to the side surface of the FP insulating film 31, that is, to the inner wall of the field plate trench.

[0075] In addition, the lower end of the Schottky barrier metal 15 is located lower than the lower end of the N-type region 22. This is to prevent the overhanging portion 13a from contacting the N-type region 22 and to prevent a decrease in the effect of the Schottky junction. However, without being limited to this, the lower end of the Schottky barrier metal 15 may be located higher than the lower end of the N-type region 22 and an insulating film may be provided between the lower end of the Schottky barrier metal 15 and the upper end of the overhanging portion 13a to prevent the overhanging portion 13a from contacting the N-type region 22.

[0076] The semiconductor device 1D further includes a P-type region 24, which is a p-type semiconductor region provided between the overhanging portion 13a and the drift region 21 in the semiconductor layer 2. The P-type region 24 is provided so as to cover the overhanging portion 13a exposed from the FP insulating film 31, and is in contact with the overhanging portion 13a and the N-type region 22. In this embodiment, the P-type region 24 is in contact with the overhanging portion 13a at its side and in contact with the N-type region 22 at its top. The top surface of the P-type region 24 does not have to be in contact with the N-type region 22. The P-type region 24 is narrower than the N-type region 22, and the drift region 21 exists between the P-type region 24 and the gate insulating film 32. The P-type region 24 is an example of a fifth semiconductor region in the claims.

[0077] 9, the width of the N-type region 22 according to this embodiment may be formed wider than the width of the N-type region 22 according to the first embodiment by approximately the width of the P-type region 24. This makes it possible to further reduce the reverse recovery charge Qrr of the semiconductor device 1D, as described later.

[0078] The p-type impurity concentration of the P-type region 24 may be the same as or different from the p-type impurity concentration of the base region 23. The p-type impurity concentration of the P-type region 24 is, for example, 1×10 17 cm -3 More than 1×10 22 cm -3 The following is the result.

[0079] P-type region 24 can be formed, for example, by implanting impurity ions of the second conductivity type into the side surface of field plate trench FT after the step of forming field plate trench FT described with reference to FIG. 5B.

[0080] In this way, in the third embodiment, by providing the protruding portion 13a electrically connected to the source electrode 11 and the P-type region 24 in contact with the protruding portion 13a, a depletion layer also extends from the P-type region 24 during reverse operation of the body diode. This makes it possible to greatly improve the breakdown voltage of the Schottky barrier diode included in the semiconductor device 1D.

[0081] Furthermore, since a sufficient breakdown voltage can be ensured as described above, the width of the N-type region 22 (width W1 in FIG. 2) can be further increased. As a result, the ratio of the Schottky barrier diode to the body diode in the semiconductor device 1D can be further increased. This allows the ratio of the current flowing to the Schottky barrier diode side when the current flows from the source electrode 11 to the drain electrode 12 to be further increased, and the reverse recovery charge Qrr of the semiconductor device 1D can be further reduced.

[0082] 9, the upper end of the FP electrode 13 is approximately at the same height as the upper surface 2a of the semiconductor layer 2 as in the second embodiment, but the position of the upper end of the FP electrode 13 is arbitrary. For example, the position of the upper end of the FP electrode 13 may be lower than the lower end of the Schottky barrier metal 15 as in the first embodiment and the second modification of the second embodiment, or may be higher than the lower end of the Schottky barrier metal 15 and lower than the upper surface 2a of the semiconductor layer 2 as in the first modification of the second embodiment.

[0083] Although the embodiment of the present invention has been described, the embodiment and examples are presented as examples and are not intended to limit the scope of the invention. The embodiment and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and examples and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention. [Explanation of symbols]

[0084] 1 Semiconductor device 11 Source electrode 12 Drain electrode 13 FP electrode 14 Gate electrode 15 Schottky Barrier Metal 16 Contact section 2. Semiconductor layer 21 Drift Region 22 N-type area 23 Base Area 24 P type area 26 Source Area 27 Drain Region 31 FP insulating film 32 Gate insulating film 33 Interlayer insulating film

Claims

1. a semiconductor layer having a first major surface and a second major surface; a first main electrode provided on the first main surface; a second main electrode provided on the second main surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a first insulating region provided in the semiconductor layer and extending from the first major surface to the first semiconductor region; a first conductive portion provided in the first insulating region and electrically connected to the first main electrode; a second insulating region provided in the semiconductor layer, extending from the first main surface to the first semiconductor region and adjacent to the first insulating region; a control electrode provided in the second insulating region; a second semiconductor region of a first conductivity type provided in the semiconductor layer and located between the first insulating region and the second insulating region; a second conductive portion located on the opposite side of the control electrode with the second semiconductor region interposed therebetween, forming a Schottky junction with the second semiconductor region, and electrically connected to the first main electrode; a third semiconductor region of the second conductivity type provided on the first semiconductor region in the semiconductor layer and located on the opposite side of the second semiconductor region with the second insulating region interposed therebetween; a fourth semiconductor region of the first conductivity type provided in the semiconductor layer and located between the third semiconductor region and the first main electrode; a contact portion provided in the third semiconductor region and the fourth semiconductor region and electrically connected to the first main electrode; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein an upper end of said first conductive portion is located higher than a lower end of said second semiconductor region.

3. The semiconductor device according to claim 2 , wherein an upper end of said first conductive portion is at substantially the same height as said first main surface.

4. the first conductive portion has a protruding portion that protrudes to a side surface of the first insulating region, 2. The semiconductor device according to claim 1, further comprising a fifth semiconductor region of a second conductivity type provided within said semiconductor layer so as to cover said protruding portion on a side surface of said first insulating region and having a narrower width than said second semiconductor region.

5. 5. The semiconductor device according to claim 1, wherein the second conductive portion is provided in the first insulating region and contacts the second semiconductor region.

6. a second control electrode provided in the semiconductor layer and positioned on the opposite side of the control electrode with the contact portion interposed therebetween; 5. The semiconductor device according to claim 1, wherein a width of said second semiconductor region is narrower than a width of said third semiconductor region between said control electrode and said second control electrode.

7. 5. The semiconductor device according to claim 1, wherein a thickness of said second insulating region on said second semiconductor region side is greater than a thickness of said second insulating region on said third semiconductor region side.

8. 5. The semiconductor device according to claim 1, wherein the second conductive portion contains platinum.

9. 5. The semiconductor device according to claim 1, wherein the second conductive portion contains at least one of platinum, cobalt, and nickel.

10. 5. The semiconductor device according to claim 1, wherein a concentration of the impurity of the first conductivity type in said second semiconductor region is equal to or lower than a concentration of the impurity of the first conductivity type in said first semiconductor region.

11. 5. The semiconductor device according to claim 1, wherein the control electrode is made of polysilicon of a first conductivity type.

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