Memory device

Abstract

To improve the integration density of memory devices.SOLUTION: A memory device of one embodiment comprises: a first semiconductor and a first insulator provided at the first position in the first direction intersecting a substrate; a first conductor having a first portion extending in the first direction and facing the first semiconductor without the first insulator and a second portion facing the first insulator without the first semiconductor; and a first charge storage film between the first portion and the first semiconductor, but not between the second portion and the first insulator.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The embodiments relate to a memory device. [Background technology]

[0002] NAND flash memory is known as a memory device capable of storing data in a non-volatile manner. In memory devices such as NAND flash memory, a three-dimensional memory structure is adopted to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-147421 Summary of the Invention [Problem to be solved by the invention]

[0004] Improve the integration density of memory devices. [Means for solving the problem]

[0005] The memory device of the embodiment comprises a first semiconductor and a first insulator arranged at a first position in a first direction intersecting a substrate, a first conductor extending in the first direction and having a first portion facing the first semiconductor without the first insulator therebetween and a second portion facing the first insulator without the first semiconductor therebetween, and a first charge storage film arranged between the first portion and the first semiconductor and not between the second portion and the first insulator. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to an embodiment. [Diagram 2]1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory device according to an embodiment. [Diagram 3] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array according to the embodiment. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of a cross-sectional structure of the memory cell array according to the embodiment. [Diagram 5] 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of a cross-sectional structure of a memory cell transistor according to the embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 3, showing an example of a cross-sectional structure of the memory cell array according to the embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of the selection transistor according to the embodiment. [Figure 8] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 10] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 12] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 14] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 16] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 17] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 18] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 19] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 20] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 21] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 22] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Diagram 23] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 24] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Diagram 25] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. [Figure 26] 1 is a plan view showing an example of a planar layout during manufacturing of a memory device according to an embodiment. [Figure 27] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and ratios of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. Configuration 1.1 Memory system configuration FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to an embodiment. The memory system 1 is a storage device configured to be connected to an external host (not shown). The memory system 1 includes, for example, an SD TM The memory system 1 includes a memory controller 2 and a memory device 3. The memory system 1 may be a memory card, a universal flash storage (UFS), or a solid state drive (SSD).

[0010] The memory controller 2 is configured with an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host. Specifically, for example, the memory controller 2 writes data requested to be written by the host to the memory device 3. Also, the memory controller 2 reads data requested to be read by the host from the memory device 3 and transmits the data to the host.

[0011] The memory device 3 is a nonvolatile memory. For example, the memory device 3 is a NAND flash memory. The memory device 3 stores data in a nonvolatile manner.

[0012] The communication between the memory controller 2 and the memory device 3 complies with, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an Open NAND flash interface (ONFI).

[0013] 1.2 Memory Device Configuration The internal configuration of the memory device according to the embodiment will be described below with reference to the block diagram shown in Fig. 1. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). The number of blocks BLK included in the memory cell array 10 may be one. The block BLK is a set of a plurality of memory cells. The block BLK is used, for example, as a data erase unit. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD that the memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to cause the sequencer 13 to execute a read operation, a write operation, an erase operation, or the like.

[0016] The address register 12 stores address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.

[0017] The sequencer 13 controls the operation of the entire memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11 to execute a read operation, a write operation, an erase operation, etc.

[0018] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltage to a signal line corresponding to a selected word line based on a page address PAd stored in the address register 12, for example.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.3 Memory cell array circuit configuration Fig. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory device according to the embodiment. Fig. 2 shows one block BLK among a plurality of blocks BLK included in a memory cell array 10. As shown in Fig. 2, the block BLK includes, for example, four string units SU0 to SU3.

[0022] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). The number of bit lines BL may be one. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage section, and stores data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0023] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to an associated bit line BL. The source of the selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of the selection transistor ST2 is connected to a source line SL.

[0024] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. The gates of the select transistors ST1 in the string units SU0 to SU3 are connected to the select gate lines SGD0 to SGD3, respectively. The gates of the select transistors ST2 are connected to the select gate line SGS.

[0025] A different column address is assigned to each of the bit lines BL0 to BLm. Each bit line BL is shared by a NAND string NS to which the same column address is assigned among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0026] A set of memory cell transistors MT connected to a common word line WL in one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." The cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0027] A set of memory cell transistors MT connected to a common bit line BL in one block BLK is called, for example, a layer unit LU. One layer unit LU includes four NAND strings NS. The four NAND strings NS included in one layer unit LU belong to string units SU0 to SU3, respectively.

[0028] The circuit configuration of the memory cell array 10 included in the memory device 3 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0029] 1.4 Memory cell array structure Next, the structure of the memory cell array according to the embodiment will be described.

[0030] The memory cell array 10 is provided above the substrate. In the following, a plane parallel to the surface of the substrate is referred to as the XY plane. Directions that intersect with each other in the XY plane are referred to as the X direction and the Y direction. The direction from the substrate toward the memory cell array is referred to as the Z direction. The Z direction may be interpreted as the upward direction.

[0031] 1.4.1 Planar Layout Fig. 3 is a plan view showing an example of a planar layout of a memory cell array according to an embodiment. Fig. 3 shows a plan view of layers of a block BLK that are approximately equal in height from a substrate (i.e., position in the Z direction). The portion shown in Fig. 3 corresponds to one layer unit LU in the circuit diagram shown in Fig. 2.

[0032] As shown in FIG. 3, in the same layer, the memory cell array 10 includes a plurality of conductive pillars CGP and SGP, a plurality of insulating pillars RP, a plurality of memory structures MS, a plurality of insulators INS, and a semiconductor CPS.

[0033] The insulator INS is an insulator extending in the Y direction. The insulator INS includes, for example, silicon oxide. In the example of Fig. 3, five insulators INS are arranged apart from each other in the X direction.

[0034] The semiconductor CPS is a semiconductor that extends in the XY plane. The semiconductor CPS includes, for example, polysilicon. The semiconductor CPS is located between two insulators INS adjacent to each other in the X direction and has a linear portion extending in the Y direction. The semiconductor CPS further has two end portions that sandwich the five insulators INS in the Y direction. The two end portions of the semiconductor CPS are connected via the linear portion.

[0035] The insulating pillars RP are insulators extending in the Z direction so as to intersect with the corresponding insulators INS. The insulating pillars RP are integral with the corresponding insulators INS. When viewed in the Z direction, each of the insulating pillars RP is completely surrounded by the corresponding insulator INS. The insulating pillars RP intersect with the same insulator INS are aligned in the Y direction.

[0036] Each of the conductive pillars CGP and SGP extends in the Z direction so as to intersect with the insulator INS and the semiconductor CPS. Each of the conductive pillars CGP and SGP is provided at the boundary between the insulator INS and the semiconductor CPS in a region where two adjacent insulators INS face each other. That is, each of the conductive pillars CGP and SGP has a side surface facing the semiconductor CPS without the insulator INS and a side surface facing the insulator INS without the semiconductor CPS when viewed in the Z direction. The conductive pillars CGP and SGP are arranged in the Y direction at the boundary between the insulator INS and the linear portion of the semiconductor CPS. In the example of FIG. 3, four conductive pillars CGP are arranged so as to be sandwiched between two conductive pillars SGP in the Y direction. The portion where each of the conductive pillars CGP and SGP faces the semiconductor CPS functions as a transistor.

[0037] The memory structure MS is provided between the semiconductor CPS and the conductive pillar CGP, and includes a charge storage film. The memory structure MS is not provided between the insulator INS and the conductive pillar CGP. That is, the memory structure MS has a fan shape when viewed in the Z direction. More specifically, the memory structure MS has a shape obtained by removing a fan shape with a radius r2 and a central angle equal to that of the fan shape from a fan shape with a radius r1 when viewed in the Z direction (r1>r2). A portion where each of the multiple conductive pillars CGP contacts the semiconductor CPS via the memory structure MS functions as a memory cell transistor MT. Note that the memory structure MS is not provided between the semiconductor CPS and the conductive pillar SGP. Therefore, a portion where each of the multiple conductive pillars SGP contacts the semiconductor CPS functions as a selection transistor ST1 or ST2, not as a memory cell transistor MT. Eight pairs of conductive pillars CGP and memory structure MS and four conductive pillars SGP provided at the boundary between one linear portion of the semiconductor CPS and the insulator INS provided at one end of the linear portion and the boundary between the linear portion and the insulator INS provided at the other end of the linear portion function as one NAND string NS. In FIG. 3, the four NAND strings NS formed by the five insulators INS and the semiconductor CPS correspond to the string units SU0 to SU3, respectively.

[0038] The linear portion of the semiconductor CPS functions as a channel of the NAND string NS. One end of both ends of the semiconductor CPS functions as a bit line BL. The other end of both ends of the semiconductor CPS functions as a source line SL.

[0039] In the same NAND string NS, two conductive pillars CGP that contact two opposing insulators INS are separated by a length a in the X direction. Two conductive pillars CGP that contact the same insulator INS and belong to different NAND strings NS are separated by a length b in the X direction. The memory structure MS has a length c (=r1-r2) in the radial direction of the corresponding conductive pillar CGP. In other words, the semiconductor CPS and the conductive pillar CGP are separated by a length c in the X direction via the memory structure MS. The conductive pillars CGP and insulating pillars RP that contact the same insulator INS and are adjacent to each other are separated by a length d.

[0040] Length a and length b may be different. More specifically, length a is preferably longer than length b (a>b). Length b may be shorter than twice length c (b<2c). Length d may be shorter than length c (d <c)。

[0041] 1.4.2 Cross-sectional structure of conductive pillar CGP Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3, showing an example of a cross-sectional structure of the memory cell array according to the embodiment. Fig. 4 mainly shows the cross-sectional structures of two conductive pillars CGP in contact with the same insulator INS and one insulating pillar RP provided in the insulator INS adjacent to the insulator INS.

[0042] 4, the memory cell array 10 includes a substrate 20, insulator layers 21, 23, and 24, a semiconductor layer 22, an insulator 37, a conductor 38, a conductive pillar CGP, and a memory structure MS. The insulator 37 includes a portion corresponding to the insulating pillar RP and a portion corresponding to the insulator INS.

[0043] The substrate 20 is, for example, a P-type semiconductor. An insulator layer 21 is provided on the upper surface of the substrate 20. The substrate 20 and the insulator layer 21 may include circuits (not shown). The circuits included in the substrate 20 and the insulator layer 21 correspond to, for example, the row decoder module 15, the sense amplifier module 16, etc.

[0044] A plurality of semiconductor layers 22 and a plurality of insulator layers 23 are alternately stacked one by one on the upper surface of the insulator layer 21. In the example of Fig. 4, five semiconductor layers 22 and five insulator layers 23 are alternately stacked one by one. In other words, a plurality of semiconductor layers 22 stacked and spaced apart in the Z direction are provided above the substrate 20. The number of stacked semiconductor layers 22 corresponds to, for example, the number of bit lines BL.

[0045] The semiconductor layer 22 corresponds to the semiconductor CPS and has a portion extending in the Y direction. The portion of the semiconductor layer 22 extending in the Y direction (i.e., the portion illustrated in FIG. 4) functions as a channel of the NAND string NS. The insulator layers 21 and 23 include, for example, silicon oxide. The semiconductor layer 22 includes, for example, polysilicon.

[0046] An insulator layer 24 is provided on the upper surface of the uppermost insulator layer 23. The insulator layer 24 includes, for example, silicon oxide.

[0047] The insulator 37 has a portion extending in the Z direction, which portion corresponds to the insulating pillar RP. The insulating pillar RP intersects with a plurality of semiconductor layers 22 and the insulating layers 23. The lower end of the insulating pillar RP reaches the insulating layer 21. The upper end of the insulating pillar RP is aligned with, for example, the upper end of the uppermost insulating layer 23.

[0048] The insulator 37 has a portion that extends in the XY plane in the same layer as the semiconductor layer 22, and this portion corresponds to the insulator INS. The insulator INS and the insulating pillar RP are provided as a continuous film.

[0049] The conductive pillar CGP extends in the Z direction so as to intersect with the multiple semiconductor layers 22 and the insulator layers 23. The lower end of the conductive pillar CGP reaches the insulator layer 21. The upper end of the conductive pillar CGP is aligned with, for example, the upper end of the uppermost insulator layer 23. The conductive pillar CGP is electrically connected to the row decoder module 15 via a conductor 38 provided in the insulator layer 24, thereby functioning as a word line WL.

[0050] In the same layer as the semiconductor layer 22, a part of the side surface of the conductive pillar CGP contacts the insulator INS. In the same layer as the semiconductor layer 22, a part of the side surface of the conductive pillar CGP that is not in contact with the insulator INS contacts the memory structure MS. The conductive pillar CGP includes a conductor film 30, and insulator films 31 and 32. The memory structure MS includes an insulator film 33, a charge storage film 34, and an insulator film 35.

[0051] The conductor film 30 extends in the Z direction. For example, the upper end of the conductor film 30 contacts the conductor 38. The lower end of the conductor film 30 is included in a layer lower than the lowermost semiconductor layer 22. The conductor film 30 includes, for example, titanium nitride.

[0052] The insulating film 31 covers the periphery of the conductive film 30 except for the upper surface. The insulating film 32 covers the periphery of the insulating film 31. The insulating film 31 includes, for example, aluminum oxide. The insulating film 32 includes, for example, silicon oxide.

[0053] The insulator film 33 covers a part of the side surface of the insulator film 32 in the same layer as the semiconductor layer 22. The charge storage film 34 covers the side surface of the insulator film 33. The insulator film 35 covers the side surface of the charge storage film 34. The side surface of the insulator film 35 is covered by the semiconductor layer 22. The insulator film 33 includes, for example, hafnium silicate. The insulator film 35 includes, for example, silicon oxide. The charge storage film 34 includes a material having a function of storing charges. Specifically, the charge storage film 34 may include a conductor such as silicon or metal. The charge storage film 34 may also include an insulator such as silicon nitride. When the charge storage film 34 includes a conductor such as silicon or metal, the memory cell transistor MT functions as a floating gate type memory cell transistor MT. When the charge storage film 34 contains an insulator such as silicon nitride, the memory cell transistor MT functions as a MONOS (metal-oxide-nitride-oxide-silicon) type memory cell transistor MT.

[0054] Fig. 5 is a cross-sectional view taken along line VV in Fig. 4, showing an example of a cross-sectional structure of a memory cell transistor according to the embodiment. More specifically, Fig. 5 shows a cross-sectional structure of a conductive pillar CGP in a layer parallel to the XY plane and including a semiconductor layer 22.

[0055] In a cross section including the semiconductor layer 22, the conductor film 30 is provided, for example, in the center of the conductive pillar CGP. The insulator film 31 surrounds the side of the conductor film 30. The insulator film 32 surrounds the side of the insulator film 31. The insulator film 33 surrounds the part of the side of the insulator film 32 that is not in contact with the insulator INS. The charge storage film 34 surrounds the side of the insulator film 33. The insulator film 35 surrounds the side of the charge storage film 34. The semiconductor layer 22 surrounds the side of the insulator film 35. In this way, the insulator film 33, the charge storage film 34, and the insulator film 35 are provided only between the conductive pillar CGP and the semiconductor layer 22, and are not provided between the conductive pillar CGP and the insulator INS.

[0056] The conductive film 30 is used as a wiring (word line WL) connected to the gate of the memory cell transistor MT. The insulator films 31, 32, and 33 are used as a block insulating film for the memory cell transistor MT. The insulator film 35 is used as a tunnel insulating film for the memory cell transistor MT. This allows the conductive pillar CGP to function as multiple memory cell transistors MT connected to the same word line WL. In other words, the conductive pillar CGP can function as at least a part of one cell unit CU.

[0057] 1.4.3 Cross-sectional structure of conductive pillar SGP Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 3, showing an example of a cross-sectional structure of the memory cell array according to the embodiment. Fig. 6 mainly shows the cross-sectional structures of two conductive pillars SGP in contact with the same insulator INS and one insulating pillar RP provided in the insulator INS adjacent to the insulator INS.

[0058] 6, the memory cell array 10 further includes a conductor 43 and a conductive pillar SGP. The structure other than the conductor 43 and the conductive pillar SGP is the same as the structure shown in FIG 4, and therefore description thereof will be omitted.

[0059] The conductive pillar SGP extends in the Z direction so as to intersect with a plurality of semiconductor layers 22 and the insulator layers 23. The lower end of the conductive pillar SGP reaches the insulator layer 21. The upper end of the conductive pillar CGP is aligned with, for example, the upper end of the uppermost insulator layer 23. The conductive pillar SGP is electrically connected to the row decoder module 15 via a conductor 43 provided in the insulator layer 24, thereby functioning as a select gate line SGS.

[0060] In the same layer as the semiconductor layer 22, a part of the side surface of the conductive pillar SGP is in contact with the insulator INS. In the same layer as the semiconductor layer 22, a part of the side surface of the conductive pillar SGP that is not in contact with the insulator INS is in contact with the semiconductor layer 22. The conductive pillar SGP includes a conductive film 40 and insulator films 41 and 42.

[0061] The conductor film 40 extends in the Z direction. For example, the upper end of the conductor film 40 contacts the conductor 43. The lower end of the conductor film 40 is included in a layer lower than the lowermost semiconductor layer 22. The conductor film 40 includes, for example, titanium nitride.

[0062] The insulating film 41 covers the periphery of the conductive film 40 except for the upper surface. The insulating film 42 covers the periphery of the insulating film 41. The insulating film 41 includes, for example, aluminum oxide. The insulating film 42 includes, for example, silicon oxide.

[0063] Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of a cross-sectional structure of a selection transistor according to an embodiment. More specifically, Fig. 7 shows a cross-sectional structure of a conductive pillar SGP in a layer parallel to the XY plane and including the semiconductor layer 22.

[0064] In a cross section including the semiconductor layer 22, the conductor film 40 is provided, for example, in the center of the conductive pillar SGP. The insulator film 41 surrounds the side surface of the conductor film 40. The insulator film 42 surrounds the side surface of the insulator film 41. The semiconductor layer 22 surrounds a part of the side surface of the insulator film 42. The part of the side surface of the insulator film 42 that is not surrounded by the semiconductor layer 22 is surrounded by the insulator 37.

[0065] The conductive film 40 is used as a wiring (select gate line SGS) connected to the gate of the select transistor ST2. The insulating films 41 and 42 are used as a block insulating film for the select transistor ST2. This allows the conductive pillar SGP to function as multiple select transistors ST2 connected to the same select gate line SGS.

[0066] In addition, in Figures 6 and 7, the cross-sectional structure of the conductive pillar SGP corresponding to the select gate line SGS has been described, but the conductive pillar SGP corresponding to the select gate line SGD also has a cross-sectional structure equivalent to that of the conductive pillar SGP corresponding to the select transistor ST2.

[0067] 1.2 Manufacturing method 8, 10, 12, 14, 16, 18, 20, 22, 24, and 26 are plan views showing an example of a planar layout during the manufacture of a memory device according to the embodiment. FIGS. 9, 11, 13, 15, 17, 19, 21, 23, 25, and 27 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to the embodiment. FIGS. 8, 10, 12, 14, 16, and 18 correspond to the planar layout shown in FIG. 3. FIGS. 20, 22, 24, and 26 correspond to the planar layout shown in FIG. 5. FIGS. 9, 11, 13, 15, 17, 19, 21, 23, 25, and 27 correspond to the cross section shown in FIG. 4.

[0068] 8 and 9, a laminated structure is formed on the upper surface of the substrate 20. Specifically, an insulator layer 21 is provided on the upper surface of the substrate 20. Then, a sacrificial member 51 and an insulator layer 23 are repeatedly laminated in this order on the upper surface of the insulator layer 21. The sacrificial member 51 includes, for example, silicon nitride.

[0069] 10 and 11, a plurality of holes are provided in the laminated structure in an area where the insulating pillars RP and the conductive pillars CGP and SGP are to be provided. Each of the plurality of holes penetrates the plurality of sacrificial members 51 and the insulator layer 23. The bottom of each of the plurality of holes reaches the insulator layer 21. Each of the plurality of holes is filled with a sacrificial member 52. The sacrificial member 52 includes, for example, amorphous silicon.

[0070] 12 and 13, the sacrificial members 52 corresponding to the insulating pillars RP are removed from the plurality of sacrificial members 52 to form a plurality of holes H1. As a result, the plurality of sacrificial members 51 stacked apart from one another are exposed inside the plurality of holes H1. Thereafter, the portions of the sacrificial members 51 where the insulators INS are to be provided are selectively removed from the plurality of holes H1 by, for example, wet etching. As a result, grooves SH1 extending in the XY plane are formed from inside the plurality of holes H1.

[0071] In the same layer, two grooves SH1 corresponding to adjacent holes H1 in the Y direction are connected. That is, the multiple holes H1 aligned in the Y direction are spatially connected via the grooves SH1. On the other hand, two grooves SH1 corresponding to adjacent holes H1 in the X direction are not connected. That is, the multiple holes H1 aligned in the X direction are separated by the sacrificial member 51. Also, the grooves SH1 expose a part of the side surface of the sacrificial member 52 in the same layer. That is, after the grooves SH1 are formed, the sacrificial member 52 has a part of the side surface exposed in the layer in which the sacrificial member 51 is provided, but still has a side surface covered by the sacrificial member 51.

[0072] 14 and 15, the trenches SH1 and the holes H1 are filled with an insulator 37. This forms a plurality of insulators INS and a plurality of insulating pillars RP.

[0073] 16 and 17, the sacrificial members 52 corresponding to the conductive pillars CGP are removed from the plurality of sacrificial members 52 to form a plurality of holes H2. As a result, the plurality of sacrificial members 51 stacked apart from one another are exposed inside the plurality of holes H2. After that, all the sacrificial members 51 (i.e., the portions where the semiconductor CPS is to be provided) are selectively removed from the plurality of holes H2 by, for example, wet etching. As a result, a groove SH2 extending in the XY plane is formed from inside the plurality of holes H2.

[0074] Next, as shown in FIGS. 18 and 19, the trenches SH2 and parts of the holes H2 are filled with a semiconductor CPS.

[0075] 20 and 21, the semiconductor CPS is partially removed by, for example, wet etching. As a result, the portions of the semiconductor CPS formed in the grooves SH2 are separated from each other to form the semiconductor layers 22, and the grooves SH3 are formed in the region where the memory structures MS are to be formed.

[0076] 22 and 23, parts of the multiple insulator layers 23 are selectively removed by, for example, wet etching. This causes the multiple grooves SH3 to expand in the Z direction. Thereafter, an insulator film 35 is formed on a portion of each of the multiple grooves SH3 that contacts the semiconductor layer 22.

[0077] 24 and 25, a charge storage film 34 is formed in a portion of each of the plurality of grooves SH3 that contacts the insulator film 35. Then, an insulator film 33 is formed in a portion of each of the plurality of grooves SH3 that contacts the charge storage film 34. As a result, the plurality of grooves SH3 are filled.

[0078] 26 and 27, a portion of the multiple insulator layers 23 is selectively removed by, for example, wet etching. After that, the insulator film 32, the insulator film 31, and the conductor film 30 are formed in this order inside the multiple holes H2 to fill the multiple holes H2.

[0079] Thereafter, the sacrificial member 52 corresponding to the conductive pillar SGP is removed to form a plurality of holes. Then, the insulating film 42, the insulating film 41, and the conductive film 40 are formed in this order in the holes to fill the holes, thereby forming a plurality of conductive pillars SGP.

[0080] Thereafter, the structure above the stacked structure of the memory cell array 10 is formed. In this manner, the memory device 3 is formed.

[0081] 1.3 Effects of the embodiment According to the embodiment, the semiconductor CPS is formed after the insulator INS is formed. Inside the hole H2 corresponding to the conductive pillar CGP, a first portion where the semiconductor CPS is exposed and a second portion where the insulator is exposed are formed in the same layer. The memory structure MS is formed by replacing a part of the semiconductor CPS through the hole H2. This allows the memory structure MS to be structured so that it is provided between the first portion of the hole H2 and the semiconductor CPS, and not provided between the second portion of the hole H2 and the insulator INS. That is, it is possible to have a structure in which the memory structure MS is not provided between two conductive pillars CGPs arranged in the X direction with the insulator INS between them. For this reason, the length b between the two conductive pillars CGPs arranged in the X direction with the insulator INS between them can be made shorter than twice the length c of the memory structure MS. Therefore, the integration degree of the memory cell array 10 can be improved compared to the case where the memory structure MS is provided so as to surround the conductive pillar CGP when viewed in the Z direction.

[0082] 2. Modifications, etc. It should be noted that various modifications can be applied to the above-described embodiment.

[0083] In the above embodiment, a case has been described in which a plurality of conductive pillars CGP belonging to a certain string unit SU and a plurality of conductive pillars CGP belonging to a string unit SU adjacent to the string unit SU are arranged in a staggered manner when viewed in the Z direction, but this is not limiting. For example, the plurality of conductive pillars CGP may be arranged in a matrix when viewed in the Z direction.

[0084] In the above embodiment, the conductive pillars CGP and SGP, and the insulating pillar RP are circular when viewed in the Z direction, but this is not limiting. For example, the conductive pillars CGP and SGP, and the insulating pillar RP may be elliptical or polygonal in shape other than a circle when viewed in the Z direction.

[0085] In the above embodiment, the conductive pillar SGP is formed after the conductive pillar CGP is formed, but the present invention is not limited to this. For example, the conductive pillar SGP may be formed after the insulator INS is formed and before the conductive pillar CGP is formed.

[0086] In the above embodiment, the case where the memory structure MS is not provided between the conductive pillar SGP and the semiconductor CPS has been described, but the present invention is not limited to this. For example, a structure equivalent to the memory structure MS provided between the conductive pillar CGP and the semiconductor CPS may be provided between the conductive pillar SGP and the semiconductor CPS. In this case, the conductive pillar SGP is manufactured in the same process as the conductive pillar CGP. Even when the memory structure MS is provided between the conductive pillar SGP and the semiconductor CPS, the conductive pillar SGP and the semiconductor CPS can function as the selection transistor ST1 or ST2.

[0087] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0088] 1. Memory system 2…Memory controller 3. Memory device 10...Memory cell array 11...Command register 12...Address register 13...Sequencer 14...Driver module 15...Row decoder module 16...Sense amplifier module 20...Substrate 21, 23, 24...Insulating layers 22...Semiconductor layer 30, 40...Conductive film 31, 32, 33, 35, 41, 42...Insulating film 34...Charge storage film 37…Insulator 38, 43…Conductor 51, 52...Sacrificial members

Claims

1. a first semiconductor and a first insulator provided at a first position in a first direction intersecting a substrate; a first conductor extending in the first direction and having a first portion facing the first semiconductor without the first insulator therebetween and a second portion facing the first insulator without the first semiconductor therebetween; a first charge storage film provided between the first portion and the first semiconductor and not provided between the second portion and the first insulator; Equipped with Memory device.

2. The first semiconductor and the first insulator are extending in a second direction intersecting the first direction, aligned in a third direction intersecting the first direction and the second direction; The memory device of claim 1 .

3. a second semiconductor provided on an opposite side of the first insulator from the first semiconductor at the first position; a second conductor extending in the first direction and having a third portion facing the second semiconductor without the first insulator therebetween and a fourth portion facing the first insulator without the second semiconductor therebetween; a second charge storage film provided between the third portion and the second semiconductor and not provided between the fourth portion and the first insulator; Further equipped with The memory device of claim 2.

4. a length between the first conductor and the second conductor in the third direction is shorter than twice a length between the first conductor and the first semiconductor in the third direction; The memory device of claim 3.

5. a second insulator provided on an opposite side of the first insulator with respect to the first semiconductor at the first position; a third conductor extending in the first direction and having a fifth portion facing the first semiconductor without the second insulator therebetween and a sixth portion facing the second insulator without the first semiconductor therebetween; a third charge storage film provided between the fifth portion and the first semiconductor and not provided between the sixth portion and the second insulator; Further equipped with The memory device of claim 3.

6. a length between the first conductor and the third conductor in the third direction is longer than a length between the first conductor and the second conductor in the third direction; The memory device of claim 5.

7. The first semiconductor and the second semiconductor are continuous films. The memory device of claim 3.

8. a fourth conductor extending in the first direction and having a seventh portion facing the first semiconductor without the first insulator therebetween and an eighth portion facing the first insulator without the first semiconductor therebetween, the fourth conductor being aligned with the first conductor in the second direction; a fourth charge storage film provided between the seventh portion and the first semiconductor and not provided between the eighth portion and the first insulator; Further equipped with The memory device of claim 2.

9. a third semiconductor and a third insulator provided at a second position different from the first position in the first direction; the first conductor further includes a ninth portion facing the third semiconductor without the third insulator therebetween, and a tenth portion facing the third insulator without the third semiconductor therebetween; a fifth charge storage film provided between the ninth portion and the third semiconductor and not provided between the tenth portion and the third insulator; The memory device of claim 1 .

10. the first charge storage film includes silicon nitride; The memory device of claim 1 .

11. The first charge storage film includes silicon or metal. The memory device of claim 1 .

12. The first charge storage film has a sector shape when viewed in the first direction. The memory device of claim 1 .

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