Semiconductor device and semiconductor storage device

Abstract

To provide a semiconductor device and a semiconductor storage device, by which a semiconductor device with high quality can be manufactured.SOLUTION: A semiconductor device includes an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end, a first electrode in contact with the first end of the oxide semiconductor, a second electrode in contact with the second end of the oxide semiconductor, a gate electrode surrounding the oxide semiconductor through a first insulating film between the first end and the second end of the oxide semiconductor, and a second insulating film provided on the first direction side of the gate electrode and surrounding the oxide semiconductor through the first insulating film. The gate electrode and the second insulating film form a hole part to accommodate at least a part of the oxide semiconductor. An inner wall of the hole part has a step difference surface formed which faces in the opposite direction of the first direction.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device and a semiconductor memory device. [Background technology]

[0002] Some semiconductor elements use metal oxide containing indium and tin for electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication US2022 / 0285350 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing process of semiconductor elements in which metal oxides are used for electrodes, there is a demand for technology for manufacturing high-quality semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device and a semiconductor memory device that enable the manufacture of high-quality semiconductor devices. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end, a first electrode in contact with the first end of the oxide semiconductor, a second electrode in contact with the second end of the oxide semiconductor, a gate electrode surrounding the oxide semiconductor between the first end and the second end of the oxide semiconductor via a first insulating film, and a second insulating film provided on the first direction side of the gate electrode and surrounding the oxide semiconductor via the first insulating film, wherein the gate electrode and the second insulating film form a hole in which at least a portion of the oxide semiconductor is accommodated, and a step surface facing in the opposite direction to the first direction is formed on an inner wall of the hole.

[0007] The semiconductor device according to the present disclosure comprises a plurality of the oxide semiconductors having a first end and a second end and extending in a first direction from the second end to the first end, a plurality of first electrodes each in contact with the first ends of the plurality of the oxide semiconductors, a plurality of second electrodes each in contact with the second ends of the plurality of the oxide semiconductors, a gate electrode extending along the second direction and surrounding the oxide semiconductor between the first end and the second end of each of the plurality of the oxide semiconductors provided along the second direction, via a plurality of first insulating films, a fourth insulating film provided in an opposite direction to the first direction relative to the gate electrode, and a fifth insulating film provided in an opposite direction to the first direction relative to the fourth insulating film between two of the oxide semiconductors adjacent in the second direction, wherein an etching rate of the fifth insulating film is greater than an etching rate of the fourth insulating film.

[0008] The semiconductor memory device of the present disclosure comprises the semiconductor device, a first capacitor electrode connected to the first electrode or the second electrode, a second capacitor electrode facing the first capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode. [Brief description of the drawings]

[0009] [Figure 1]2 is a circuit diagram for explaining an example of a circuit configuration of a memory cell array according to the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor memory device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane. [Diagram 3] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device of the first example of the first embodiment. [Figure 4] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device of the first example of the first embodiment. [Diagram 5] 5 is a cross-sectional view taken along line VV shown in FIGS. 3 and 4. FIG. [Figure 6] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 7] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 8] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 9] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 10] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 11] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 12] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 13] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 14] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 15] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 16] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 17] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 18] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 19] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 20] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 21] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 22] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 23] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 24] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 25] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 26] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 27] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 28] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 29] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 30] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 31]1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 32] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 33] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 34] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 35] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 36] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 37] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 38] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Figure 39] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 40] 1A to 1C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 41] 1A to 1C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the first example of the first embodiment. [Diagram 42] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the second example of the first embodiment. [Diagram 43] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device of the second example of the first embodiment. [Diagram 44] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a second example of the first embodiment. [Diagram 45] 5A to 5C are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second example of the first embodiment. [Diagram 46] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the third example of the first embodiment. [Figure 47] FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to a third example of the first embodiment. [Figure 48] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a third example of the first embodiment. [Figure 49] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of a semiconductor device according to a third example of the first embodiment. [Figure 50] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the fourth example of the first embodiment. [Figure 51] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fourth example of the first embodiment. [Figure 52] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a fourth example of the first embodiment. [Figure 53] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of a semiconductor device according to a fourth example of the first embodiment. [Figure 54] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the fifth example of the first embodiment. [Figure 55] FIG. 11 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fifth example of the first embodiment. [Figure 56] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to a sixth example of the first embodiment. [Figure 57] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to a sixth example of the first embodiment. [Figure 58] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the seventh example of the first embodiment. [Figure 59] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the seventh example of the first embodiment. [Figure 60] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a seventh example of the first embodiment. [Figure 61] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of a semiconductor device according to a seventh example of the first embodiment. [Figure 62] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device according to a seventh example of the first embodiment. [Figure 63] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of a semiconductor device according to a seventh example of the first embodiment. [Figure 64] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the eighth example of the first embodiment. [Figure 65] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the eighth example of the first embodiment. [Figure 66] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the ninth example of the first embodiment. [Figure 67] FIG. 13 is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the ninth example of the first embodiment. [Figure 68] FIG. 11 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a second embodiment, showing a cross-sectional view parallel to the ZX plane. [Figure 69] FIG. 13 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a second embodiment, showing a cross-sectional view parallel to the YZ plane. [Figure 70]10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 71] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 72] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 73] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 74] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 75] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 76] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 77] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 78] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 79] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 80] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 81] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 82] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 83] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 84] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 85] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 86] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 87] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 88] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 89] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 90] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 91] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 92] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 93] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 94] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 95] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 96] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 97] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 98] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 99] 10A to 10D are cross-sectional views parallel to the YZ plane showing a manufacturing process of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate understanding of the description, the same components in each drawing are denoted by the same reference numerals as much as possible, and duplicated description will be omitted.

[0011] [First embodiment] The configuration of the semiconductor memory device according to the first embodiment will be described. Each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, the Y-axis, and the Z-axis form a right-handed three-dimensional Cartesian coordinate system. Hereinafter, the direction of the X-axis arrow may be called the X-axis + direction, and the direction opposite to the arrow may be called the X-axis - direction, and the same applies to the other axes. The Z-axis + direction and the Z-axis - direction may be called "upper" and "lower", respectively. Furthermore, the planes perpendicular to the X-axis, Y-axis, or Z-axis may be called the YZ plane, ZX plane, or XY plane, respectively. Furthermore, the Z-axis direction may be called the "vertical direction". "Upward", "downward", and "vertical direction" are terms that indicate the relative positional relationship within the drawing, and are not terms that define the orientation based on the vertical direction.

[0012] In addition, unless otherwise specifically explained, the dimensions of components shown in each drawing may be shown differently from their actual dimensions in order to make the explanation easier to understand.

[0013] In this specification, the term "connection" includes not only a physical connection but also an electrical connection, and unless otherwise specified, includes not only a direct connection but also an indirect connection.

[0014] In this specification, the term "formed above" does not only mean a case where the material is formed in contact with the material above, but also includes a case where the material is formed above via another object, unless otherwise specified. The same applies to "formed below" and the like.

[0015] The semiconductor memory device 101 according to the first embodiment is an oxide semiconductor random access memory (OS-RAM) and includes a memory cell array.

[0016] As shown in FIG. 1, the memory cell array includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0017] FIG. 1 shows a word line WL n , word line WL n+1 and word line WL n+2 (where n is a positive integer). Also, in FIG. 1, as an example of the bit line BL, m , bit line BL m+1 and bit line BL m+2 (where m is a positive integer.) The number of memory cells MC is not limited to the number shown in FIG.

[0018] A plurality of memory cells MC are arranged in, for example, a matrix to form a memory cell array. The memory cell MC includes a memory transistor MTR, which is a field effect transistor (FET), and a memory capacitor MCP.

[0019] A series of memory cells MC arranged in the row direction are connected to a word line WL (e.g., word line WL n A series of memory cells MC arranged in the column direction is connected to a bit line BL (e.g., bit line BL m+2 )

[0020] Specifically, the gate of the memory transistor MTR included in the memory cell MC is connected to a word line WL corresponding to the row to which the memory cell MC belongs, and one of the source and drain of the memory transistor MTR is connected to a bit line BL corresponding to the column to which the memory cell MC belongs.

[0021] One electrode of a memory capacitor MCP included in a memory cell MC is connected to the other of the source or drain of a memory transistor MTR included in the memory cell MC, and the other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0022] The memory cell MC is configured to be able to hold data by storing charge in the memory capacitor MCP due to a current flowing through the corresponding bit line BL, by switching the memory transistor MTR based on the potential of the corresponding word line WL.

[0023] As shown in FIG. 2, the semiconductor memory device 101 includes a semiconductor substrate 10, a circuit 11, a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35, 45 and 63.

[0024] Capacitor 20 includes a conductor 21, an insulating film 22 (an example of a "dielectric film"), a conductor 23, a capacitor electrode 24 (an example of a "first capacitor electrode"), and a capacitor electrode 25 (an example of a "second capacitor electrode").

[0025] The semiconductor device 30 includes a field effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 (an example of a "first electrode") provided above the field effect transistor 40, and a lower electrode 32 (an example of a "second electrode") provided below the field effect transistor 40.

[0026] The field effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor") corresponding to a channel, a gate insulating film 43 (an example of a "first insulating film"), and a conductive layer 42 (an example of a "gate electrode").

[0027] The oxide semiconductor layer 70 is formed in the insulating layer 45, and has an upper end 70a (an example of a "first end") and a lower end 70b (an example of a "second end"). The oxide semiconductor layer 70 is a columnar body extending in the Z-axis + direction (an example of a "first direction") from the lower end 70b to the upper end 70a. The oxide semiconductor layer 70 forms a channel of the field effect transistor 40, and the oxide semiconductor layer 70 has an amorphous structure.

[0028] The conductive layer 42 functions as a gate electrode of the field effect transistor 40, and surrounds the oxide semiconductor layer 70 between an upper end 70a and a lower end 70b of the oxide semiconductor layer 70 via a gate insulating film 43. The conductive layer 42 contains, for example, tungsten.

[0029] The gate insulating film 43 includes, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen.

[0030] The upper electrode 50 is formed in the positive Z-axis direction with respect to the oxide semiconductor layer 70, and is in contact with an upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0031] The metal film 50c includes tungsten (W). The metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70 and includes a metal oxide. The metal oxide includes, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin-oxide (ITO).

[0032] The barrier metal layer 50b contains titanium and nitrogen, and is formed between the metal oxide layer 50a and the metal film 50c. In this embodiment, the barrier metal layer 50b is made of, for example, titanium nitride (TiN).

[0033] The lower electrode 32 is in contact with a lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 is formed of, for example, an indium-tin-oxide (ITO) layer containing a metal oxide such as ITO.

[0034] The lower electrode 32 is not limited to ITO, and may be made of at least one of the following elements: indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0035] The circuit 11 constitutes peripheral circuits such as a decoder for selecting a specific memory cell MC from among a plurality of memory cells MC, i.e., capacitors 20 and field effect transistors 40, of the semiconductor memory device 101, a sense amplifier connected to the bit line BL, and a register constituted by an SRAM. The circuit 11 may include a CMOS circuit having field effect transistors, that is, a P-channel field effect transistor (Pch-FET) and an N-channel field effect transistor (Nch-FET), formed by a CMOS process.

[0036] The field effect transistors of the circuit 11 can be formed using a semiconductor substrate 10 such as a single crystal silicon substrate. The Pch-FET and Nch-FET are so-called horizontal field effect transistors that have a channel region, a source region, and a drain region in the semiconductor substrate 10 and have a channel for flowing carriers in the X-axis direction or the Y-axis direction approximately parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. The semiconductor substrate 10 may have a conductivity type of P type to N type. For convenience, FIG. 2 illustrates an example of the field effect transistor of the circuit 11.

[0037] The capacitor 20 is a memory capacitor MCP included in the memory cell MC (see FIG. 1). Although four capacitors 20 are illustrated in FIG. 2, the number of capacitors 20 is not limited to four.

[0038] In this embodiment, the capacitor 20 is provided above the semiconductor substrate 10. The capacitor electrode 24 of the capacitor 20 is connected to the conductor 21 and the lower electrode 32. The capacitor electrode 25 faces the capacitor electrode 24. The insulating film 22 is provided between the capacitor electrodes 24 and 25.

[0039] The capacitor 20 is a three-dimensional capacitor such as a pillar-type capacitor. Note that, as the capacitor of this embodiment, other capacitors having a configuration capable of storing electric charge may be adopted.

[0040] The conductor 21 abuts against the lower end face of the lower electrode 32 and has a shape extending downward from that end. The capacitor electrode 24 is formed so as to cover the lower electrode 32 and the conductor 21. The insulating film 22 is formed so as to cover the capacitor electrode 24. The capacitor electrode 25 surrounds a lower portion of the insulating film 22 and has a lower end abutting against the upper end face of the conductor 23.

[0041] The conductor 21 may include a material such as amorphous silicon. The insulating film 22 may include a material such as hafnium oxide. The conductor 23 and the capacitor electrodes 24 and 25 may include a material such as tungsten (W) and titanium nitride (TiN).

[0042] The conductor 33 includes a wiring that electrically connects the circuit 11 and the semiconductor device 30. The conductor 33 may include a via wiring, and has a via wiring that extends in the Z-axis direction as shown in Fig. 2, for example, and connects the word line WL and the circuit 11 provided on the semiconductor substrate 10. The conductor 33 includes, for example, copper.

[0043] The insulating layer 34 is provided between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0044] The insulating layer 35 is provided above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0045] The semiconductor device 30 is provided above the capacitor 20. A field effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC (see FIG. 1).

[0046] In the semiconductor device 30, the field effect transistor 40 is provided above the lower electrode 32. In particular, the oxide semiconductor layer 70 of the field effect transistor 40 is located in a direction away from the semiconductor substrate 10 with respect to the lower electrode 32, that is, above the lower electrode 32.

[0047] The upper electrode 50 is located in a direction away from the semiconductor substrate 10, i.e., above the oxide semiconductor layer 70. With this configuration, the field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (up-down direction) that is approximately perpendicular to the surface of the semiconductor substrate 10.

[0048] The oxide semiconductor layer 70 is a semiconductor in which oxygen vacancies serve as donors, and contains indium (In), zinc (Zn), and gallium (Ga) as metal elements. In particular, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, that is, IGZO (InGaZnO). The oxide semiconductor layer 70 may be another type of oxide semiconductor.

[0049] Fig. 3 shows a cross-sectional view of the semiconductor device 30 as seen at a cross-section 70ZX parallel to the ZX plane and included in the oxide semiconductor layer 70. Fig. 4 shows a cross-sectional view of the semiconductor device 30 as seen at a cross-section 70YZ parallel to the YZ plane and included in the oxide semiconductor layer 70. Fig. 5 is a cross-sectional view taken along the cutting line V-V shown in Figs. 3 and 4.

[0050] Hereinafter, a first example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a first example of the first embodiment) will be described.

[0051] (First Example of First Embodiment) 3 to 5, in the first example of the first embodiment, the semiconductor device 30 further includes a liner film 301 (an example of a "third insulating film") and a spacer film 311. The gate insulating film 43 includes insulating films 43a and 43b. The insulating layer 45 includes insulating films 45a, 45b, and 45c.

[0052] The multiple conductive layers 42 are repeatedly provided in the positive direction of the X-axis (an example of a "third direction"). The multiple oxide semiconductor layers 70 are arranged two-dimensionally. That is, some of the multiple oxide semiconductor layers 70 are provided along the positive direction of the Y-axis (an example of a "second direction"). Furthermore, other parts of the multiple oxide semiconductor layers 70 are provided along the positive direction of the X-axis.

[0053] The conductive layer 42 extends along the +Y direction of the Y axis, and surrounds, via a plurality of gate insulating films 43, the plurality of oxide semiconductor layers 70 provided along the +Y direction of the Y axis.

[0054] In detail, the conductive layer 42 includes a surrounding portion 42b (an example of a "first portion") that surrounds the oxide semiconductor layer 70, and a connecting portion 42c (an example of a "second portion") that connects the two surrounding portions 42b.

[0055] When the conductive layer 42 is viewed from above, the width of the connecting portion 42c in the X-axis direction is narrower than the width of the surrounding portion 42b in the X-axis direction.

[0056] The spacer film 311 (an example of a "second insulating film") is provided on the positive Z-axis direction side of the conductive layer 42. The spacer film 311 is, for example, an oxide of silicon. The spacer film 311 includes a cylindrical portion 311a and a plate-shaped portion 311b.

[0057] The cylindrical portion 311a is provided above the surrounding portion 42b of the conductive layer 42, and extends approximately parallel to the Z-axis. In detail, a lower end of the cylindrical portion 311a forms an annular surface in contact with the upper surface 42a of the conductive layer 42. The cylindrical portion 311a surrounds the oxide semiconductor layer 70 via the gate insulating film 43. The plate-like portion 311b is provided above the connecting portion 42c of the conductive layer 42, and extends approximately parallel to the XY plane.

[0058] The insulating films 45a and 45b are respectively provided above the plate-shaped portion 311b and below the conductive layer 42. The insulating films 45a and 45b are made of, for example, an oxide of silicon.

[0059] The insulating film 45c separates two conductive layers 42 adjacent in the +X-axis direction. In particular, the insulating film 45c is located between two conductive layers 42 adjacent in the +X-axis direction, and extends substantially parallel to the Y-axis.

[0060] An upper end of the insulating film 45c is connected to the lower surface of the insulating film 45a. A lower portion of the insulating film 45c is buried in the insulating film 45b. In this embodiment, the insulating films 45a and 45c are integrally formed.

[0061] The surrounding portion 42b of the conductive layer 42 and the cylindrical portion 311a of the spacer film 311 form a hole 401 in which at least a portion of the oxide semiconductor layer 70 is accommodated. In this embodiment, the hole 401 accommodates an upper portion of the oxide semiconductor layer 70. Note that the hole 401 may be configured to accommodate the entire oxide semiconductor layer 70.

[0062] A step surface 401a facing the negative Z-axis direction is formed on the inner wall 401b of the hole 401. The step surface 401a is located between the conductive layer 42 and the upper electrode 50. The step surface 401a has an annular shape when viewed from below.

[0063] In this embodiment, the inner diameter of the lower end of the cylindrical portion 311a in the hole 401 is smaller than the inner diameter of the upper part of the surrounding portion 42b, so that the portion of the lower end face of the cylindrical portion 311a near the center forms the step surface 401a. The upper surface 42a of the conductive layer 42 and the step surface 401a are aligned.

[0064] The gate insulating film 43 surrounds an upper part of the oxide semiconductor layer 70 over the entire periphery. The gate insulating film 43 is made up of two layers, insulating films 43a and 43b. The insulating film 43a is provided closer to the oxide semiconductor layer 70 than the insulating film 43b. The upper ends of the insulating films 43a and 43b contact the metal oxide layer 50a. The insulating film 43a contains, for example, an oxide of silicon. The insulating film 43b contains, for example, a nitride of silicon.

[0065] The liner film 301 is located at least between the conductive layer 42 and the insulating film 45b and the gate insulating film 43. The liner film 301 surrounds a part of a lower portion of the oxide semiconductor layer 70 from the outside of the gate insulating film 43 over the entire periphery. In detail, a lower end of the liner film 301 contacts the lower electrode 32. An upper end of the liner film 301 contacts a step surface 401a of the hole portion 401, i.e., a lower end surface of the cylindrical portion 311a.

[0066] The liner film 301 contains, for example, at least one of silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one of oxygen and nitrogen. In this embodiment, the liner film 301 contains silicon nitride. The liner film 301 may contain silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide, strontium oxide, or the like.

[0067] [Method of manufacturing semiconductor device] A method for manufacturing the semiconductor device 30 will be described below as an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0068] First, as shown in Fig. 6 and Fig. 7, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are provided in this order above the insulating layer 35. The insulating film 45b, the conductive layer 42, and the insulating film 45ba extend substantially parallel to the XY plane. A transistor hole TH is formed that extends substantially parallel to the Z axis and penetrates the insulating film 45ba, the conductive layer 42, and the insulating film 45b, and is then cleaned. The lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0069] 8 and 9, a liner film 301 having a thickness of 3 nm or more is formed above the semiconductor device 30 by, for example, atomic layer deposition. As a result, the inner wall of the transistor hole TH is covered with the liner film 301, and the lower electrode 32 is not exposed.

[0070] 10 and 11, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30. As a result, the transistor hole TH is filled with the sacrificial amorphous silicon layer 170.

[0071] 12 and 13, the sacrificial amorphous silicon layer 170 is etched back to remove an upper part of the sacrificial amorphous silicon layer 170 and expose an upper surface of the insulating film 45ba. At this time, the upper end of the sacrificial amorphous silicon layer 170 is located above the conductive layer 42 inside the transistor hole TH, for example.

[0072] 14 and 15, the insulating film 45ba is removed by etching. Then, the liner film 301 exposed above the conductive layer 42 is removed by etching. As a result, the upper surface 42a of the conductive layer 42 and the upper end of the liner film 301 are aligned.

[0073] 16 and 17, a spacer film 311 is formed above the semiconductor device 30. As a result, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42a of the conductive layer 42 are covered with the spacer film 311.

[0074] 18 and 19, a mask is formed by performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30 by lithography, and then a groove portion 45ca is formed in the semiconductor device 30 by etching, the groove portion 45ca penetrating to the insulating film 45b and extending substantially parallel to the Y-axis. As a result, the spacer film 311 is separated into a cylindrical portion 311a and a plate-shaped portion 311b. The conductive layer 42 is also separated into a plurality of electrodes extending substantially parallel to the Y-axis and repeatedly provided in the + direction of the X-axis. The electrodes correspond to the word lines WL (see FIG. 1).

[0075] The surrounding portion 42b of the conductive layer 42 is formed by a self-align process. In detail, even if the mask formation position by the lithography method is shifted, the cylindrical portion 311a of the spacer film 311 located on the side surface of the sacrificial amorphous silicon layer 170 functions as a mask, so that the surrounding portion 42b is formed in a self-aligned manner around the transistor hole TH.

[0076] 20 and 21, insulating films 45c and 45a are integrally formed above the semiconductor device 30. Then, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing, whereby the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a.

[0077] Next, as shown in FIGS. 22 and 23, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0078] Next, an insulating film 43b is formed above the semiconductor device 30, as shown in FIGS.

[0079] Next, an insulating film 43a is formed above the semiconductor device 30, as shown in FIGS.

[0080] Next, as shown in FIGS. 28 and 29, the upper part of the semiconductor device 30 is etched back by reactive ion etching to expose the insulating film 45a and the lower electrode 32 at the bottom of the transistor hole TH.

[0081] 30 and 31, an oxide semiconductor layer 70 is formed inside the transistor hole TH. Then, the upper surface of the semiconductor device 30 is chemically and mechanically polished.

[0082] 32 and 33, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30. Then, a LPHM (Landing Pad Hard Mask) film 50e containing, for example, an oxide of silicon is formed above the metal film 50c.

[0083] 34 and 35, a mask is formed by performing film formation, resist coating, exposure, development, and peeling on the surface of the semiconductor device 30 by lithography, and then an upper electrode 50 functioning as a landing pad is formed by etching on the semiconductor device 30. The upper electrode 50 includes a barrier metal layer 51a, a barrier metal layer 50b, and a metal film 50c.

[0084] 36 and 37, an LP liner film 50d containing, for example, an oxide of silicon is formed on the upper surface of the semiconductor device 30. An insulating layer 63 is formed above the LP liner film 50d to fill the gap caused by the LP liner film 50d. The insulating layer 63 contains, for example, an oxide of silicon. Then, the upper surface of the semiconductor device 30 is chemically mechanically polished.

[0085] 38 and 39, a barrier metal layer 51a, a conductive layer 51b, and a barrier metal layer 51c are formed from bottom to top on the upper surface of the semiconductor device 30. The barrier metal layers 51a and 51c include, for example, titanium nitride. The conductive layer 51b includes, for example, tungsten.

[0086] Then, bit line hard mask (BLHM) films 66a and 66b are formed from bottom to top on the upper surface of the barrier metal layer 51c. The BLHM films 66a and 66b include, for example, a silicon nitride and a silicon oxide, respectively.

[0087] 40 and 41, a mask is formed by performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30 by lithography, and then a groove 66ca is formed in the semiconductor device 30 by etching, penetrating the insulating layer 63 and the metal film 50c and extending substantially parallel to the X-axis. As a result, the barrier metal layer 51a, the conductive layer 51b, and the barrier metal layer 51c are separated into electrodes that extend substantially parallel to the X-axis and are repeatedly provided in the +Y-axis direction. These electrodes correspond to the bit lines BL (see FIG. 1).

[0088] 3 and 4, an insulating film 66c filling the groove portion 66ca is formed above the semiconductor device 30. The insulating film 66c includes, for example, an oxide of silicon.

[0089] (effect) If the liner film 301 is not formed, when the sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 in a reducing atmosphere, the sacrificial amorphous silicon layer 170 is formed directly on the lower electrode 32 including ITO. At this time, silicon whiskers may be generated at the contact portion between the lower electrode 32 and the sacrificial amorphous silicon layer 170.

[0090] 10 and 11, when the sacrificial amorphous silicon layer 170 is formed, the inner wall of the transistor hole TH is covered with the liner film 301, and the lower electrode 32 is not exposed. This prevents the lower electrode 32 from contacting the sacrificial amorphous silicon layer 170, thereby suppressing the generation of silicon whiskers.

[0091] A second example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a second example of the first embodiment) will be described below.

[0092] (Second Example of First Embodiment) As shown in Figures 42 and 43, the semiconductor device 30 of the second example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 and 4 in that the step surface 401a in the hole 401 is located above the surface 42a of the conductive layer 42 and below the lower surface of the upper electrode 50.

[0093] [Manufacturing method of the semiconductor device 30 according to the second example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the second example of the first embodiment, the sacrificial amorphous silicon layer 170 is etched back to remove an upper portion of the sacrificial amorphous silicon layer 170 (see FIGS. 12 and 13), and then an upper portion of the liner film 301 is removed by etching, as shown in FIGS. 44 and 45. As a result, the upper end of the liner film 301 is positioned below the upper end of the sacrificial amorphous silicon layer 170. The position of the upper end of the liner film 301 can be adjusted by controlling the amount of liner film 301 removed.

[0094] Hereinafter, a third example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a third example of the first embodiment) will be described.

[0095] (Third example of the first embodiment) As shown in Figures 46 and 47, the semiconductor device 30 of the third example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 and 4 in that the upper end of the liner film 301 contacts the upper electrode 50 and no step surface 401a is formed in the hole portion 401.

[0096] [Manufacturing method of the semiconductor device 30 according to the third example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the third example of the first embodiment, after the insulating film 45ba is removed, instead of removing the liner film 301 exposed above the conductive layer 42 by etching (see Figures 14 and 15), as shown in Figures 48 and 49, only the insulating film 45ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 remains.

[0097] Hereinafter, a fourth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a fourth example of the first embodiment) will be described.

[0098] (Fourth Example of First Embodiment) As shown in Figures 50 and 51, the semiconductor device 30 of the fourth example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 and 4 in that the gate insulating film 43 does not include an insulating film 43b.

[0099] [Manufacturing method of the semiconductor device 30 according to the fourth example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the fourth example of the first embodiment, instead of forming the insulating film 43b above the semiconductor device 30 (see Figs. 24 and 25), an insulating film 43a is formed above the semiconductor device 30 as shown in Figs. 52 and 53. This makes it possible to eliminate the step of forming the insulating film 43b containing silicon nitride.

[0100] A fifth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as the fifth example of the first embodiment) will be described below.

[0101] (Fifth Example of First Embodiment) As shown in Figures 54 and 55, the semiconductor device 30 of the fifth example of the first embodiment differs from the semiconductor device 30 of the fourth example of the first embodiment shown in Figures 50 and 51 in that the step surface 401a in the hole 401 is located above the surface 42a of the conductive layer 42 and below the lower surface of the upper electrode 50.

[0102] With this configuration, the possibility of contact between the conductive layer 42 and the insulating film 43a can be reduced, making it possible to suppress an increase in gate leakage.

[0103] [Manufacturing method of the semiconductor device 30 according to the fifth example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the fifth example of the first embodiment, an upper part of the liner film 301 is removed by etching as shown in Fig. 44 and Fig. 45. Also, an insulating film 43a is formed above the semiconductor device 30 as shown in Fig. 52 and Fig. 53.

[0104] A sixth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as the sixth example of the first embodiment) will be described below.

[0105] (Sixth Example of First Embodiment) As shown in Figures 56 and 57, the semiconductor device 30 of the sixth example of the first embodiment differs from the semiconductor device 30 of the fourth example of the first embodiment shown in Figures 50 and 51 in that the upper end of the liner film 301 contacts the upper electrode 50 and no step surface 401a is formed in the hole 401.

[0106] [Manufacturing method of the semiconductor device 30 according to the sixth example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the sixth example of the first embodiment, as shown in Fig. 48 and Fig. 49, only the insulating film 45ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 is left. Also, as shown in Fig. 52 and Fig. 53, an insulating film 43a is formed above the semiconductor device 30.

[0107] A seventh example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as the seventh example of the first embodiment) will be described below.

[0108] (Seventh Example of First Embodiment) As shown in FIGS. 58 and 59, the semiconductor device 30 of the seventh example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in FIGS.

[0109] [Manufacturing method of the semiconductor device 30 according to the seventh example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the seventh example of the first embodiment, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching (see Figures 22 and 23), and then the liner film 301 is removed by etching, as shown in Figures 60 and 61.

[0110] Then, as shown in FIGS. 62 and 63, an insulating film 43b and an insulating film 43a are formed in this order above the semiconductor device 30.

[0111] In the semiconductor device 30 of the seventh example of the first embodiment, the liner film 301 is removed, and therefore, the insulating film 43b and the insulating film 43a are formed from the inner surface of the cylindrical portion 311a of the spacer film 311 to the step surface 401a and the inner surface of the surrounding portion 42b of the conductive layer 42.

[0112] Therefore, the inner surface of the insulating film 43a faces in the negative Z-axis direction and includes a step surface 43aa that is annular when viewed from below.

[0113] When the semiconductor device 30 is viewed from above, a part or all of the insulating film 43a facing the conductive layer 42 is hidden by the step surface 43aa and cannot be seen. Therefore, when the upper part of the semiconductor device 30 is etched back by reactive ion etching (see FIGS. 28 and 29), the part or all of the insulating film 43a facing the conductive layer 42 can be prevented from being damaged by the reactive ion etching. This makes it possible to suppress the occurrence of gate leakage.

[0114] An eighth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as the eighth example of the first embodiment) will be described below.

[0115] (Eighth Example of First Embodiment) As shown in Figures 64 and 65, the semiconductor device 30 of the eighth example of the first embodiment differs from the semiconductor device 30 of the seventh example of the first embodiment shown in Figures 58 and 59 in that the step surface 401a in the hole 401 is located above the surface 42a of the conductive layer 42 and below the lower surface of the upper electrode 50.

[0116] With this configuration, the step surface 43aa can be separated from the conductive layer 42, so that the occurrence of gate leakage due to electric field concentration at the step surface 43aa can be suppressed.

[0117] [Method of manufacturing the semiconductor device 30 according to the eighth example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the eighth example of the first embodiment, an upper part of the liner film 301 is removed by etching as shown in Fig. 44 and Fig. 45. The liner film 301 is removed by etching as shown in Fig. 60 and Fig. 61. Then, an insulating film 43b and an insulating film 43a are formed in this order above the semiconductor device 30 as shown in Fig. 62 and Fig. 63.

[0118] A ninth example of the semiconductor device 30 according to the first embodiment (hereinafter, may be referred to as a ninth example of the first embodiment) will be described below.

[0119] (Ninth Example of First Embodiment) As shown in Figures 66 and 67, the semiconductor device 30 of the ninth example of the first embodiment differs from the semiconductor device 30 of the seventh example of the first embodiment shown in Figures 58 and 59 in that the upper end of the liner film 301 contacts the upper electrode 50, and a step surface 401a in the hole 401 and a step surface 43aa in the insulating film 43a are not formed.

[0120] [Manufacturing method of the semiconductor device 30 according to the ninth example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the ninth example of the first embodiment, as shown in Fig. 48 and Fig. 49, only the insulating film 45ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 is left. As shown in Fig. 60 and Fig. 61, the liner film 301 is removed by etching. Then, the insulating film 43b and the insulating film 43a are formed in this order above the semiconductor device 30, as shown in Fig. 62 and Fig. 63.

[0121] [Second embodiment] A semiconductor device 30B according to the second embodiment will be described. In the second and subsequent embodiments, the description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects and advantages due to the same configuration will not be mentioned in each embodiment.

[0122] Fig. 68 shows a cross-sectional view of the semiconductor device 30B when viewed at a cross section 70ZX parallel to the ZX plane and included in the oxide semiconductor layer 70. Fig. 69 shows a cross-sectional view of the semiconductor device 30B when viewed at a cross section 70YZ parallel to the YZ plane and included in the oxide semiconductor layer 70.

[0123] As shown in Figures 68 and 69, compared to the semiconductor device 30 shown in Figures 3 to 5, the semiconductor device 30B of the second embodiment has an insulating film 501 (an example of a "fifth insulating film") instead of the liner film 301.

[0124] The insulating layer 45 includes a layer L1 including an insulating film 45a, a layer L2 including a plate-shaped portion 311b, a layer L3 (an example of a "first layer") including a plurality of conductive layers 42, a layer L4 (an example of a "second layer") including an insulating film 45b (an example of a "fourth insulating film"), and a layer L5 (an example of a "third layer") including an insulating film 501.

[0125] The layers L1, L2, L3, L4, and L5 are provided in this order from above. The insulating film 45c (an example of a "sixth insulating film") is located between two conductive layers 42 adjacent in the +X-axis direction, extends along the +Y-axis direction, and divides the layers L2, L3, L4, and L5.

[0126] The lower end of the insulating film 45c contacts the insulating layer 35 (an example of the “seventh insulating film”) provided between the two lower electrodes 32.

[0127] The insulating film 501 is provided below the insulating film 45b between two oxide semiconductor layers 70 adjacent in the +Y-axis direction (see FIG. 69).

[0128] The insulating film 501 is provided below the insulating film 45b, both side surfaces of which are sandwiched between the two insulating films 45c, between two oxide semiconductor layers 70 adjacent in the positive X-axis direction (see FIG. 68).

[0129] The insulating film 501 contains at least one element selected from the group consisting of aluminum, silicon, hafnium, lanthanum, niobium, yttrium, tantalum, vanadium, and magnesium, and oxygen. In this embodiment, the insulating film 501 is an oxide of aluminum. The etching rate of the insulating film 501 is higher than that of the insulating film 45b.

[0130] The gate insulating film 43 surrounds an upper part of the oxide semiconductor layer 70 along the circumferential direction of the oxide semiconductor layer 70. The oxide semiconductor layer 70 includes a large diameter portion 70c between a lower end 43c of the gate insulating film 43 and the lower electrode 32, the large diameter portion 70c having a diameter larger than the diameter of the gate insulating film 43 at the end 43c.

[0131] [Method of manufacturing semiconductor device] Hereinafter, a method for manufacturing the semiconductor device 30B will be described as an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0132] First, as shown in Fig. 70 and Fig. 71, an insulating film 501, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are provided in this order above the insulating layer 35. The insulating film 501, the insulating film 45b, the conductive layer 42, and the insulating film 45ba extend substantially parallel to the XY plane. A transistor hole TH is formed that extends substantially parallel to the Z axis and penetrates the insulating film 501 partway through the insulating film 45ba, the conductive layer 42, and the insulating film 45b, and is then cleaned. At the bottom of the transistor hole TH, the insulating film 501 is exposed, but the lower electrode 32 is not exposed.

[0133] 72 and 73, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30B. As a result, the transistor hole TH is filled with the sacrificial amorphous silicon layer 170.

[0134] Next, as shown in FIGS. 74 and 75, the sacrificial amorphous silicon layer 170 is etched back, whereby an upper portion of the sacrificial amorphous silicon layer 170 is removed and the upper surface of the insulating film 45ba is exposed.

[0135] Next, as shown in FIGS. 76 and 77, the insulating film 45ba is removed by etching.

[0136] 78 and 79, a spacer film 311 is formed above the semiconductor device 30B. As a result, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42a of the conductive layer 42 are covered with the spacer film 311.

[0137] 80 and 81, a mask is formed by performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30B by lithography, and then a groove portion 45ca is formed in the semiconductor device 30B by etching, the groove portion 45ca penetrating to the insulating film 501 and extending substantially parallel to the Y-axis. As a result, the spacer film 311 is separated into a cylindrical portion 311a and a plate-shaped portion 311b. The conductive layer 42 is also separated into a plurality of electrodes extending substantially parallel to the Y-axis and repeatedly provided in the + direction of the X-axis. The electrodes correspond to the word lines WL (see FIG. 1).

[0138] Next, as shown in FIGS. 82 and 83, insulating films 45c and 45a are integrally formed above the semiconductor device 30B.

[0139] Next, as shown in FIGS. 84 and 85, the upper surface of the semiconductor device 30B is chemically and mechanically polished, whereby the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a.

[0140] Next, as shown in FIGS. 86 and 87, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0141] Next, as shown in FIGS. 88 and 89, an insulating film 43b and an insulating film 43a are formed in this order above the semiconductor device 30B.

[0142] Next, as shown in FIGS. 90 and 91, the upper part of the semiconductor device 30B is etched back by reactive ion etching to expose the insulating film 45a and the insulating film 501 at the bottom of the transistor hole TH.

[0143] 92 and 93, the insulating film 501 exposed at the bottom of the transistor hole TH is wet-etched to remove a part of the insulating film 501. Since the etching rate of the insulating film 501 is higher than the etching rate of the insulating film 45b, the amount of the insulating film 501 removed is larger than the amount of the insulating film 45b removed. Then, a space 270 having a diameter larger than the diameter of the gate insulating film 43 at the end 43c is formed between the lower end 43c of the gate insulating film 43 and the lower electrode 32.

[0144] 94 and 95, the oxide semiconductor layer 70 is formed inside the transistor hole TH. At this time, the oxide semiconductor layer 70 filling the space 270 forms the large diameter portion 70c.

[0145] Next, as shown in FIGS. 96 and 97, the upper surface of the semiconductor device 30B is chemically and mechanically polished.

[0146] 98 and 99, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30B. Then, an LPHM film 50e containing, for example, an oxide of silicon is formed above the metal film 50c.

[0147] (effect) If the insulating film 501 is not formed, when the transistor hole TH is formed and then the residue inside the transistor hole TH is removed by dry or wet cleaning, the ITO contained in the lower electrode 32 may be damaged by the cleaning agent.

[0148] In contrast, in this embodiment, as shown in Figures 70 and 71, the lower electrode 32 is not exposed at the bottom of the transistor hole TH, so that the ITO contained in the lower electrode 32 can be prevented from being damaged by the cleaning agent.

[0149] In addition, if the insulating film 501 is not formed, when the sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 in a reducing atmosphere, the sacrificial amorphous silicon layer 170 is formed directly on the lower electrode 32 including ITO. At this time, silicon whiskers may be generated at the contact portion between the lower electrode 32 and the sacrificial amorphous silicon layer 170.

[0150] 72 and 73, when the sacrificial amorphous silicon layer 170 is formed, the insulating film 501 is exposed at the bottom of the transistor hole TH, instead of the lower electrode 32. This prevents the lower electrode 32 from contacting the sacrificial amorphous silicon layer 170, thereby suppressing the generation of silicon whiskers.

[0151] Furthermore, if insulating film 501 is not formed, when gate insulating film 43 is formed, conductive layer 42 containing tungsten and lower electrode 32 containing ITO are exposed, which may cause tungsten whiskers to form.

[0152] In contrast, in this embodiment, when the gate insulating film 43 is formed, the insulating film 501, not the lower electrode 32, is exposed at the bottom of the transistor hole TH as shown in Figures 88 and 89. This makes it possible to prevent both the conductive layer 42 and the lower electrode 32 from being exposed, thereby suppressing the generation of tungsten whiskers.

[0153] In addition, since the large diameter portion 70c is formed below the oxide semiconductor layer 70, the contact area between the lower end 70b of the oxide semiconductor layer 70 and the lower electrode 32 can be increased, and the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 can be reduced.

[0154] In the semiconductor device 30 of the first to ninth examples of the first embodiment, the step surface 401a is provided between the conductive layer 42 and the upper electrode 50, but the present invention is not limited to this. The step surface 401a may be provided below the surface 42a of the conductive layer 42.

[0155] (a) The second electrode contains at least one element of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0156] (b) A third insulating film is in contact with the gate electrode and the second electrode.

[0157] (c) The third insulating film contains at least one element of silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one element of oxygen and nitrogen.

[0158] (d) The third insulating film is silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide, or strontium oxide.

[0159] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Any design modifications made by a person skilled in the art to these specific examples are also included within the scope of the present disclosure as long as they have the features of the present disclosure. The elements of each of the above-mentioned specific examples and their arrangements, conditions, shapes, etc. are not limited to those exemplified and can be changed as appropriate. The combination of each of the elements of each of the above-mentioned specific examples can be changed as appropriate as long as no technical contradiction occurs. [Explanation of symbols]

[0160] 10...Semiconductor substrate 11...Circuit 20…Capacitor 21...Conductor 22...Insulating film 23...Conductor 24, 25...Capacitor electrodes 30, 30B...Semiconductor device 32…Lower electrode 33...Conductor 34, 35…Insulating layer 40...Field effect transistor 42...Conductive layer 42a...side 42b…Encirclement 42c...Connection part 43...Gate insulating film 43a, 43b...insulating film 43aa…step surface 43c...end 45…Insulating layer 45a, 45b, 45ba, 45c...insulating film 45ca…Groove 50…Top electrode 50a...metal oxide layer 50b...Barrier metal layer 50c…Metal film 70...Oxide semiconductor layer 170…Sacrificial amorphous silicon layer 270…space 70a…Top end 70b…lower end 70c…Large diameter section 101...Semiconductor memory device 301...Liner membrane 311...Spacer film 311a...Cylindrical part 311b…Plate-shaped part 401...Hole 401a…Step surface 401b…inner wall 501...insulating film L1, L2, L3, L4, L5... layers

Claims

1. an oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a gate electrode surrounding the oxide semiconductor via a first insulating film between the first end and the second end of the oxide semiconductor; a second insulating film provided on the first direction side of the gate electrode and surrounding the oxide semiconductor via the first insulating film; a hole in which at least a portion of the oxide semiconductor is accommodated is formed by the gate electrode and the second insulating film; A step surface facing in a direction opposite to the first direction is formed on an inner wall of the hole. Semiconductor device.

2. The first insulating film is in contact with the first electrode. The semiconductor device according to claim 1 .

3. the step surface is located between the gate electrode and the first electrode; The semiconductor device according to claim 1 .

4. a surface of the gate electrode on the first direction side and the step surface are aligned with each other; The semiconductor device according to claim 1 .

5. The semiconductor device includes: a third insulating film located at least between the gate electrode and the first insulating film, the third insulating film having an end on the first direction side and an end on the opposite direction side in contact with the step surface and the second electrode, respectively; The semiconductor device according to claim 1 .

6. The semiconductor device includes: a plurality of the oxide semiconductors provided along a second direction intersecting the first direction; the gate electrode extends along the second direction and surrounds the oxide semiconductors via the first insulating films, the gate electrode includes a first portion surrounding the oxide semiconductor and a second portion connecting two of the first portions; The width of the second portion is narrower than the width of the first portion. The semiconductor device according to claim 1 .

7. a plurality of oxide semiconductors each having a first end and a second end and extending in a first direction from the second end to the first end; a plurality of first electrodes respectively in contact with the first ends of the plurality of oxide semiconductors; a plurality of second electrodes respectively in contact with the second ends of the plurality of oxide semiconductors; a gate electrode extending along a second direction intersecting the first direction and surrounding the oxide semiconductors between the first end and the second end of each of the oxide semiconductors provided along the second direction, with a plurality of first insulating films interposed therebetween; a fourth insulating film provided in a direction opposite to the first direction with respect to the gate electrode; a fifth insulating film provided between two of the oxide semiconductors adjacent to each other in the second direction, in a direction opposite to the first direction with respect to the fourth insulating film; an etching rate of the fifth insulating film is greater than an etching rate of the fourth insulating film; Semiconductor device.

8. The semiconductor device includes: a plurality of the gate electrodes repeatedly provided in a third direction intersecting the first direction and the second direction; a first layer including the plurality of gate electrodes; a second layer including the fourth insulating film; a third layer including the fifth insulating film; a sixth insulating film located between two of the oxide semiconductors adjacent to each other in the third direction, extending along the second direction, and dividing the first layer, the second layer, and the third layer. The semiconductor device according to claim 7.

9. The semiconductor device includes: A seventh insulating film is provided between the second electrodes, The sixth insulating film is in contact with the seventh insulating film. The semiconductor device according to claim 8.

10. the gate electrode includes a first portion surrounding the oxide semiconductor and a second portion connecting two of the first portions; The width of the second portion is narrower than the width of the first portion. The semiconductor device according to claim 7.

11. the fifth insulating film contains at least one element selected from the group consisting of aluminum, silicon, hafnium, lanthanum, niobium, yttrium, tantalum, vanadium, and magnesium, and oxygen; The semiconductor device according to claim 7.

12. a columnar oxide semiconductor having a first end and a second end and extending in a first direction from the second end to the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a first insulating film surrounding the oxide semiconductor along a circumferential direction of the oxide semiconductor; a gate electrode surrounding the oxide semiconductor via the first insulating film between the first end and the second end of the oxide semiconductor, The oxide semiconductor is a large diameter portion having a diameter larger than a diameter of the first insulating film at an end portion of the first insulating film between the second electrode and an end portion of the first insulating film in a direction opposite to the first direction; Semiconductor device.

13. The semiconductor device according to claim 1, 6 or 11; a first capacitor electrode connected to the first electrode or the second electrode; a second capacitor electrode facing the first capacitor electrode; a dielectric film provided between the first capacitor electrode and the second capacitor electrode. Semiconductor memory device.

Images