Capacitor structure

Abstract

To provide a capacitor structure for a three-dimensional AND flash memory device.SOLUTION: A capacitor includes a substrate 100 including a capacitor array region 100a and a capacitor step region 100b, an array lower circuit (CuA) structure body 102 disposed on the substrate, a bottom part conductive layer 104 disposed on the CuA structure body, a multilayer structure body 106 disposed on the bottom part conductive layer, and a plurality of pillar structure bodies 112. The multilayer structure body includes a dielectric layer 106a and a conductive layer 106 alternately stacked. The conductive layer in the capacitor step region is disposed in a step-like shape. The pillar structure bodies are disposed in an array form in the capacitor array region, and penetrate the multilayer structure body and the bottom part conductive layer. A part of the conductive layer is electrically connected to a first common voltage source P1 and the rest of the conductive layer and the bottom part conductive layer are electrically connected to a second common voltage source P2.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor structures, and more particularly to capacitor structures. [Background technology]

[0002] For 3D-AND memory devices, as the load on the array increases, the demand for high capacitance increases accordingly. Generally, capacitance is proportional to area, so the area occupied by the 3D-AND memory device increases accordingly. In particular, for high-capacity circuits, placing capacitors in the peripheral area of ​​the array structure of the 3D-AND memory device significantly increases the chip area occupied by these capacitors. Summary of the Invention [Problem to be solved by the invention]

[0003] Techniques are provided for providing a capacitor structure that can be applied to and integrated with a 3D AND flash memory device. [Means for solving the problem]

[0004] The present disclosure provides a capacitor structure in which some of the conductive layers of a laminate structure are electrically connected to a common voltage source, and the remaining portions of the conductive layers of the laminate structure and a bottom conductive layer therebelow are electrically connected to another common voltage source.

[0005] The capacitor structure of the present disclosure includes a substrate, an under-array circuit (CuA) structure, a bottom conductive layer, a stack structure, and a plurality of pillar structures. The substrate has a capacitor array region and a capacitor stair region. The under-array circuit structure is disposed on the substrate. The bottom conductive layer is disposed on the under-array circuit structure. The stack structure is disposed on the bottom conductive layer and includes a plurality of first dielectric layers and a plurality of conductive layers stacked alternately, the plurality of conductive layers in the capacitor stair region being arranged in a stair-like manner. The pillar structures are arranged in an array in the capacitor array region and penetrate the stack structure and the bottom conductive layer. Some of the conductive layers are electrically connected to a first common voltage source, and the remainder of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

[0006] In one embodiment of the capacitor structure of the present disclosure, some of the conductive layers include odd-numbered conductive layers of the plurality of conductive layers and the remainder of the plurality of conductive layers include even-numbered conductive layers of the plurality of conductive layers.

[0007] In one embodiment of the capacitor structure of the present disclosure, at least one pair of adjacent conductive layers is electrically connected to the first common voltage source or the second common voltage source.

[0008] In one embodiment of the capacitor structure of the present disclosure, the bottom conductive layer and the lowermost conductive layer of the plurality of conductive layers are electrically connected to a first common voltage source or the second common voltage source.

[0009] In one embodiment of the capacitor structure of the present disclosure, one conductive layer connected to a first common voltage source, an adjacent conductive layer connected to a second common voltage source, and a first dielectric layer therebetween constitute a capacitive unit.

[0010] In one embodiment of the capacitor structure of the present disclosure, the capacitor structure further includes a plurality of conductive pillars located within the capacitor staircase region and disposed within the plurality of conductive layers and the bottom conductive layer, such that the plurality of conductive layers and the bottom conductive layer are electrically connected to a corresponding common voltage source via the plurality of conductive pillars.

[0011] In one embodiment of the capacitor structure of the present disclosure, each of the plurality of pillar structures includes a first insulating pillar.

[0012] In one embodiment of the capacitor structure of the present disclosure, each of the plurality of pillar structures further includes a second insulating pillar disposed within the first insulating pillar.

[0013] In one embodiment of the capacitor structure of the present disclosure, each of the multiple pillar structures further includes a semiconductor layer disposed between the first insulating pillar and the stack structure and between the first insulating pillar and the bottom conductive layer, and an insulating layer disposed between the semiconductor layer and the stack structure and between the semiconductor layer and the bottom conductive layer.

[0014] In one embodiment of the capacitor structure of the present disclosure, each semiconductor layer is electrically connected to a third common voltage source through a conductive plug.

[0015] In one embodiment of the capacitor structure of the present disclosure, the conductive layer connected to a first common voltage source, the semiconducting layer, and the insulating layer therebetween constitute a capacitive unit.

[0016] In one embodiment of the capacitor structure of the present disclosure, the conductive layer connected to a second common voltage source, the semiconducting layer, and the insulating layer therebetween constitute a capacitive unit.

[0017] In one embodiment of the capacitor structure of the present disclosure, the under-array circuit structure further includes a metal oxide semiconductor capacitor.

[0018] In one embodiment of the capacitor structure of the present disclosure, the bottom conductive layer and the stack structure have a first annular trench that penetrates the bottom conductive layer and the stack structure, and the first annular trench surrounds the stack structure in the capacitor array region and the capacitor staircase region.

[0019] In one embodiment of the capacitor structure of the present disclosure, the bottom conductive layer and the stack structure have a plurality of second annular trenches, each of which penetrates the bottom conductive layer and the stack structure, and each of which extends along a row direction of the capacitor array region and surrounds at least one row of the pillar structures and the stack structure in the capacitor staircase region to form an independent bottom conductive sector.

[0020] In one embodiment of the capacitor structure of the present disclosure, the capacitor structure further includes a second dielectric layer located between the first dielectric layers, corresponding to the position of the conductive layer in the stacking direction of the laminate structure, and disposed between adjacent conductive sectors.

[0021] In one embodiment of the capacitor structure of the present disclosure, a second dielectric layer is disposed between the conductive layers of adjacent conductive sectors.

[0022] In one embodiment of the capacitor structure of the present disclosure, the material of the second dielectric layer is different from the material of the first dielectric layer. Effect of the Invention

[0023] In the capacitor structure of the present disclosure, some of the conductive layers of the laminated structure are electrically connected to a common voltage source, while the remaining conductive layers of the laminated structure and the bottom conductive layer therebelow are electrically connected to another common voltage source. In this way, the two conductive layers and the dielectric layer therebetween can form a capacitive unit, and the bottom conductive layer of the laminated structure, the bottom conductive layer therebelow, and the dielectric layer therebetween can form a capacitive unit. [Brief description of the drawings]

[0024] [Figure 1A] 1 is a schematic cross-sectional view of a capacitor structure according to a first embodiment of the present disclosure.

[0025] [Figure 1B] 1 is a schematic top view of a capacitor structure according to a first embodiment of the present disclosure;

[0026] [Diagram 2] FIG. 2 is a schematic perspective view of a metal oxide semiconductor capacitor included in an under-array circuit structure according to one embodiment of the present disclosure.

[0027] [Diagram 3] FIG. 4 is a schematic cross-sectional view of a capacitor structure according to a second embodiment of the present disclosure.

[0028] [Figure 4] FIG. 4 is a schematic cross-sectional view of a capacitor structure according to a third embodiment of the present disclosure.

[0029] [Figure 5A] FIG. 13 is a schematic top view of a capacitor structure according to a fourth embodiment of the present disclosure.

[0030] [Figure 5B] FIG. 5B is a schematic cross-sectional view taken along line BB in FIG. 5A.

[0031] [Figure 6] 1 is a perspective view showing a laminated structure of a capacitor structure according to a first embodiment.

[0032] [Figure 7A] FIG. 13 illustrates adjusting the electrical connection relationships between the conductive layers of the stack, the bottom conductive layer, and the common voltage source to obtain a desired capacitance value. [Figure 7B] FIG. 13 illustrates adjusting the electrical connection relationships between the conductive layers of the stack, the bottom conductive layer, and the common voltage source to obtain a desired capacitance value. [Figure 7C]FIG. 13 illustrates adjusting the electrical connection relationships between the conductive layers of the stack, the bottom conductive layer, and the common voltage source to obtain a desired capacitance value. [Figure 7D] FIG. 13 illustrates adjusting the electrical connection relationships between the conductive layers of the stack, the bottom conductive layer, and the common voltage source to obtain a desired capacitance value. [Figure 7E] FIG. 13 illustrates adjusting the electrical connection relationships between the conductive layers of the stack, the bottom conductive layer, and the common voltage source to obtain a desired capacitance value. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The following embodiments are provided and described in detail with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present disclosure. The drawings are provided for the purpose of explanation only and are not drawn to scale. For ease of understanding, the same components are denoted by the same reference numerals in the following description.

[0034] As used herein, the terms "including," "comprising," "having," and the like are all open-ended terms, meaning "including but not limited to."

[0035] Additionally, directional terms such as "above," "below," and the like, referred to in the text are used only to refer to the orientation of the drawings and are not used to limit the present disclosure. Thus, "above" and "below" can be used interchangeably, and it should be understood that when an element, such as a layer or film, is disposed "over" another element, the element may be disposed directly on the other element, or there may be intervening elements disposed therebetween. On the other hand, when an element is described as being "disposed directly on" another element, there are no intervening elements disposed therebetween.

[0036] The capacitor structure of the present disclosure can be applied to and integrated with a three-dimensional AND flash memory device. Specifically, the capacitor structure of the present disclosure and the three-dimensional AND flash memory structure can be formed in the same process. The same stack structure including multiple dielectric layers and multiple conductive layers stacked alternately can be used to form the capacitor structure of the present disclosure and the three-dimensional AND flash memory structure. In other words, the capacitor structure of the present disclosure can have a main scheme similar to that of the three-dimensional AND flash memory structure. Therefore, there is no need to place additional capacitors in the peripheral area of ​​the array structure of the three-dimensional AND memory device, which can greatly save chip area. This will be described in detail below.

[0037] FIG 1A is a schematic cross-sectional view of a capacitor structure according to a first embodiment of the present disclosure. FIG 1B is a schematic top view of a capacitor structure according to a first embodiment of the present disclosure. For clarity of the drawings and convenience of illustration, a laminated structure including a plurality of dielectric layers and a plurality of conductive layers alternately laminated is omitted from FIG 1B. Also, FIG 1A may be a cross-sectional view taken along line AA of FIG 1B.

[0038] 1A and 1B, the capacitor structure 10 of this embodiment includes a substrate 100, an array under-circuit structure 102, a bottom conductive layer 104, a stack structure 106, a dielectric layer 108, a conductive pillar 110a, a conductive pillar 110b, and a pillar structure 112. In this embodiment, the substrate 100 is a silicon substrate and has a capacitor array region 100a and a capacitor staircase region 100b. The substrate 100 may also have a memory region (not shown) other than the capacitor array region 100a and the capacitor staircase region 100b. The capacitor structure 10 of this embodiment and the three-dimensional AND flash memory structure can be formed in the same manufacturing process, so that both have a similar main scheme, and the same or similar components in the capacitor array region 100a and the capacitor staircase region 100b are arranged in the memory region mentioned above.

[0039] The under-array circuit structure 102 is disposed on the substrate 100. The under-array circuit structure 102 may include transistors, interconnect structures, and a dielectric layer covering the transistors and interconnect structures, although the present disclosure is not limited thereto. The detailed structure of the under-array circuit structure 102 is well known to those skilled in the art and will not be repeated herein. In FIG. 1A, a detailed scheme of the under-array circuit structure 102 is not illustrated for clarity and convenience of illustration.

[0040] The bottom conductive layer 104 is disposed above the under-array circuit structure 102. The bottom conductive layer 104 can be a polysilicon layer, although the present disclosure is not limited thereto. In this embodiment, the bottom conductive layer 104 located in the capacitor array region 100a and the capacitor staircase region 100b can function as an electrode layer of the capacitor (described below), and the bottom conductive layer 104 located in the memory region of the substrate 100 can function as a ground layer.

[0041] The laminated structure 106 is disposed on the bottom conductive layer 104. The laminated structure 106 includes a plurality of dielectric layers 106a and a plurality of conductive layers 106b that are alternately laminated. In this embodiment, the dielectric layer 106a can be a silicon oxide layer, and the conductive layer 106b can be a metal layer, but the present disclosure is not limited thereto. Furthermore, in this embodiment, the dielectric layer 106a and the conductive layer 106b are alternately laminated on the bottom conductive layer 104, the top dielectric layer 106a covers the top conductive layer 106b, and in the capacitor staircase region 100b, these conductive layers 106b are arranged in a staircase shape. That is, in the capacitor staircase region 100b, the sidewall SW at the end of the top conductive layer 106b is located on the top surface of the lower conductive layer 106b, and a part of the top surface of the lower conductive layer 106b is exposed. Also, the top dielectric layer 106a covers a portion of the top conductive layer 106b, so that another portion of the top surface of the top conductive layer 106b is exposed. In Fig. 1A, the laminated structure 106 includes five dielectric layers 106a and four conductive layers 106b, but the number of dielectric layers 106a and conductive layers 106b is not limited by this disclosure.

[0042] The dielectric layer 108 covers the stacked structure 106. The conductive pillars 110a are disposed in the dielectric layer 108 in the capacitor staircase region 100b, and each of these conductive pillars 110a is connected to a corresponding one of the conductive layers 106b arranged in a staircase pattern. Also, the conductive pillars 110b are disposed in the dielectric layer 108 in the capacitor staircase region 100b and connected to the bottom conductive layer 104. In this embodiment, as shown in FIG. 1B, from the top view, the conductive pillars 110a connected to the first group of conductive layers 106b (e.g., the odd-numbered conductive layers 106b) and the conductive pillars 110a connected to the second group of conductive layers 106b (e.g., the even-numbered conductive layers 106b) are staggered, and the conductive pillars 110b connected to the bottom conductive layer 104 and the adjacent conductive pillars 110a connected to the bottom conductive layer 106b are staggered, but the present disclosure is not limited thereto.

[0043] In this embodiment, the capacitor structure 10 can have a main scheme similar to that of the three-dimensional AND flash memory structure located in the memory area of ​​the substrate 100, and the difference between them is that in the capacitor structure 10, a part of the conductive layer 106b of the stacked structure 106 is electrically connected to a common voltage source through the conductive pillar 110a, while the rest of the conductive layer 106b of the stacked structure 106 and the bottom conductive layer 104 are electrically connected to another common voltage source through the conductive pillar 110a and the conductive pillar 110b. One of the two common voltage sources is a high voltage source, and the other of the two common voltage sources is a low voltage source.

[0044] Specifically, in this embodiment, from bottom to top, the bottom conductive layer 104 is electrically connected to a common voltage source P1 via the conductive pillar 110b, the second conductive layer 106b and the fourth conductive layer 106b are electrically connected to a common voltage source P1 via the conductive pillar 110a, and the first conductive layer 106b and the third conductive layer 106b are electrically connected to a common voltage source P2 via the conductive pillar 110a, where the common voltage source P1 can be a low voltage source and the common voltage source P2 can be a high voltage source. In this manner, the bottom conductive layer 104, the first conductive layer 106b, and the dielectric layer 106a therebetween can constitute a capacitive unit, the first conductive layer 106b, the second conductive layer 106b, and the dielectric layer 106b therebetween can constitute a capacitive unit, the second conductive layer 106b, the third conductive layer 106b, and the dielectric layer 106a therebetween can constitute a capacitive unit, and the third conductive layer 106b, the fourth conductive layer 106b, and the dielectric layer 106b therebetween can constitute a capacitive unit.

[0045] In the case of a three-dimensional AND flash memory structure of a similar scheme, the conductive layers in the stacked structure are not connected to a common voltage source, so the conductive layers do not function as electrodes of a capacitor, and no capacitance occurs between adjacent conductive layers. That is, the three-dimensional AND flash memory structure is similar to the capacitor structure 10 in main scheme, but its function is completely different.

[0046] Also, the pillar structures 112 are arranged in an array in the capacitor array region 100a and penetrate the stack structure 106 and the bottom conductive layer 104. In this embodiment, each pillar structure 112 includes an insulating pillar 112a and an insulating pillar 112b located in the insulating pillar 112a, but the present disclosure is not limited thereto. In other embodiments, each pillar structure 112 may include only the insulating pillar 112a. The material of the insulating pillar 112a is different from the material of the insulating pillar 112b. In one embodiment, the material of the insulating pillar 112a can be silicon oxide, and the material of the insulating pillar 112b can be silicon nitride, but the present disclosure is not limited thereto. In this embodiment, the pillar structures 112 are configured to support and stabilize the stack structure 106 and do not have a conductive function.

[0047] Furthermore, in this embodiment, multiple insulating support pillars 113 are disposed in the capacitor staircase region 100b, penetrating the dielectric layer 108, the stack structure 106, and the bottom conductive layer 104. The support pillars 113 may have the same or similar scheme as the pillar structure 112. The width of the support pillars 113 may be smaller than the width of the pillar structure 112. The heights of the support pillars 113 may be the same. In this embodiment, two support pillars 113 constitute a support pillar group and are disposed next to the corresponding conductive pillar 110a or conductive pillar 110b. From a top view, the conductive pillars 110a connected to the first group of conductive layers 106b and the conductive pillars 110a connected to the second group of conductive layers 106b are arranged in a staggered pattern, and the conductive pillars 110b connected to the bottom conductive layer 104 and the adjacent conductive pillars 110a connected to the bottom conductive layer 106b are also arranged in a staggered pattern, such that these support pillar groups are also arranged in a staggered pattern within the capacitor staircase region 100b.

[0048] In this embodiment, as shown in FIG. 1B, the bottom conductive layer 104 and the stacked structure 106 have an annular trench TR. The annular trench TR penetrates the bottom conductive layer 104 and the stacked structure 106 and surrounds the stacked structure 106 in the capacitor array region 100a and the capacitor staircase region 100b, so that the bottom conductive layer 104 in the capacitor structure 10 is electrically insulated from the bottom conductive layer 104 outside the annular trench TR (e.g., the bottom conductive layer 104 in the memory region). In this way, the capacitor structure 10 can be guaranteed to have a stable capacitance without external electrical influence. For example, parasitic capacitance can be avoided.

[0049] Also, in this embodiment, as shown in FIG. 1B, the bottom conductive layer 104 and the laminated structure 106 have a plurality of lateral trenches SLT therein. In the capacitor array region 100a, each lateral trench SLT extends along a row direction (e.g., X direction) and is located between two adjacent rows of the insulating pillars 112 in a column direction (e.g., Y direction). In this manner, the laminated structure 106 can be divided into a plurality of blocks, and each block can be regarded as an independent sub-capacitor structure of the capacitor structure 10. For example, as shown in FIG. 6, the capacitor structure 10 can have four lateral trenches SLT, so that the laminated structure 106 can be divided into five blocks, that is, the capacitor structure 10 includes five sub-capacitor structures 10a. In FIG. 6, for clarity of the drawing and convenience of explanation, only the dielectric layer 106a and the conductive layer 106b in the laminated structure 106 and the bottom conductive layer 104 are illustrated.

[0050] Furthermore, in order to further increase the capacitance value of the capacitor structure 10, in one embodiment, the array under-circuit structure 102 may have a plurality of metal oxide semiconductor capacitors 20. As shown in FIG. 2, in the metal oxide semiconductor capacitor 20, the gate dielectric layer 20a and the gate 20b are sequentially disposed on the substrate 100, the contact 22 is connected to the gate 20b, and the contact 24 is connected to the substrate 100. The substrate 100 may include a doped region. Each gate 20b is electrically connected to a common voltage source through the contact 22, and the substrate 100 is electrically connected to another voltage source through the contact 24. In this way, in each metal oxide semiconductor capacitor 20, the gate 20b, the substrate 100, and the gate dielectric layer 20a therebetween may constitute a capacitance unit.

[0051] In the capacitor structure 10 of this embodiment, in addition to the metal oxide semiconductor capacitor 20, multiple dielectric layers 106a and multiple conductive layers 106b alternately stacked on the bottom conductive layer 104 can form multiple capacitor units. Therefore, compared with a 3D AND flash memory structure of a similar scheme, the capacitor structure 10 of this embodiment can have a larger capacitance. Furthermore, in this embodiment, the number of capacitor units can be increased by increasing the number of stacked dielectric layers 106a and conductive layers 106b, so that the capacitor structure of this embodiment can have a larger capacitance per unit area. In other words, a capacitor structure with a higher capacitance can be obtained without increasing the layout area.

[0052] Furthermore, for the capacitor structure 10, the electrical connection relationships between the conductive layer 106b, the bottom conductive layer 104, and the common voltage sources P1 and P2 can be adjusted according to actual requirements to obtain a desired capacitance value, as will be described in detail below.

[0053] 7A-7E show adjusting the electrical connection relationship between the conductive layer, the bottom conductive layer, and the common voltage source of the laminated structure to obtain a desired capacitance value. In FIG. 7A-7E, for clarity of the drawings and convenience of explanation, only the dielectric layer 106a and the conductive layer 106b, the bottom conductive layer 104, and the common voltage sources P1 and P2 in the laminated structure are shown. Also, in FIG. 7A-7E, the same elements as those in the first embodiment are given the same reference numerals, and the details thereof will not be further described in this specification.

[0054] 7A, the laminated structure 106 includes 32 conductive layers 106b. As described in FIG. 1A, the even-numbered conductive layers 106b and the bottom conductive layer 104 are electrically connected to a common voltage source P1, and the odd-numbered conductive layers 106b are electrically connected to a common voltage source P2. In this way, the capacitor structure 10 can have 32 groups of capacitive couplings with a total capacitance value C.

[0055] 7B, the 32nd conductive layer 106b is adjusted to be connected to a common voltage source P2, and the 31st conductive layer 106b is adjusted to be connected to a common voltage source P1, so that no capacitive unit can be formed between the 31st conductive layer 106b and the 30th conductive layer 106b. In this way, the capacitor structure 10 has 31 groups of capacitive couplings with a total capacitance of about 96.9% of C.

[0056] 7C, the first conductive layer 106b is adjusted to be connected to a common voltage source P1, so that no capacitive unit can be formed between the first conductive layer 106b and the second conductive layer 106b, and no capacitor unit can be formed between the first conductive layer 106b and the bottom conductive layer 104. In this way, the capacitor structure 10 has 30 groups of capacitive couplings with a total capacitance of about 93.8% of C.

[0057] 7D, the first conductive layer 106b is adjusted to be connected to a common voltage source P1, the 32nd conductive layer 106b is adjusted to be connected to a common voltage source P2, and the 31st conductive layer 106b is adjusted to be connected to a common voltage source P2, so that no capacitor unit can be formed between the first conductive layer 106b and the second conductive layer 104, no capacitor unit can be formed between the first conductive layer 106b and the bottom conductive layer 104, and no capacitor unit can be formed between the 31st conductive layer 106b and the 30th conductive layer 106b. In this way, the capacitor structure 10 has 29 groups of capacitive couplings with a total capacitance of about 90.6% of C.

[0058] 7E, the first conductive layer 106b and the third conductive layer 106b are adjusted to be connected to a common voltage source P1, and no capacitor unit is formed between the first conductive layer 106b and the second conductive layer 106b, no capacitor unit is formed between the second conductive layer 106b and the bottom conductive layer 104, no capacitor unit is formed between the second conductive layer 106b and the third conductive layer 106b, and no capacitor unit is formed between the third conductive layer 106b and the fourth conductive layer 106b. In this way, the capacitor structure 10 has 28 groups of capacitive couplings, with a total capacitance of about 87.5% of C.

[0059] In view of the above, the electrical connection relationships between the conductive layers of the stack, the bottom conductive layer, and the common voltage source can be easily adjusted to obtain a desired capacitance value.

[0060] 3 is a schematic cross-sectional view of a capacitor structure according to a second embodiment of the present disclosure, in which the same components as those in the first embodiment are given the same reference numerals, and the details thereof will not be described further herein.

[0061] Referring to FIG. 3, the difference between the capacitor structure 30 of this embodiment and the capacitor structure 10 is that the pillar structure 112 is replaced with a pillar structure 300 in the capacitor structure 30. Specifically, each pillar structure 300 further includes a semiconductor layer 300a and an insulating layer 300b in addition to the insulating pillar 112a and the insulating pillar 112b. The semiconductor layer 300a may include doped polysilicon. The semiconductor layer 300a is disposed between the insulating pillar 112a and the stacked structure 106, and between the insulating pillar 112a and the bottom conductive layer 104. The insulating layer 300b is disposed between the semiconductor layer 300a and the stacked structure 106, and between the semiconductor layer 300a and the bottom conductive layer 104. That is, the pillar structure 300 has a structure similar to that of the vertical channel pillar structure in the memory region, and the semiconductor layer 300a corresponds to the channel layer of the vertical channel pillar structure. However, unlike the vertical channel pillar structure, the pillar structure 300 of this embodiment is electrically floating and is not electrically connected to other components through conductive pillars.

[0062] In this embodiment, the bottom conductive layer 104 and the stacked structure 106 have an annular trench (e.g., the annular trench TR in FIG. 1B of the first embodiment) penetrating the bottom conductive layer 104 and the stacked structure 106, such that the bottom conductive layer 104 in the capacitor structure 30 is separated and electrically insulated from the bottom conductive layer 104 in another region outside the annular trench.

[0063] In the above first and second embodiments, the pillar structures 112 and the pillar structures 300 in the capacitor array region 100a do not need to be electrically connected to an external voltage source, i.e., no additional circuit layer is needed to electrically connect the pillar structures 112 and the pillar structures 300 to an external voltage source. In this way, the wiring in the capacitor array region 100a and in the peripheral region (e.g., memory region) outside the capacitor staircase region 100b can extend through the capacitor array region 100a (the space above the pillar structures 112 and the pillar structures 300), which can increase the flexibility of the wiring layout design.

[0064] 4 is a schematic cross-sectional view of a capacitor structure according to a third embodiment of the present disclosure, in which the same components as those in the second embodiment are given the same reference numerals and will not be described in detail further herein.

[0065] Referring to FIG. 4, the capacitor structure 40 of this embodiment differs from the capacitor structure 30 in that the pillar structure 300 is replaced with a pillar structure 400 in the capacitor structure 40. Specifically, each pillar structure 400 further includes two conductive plugs 400a in addition to the insulating pillar 112a, the insulating pillar 112b, the semiconductor layer 300a, and the insulating layer 300b. The conductive plugs 400a are disposed in the insulating pillar 112a and are separated from each other via the insulating pillar 112b. The conductive plugs 400a are connected to the semiconductor layer 300a, and allow the semiconductor layer 300a to be electrically connected to an external component via the conductive plugs 400a. That is, the pillar structure 400 has a structure similar to that of the vertical channel pillar structure in the memory region, the semiconductor layer 300a corresponds to the channel layer of the vertical channel pillar structure, and the conductive plugs 400a correspond to the source / drain pillars of the vertical channel pillar structure. However, unlike the vertical channel pillar structure, each semiconductor layer 300a in this embodiment is electrically connected to a common voltage source P3 via two conductive plugs 400a.

[0066] Thus, in the capacitor structure 40, two adjacent conductive layers 106b and the dielectric layer 106a therebetween can constitute a capacitive unit, the bottom conductive layer 106b, the bottom conductive layer 104 and the dielectric layer 106a therebetween can constitute a capacitive unit, and the conductive layer 106a, the semiconductor layer 300a and the insulating layer 300b therebetween can constitute a capacitive unit.

[0067] In this embodiment, the bottom conductive layer 104 and the stacked structure 106 have an annular trench (e.g., the annular trench TR in FIG. 1B of the first embodiment) penetrating the bottom conductive layer 104 and the stacked structure 106, such that the bottom conductive layer 104 in the capacitor structure 40 is separated and electrically insulated from the bottom conductive layer 104 in another region outside the annular trench.

[0068] In addition, in order to more precisely control the capacitance of the capacitor structure, the bottom conductive layer 104 located in the annular trench TR can be divided into multiple independent conductive sectors to further avoid the occurrence of parasitic capacitance. In the following, the structure of the first embodiment (having the pillar structure 112) is taken as an example, but the present invention is not limited thereto.

[0069] FIG. 5A is a schematic top view of a capacitor structure according to a fourth embodiment of the present disclosure. FIG. 5B is a schematic cross-sectional view taken along line AA in FIG. 5A. In FIG. 5A and FIG. 5B, the same components as those in the first embodiment are given the same reference numerals, and the details thereof will not be described further in this specification. Also, in FIG. 5A, the dielectric layer 106a in the laminated structure 106 is omitted for the sake of clarity of the drawings and convenience of explanation.

[0070] 5A and 5B, the bottom conductive layer 104 and the stacked structure 106 have a plurality of annular trenches TR1. Each annular trench TR1 penetrates the bottom conductive layer 104 and the stacked structure 106 and divides the bottom conductive layer 104 and the stacked structure 106 into a plurality of independent conductive sectors 500. In this embodiment, each annular trench TR1 extends along the row direction of the capacitor array region 100a and surrounds at least one row of the pillar structures 112 and the stacked structure 106 in the capacitor staircase region 100b. Furthermore, in this embodiment, in order to avoid interference between adjacent conductive sectors 500 (e.g., occurrence of parasitic capacitance), the adjacent conductive sectors 500 are separated by a space including at least two rows of the pillar structures 112, but the present disclosure is not limited thereto.

[0071] Furthermore, in this embodiment, each conductive sector 500 surrounds one row of the pillar structures 112, but the present disclosure is not limited thereto. In other embodiments, each conductive sector 500 can surround two, four, eight, or more rows of the pillar structures 112, depending on actual requirements.

[0072] Furthermore, in this embodiment, in the region between two adjacent conductive sectors 500 in the laminated structure 106, a dielectric layer 502 is disposed between adjacent dielectric layers 106a along the stacking direction, corresponding to the position of conductive layer 106b. Furthermore, the dielectric layer 502 is disposed between two rows of conductive layers 106b. The material of the dielectric layer 502 is different from the material of the dielectric layer 106a. In one embodiment, the dielectric layer 502 can be a silicon nitride layer, and the dielectric layer 106a can be a silicon oxide layer, although the present disclosure is not limited thereto.

[0073] Specifically, the conductive layer 106b in the laminated structure 106 is formed by replacing the dielectric layer 502 in the alternating stack of the dielectric layers 106a and 502 with a conductive material. The above-mentioned replacement method includes, for example, removing the dielectric layer 502 through the annular trench TR1 using hot phosphoric acid, and then filling with a conductive material. In this embodiment, the part of the dielectric layer 502 adjacent to the annular trench TR1 is removed, while the other part of the dielectric layer 502 is left. In this way, the arrangement of the annular trench TR1 allows the conductive sector 500 to be independently arranged and separated from another adjacent conductive sector 500 by the dielectric layer 502. In this way, since there is an insulating structure including the dielectric layer 106a and the dielectric layer 502 between the two adjacent conductive sectors 500, the capacitance of the capacitor structure in the two adjacent conductive sectors 500 can be more stable without being affected by mutual interference. [Industrial Applicability]

[0074] The capacitor structure of the present invention can be applied to a 3D AND flash memory device.

[0075] The above disclosure has been disclosed as an embodiment, but it is not used to limit the disclosure. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the disclosure should be defined by the scope of the attached patent application. [Explanation of symbols]

[0076] 10, 30, 40, 50: Capacitor structure 10a: Sub-capacitor structure 20: Metal oxide semiconductor capacitor 20a: Gate dielectric layer 20b: Gate 22, 24: Contacts 100: Substrate 100a: Capacitor array area 100b: Capacitor staircase area 102: Under-array circuit structure 104: Bottom conductive layer 106: Laminated structure 106a, 108, 502: dielectric layer 106b: Conductive layer 110a, 110b: conductive pillars 112, 300, 400: Pillar structure 112a, 112b: insulating pillars 300a: Semiconductor layer 300b: insulating layer 400a: Conductive plug 500: Conductive sector P1, P2, P3: Common voltage source SLT: Trench SW: Side wall TR, TR1: Circular trench

Claims

1. 1. A capacitor structure comprising: a substrate having a capacitor array region and a capacitor staircase region; an under-array circuit structure disposed on the substrate; a bottom conductive layer disposed on the under-array circuit structure; a stack structure including a plurality of first dielectric layers and a plurality of conductive layers arranged alternately on the bottom conductive layer, the stack structure including a plurality of first dielectric layers and a plurality of conductive layers arranged in a staircase pattern in the capacitor staircase region; a plurality of pillar structures arranged in an array and penetrating the stack structure and the bottom conductive layer in the capacitor array area; Equipped with A capacitor structure, wherein some of the plurality of conductive layers are electrically connected to a first common voltage source, and the remainder of the plurality of conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

2. 2. The capacitor structure of claim 1 , wherein the portion of the conductive layers comprises odd-numbered conductive layers of the plurality of conductive layers and the remainder of the plurality of conductive layers comprises even-numbered conductive layers of the plurality of conductive layers.

3. 10. The capacitor structure of claim 1, wherein at least one pair of adjacent conductive layers is electrically connected to the first common voltage source or the second common voltage source.

4. 2. The capacitor structure of claim 1, wherein the bottom conductive layer and a lowermost conductive layer of the plurality of conductive layers are electrically connected to the first common voltage source or to the second common voltage source.

5. 2. The capacitor structure of claim 1, wherein one conductive layer connected to the first common voltage source, an adjacent conductive layer connected to the second common voltage source, and the first dielectric layer therebetween constitute a capacitive unit.

6. 2. The capacitor structure of claim 1, further comprising a plurality of conductive pillars located within the capacitor staircase region and disposed on the plurality of conductive layers and the bottom conductive layer, such that the plurality of conductive layers and the bottom conductive layer are electrically connected to a corresponding common voltage source through the plurality of conductive pillars.

7. The capacitor structure of claim 1 , wherein each of the plurality of pillar structures comprises a first insulating pillar.

8. The capacitor structure of claim 7 , wherein each of the plurality of pillar structures further comprises a second insulating pillar disposed within the first insulating pillar.

9. Each of the plurality of pillar structures includes: a semiconductor layer disposed between the first insulating pillar and the stack structure and between the first insulating pillar and the bottom conductive layer; an insulating layer disposed between the semiconductor layer and the stack and between the semiconductor layer and the bottom conductive layer; The capacitor structure of claim 7 further comprising:

10. 10. The capacitor structure of claim 9, wherein each semiconductor layer is electrically connected to a third common voltage source through a conductive plug.

11. 11. The capacitor structure of claim 10, wherein the conductive layer connected to the first common voltage source, the semiconducting layer, and the insulating layer therebetween constitute a capacitive unit.

12. 11. The capacitor structure of claim 10, wherein the conductive layer connected to the second common voltage source, the semiconducting layer, and the insulating layer therebetween constitute a capacitive unit.

13. The capacitor structure of claim 1 , wherein the under-array circuit structure further comprises a metal oxide semiconductor capacitor.

14. 2. The capacitor structure of claim 1, wherein the bottom conductive layer and the stack structure have a first annular trench extending through the bottom conductive layer and the stack structure, the first annular trench surrounding the stack structure in the capacitor array region and the capacitor staircase region.

15. 2. The capacitor structure of claim 1, wherein the bottom conductive layer and the stacked structure have a plurality of second annular trenches, each of the plurality of second annular trenches penetrating the bottom conductive layer and the stacked structure, each of the plurality of second annular trenches extending along a row direction of the capacitor array region and surrounding at least one row of the pillar structures and the stacked structures in the capacitor staircase region to form an independent bottom conductive sector.

16. 16. The capacitor structure of claim 15, further comprising a second dielectric layer located between the first dielectric layers, corresponding to a position of the conductive layer in a stacking direction of the laminate structure, and disposed between adjacent conductive sectors.

17. 17. The capacitor structure of claim 16, wherein the second dielectric layer is disposed between the conductive layers of the adjacent conductive sectors.

18. 20. The capacitor structure of claim 16, wherein the material of the second dielectric layer is different from the material of the first dielectric layer.

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