Manufacturing method for power module, and test method

Abstract

To provide a manufacturing method and a test method for detecting a defect of a semiconductor element in a middle step before a power module is completed.SOLUTION: A manufacturing method for a power module in an example includes the steps of: bonding a semiconductor element 40 to a lower substrate 20; disposing an upper part bonding member 82 at an upper part of the semiconductor element; bringing a plurality of contact pins 120 of a probe device into contact with an upper bonding member; electrically connecting the probe device to a tester 200 to test the electric characteristic of the semiconductor element; and bonding an upper substrate to the semiconductor element through the upper bonding member.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a manufacturing method and a testing method for a power module, and more particularly to a manufacturing method and a testing method that can test electrical characteristics of a power module before the power module is completed. [Background technology]

[0002] A power module is a device used to convert DC power to AC power when driving a motor of a hybrid vehicle, an electric vehicle, etc. Typically, a power module includes a substrate, a power semiconductor element which is a switching element bonded to the substrate, a power lead which applies power to the power semiconductor element, and a signal lead which provides a control signal to the power semiconductor element.

[0003] After the power modules are manufactured, they are screened as good or bad by an electrical characteristic test. The electrical characteristic test performed on the power modules may be generally performed as an end-of-line (EOL) evaluation process, and may include a direct current (DC) test, an alternating current (AC) test, and a withstand voltage test.

[0004] Conventionally, electrical characteristics are tested on a power module in the form of a finished product after packaging, so defects in semiconductor devices cannot be detected in advance. In addition, even if a semiconductor device has a problem, all subsequent processes must be carried out, resulting in unnecessary consumption of materials and large process losses. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a manufacturing method and a testing method for a power module that can test electrical characteristics by contacting an inspection device with solder members arranged on a semiconductor element in order to detect defects in the semiconductor element in an intermediate process before the power module is completed. [Means for solving the problem]

[0006] A method for manufacturing a power module according to an embodiment of the present invention may include the steps of bonding a semiconductor device to a lower substrate, disposing an upper bonding member on an upper portion of the semiconductor device, contacting a probe device with the upper bonding member, electrically connecting the probe device to a tester to test electrical characteristics of the semiconductor device, and bonding an upper substrate to the semiconductor device via the upper bonding member.

[0007] In one embodiment, the method may further include a molding step performed after the step of bonding the upper substrate.

[0008] In one embodiment, the method further includes a step of wire bonding the signal leads to the semiconductor device, the wire bonding being performed between the step of testing electrical characteristics of the semiconductor device and the step of bonding the upper substrate.

[0009] In one embodiment, the semiconductor device may be bonded to the lower substrate via a lower bonding member disposed between a lower surface of the semiconductor device and the lower substrate.

[0010] In one embodiment, the lower and upper connecting members may include an electrically conductive material.

[0011] In an embodiment, the lower joining member and the upper joining member may include a material capable of at least one of soldering and sintering.

[0012] In one embodiment, the probe device includes a contact pin electrically connected to the tester and configured to contact the upper bonding member, and the contact pin can be configured to be electrically connected to the semiconductor element via the upper bonding member.

[0013] In an embodiment, the probe apparatus further includes a plate to which the contact pins are detachably coupled, and the semiconductor device and the contact pins may be configured in a plurality of pieces.

[0014] In one embodiment, the step of contacting the probe device with the upper bonding member may include adjusting the number and positions of the contact pins coupled to the plate corresponding to the number and positions of the semiconductor elements.

[0015] In one embodiment, the step of disposing an upper bonding member on the upper portion of the semiconductor element may include disposing a first upper bonding member on an upper surface of the semiconductor element, and the probe device may be configured to contact the first upper bonding member.

[0016] In one embodiment, the step of disposing an upper bonding member on the upper part of the semiconductor element may include the steps of disposing a first upper bonding member on an upper surface of the semiconductor element, disposing a spacer on the upper part of the first upper bonding member, and disposing a second upper bonding member on the upper part of the spacer, and the probe device may be configured to contact the second upper bonding member.

[0017] In an embodiment, the probe device may be configured to be electrically connected to the semiconductor device via the second upper bonding member, the spacer, and the first upper bonding member.

[0018] In one embodiment, in testing an electrical characteristic of the semiconductor device, the tester may apply an electrical signal to the semiconductor device via the probe device.

[0019] A method for testing a power module according to an embodiment of the present invention includes the steps of preparing a power module to be tested for testing electrical characteristics, contacting a probe device with the power module to be tested, and electrically connecting the probe device to a tester to apply an electrical signal to the power module to be tested. The step of preparing the power module to be tested includes the step of manufacturing a power module work in process in which a semiconductor element is bonded to a lower substrate and a bonding member is disposed on an upper portion of the semiconductor element, and the probe device may contact the bonding member disposed on the upper portion of the semiconductor element.

[0020] In one embodiment, the probe device includes contact pins provided in a number corresponding to the semiconductor element, and the contact pins can be configured to contact the bonding member when the probe device is brought into contact with the power module to be tested.

[0021] In one embodiment, the joining member may include an electrically conductive material.

[0022] In one embodiment, the finished power module may have a structure in which the semiconductor device is disposed and bonded between an upper substrate and a lower substrate, and the in-process power module may be in a state before the upper substrate is bonded to the upper part of the semiconductor device via the bonding member. Effect of the Invention

[0023] According to an embodiment of the present invention, by detecting defects in semiconductor devices before a power module is completed, material and process costs can be reduced and the cause of defects in the semiconductor devices can be easily analyzed.

[0024] In addition, according to one embodiment of the present invention, before an upper substrate is bonded to a double-sided cooled power module, a probe device is brought into contact with a bonding member disposed on an upper surface of a semiconductor device bonded to a lower substrate to perform testing, thereby enabling testing without damaging the semiconductor device. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a perspective view of a power module according to an embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view of a power module according to an embodiment of the present invention. [Diagram 3] 1 shows a probe apparatus for testing electrical characteristics of a power module according to an embodiment of the present invention. [Figure 4] 1 illustrates a method for testing a power module according to an embodiment of the present invention. [Diagram 5] 4A and 4B are schematic diagrams illustrating a state in which a probe device and a power module are in contact with each other in a method of testing a power module according to an embodiment of the present invention; [Figure 6] 4A and 4B are schematic diagrams illustrating a state in which a probe device and a power module are in contact with each other in a method of testing a power module according to an embodiment of the present invention; [Figure 7a] 4 shows a manufacturing process for a power module according to an embodiment of the present invention. [Figure 7b] 4 shows a manufacturing process for a power module according to an embodiment of the present invention. [Figure 7c] 4 shows a manufacturing process for a power module according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Since the present invention can be modified in various ways and has various embodiments, specific embodiments are shown in the drawings and described in detail. However, this is not intended to limit the present invention to the specific embodiments, and it can be understood that the present invention includes all modifications, equivalents, and alternatives included in the spirit and technical scope of the present invention.

[0027] Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another. For example, a first component may be named a second component, and similarly, the second component may be named a first component, without departing from the scope of the invention. The term "and / or" includes any combination of items listed in plural or any of items listed in plural.

[0028] The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the present invention. A singular expression includes a plural expression unless the context clearly indicates otherwise. In this application, the terms "include" or "have" specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and should be understood not to preclude the presence or additional possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0029] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as having an ideal or overly formal meaning unless expressly defined in this application.

[0030] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0031] FIG. 1 is a perspective view of a power module 1 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the power module 1 according to the embodiment of the present invention.

[0032] FIG. 2 is a diagram that illustrates a cross section of the power module 1 shown in FIG. 1 taken along line AA'.

[0033] 1 and 2, a power module 1 according to an embodiment may include a housing 10, a lower substrate 20, an upper substrate 30, a semiconductor device 40, power leads 50, signal leads 60, wires W, a spacer 70, and a joining member 80.

[0034] The housing 10 may house therein at least some of the components constituting the power module 1. For example, the housing 10 may surround the components disposed between the lower substrate 20 and the upper substrate 30 such that at least some of the lower substrate 20, the upper substrate 30, the power leads 50, and the signal leads 60 are exposed to the outside of the housing 10. The housing 10 may be a molding part made of an insulating material that molds the components constituting the power module 1.

[0035] The lower substrate 20 may include an insulating layer 22 and metal layers 21, 23 disposed on both sides of the insulating layer 22. The metal layers 21, 23 may include a first metal layer 21 bonded to an upper surface of the insulating layer 22 and a second metal layer 23 bonded to a lower surface of the insulating layer 22. The first metal layer 21 of the lower substrate 20 may be in electrical contact with a lower surface of the semiconductor element 40. At least a portion (e.g., a lower surface) of the second metal layer 23 of the lower substrate 20 may be located outside the housing 10 and exposed. Although not shown, the second metal layer 23 of the lower substrate 20 may be in contact with a cooling channel for cooling the power module 1.

[0036] The upper substrate 30 may include an insulating layer 32 and metal layers 31, 33 disposed on both sides of the insulating layer 32. The metal layers 31, 33 may include a first metal layer 33 bonded to a lower surface of the insulating layer 32 and a second metal layer 31 bonded to an upper surface of the insulating layer 32. The first metal layer 33 of the upper substrate 30 may be in electrical contact with an upper surface of the semiconductor element 40 via a first spacer 71. At least a portion (e.g., an upper surface) of the second metal layer 31 of the upper substrate 30 may be located outside the housing 10 and exposed. Although not shown, the second metal layer 31 of the upper substrate 30 may be in contact with a cooling channel for cooling the power module 1.

[0037] The lower substrate 20 and the upper substrate 30 may be double bonded copper (DBC) substrates. For example, the upper substrate 30 and the lower substrate 20 may have insulating layers 22 and 32 made of a ceramic material and metal layers 21, 23, 31 and 33 made of a copper material, but are not limited thereto.

[0038] The lower substrate 20 and the upper substrate 30 may be electrically connected via a spacer 70. For example, the first metal layer 21 of the lower substrate 20 and the first metal layer 33 of the upper substrate 30 may be electrically connected via a second spacer 72. A portion of the first metal layer 21 of the lower substrate 20 electrically connected to the lower surface of the semiconductor device 40 and a portion of the first metal layer 21 of the lower substrate 20 electrically connected to the first metal layer 33 of the upper substrate 30 via the second spacer 72 may be configured to be electrically insulated.

[0039] The semiconductor device (or semiconductor chip) 40 may be disposed between the lower substrate 20 and the upper substrate 30. For example, the semiconductor device 40 may be bonded to a first metal layer 21 of the lower substrate 20 and positioned between the lower substrate 20 and the upper substrate 30. The semiconductor device 40 may be electrically connected to the upper substrate 30 and the lower substrate 20. For example, the semiconductor device 40 may have power terminals (not shown) formed on an upper surface and a lower surface, through which a current for power conversion is input and output, respectively, and the power terminal formed on the lower surface may be electrically connected to the lower substrate 20 and the power terminal formed on the upper surface may be electrically connected to the upper substrate 30. The semiconductor device 40 may be formed of, but is not limited to, an IGBT (Insulated Gate Bipolar Transistor) and a diode.

[0040] A lower surface of the semiconductor element 40 may be joined to the first metal layer 21 of the lower substrate 20 via a lower bonding member 81. An upper surface of the semiconductor element 40 may be joined to the first spacer 71 via an upper bonding member (e.g., a first upper bonding member) 82. For example, the semiconductor element 40 may be electrically connected to the first metal layer 33 of the upper substrate 30 via the first spacer 71. The semiconductor element 40 may be electrically connected to the signal lead 60 via a wire W.

[0041] The power lead 50 is connected to the semiconductor element 40 to transmit and receive high voltage current. The power lead 50 may be electrically connected to the semiconductor element 40. The power lead 50 may be configured in a plurality of pieces. At least a portion of the power lead 50 may be electrically connected to the first metal layer 21 of the lower substrate 20 via a bonding member 80. For example, the power lead 50 may be bonded to an upper surface of the first metal layer 21 of the lower substrate 20 together with the semiconductor element 40. A portion of the power lead 50 may be exposed to the outside of the housing 10 to transmit and receive power to and from the outside of the power module 1. The power lead 50 may extend from the inside of the housing 10 to the outside of the housing 10 such that at least a portion of the power lead 50 is exposed to the outside of the housing 10.

[0042] The signal lead 60 may transmit a control signal for controlling the semiconductor device 40 from the outside of the power module 1. The signal lead 60 may be composed of a plurality of signal leads. The signal lead 60 may extend from the inside of the housing 10 to the outside of the housing 10 such that at least a portion of the signal lead 60 is exposed to the outside of the housing 10. The signal lead 60 may be electrically connected to the semiconductor device 40 via a wire W.

[0043] The spacer 70 may include a first spacer 71 disposed between the upper substrate 30 and the semiconductor device 40 and a second spacer 72 disposed between the upper substrate 30 and the lower substrate 20 .

[0044] The first spacer 71 may have an upper surface bonded to the first metal layer 33 of the upper substrate 30 and a lower surface bonded to the semiconductor device 40 to form an electrical connection between the upper substrate 30 and the semiconductor device 40. For example, the lower surface of the first spacer 71 may be electrically and physically bonded to the semiconductor device 40 (e.g., the upper surface of the semiconductor device 40) via a first upper bonding member 82, and the upper surface of the first spacer 71 may be electrically and physically bonded to the first metal layer 33 of the upper substrate 30 (e.g., the lower surface of the first metal layer 33) via a second upper bonding member 83.

[0045] The second spacer 72 may have an upper surface bonded to the first metal layer 33 of the upper substrate 30 and a lower surface bonded to the first metal layer 21 of the lower substrate 20 to form an electrical connection between the upper substrate 30 and the lower substrate 20. For example, the upper and lower surfaces of the second spacer 72 may be electrically and physically bonded to the first metal layer 33 of the upper substrate 30 (e.g., the lower surface of the first metal layer 33) and the first metal layer 21 of the lower substrate 20 (e.g., the upper surface of the first metal layer 21) via a bonding member 80, respectively.

[0046] The joining member 80 can electrically and physically join components arranged on both sides of the joining member 80. For example, the components arranged on both sides of the joining member 80 can be electrically connected and mechanically (or physically) joined at the same time via the joining member 80. The joining member 80 can include various materials capable of soldering and / or sintering. For example, the joining member 80 can correspond to a solder member and / or a sintered member.

[0047] 1 and 2, the power module 1 according to an embodiment may be a double-sided cooling (DSC) power module configured to have a semiconductor device 40 disposed between an upper substrate 30 and a lower substrate 20. However, the structure of the power module 1 is not limited to the embodiment shown in the drawings, and may be modified in various ways within a range in which a structure in which the semiconductor device 40 is disposed between the upper and lower substrates 20 and 30 and heat generated by the semiconductor device 40 is cooled by a cooler (not shown) provided outside the two substrates can be realized.

[0048] FIG. 3 shows a probe apparatus 100 for testing electrical characteristics of a power module 1 according to an embodiment of the present invention.

[0049] 3, a probe apparatus 100 according to an embodiment can be used to contact at least a portion of a power module 1 to inspect and test electrical characteristics of the power module 1. The probe apparatus 100 can electrically couple and connect the power module 1 to a test apparatus (or tester).

[0050] The probe apparatus 100 according to one embodiment may include a plate 110 and a number of contact pins 120 disposed on the plate 110 .

[0051] The plate 110 has a plurality of contact pins 120 attached thereto, and the plurality of contact pins 120 may be coupled to one surface of the plate 110. For example, the plate 110 may correspond to a probe card.

[0052] The contact pins 120 can be coupled to the plate 110 as an electrical connector. The contact pins 120 can contact some components (e.g., the semiconductor device 40) of the power module 1 to be tested. For example, the contact pins 120 can include pogo pins or spring-loaded pins.

[0053] The contact pins 120 may electrically connect the tester and the power module 1. The contact pins 120 may be electrically connected to the tester while being coupled to the plate 110. For example, the contact pins 120 may be electrically connected to the tester using separate electric wires. However, the manner in which the contact pins 120 are electrically connected to the tester is not limited to the above examples.

[0054] According to various embodiments, the contact pins 120 may be electrically connected to the tester through the plate 110. For example, the plate 110 may be formed of a circuit board and electrically connected to the tester, and the contact pins 120 may be electrically connected to and connected to the plate 110, thereby being electrically connected to the tester through the plate 110.

[0055] The contact pins 120 may be detachably coupled to the plate 110. For example, the probe apparatus 100 may be configured to change the number of the contact pins 120 and the positions at which the contact pins 120 are coupled to the plate 110 in response to the positions and number of the semiconductor elements 40 arranged in the power module 1 to be tested. The plate 110 may be formed with a plurality of coupling holes (not shown) to which the contact pins 120 may be coupled, and the contact pins 120 may be coupled to coupling holes that can contact the semiconductor elements 40 among the plurality of coupling holes in response to the positions and / or number of the semiconductor elements 40. For example, in the process of testing the power module 1 using the probe apparatus 100, the number and / or positions of the contact pins 120 may be appropriately changed depending on the number and / or positions of the semiconductor elements 40.

[0056] FIG. 4 shows a method for testing a power module 1 according to an embodiment of the present invention, and FIG. 5 shows a schematic diagram of a state in which a probe device 100 and a power module 1 are in contact with each other in the method for testing a power module 1 according to an embodiment of the present invention.

[0057] 4 and 5, a method for testing electrical characteristics of a power module 1 according to an embodiment may be performed in an intermediate process before the manufacture of the power module 1 shown in FIGs. 1 and 2 is completed. In describing FIGs. 4 and 5, reference will be made to FIGs. 1 and 2 together.

[0058] Hereinafter, the testing method of the power module 1 according to one embodiment will be described as a method of testing DC characteristics of the semiconductor device 40 of the power module 1, however, the electrical characteristics and items to be evaluated through the testing method of the present invention are not limited to DC characteristics.

[0059] The DC test is a test in which a preset voltage and / or current is applied to the power module 1 to measure DC characteristics such as open / short, input current, output voltage, and power supply current, thereby evaluating whether the semiconductor elements 40 in the power module 1 are operating correctly.

[0060] In one embodiment of the method for testing a power module 1, the power module 1 to be tested (DUT; Device Under Test) may be in a work-in-process state before the double-sided cooled power module 1 of Figures 1 and 2 is completed.

[0061] The power module 1 to be tested may be a power module work-in-progress (e.g., the power module work-in-progress shown in 703 of FIG. 7b) in which at least one semiconductor element 40 is bonded to a lower substrate 20 and a bonding member 80 for bonding an upper substrate (e.g., upper substrate 30 of FIG. 1 and FIG. 2) and / or a spacer (e.g., spacer 70 of FIG. 2) is disposed on the upper portion of the semiconductor element 40.

[0062] For example, the power module 1 to be tested may be in a state in which the lower substrate 20 and the semiconductor device 40 are bonded (e.g., first soldering and / or sintering) via a lower bonding member 81 disposed between the lower substrate 20 and the lower surface 41 of the semiconductor device 40, and an upper bonding member (e.g., first upper bonding member) 82 is disposed on the upper surface 42 of the semiconductor device 40 before the upper substrate 30 (or the upper substrate 30 and the first spacer 71) is bonded (e.g., second soldering and / or sintering) to the semiconductor device 40. Here, the upper bonding member 82 may be bonded to the upper surface 42 of the semiconductor device 40 by melting and solidifying together with the lower bonding member 81 during the process of bonding the semiconductor device 40 and the lower substrate 20.

[0063] The semiconductor elements 40 bonded to the lower substrate 20 may be multiple in number. Also, the number and / or positions of the semiconductor elements 40 are not limited to those in the illustrated embodiment.

[0064] The method for testing the power module 1 may include the steps of preparing the power module 1 to be tested, contacting the probe device 100 (e.g., a plurality of contact pins 120) with the upper bonding member 82, and applying an electrical signal for testing. Here, the step of preparing the power module 1 to be tested may refer to the step of manufacturing a work-in-progress in which the upper bonding member 82 is disposed on the upper part of the semiconductor element 40 bonded to the lower substrate 20. According to various embodiments, at least some steps of the method for testing the power module 1 may be included in a method for manufacturing the power module 1 (e.g., see FIGS. 7a, 7b, and 7c).

[0065] In the method for testing the power module 1, the probe apparatus 100 may be configured such that the plurality of contact pins 120 contact the upper bonding member 82 disposed on the upper surface 42 of the semiconductor device 40 on the upper portion of the power module 1 under test. The plurality of contact pins 120 may be electrically connected to the semiconductor device 40 by contacting the electrically conductive upper bonding member 82. For example, the plurality of contact pins 120 may transmit an electrical signal applied from the DC tester 200 to the semiconductor device 40 via the upper bonding member 82.

[0066] The probe apparatus 100 may be electrically connected to the DC tester 200. For example, the probe apparatus 100 may have a shape in which the contact pins 120 are disposed penetrating from the lower surface to the upper surface of the plate 110, and some of the contact pins 120 penetrating the upper surface of the plate 110 may be electrically connected to the DC tester 200. The contact pins 120 may be electrically connected to the DC tester 200 via conductors. However, the electrical connection between the contact pins 120 and the DC tester 200 is not limited to the illustrated embodiment.

[0067] The DC tester 200 can apply and sense electrical signals for DC testing to the semiconductor device 40 through the contact pins 120. For example, the contact pins 120 of the probe device 100 are brought into contact with the upper bonding member 82 disposed on the upper surface 42 of the semiconductor device 40, and then the DC tester 200 sets current and / or voltage application conditions according to each terminal circuit and applies the set current and / or voltage to perform testing. The DC test process for semiconductors is a well-known technique widely known in the art, and therefore a detailed description of a more specific method will be omitted.

[0068] According to the testing method of the present invention, a probe device 100 is brought into contact with the bonding member 80 arranged on the upper part of the semiconductor element 40 in an intermediate process before the power module 1 is completed to test the electrical characteristics, so that defects can be detected early in the manufacturing process without damaging or breaking the semiconductor element 40.

[0069] FIG. 6 is a schematic diagram showing a state where a probe device 100 and a power module 1 are in contact with each other in a method for testing a power module 1 according to an embodiment of the present invention.

[0070] Referring to FIG. 6, unlike the embodiment shown in FIG. 5, in a method for testing a power module 1, a probe device 100 may be configured to contact an upper bonding member (e.g., a second upper bonding member) 83 arranged on the upper part of the first spacer 71 while the first spacer 71 is bonded to the upper surface 42 of the semiconductor element 40.

[0071] 6, the power module 1 to be tested may be in a state in which the lower substrate 20, the semiconductor device 40, and the first spacer 71 are bonded (e.g., first soldering and / or sintering) in a stacked state via a lower bonding member 81 disposed between the lower surface 41 of the semiconductor device 40 and the lower substrate 20, and a first upper bonding member 82 disposed between the upper surface 42 of the semiconductor device 40 and the first spacer 71, and a second upper bonding member 83 is disposed on the upper surface 42 of the first spacer 71 before the upper substrate 30 is bonded (e.g., second soldering and / or sintering). Here, the second upper bonding member 83 may be bonded to the upper surface of the first spacer 71 as it melts and solidifies together with the lower bonding member 81 and the first upper bonding member 82 during the process of bonding the semiconductor device 40, the lower substrate 20, and the first spacer 71.

[0072] 6, the contact pins 120 may be configured to contact the second upper bonding member 83 disposed on the upper surface of the first spacer 71. The contact pins 120 may be electrically connected to the semiconductor device 40 via the first spacer 71 and the first upper bonding member 82 by contacting the second upper bonding member 83 having electrical conductivity. For example, the contact pins 120 may transmit an electrical signal applied from the DC tester 200 to the semiconductor device 40 via the second upper bonding member 83, the first spacer 71, and the first upper bonding member 82.

[0073] 7a, 7b and 7c show a method for manufacturing a power module 1 according to an embodiment of the present invention.

[0074] 7a, 7b and 7c, the method for manufacturing the power module 1 according to an embodiment of the present invention may include the test method (or test process) of the power module 1 described with reference to FIGS. 4 to 6.

[0075] A manufacturing method of a power module 1 according to one embodiment of the present invention may include step 701 of mounting components on a lead frame, step 702 of bonding a semiconductor device to a lower substrate, step 703 of arranging a bonding member on the upper part of the semiconductor device, step 704 of testing electrical characteristics by contacting a probe device with the bonding member on the upper part of the semiconductor device, step 705 of bonding the upper substrate, and step 706 of molding.

[0076] Step 702 of bonding the semiconductor device to the lower substrate and step 703 of disposing a bonding member on the semiconductor device may be performed simultaneously. For example, a lower bonding member 81 may be disposed between the lower substrate 20 and the semiconductor device 40, and an upper bonding member 80 may be disposed on the semiconductor device 40. Heat may be applied to melt and solidify the bonding member 80 in a state where the semiconductor device 40 is bonded to the lower substrate 20 and the bonding member 80 may be disposed on the semiconductor device 40 at the same time. However, this is merely an example, and the manufacturing method is not limited to the above.

[0077] In step 704 of contacting the bonding member on the top of the semiconductor element with a probe device to test electrical characteristics, the bonding member 80 disposed on the top of the semiconductor element 40 can be a first top bonding member 82 or a second top bonding member 83, which can be determined according to various embodiments of the manufacturing method.

[0078] For example, in the step 703 of disposing a bonding member on the semiconductor device according to the manufacturing method, only the first upper bonding member 82 may be disposed on the semiconductor device 40, and in this case, the probe device 100 may contact the first upper bonding member 82. In addition, in this case, the step 705 of bonding the upper substrate is performed in such a manner that the upper substrate 30 with the first spacer 71 bonded thereto is bonded to the semiconductor device 40.

[0079] In another example, in step 703 of disposing a bonding member on the semiconductor device according to the manufacturing method, a first upper bonding member 82, a first spacer 71, and a second upper bonding member 83 may be sequentially stacked on the upper part of the semiconductor device 40, and in this case, the probe device 100 may contact the second upper bonding member 83. Also, in this case, step 705 of bonding the upper substrate is performed in such a manner that the upper substrate 30 is bonded to the first spacer 71 in a state where it is bonded to the upper part of the semiconductor device 40.

[0080] In the molding step 706, an epoxy molding compound (EMC) is melted and then cured to form a housing (e.g., the housing 10 in FIG. 1) for enclosing and protecting the semiconductor device 40. For example, the molding step 706 may correspond to an encapsulation process.

[0081] Although not shown, in the method for manufacturing the power module 1 according to the embodiment, a process of connecting the signal lead 60 and the semiconductor element 40 with a wire W may be performed before the step 705 of bonding the upper substrate.

[0082] Also, although not shown, in the method of manufacturing the power module 1, a trimming process may be performed after the molding step 706 to remove dambars that maintain the shape of the lead frame 90 to separate the power leads 50 and the signal leads 60 from the lead frame 90. For example, as the trimming process is performed in the state of step 706 of Fig. 7c, the power module 1 may have the shape shown in Fig. 1.

[0083] On the other hand, the manufacturing methods shown in Figures 7a, 7b and 7c are illustrative, and the manufacturing method of the power module 1 according to one embodiment is not limited to the illustrated embodiment, and some steps may be omitted and / or added, or some steps may be merged and / or separated depending on various embodiments.

[0084] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible without departing from the technical idea of ​​the present invention described in the claims.

[0085] In addition, in the embodiments of the present invention, some components may be omitted, and the configurations of the embodiments may be combined with each other. [Explanation of symbols]

[0086] 1 Power Module 10 housing 20 lower board 30 Upper substrate 40 Semiconductor element 41 Lower surface 42 Upper surface 50 Power Leads 60 Signal Leads 70 Spacer 71 First spacer 72 second spacer 80 joining member 81 lower joint member 82 first upper joint member 83 second upper joining member 90 lead frame W Wire 100 Probe device 110 Plate 120 Multiple Contact Pins 200 Tester

Claims

1. bonding a semiconductor device to a lower substrate; disposing an upper bonding member on an upper portion of the semiconductor device; contacting a probe device with the upper joint member; electrically connecting the probe device to a tester to test electrical characteristics of the semiconductor device; and bonding an upper substrate to the semiconductor element via the upper bonding member.

2. The method of claim 1 , further comprising a molding step performed after the step of bonding the upper substrate.

3. The method further includes the step of wire-bonding a signal lead to the semiconductor element, 2. The method of claim 1, wherein the wire bonding is performed between the step of testing electrical characteristics of the semiconductor device and the step of bonding the upper substrate.

4. The method for manufacturing a power module according to claim 1 , wherein the semiconductor element is bonded to the lower substrate via a lower bonding member disposed between a lower surface of the semiconductor element and the lower substrate.

5. The method for manufacturing a power module according to claim 4 , wherein the lower joining member and the upper joining member include a material having electrical conductivity.

6. The method for manufacturing a power module according to claim 5 , wherein the lower joining member and the upper joining member include a material capable of at least one of soldering and sintering.

7. the probe device includes a contact pin electrically connected to the tester and configured to contact the upper joint member; The method of claim 1 , wherein the contact pin is configured to be electrically connected to the semiconductor element through the upper joining member.

8. The probe device further includes a plate to which the contact pin is detachably coupled; The method for manufacturing a power module according to claim 7 , wherein the semiconductor element and the contact pin are constituted by a plurality of pieces.

9. The step of contacting the probe device with the upper joint member comprises: The method of claim 8 , further comprising adjusting the number and positions of the contact pins coupled to the plate in accordance with the number and positions of the semiconductor elements.

10. The step of disposing an upper bonding member on an upper portion of the semiconductor device includes: disposing a first upper bonding member on an upper surface of the semiconductor device; The method for manufacturing a power module according to claim 1 , wherein the probe device is configured to contact the first upper joining member.

11. The step of disposing an upper bonding member on an upper portion of the semiconductor device includes: disposing a first upper bonding member on an upper surface of the semiconductor chip; disposing a spacer on the first upper joining member; and disposing a second upper joining member on an upper portion of the spacer; The method for manufacturing a power module according to claim 1 , wherein the probe device is configured to contact the second upper joining member.

12. The method of claim 11 , wherein the probe device is configured to be electrically connected to the semiconductor device via the second upper joining member, the spacer, and the first upper joining member.

13. 2. The method of claim 1, wherein in the step of testing the electrical characteristics of the semiconductor device, the tester applies an electrical signal to the semiconductor device through the probe device.

14. providing a test power module for testing electrical characteristics; contacting a probe device with the power module under test; electrically connecting the probe device to a tester and applying an electrical signal to the power module under test; The step of preparing a power module to be tested includes: The method includes manufacturing a power module in a state in which a semiconductor element is bonded to a lower substrate and a bonding member is disposed on an upper portion of the semiconductor element, The method for testing a power module, wherein the probe device contacts the bonding member disposed on an upper portion of the semiconductor element.

15. the probe device includes contact pins provided in a number corresponding to the semiconductor device; The method for testing a power module according to claim 14, wherein the contact pins are configured to contact the joining members in the step of contacting the probe device with the power module to be tested.

16. The method for testing a power module according to claim 14 , wherein the joining member includes a material having electrical conductivity.

17. The completed power module has a structure in which the semiconductor device is disposed and bonded between an upper substrate and a lower substrate, 15. The power module testing method according to claim 14, wherein the power module in-process is in a state before the upper substrate is bonded to the upper portion of the semiconductor element via the bonding member.

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