Semiconductor module and manufacturing method for the same

Abstract

To provide a semiconductor module in which the parasitic capacitance is reduced by effectively shortening a current path, and a manufacturing method for the same.SOLUTION: In a semiconductor module 100, a chip 120 is disposed on a substrate 110 and electrically connected to the substrate 110. A signal assembly 130 is disposed in a normal direction of the substrate 110 on the substrate 110 and is electrically connected to the substrate 110. A first molding material 140 is disposed on the substrate 110. The first molding material 140 covers at least the chip 120, and has at least one opening part. The opening part exposes the signal assembly 130. A second molding material 150 is disposed on the substrate 110 and fills the opening part. The second molding material 150 exists between the signal assembly 130 and the first molding material 140, and covers the signal assembly 130. At least one contact interface B is formed between the second molding material 150 and the first molding material 140.SELECTED DRAWING: Figure 1D

Description

[Technical field]

[0001] The present invention relates to a module and a manufacturing method thereof, and more particularly to a semiconductor module and a manufacturing method thereof. [Background technology]

[0002] In order to increase the power density of power devices and achieve low-cost requirements, multiple semiconductor devices are often combined in a package structure to form a power module, which provides high output power in a small package structure. Generally, the signal source of the power module protrudes from the side of the package. However, this design increases the current path, which increases the parasitic inductance, affecting the performance of the device. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a semiconductor module that can effectively shorten the current path and reduce the parasitic inductance, and has better structural reliability.

[0004] The present invention further provides a method for manufacturing a semiconductor module. [Means for solving the problem]

[0005] The semiconductor module of the present invention includes a substrate, at least one chip, at least one signal assembly, a first molding material, and a second molding material. The at least one chip is disposed on the substrate and electrically connected to the substrate. The at least one signal assembly is disposed on the substrate in a normal direction of the substrate and electrically connected to the substrate. The first molding material is disposed on the substrate. The first molding material at least covers the at least one chip and has at least one opening, and the at least one opening exposes the at least one signal assembly. The second molding material is disposed on the substrate and fills the at least one opening. The second molding material is located between the at least one signal assembly and the first molding material and covers the at least one signal assembly. At least one contact interface is formed between the second molding material and the first molding material.

[0006] In one embodiment of the present invention, the at least one signal assembly includes at least one power semiconductor package signal connection element and at least one embedded signal pin. The at least one power semiconductor package signal connection element is disposed on a substrate. The first molding material exposes the at least one power semiconductor package signal connection element. The at least one embedded signal pin is inserted into the at least one power semiconductor package signal connection element. The second molding material covers a portion of the at least one power semiconductor package signal connection element and the at least one embedded signal pin.

[0007] In one embodiment of the present invention, the semiconductor module further includes at least one connector electrically connecting the at least one chip and the substrate.

[0008] In one embodiment of the invention, a substrate has opposing upper and lower surfaces and includes a plurality of pins, each pin including an inner pin portion and an outer pin portion, a first molding material covering the upper surface of the substrate and the inner pin portion of each pin, and an outer pin portion of each pin protruding from the first molding material.

[0009] The manufacturing method of the semiconductor module of the present invention includes the following steps. A substrate is provided. At least one chip is disposed on the substrate. The at least one chip is electrically connected to the substrate. At least one signal assembly is disposed on the substrate in a normal direction of the substrate, and the at least one signal assembly is electrically connected to the substrate. A first molding material is formed on the substrate. The first molding material at least covers the at least one chip and has at least one opening. The at least one opening exposes the at least one signal assembly. A second molding material is formed on the substrate and fills the at least one opening. The second molding material is located between the at least one signal assembly and the first molding material and covers the at least one signal assembly. At least one contact interface is formed between the second molding material and the first molding material.

[0010] In one embodiment of the present invention, the at least one signal assembly includes at least one power semiconductor package signal connection element and at least one embedded signal pin. Before the first molding material is formed on the substrate, the at least one power semiconductor package signal connection element is disposed on the substrate. When the first molding material is formed on the substrate, the first molding material exposes the at least one power semiconductor package signal connection element. Before the second molding material is formed on the substrate, the at least one embedded signal pin is inserted into the at least one power semiconductor package signal connection element. When the second molding material is formed on the substrate, the second molding material covers the at least one power semiconductor package signal connection element and a portion of the at least one embedded signal pin.

[0011] In one embodiment of the present invention, the method for manufacturing a semiconductor module further includes forming at least one connector before the first molding material is formed on the substrate, the at least one connector electrically connecting the at least one chip and the substrate.

[0012] In one embodiment of the invention, a substrate has opposing top and bottom surfaces and includes a plurality of pins. When a first molding material is formed on the substrate, the first molding material covers the top surface of the substrate and a portion of each pin, where the portion of each pin is defined as an inner pin portion of each pin, and another portion of each pin protrudes from the first molding material, where the other portion of each pin is defined as an outer pin portion of each pin.

[0013] In one embodiment of the present invention, a method for producing a second molding material on a substrate includes filling at least one opening with a liquid epoxy resin.

[0014] In one embodiment of the present invention, the substrate comprises a Direct Bonded Copper (DBC) substrate, an Insulated Metal Substrate (IMS) substrate, or an active metal bonding (AMB) substrate. Effect of the Invention

[0015] Based on the above, in the design of the semiconductor module of the present invention, the signal assembly is disposed on the substrate in the normal direction of the substrate and electrically connected to the substrate. The first molding material covers the chip and exposes the signal assembly, and the second molding material covers the signal assembly, and a contact interface is formed between the second molding material and the first molding material. This design effectively shortens the current path between the substrate and the signal assembly and reduces the parasitic inductance. Because the first molding material and the second molding material are formed as independent members, this design can effectively balance the packaging stress and increase the tensile force of the signal assembly, thereby improving the structural reliability of the semiconductor module of the present invention.

[0016] In order to make the foregoing more easily understandable, several embodiments are described in detail below with reference to the drawings. [Brief description of the drawings]

[0017] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Figure 1A] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor module according to an embodiment of the present invention. [Figure 1B] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor module according to an embodiment of the present invention. [Figure 1C] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor module according to an embodiment of the present invention. [Figure 1D] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor module according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] 1A to 1D are schematic cross-sectional views showing a method for manufacturing a semiconductor module according to an embodiment of the present invention. Regarding the method for manufacturing a semiconductor module in this embodiment, first, referring to FIG. 1A, a substrate 110 is provided. The substrate 110 is, for example, a direct bonded copper (DBC) substrate, an insulated metal substrate (IMS), or an active metal bond (AMB) substrate, but is not limited thereto. In this embodiment, the substrate 110 has an upper surface S1 and a lower surface S2 facing each other, and the substrate 110 includes a plurality of pins 115 (two pins 115 are shown in schematic form). The pins 115 are each disposed on the upper surface S1 of the substrate 110.

[0019] 1A, at least one chip 120 (two chips 120 are shown diagrammatically) is disposed on the substrate 110. The chips 120 are spaced apart from each other on the top surface S1 of the substrate 110 and are located between the pins 115. The chips 120 may be, for example, an insulated gate bipolar transistor (IGBT) or a silicon carbide metal oxide semiconductor field-effect transistor diode (SiC MOSFET Diode).

[0020] 1A again, at least one connector 125 (four connectors 125 are shown in schematic form) is formed. The connector 125 electrically connects the chip 120 and the substrate 110. That is, the chip 120 is electrically connected to the substrate 110 via the connector 125. Here, the connector 125 may be, for example, but is not limited to, a welding wire or a metal clip.

[0021] Next, referring again to FIG. 1A, at least one signal assembly 130 (two signal assemblies 130 are shown in schematic form) is disposed on the substrate 110 along the normal direction N of the substrate 110. Furthermore, each signal assembly 130 includes a power semiconductor package signal connection element 132 and an embedded signal pin 134 (see FIG. 1C). Here, the power semiconductor package signal connection element 132 of each signal assembly 130 is first disposed on the upper surface S1 of the substrate 110 in a direction perpendicular to the extension direction (i.e., the normal direction N) of the substrate 110. That is, the power semiconductor package signal connection element 132 and the chip 120 are disposed on the same surface of the substrate 110. The power semiconductor package signal connection element 132 is located between the chip 120 and the pin 115, and the power semiconductor package signal connection element 132 may be fixed on the substrate 110 by, for example, welding.

[0022] Next, referring to FIG. 1B, a first molding material 140 is formed on the substrate 110 by molding. The first molding material 140 covers at least the chip 120 and has at least one opening 142 (two openings 142 are shown in schematic form). Each opening 142 exposes a corresponding power semiconductor package signal connection element 132 of the signal assembly 130. That is, in this embodiment, the opening 142 is not formed by mechanical or laser drilling. Here, for example, the diameter of the opening 142 gradually decreases from the direction away from the substrate 110 to the direction toward the substrate 110, but is not limited thereto. As shown in FIG. 1B, the first molding material 140 covers a part of the upper surface S1 of the substrate 110, the chip 120, the connector 125, and a part of each pin 115. Here, the part of each pin 115 may be defined as an inner pin portion 115a of each pin. Another portion of each pin 115 protrudes from the first molding material 140, where the other portion of each pin 115 may be defined as an outer pin portion 115b of each pin 115. Here, the material of the first molding material 140 is, for example, a solid epoxy molding compound (EMC).

[0023] 1C, the embedded signal pin 134 is correspondingly inserted into the power semiconductor package signal connection element 132, and the signal assembly 130 and the substrate 110 are electrically connected. Here, the embedded signal pin 134 is embodied as a vertical signal terminal and directly inserted into (contacts) the upper surface S1 of the substrate 110, which can effectively shorten the current path between the substrate 110 and the signal assembly 130 and reduce the parasitic inductance.

[0024] Finally, referring to FIG. 1C and FIG. 1D at the same time, the second molding material 150 is formed on the substrate 110 to fill the opening 142. The method of forming the second molding material 150 on the substrate 110 is, for example, to fill the opening 142 with liquid epoxy resin. That is, the material of the second molding material 150 is liquid epoxy resin. Since the second molding material 150 and the first molding material 140 are independent members that are not integrally formed but are formed separately, a contact interface B is formed between the second molding material 150 and the first molding material 140. Here, the second molding material 150 is located between the signal assembly 130 and the first molding material 140, and the second molding material 150 covers a part of the power semiconductor package signal connection element 132 and the embedded signal pin 134 of the signal assembly 130. That is, a portion of the embedded signal pin 134 protrudes from the second molding material 150 , and the portion of the embedded signal pin 134 protruding from the second molding material 150 is parallel to the normal direction N of the substrate 110 .

[0025] Since the first molding material 140 and the second molding material 150 are formed at different times, a contact interface B is formed between them, and the first molding material 140 and the second molding material 150 have different colors and light refractive indices. During mounting, due to the mismatch in thermal expansion coefficient between the materials of the elements, the board is prone to warping due to residual stress caused by temperature changes. In this embodiment, the first molding material 140 is first formed by molding, and then the second molding material 150 is injected / filled into the opening 142 of the first molding material 140, which can effectively balance the packaging stress and also increase the tensile force of the embedded signal pin 134 of the signal assembly 130, so that the semiconductor module 100 of this embodiment can have better structural reliability.

[0026] Furthermore, since the first molding material 140 having the opening 142 is formed by molding, the opening 142 can correspondingly expose the power semiconductor package signal connection element 132 of the signal assembly 130, and there is no need to remove a part of the molding material, and the embedded signal pin 134 is inserted into the power semiconductor package signal connection element 132 in direct contact with the substrate 110, so there is no need for solder connection, and the cost is effectively reduced.

[0027] Structurally, referring again to FIG. 1D, the semiconductor module 100 includes a substrate 110, a chip 120, a signal assembly 130, a first molding material 140, and a second molding material 150. The chip 120 is disposed on the substrate 110 and is electrically connected to the substrate 110. The signal assembly 130 is disposed on the substrate 110 along a normal direction N of the substrate 110 and is electrically connected to the substrate 110. The first molding material 140 is disposed on the substrate 110. The first molding material 140 covers at least the chip 120 and has an opening 142, which exposes the signal assembly 130. The second molding material 150 is disposed on the substrate 110 and fills the opening 142. The second molding material 150 is located between the signal assembly 130 and the first molding material 140 and covers the signal assembly 130, and a contact interface B is formed between the second molding material 150 and the first molding material 140.

[0028] Further, in this embodiment, the substrate 110 has an upper surface S1 and a lower surface S2 facing each other, and includes a plurality of pins 115. Each pin 115 includes an inner pin portion 115a and an outer pin portion 115b. The first molding material 140 covers the upper surface S1 of the substrate 110 and the inner pin portion 115a of each pin 115, and the outer pin portion 115b of each pin 115 protrudes from the first molding material 140. Furthermore, the semiconductor module 100 also includes a connector 125 that electrically connects the chip 120 and the substrate 110. Further, the signal assembly 130 of this embodiment includes a power semiconductor package signal connection element 132 and an embedded signal pin 134. The power semiconductor package signal connection element 132 is disposed on the substrate 110, and the first molding material 140 exposes the power semiconductor package signal connection element 132. The embedded signal pin 134 is inserted into the power semiconductor package signal connection element 132 and directly contacts the substrate 110. Here, the second molding material 150 covers the power semiconductor package signal connection elements 132 and a portion of the buried signal pins 134 .

[0029] In summary, in the design of the semiconductor module of the present invention, the signal assembly is disposed on the substrate in the normal direction of the substrate and is physically and electrically connected to the substrate, the first molding material covers the chip and exposes the signal assembly, the second molding material covers the signal assembly, and a contact interface is formed between the second molding material and the first molding material. This design effectively shortens the current path between the substrate and the signal assembly, reduces the parasitic inductance, and the first molding material and the second molding material are formed as independent members, so that the packaging stress and the tensile force can be effectively balanced, and the tensile force of the signal assembly can be increased, thereby improving the structural reliability of the semiconductor module of the present invention.

[0030] It will be apparent to one skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the above, it is intended that the present invention cover modifications and variations provided they come within the scope of the following claims and their equivalents. [Industrial Applicability]

[0031] The semiconductor module and its manufacturing method of the present invention can be applied to effectively shorten the current path between the substrate and the signal assembly and reduce the parasitic inductance, thereby improving the structural reliability of the semiconductor module of the present invention. [Explanation of symbols]

[0032] 100: Semiconductor module 110: Circuit board 115: Pin 115a: Inner pin part 115b: Outer pin part 120: Chip 125: Connector 130: Signal Assembly 132: Power semiconductor package signal connection element 134: Buried signal pin 140: First molding material 142: Opening 150: Second molding material B: Contact interface S1: First side S2: Second Side N: Normal direction

Claims

1. A substrate; at least one chip disposed on and electrically connected to the substrate; at least one signal assembly disposed on the substrate in a normal direction to the substrate and electrically connected to the substrate; a first molding material disposed on the substrate, at least covering the at least one chip and having at least one opening, the at least one opening exposing the at least one signal assembly; a second molding material disposed on the substrate, filling the at least one opening, and positioned between the at least one signal assembly and the first molding material, covering the at least one signal assembly; wherein at least one contact interface is formed between the second molding material and the first molding material.

2. at least one power semiconductor package signal connection element disposed on the substrate, the first molding material exposing the at least one power semiconductor package signal connection element; 2. The semiconductor module of claim 1, further comprising: at least one embedded signal pin inserted into at least one power semiconductor package signal connection element, the second molding material covering the at least one power semiconductor package signal connection element and a portion of the at least one embedded signal pin.

3. The semiconductor module of claim 1 , further comprising at least one connector electrically connecting said at least one chip and said substrate.

4. the substrate has opposing upper and lower surfaces and includes a plurality of pins; 2. The semiconductor module of claim 1, wherein each of the plurality of pins has an inner pin portion and an outer pin portion, the first molding material covers the top surface of the substrate and the inner pin portions of each of the plurality of pins, and the outer pin portions of each of the plurality of pins protrude from the first molding material.

5. Providing a substrate; disposing at least one chip on the substrate, the chip being electrically connected to the substrate; disposing at least one signal assembly on the substrate in a normal direction to the substrate and electrically connected to the substrate; forming a first molding material on the substrate, the first molding material at least covering the at least one chip and having at least one opening, the at least one opening exposing the at least one signal assembly; forming a second molding material on the substrate, the second molding material filling the at least one opening and positioned between the at least one signal assembly and the first molding material and covering the at least one signal assembly; and forming at least one contact interface between the second molding material and the first molding material.

6. the at least one signal assembly comprises at least one power semiconductor package signal connection element and at least one embedded signal pin; disposing the at least one power semiconductor package signal connection element on the substrate before forming the first molding material on the substrate; When forming the first molding material on the substrate, the first molding material exposes the at least one power semiconductor package signal connection element; inserting the at least one embedded signal pin into the at least one power semiconductor package signal connection element before forming the second molding material on the substrate; 6. The method for manufacturing a semiconductor module according to claim 5, further comprising: when forming the second molding material on the substrate, the second molding material covers the at least one power semiconductor package signal connection element and a portion of the at least one embedded signal pin.

7. The method for manufacturing a semiconductor module according to claim 5 , further comprising forming at least one connector that electrically connects at least one chip and the substrate before forming the first molding material on the substrate.

8. the substrate has opposing upper and lower surfaces and includes a plurality of pins; 6. The method for manufacturing a semiconductor module according to claim 5, wherein when the first molding material is formed on the substrate, the first molding material covers the top surface of the substrate and a portion of each of the plurality of pins, wherein the portion of each of the plurality of pins is defined as an inner pin portion, and another portion of each of the plurality of pins protrudes from the first molding material, wherein the other portion of each of the plurality of pins is defined as an outer pin portion of each of the plurality of pins.

9. The method for manufacturing a semiconductor module according to claim 5 , wherein forming the second molding material on the substrate includes filling at least one opening with a liquid epoxy resin.

10. The method of claim 5 , wherein the substrate comprises a direct bond copper substrate, an insulated metal substrate, or an active metal bond substrate.

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