Array substrate and display device

Abstract

To reduce a load on a second wiring line.SOLUTION: An array substrate 21 includes: a first wiring line 25; a second wiring line 26; a semiconductor section 27D extending to cross the first wiring line 25 and including one end portion disposed to overlap the second wiring line 26; a first insulation film 32 interposed between the first wiring line 25 and the semiconductor section 27D; a first electrode 27A composed of a portion of the first wiring line 25 and overlapping the semiconductor section 27D via the first insulation film 32; a second electrode 27B composed of a portion of the second wiring line 26 and overlapping the semiconductor section 27D and being connected to the semiconductor section 27D; and a third electrode 27C disposed to overlap the other end portion of the semiconductor section 27D and connected to the semiconductor section 27D. The semiconductor section 27D is configured as a resistance lowered section 38 in which a portion not overlapping the first electrode 27A has a lowered resistance, and has a first overlapping portion 43 disposed to overlap portions of the first electrode 27A and the second wiring line 26.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The technology disclosed in this specification relates to an array substrate and a display device. [Background technology]

[0002] Conventionally, one example of a display device is known from Patent Document 1. In the display device described in Patent Document 1, in a bottom-gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer is formed as a channel protective layer in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer, and an oxide insulating layer is formed to cover the periphery (including the side surface) of the stack of the oxide semiconductor layers when the oxide insulating layer is formed. In addition, a source electrode layer and a drain electrode layer are formed so as not to overlap with the channel protective layer, and the insulating layer on the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-205435 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the display device described in the above Patent Document 1, the high-resistance source region of the oxide semiconductor layer is connected to a portion branched off from the source wiring, and the oxide semiconductor layer is arranged so as not to overlap with the source wiring. Therefore, parasitic capacitance tends to increase between the high-resistance source region of the oxide semiconductor layer, which has the same potential as the source wiring, and other electrodes and wiring, and there is a problem that the load on the source wiring becomes excessive due to the parasitic capacitance.

[0005] The technology described in this specification was completed based on the above circumstances, and aims to reduce the load on the second wiring. [Means for solving the problem]

[0006] (1) An array substrate related to the technology described in this specification includes a first wiring, a second wiring intersecting the first wiring, a semiconductor section made of a semiconductor material, extending across the first wiring, one end of which is arranged to overlap the second wiring, a first insulating film interposed between the first wiring and the semiconductor section, a first electrode consisting of a portion of the first wiring that overlaps the semiconductor section via the first insulating film, a second electrode consisting of a portion of the second wiring that overlaps the semiconductor section and is connected to the semiconductor section, and a third electrode arranged to overlap the other end of the semiconductor section and connected to the semiconductor section, wherein the semiconductor section has a first overlapping portion in which a portion not overlapping with the first electrode is a low-resistance region in which resistance is reduced, and which is arranged to overlap a portion of the first electrode and a portion of the second wiring.

[0007] (2) In addition to the above (1), the array substrate may further include a first extension portion in which the semiconductor portion extends along an oblique direction inclined with respect to both the first wiring and the second wiring and crosses the first wiring, and the first overlap portion is formed from a part of the first extension portion.

[0008] (3) In addition to the above (2), the array substrate may further include a semiconductor portion having a second extension portion including the one end and extending parallel to the second wiring, the second extension portion being continuous with the first extension portion and overlapping the second wiring.

[0009] (4) In addition to the above (2) or (3), the array substrate may be arranged so that the semiconductor portion is arranged such that the portion of the low-resistance region from the other end to the first wiring does not overlap with the second wiring.

[0010] (5) In addition to the above (1), the array substrate may further include a third extension portion in which the semiconductor portion extends along the second wiring in a manner overlapping with the second wiring and crosses the first wiring, and the first overlapping portion is formed as a part of the third extension portion.

[0011] (6) In addition to the above (5), the array substrate may further include a first shading portion extending along the first wiring in a manner overlapping with the first wiring and being wider than the first wiring, and the first shading portion may have a second overlap portion not overlapping with the first wiring and overlapping with a portion of the third extension portion.

[0012] (7) A display device according to the technology described in this specification includes the array substrate according to any one of (1) to (6) above, and a counter substrate disposed opposite the array substrate. Effect of the Invention

[0013] According to the technique described in this specification, the load on the second wiring can be reduced. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic perspective view showing a state in which a user wears a head-mounted display according to a first embodiment on his or her head. [Diagram 2] FIG. 1 is a schematic side view showing an optical relationship between a liquid crystal display device and a lens unit provided in a head-mounted device constituting a head-mounted display according to a first embodiment, and a user's eyeball. [Diagram 3] 1 is a schematic plan view of a liquid crystal panel and a flexible substrate included in a liquid crystal display device according to a first embodiment; [Figure 4] 1 is a schematic cross-sectional view of a liquid crystal panel according to a first embodiment of the present invention; [Diagram 5] FIG. 2 is a plan view showing a pixel arrangement in a display area of ​​an array substrate provided in the liquid crystal panel according to the first embodiment; [Figure 6] 6 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vi-vi in ​​FIG. [Figure 7]6 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vii-vii of FIG. 5 . [Figure 8] FIG. 1 is a plan view showing pixels in a display region of a liquid crystal panel according to a first embodiment, in which a first metal film and a fourth metal film are shown in a shaded manner. [Figure 9] FIG. 2 is a plan view showing pixels in a display region of the liquid crystal panel according to the first embodiment, in which the semiconductor film and the second metal film are shown in a shaded manner. [Figure 10] FIG. 1 is a plan view showing pixels in a display region of a liquid crystal panel according to a first embodiment, in which a first overlapping portion is shown shaded; [Figure 11] FIG. 1 is a plan view showing a pixel in Comparative Example 1 of Comparative Experiment 1 according to the first embodiment, in which a semiconductor film and a second metal film are shaded. [Figure 12] Table showing the experimental results of Comparative Experiment 1 according to the first embodiment [Figure 13] FIG. 7 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a second embodiment taken along the same line as in FIG. 6; [Figure 14] FIG. 8 is a cross-sectional view showing a cross-sectional structure of a liquid crystal panel according to a second embodiment taken along the same line as in FIG. 7; [Figure 15] FIG. 11 is a plan view showing pixels in a display region of a liquid crystal panel according to a third embodiment, in which a semiconductor film and a second metal film are shown in a shaded manner. [Figure 16] FIG. 11 is a plan view showing pixels in a display region of a liquid crystal panel according to a third embodiment, in which a first overlapping portion and a second overlapping portion are shown shaded. [Figure 17] Table showing the experimental results of Comparative Experiment 2 according to the third embodiment DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] <Embodiment 1> A first embodiment will be described with reference to Fig. 1 to Fig. 12. In this embodiment, a goggle-type head-mounted display (HMD) 10HMD and a liquid crystal display device (display device) 10 used therein are illustrated. Note that an X-axis, a Y-axis, and a Z-axis are shown in a part of each drawing, and each axis direction is drawn to be the direction shown in each drawing.

[0016] The appearance of a goggle-type head mounted display 10HMD will be described with reference to Fig. 1. The head mounted display 10HMD includes a head mounted device 10HMDa that is mounted on a user's head 10HD, as shown in Fig. 1. The head mounted device 10HMDa surrounds both of the user's eyes.

[0017] The configuration of the head-mounted device 10HMDa will be described with reference to FIG. 2. As shown in FIG. 2, the head-mounted device 10HMDa incorporates at least a liquid crystal display device 10 for displaying an image and a lens unit 10RE for focusing the image displayed on the liquid crystal display device 10 on the user's eyeball 10EY. The liquid crystal display device 10 includes at least a liquid crystal panel (display device) 11 and a backlight device (illumination device) 12 for irradiating the liquid crystal panel 11 with light. The main surface of the liquid crystal panel 11 facing the lens unit 10RE is a display surface 11DS for displaying an image. The lens unit 10RE is disposed between the liquid crystal display device 10 and the user's eyeball 10EY. The lens unit 10RE imparts a refracting effect to light. By adjusting the focal length of the lens unit 10RE, the user can recognize that an image focused on the retina 10EYb via the crystalline lens 10EYa of the eyeball 10EY is displayed on a virtual display 10VD that appears to be located at a distance L2 from the eyeball 10EY. This distance L2 is much larger than the actual distance L1 from the eyeball 10EY to the liquid crystal display device 10. This allows the user to view an enlarged image, which is a virtual image, displayed on the virtual display 10VD, which has a screen size (e.g., about several tens of inches to several hundreds of inches) that is much larger than the screen size (e.g., about several tenths of an inch to a few inches) of the liquid crystal display device 10.

[0018] It is possible to mount one liquid crystal display device 10 on the head mounted device 10HMDa and display an image for the right eye and an image for the left eye on the liquid crystal display device 10. Alternatively, it is possible to mount two liquid crystal display devices 10 on the head mounted device 10HMDa and display an image for the right eye on one liquid crystal display device 10 and an image for the left eye on the other liquid crystal display device 10. The head mounted device 10HMDa may also be provided with earphones or the like that are placed against the user's ears to output sound.

[0019] The configuration of the liquid crystal panel 11 provided in the liquid crystal display device 10 will be described with reference to FIG. 3 and the like. The configuration of the backlight device 12 is as known, and includes, for example, a light source such as an LED and an optical member that converts light from the light source into planar light by applying an optical effect. As shown in FIG. 3, the liquid crystal panel 11 has a rectangular shape as a whole in a planar view. The central part of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. The outer peripheral part of the screen of the liquid crystal panel 11, which is a frame-like part surrounding the display area AA, is a non-display area NAA where no image is displayed. The area surrounded by the dashed line in FIG. 3 is the display area AA. The liquid crystal panel 11 according to this embodiment is used in the head-mounted display 10HMD described above, and therefore has extremely high resolution, with a pixel density of, for example, about 1000 ppi or more.

[0020] As shown in FIG. 3, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. The substrate 20 and 21 are arranged on the front side as the counter substrate (second substrate, CF substrate) 20, and the substrate 20 and 21 are arranged on the back side as the array substrate (first substrate, active matrix substrate) 21. The counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner side of the substrates 20GS and 21GS, which are made of glass and have almost transparent and excellent light transmission. The substrates 20GS and 21GS contain, for example, non-alkali glass as a main material. The array substrate 21 is larger than the counter substrate 20, and a part of it protrudes laterally from the counter substrate 20. The flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 is configured by forming a large number of wiring patterns on a base material having insulating properties and flexibility. One end of the flexible substrate 13 is connected to the array substrate 21, and the other end is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0021] As shown in FIG. 3, the non-display area NAA of the liquid crystal panel 11 is provided with a circuit section (peripheral circuit section) 14. The circuit section 14 includes a first circuit section 14A and a second circuit section 14B. A pair of the first circuit sections 14A are arranged to sandwich the display area AA from both sides in the X-axis direction. The first circuit section 14A is provided in a strip-shaped range extending along the Y-axis direction. The first circuit section 14A is for supplying scanning signals to gate wiring 25 described later, and is monolithically provided on the array substrate 21. The first circuit section 14A is a GDM (Gate Driver Monolithic) circuit. The first circuit section 14A includes a shift register circuit that outputs scanning signals at a predetermined timing, a buffer circuit that amplifies the scanning signals, and the like. The second circuit section 14B is arranged at a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit section 14B is provided in a strip-shaped range extending along the X-axis direction. The second circuit section 14B is for supplying image signals (data signals) to the source wirings 26 described later, and is monolithically provided on the array substrate 21. The second circuit section 14B includes an SSD (Source Shared Driving) circuit, etc. The second circuit section 14B has a switch function for distributing image signals supplied by the flexible substrate 13 to each source wiring 26, etc.

[0022] Next, the cross-sectional configuration of the liquid crystal panel 11 will be outlined with reference to FIG. 4. As shown in FIG. 4, the pair of substrates 20, 21 are disposed facing each other with a gap in the Z-axis direction, which is the normal direction of the main surfaces of the substrates 20, 21. Between the pair of substrates 20, 21, at least a liquid crystal layer 22 and a seal portion 23 for sealing (sealing) the liquid crystal layer 22 are interposed. The liquid crystal layer 22 contains liquid crystal molecules, which are a substance whose optical properties change with the application of an electric field. The seal portion 23 has a rectangular frame shape (endless ring shape) as a whole in a plan view, and surrounds the liquid crystal layer 22 all around in the non-display area NAA. The seal portion 23 maintains a gap (cell gap) equivalent to the thickness of the liquid crystal layer 22. A polarizing plate 24 is attached to each of the outer surfaces of the pair of substrates 20, 21.

[0023] An outline of the pixel arrangement in the display area AA of the array substrate 21 will be described with reference to FIG. 5. As shown in FIG. 5, a plurality of gate wirings (first wiring, scanning wiring) 25 and source wirings (second wiring, image wiring) 26 are arranged in a lattice pattern on the inner surface of the display area AA of the array substrate 21. The gate wirings 25 extend along the X-axis direction so as to cross the display area AA. A plurality of the gate wirings 25 are arranged in parallel at intervals in the Y-axis direction. The plurality of gate wirings 25 are supplied with a scanning signal output from the first circuit section 14A. The source wirings 26 extend along the Y-axis direction so as to cross the display area AA, and intersect with the gate wirings 25. A plurality of the source wirings 26 are arranged at intervals in the X-axis direction. The image signal output from the second circuit section 14B is distributed to the source wirings 26. A TFT (switching element) 27 and a pixel electrode 28 are provided near the intersection of the gate wirings 25 and the source wirings 26. The TFTs 27 and the pixel electrodes 28 are regularly arranged in a row along the X-axis direction and the Y-axis direction. The TFTs 27 have a gate electrode (first electrode) 27A, a source electrode (second electrode) 27B, a drain electrode (third electrode) 27C, and a semiconductor portion 27D. The gate electrode 27A is connected to the gate wiring 25. The source electrode 27B is connected to the source wiring 26. The drain electrode 27C is connected to the pixel electrode 28. The semiconductor portion 27D is made of a semiconductor material, and one end is connected to the source electrode 27B and the other end is connected to the drain electrode 27C, and a portion located in the middle of both ends is arranged to overlap with the gate electrode 27A. When the TFTs 27 are driven based on a scanning signal supplied from the gate wiring 25 to the gate electrode 27A, they charge the pixel electrode 28 to a potential based on an image signal supplied from the source wiring 26 to the source electrode 27B. The pixel electrode 28 is elongated with the Y-axis direction as the longitudinal direction.

[0024] As shown in FIG. 6, a common electrode 30 is provided on the inner surface of the display area AA of the array substrate 21. The common electrode 30 is located above the pixel electrodes 28 and is arranged over almost the entire display area AA. As a result, the common electrode 30 overlaps all the pixel electrodes 28 arranged in the display area AA. In this manner, in the array substrate 21 according to the present embodiment, the "upper electrode" that is the electrode located on the upper layer side of the pixel electrodes 28 and the common electrode 30 is the common electrode 30, and the "lower electrode" that is the electrode located on the lower layer side is the pixel electrode 28. A plurality of slits 30A are formed in the portions of the common electrode 30 that overlap the plurality of pixel electrodes 28. A common potential signal that is a common potential (reference potential) is supplied to the common electrode 30. When the pixel electrodes 28 are charged to a potential based on an image signal transmitted to the source wiring 26 in response to the driving of the TFT 27, a potential difference occurs between the pixel electrodes 28 and the common electrode 30. Then, a fringe electric field (oblique electric field) including a component in the normal direction to the main surface of the array substrate 21, in addition to a component along the main surface of the array substrate 21, is generated between the opening edge of the slit 30A in the common electrode 30 and the pixel electrode 28. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is performed based on the orientation state of the liquid crystal molecules. In other words, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0025] Next, various films laminated on the glass substrate 21GS of the array substrate 21 will be described in detail with reference to Figures 6 and 7. As shown in Figures 6 and 7, the glass substrate 21GS of the array substrate 21 is laminated with at least the following films in order from the lower layer side (glass substrate 21GS side): a first metal film, a base coat film 31, a semiconductor film, a gate insulating film (first insulating film) 32, a second metal film, a first interlayer insulating film 33, a third metal film, a second interlayer insulating film 34, a first transparent electrode film, a first planarizing film 35, a second transparent electrode film, a third interlayer insulating film 36, a third transparent electrode film, and an alignment film. Note that the alignment film is not shown.

[0026] The first metal film, the second metal film, and the third metal film are each a single layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and thus have electrical conductivity and light shielding properties. Of these, the first metal film is, for example, a single layer film made of W (tungsten), and its thickness is, for example, about 50 nm. The first metal film constitutes the first light shielding portion 37, as shown in FIG. 7. The second metal film is, for example, a laminated film made of Ti (titanium) with a thickness of about 100 nm, Al (aluminum) with a thickness of about 150 nm, and Ti with a thickness of about 30 nm, in that order from the lower layer side. The second metal film constitutes the gate wiring 25 and the gate electrode 27A. The portion of the gate wiring 25 that overlaps the semiconductor portion 27D in a plan view becomes the gate electrode 27A. The third metal film is, for example, a laminated film made of Ti (titanium) with a thickness of about 60 nm, Al (aluminum) with a thickness of about 300 nm, and Ti with a thickness of about 20 nm, in that order from the lower layer side. 6, the third metal film forms the source wiring 26. A portion of the source wiring 26 that overlaps the semiconductor portion 27D in a plan view serves as a source electrode 27B.

[0027] The first transparent electrode film, the second transparent electrode film, and the third transparent electrode film are made of a transparent electrode material. Of these, the first transparent electrode film is made of, for example, IZO (Indium Zinc Oxide) and has a film thickness of, for example, about 100 nm. The first transparent electrode film constitutes the drain electrode 27C as shown in FIG. 7. One end portion of the drain electrode 27C is connected to the semiconductor portion 27D. The second transparent electrode film is made of, for example, IZO and has a film thickness of, for example, about 100 nm. The second transparent electrode film constitutes the pixel electrode 28. One end portion of the pixel electrode 28 is connected to the other end portion of the drain electrode 27C. The third transparent electrode film is made of, for example, IZO and has a film thickness of, for example, about 100 nm. The third transparent electrode film constitutes the common electrode 30.

[0028] The semiconductor film is made of an oxide semiconductor material. More specifically, the semiconductor film is made of an oxide thin film containing indium (In), gallium (Ga), and zinc (Zn), which are types of oxide semiconductors. The oxide thin film containing indium (In), gallium (Ga), and zinc (Zn) is amorphous or crystalline. The semiconductor film has a thickness of, for example, about 50 nm. The oxide semiconductor material of the semiconductor film has a characteristic of having a higher resistance value when no voltage is applied (off state) compared to a silicon semiconductor material. In addition, the oxide semiconductor material of the semiconductor film has a higher electron mobility compared to an amorphous silicon semiconductor material.

[0029] The semiconductor film according to this embodiment is partially made to have low resistance by a low resistance treatment in the manufacturing process, and as a result, the semiconductor portion 27D includes a low resistance region 38. A region of the semiconductor portion 27D that is not subjected to the low resistance treatment is a non-low resistance region 39. Note that in FIG. 7 and other figures, the low resistance region 38 in the semiconductor portion 27D is illustrated as being hatched. The non-low resistance region 39 in the semiconductor portion 27D is made capable of transferring charges only under specific conditions (when a scanning signal is supplied to the gate electrode 27A). In other words, the non-low resistance region 39 functions as a channel region under specific conditions. The non-low resistance region 39 is a portion of the semiconductor portion 27D that overlaps with the gate electrode 27A in a plan view. The low resistance region 38 is a portion of the semiconductor portion 27D that does not overlap with the gate electrode 27A in a plan view. The low resistance region 38 has a resistivity as low as, for example, 1 / 10000000000 to 1 / 100 compared to the non-low resistance region 39, and is always capable of transferring charges, functioning as a conductor. The low resistance treatment of the semiconductor film is performed in the manufacturing process of the array substrate 21 by using the gate wiring 25 and the gate electrode 27A as a mask after the gate wiring 25 and the gate electrode 27A made of the second metal film are provided. In the low resistance treatment, the low resistance treatment is selectively performed on the portion of the semiconductor film that is not covered by the gate wiring 25 and the gate electrode 27A (non-overlapping portion, exposed portion), and the low resistance treatment is not performed on the portion covered by the gate wiring 25 and the gate electrode 27A (overlapping portion, non-exposed portion). The low resistance treatment includes, for example, a plasma treatment using gas such as NH3, H2, N2, He, and an annealing treatment. The low resistance region 38 includes a first low resistance region (source region) 38A connected to the source electrode 27B, and a second low resistance region (drain region) 38B connected to the drain electrode 27C.

[0030] The base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, the second interlayer insulating film 34, and the third interlayer insulating film 36 are all made of inorganic materials (inorganic resin materials). Among these, the base coat film 31 is made of, for example, SiO2 (silicon oxide, silicon oxide) having a thickness of about 100 nm, SiN x The base coat film 31 is a laminated film made of silicon nitride. The base coat film 31 is interposed between the first light-shielding portion 37 and the gate wiring 25 and gate electrode 27A to keep them in an insulating state. The gate insulating film 32 is, for example, a single layer film made of SiO2 and has a thickness of, for example, about 85 nm. The gate insulating film 32 is interposed between the gate wiring 25 and gate electrode 27A and the semiconductor portion 27D to keep them in an insulating state. The first interlayer insulating film 33 is, for example, a single layer film made of SiO2 and has a thickness of, for example, about 500 nm. The first interlayer insulating film 33 is interposed between the gate wiring 25 and source wiring 26 to keep them in an insulating state. The second interlayer insulating film 34 is, for example, a single layer film made of SiO2 and has a thickness of, for example, about 500 nm. The second interlayer insulating film 34 is interposed between the source wiring 26 and drain electrode 27C to keep them in an insulating state. For example, SiN x The third interlayer insulating film 36 is interposed between the pixel electrode 28 and the common electrode 30 to keep them in an insulated state.

[0031] The first planarization film 35 is made of PMMA (acrylic resin), which is a type of organic material (organic resin material). The first planarization film 35 made of an organic material is usually thicker than the base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, the second interlayer insulating film 34, and the third interlayer insulating film 36, which are made of an inorganic material. Specifically, the thickness of the first planarization film 35 is, for example, about 2 μm. The first planarization film 35 is interposed between the drain electrode 27C and the pixel electrode 28.

[0032] On the other hand, as shown in Fig. 6 and Fig. 7, a color filter 29, a second light-shielding portion 40, a spacer 41, and an alignment film are formed on the glass substrate 20GS of the counter substrate 20. The alignment film is not shown. The alignment films on the counter substrate 20 and the array substrate 21 are made of an organic material such as polyimide. Each alignment film is provided on the innermost side (closest to the liquid crystal layer 22) of the counter substrate 20 and the array substrate 21, respectively. The alignment film has a function of aligning liquid crystal molecules by performing a photo-alignment treatment on the upper surface facing the liquid crystal layer 22.

[0033] As shown in FIG. 6 and FIG. 7, the color filter 29 is arranged so as to overlap with the pixel electrode 28 of the array substrate 21, and constitutes a pixel, which is a display unit, together with the overlapping pixel electrode 28. The color filter 29 includes a plurality of types (three types) of different colors. The plurality of types of color filters 29 that exhibit different colors are arranged side by side in the extension direction (X-axis direction) of the gate wiring 25. In other words, the arrangement direction of the plurality of types of color filters 29 that exhibit different colors coincides with the X-axis direction. The plurality of types of color filters 29 that exhibit different colors extend along the extension direction (Y-axis direction) of the source wiring 26. In this way, the plurality of types of color filters 29 that exhibit different colors are arranged in a vertical stripe pattern as a whole. The plurality of color filters 29 that exhibit different colors are arranged so that their boundaries (color boundaries) overlap with the source wiring 26. The color filters 29 include three types of filters: a green color filter (first color filter) that exhibits green, a blue color filter (second color filter) that exhibits blue, and a red color filter (third color filter) that exhibits red. The green color filter, together with the overlapping pixel electrode 28, constitutes a green pixel (first pixel) that exhibits green. The blue color filter, together with the overlapping pixel electrode 28, constitutes a blue pixel (second pixel) that exhibits blue. The red color filter, together with the overlapping pixel electrode 28, constitutes a red pixel (third pixel) that exhibits red. In FIG. 6 and other figures, the colors exhibited by the color filters 29 are indicated by the letters R (Red), G (Green), and B (Blue).

[0034] The second light-shielding portion 40 is made of a synthetic resin material having excellent light-shielding properties, and is provided on the inner surface of the glass substrate 20GS as shown in FIG. 6. The second light-shielding portion 40 extends along the Y-axis direction and is arranged so as to overlap the source wiring 26 provided on the array substrate 21. A plurality of the second light-shielding portions 40 are arranged in a line at intervals in the X-axis direction, and are arranged in a vertical stripe shape in a plan view. The plurality of second light-shielding portions 40 are respectively arranged at the color boundaries of the plurality of color filters 29 that exhibit different colors. The arrangement intervals of the plurality of second light-shielding portions 40 are approximately equal to the arrangement intervals of the source wiring 26. The second light-shielding portion 40 can block light from passing between pixels that exhibit different colors. This makes it difficult for color mixing to occur, and thus ensures the display independence of the display of each pixel that exhibits each color.

[0035] As shown in FIG. 7, the spacer 41 protrudes from the counter substrate 20 toward the array substrate 21 along the Z-axis direction (the normal direction of the main surface of the counter substrate 20). In detail, the spacer 41 is made of a resin material, protrudes from the surface of the color filter 29 toward the array substrate 21 in the display area AA of the counter substrate 20 along the Z-axis direction, and its protruding tip surface faces the array substrate 21. The spacer 41 is generally in the shape of a slightly tapered column. The spacer 41 may include two types of spacers having different protruding heights from the color filter 29. FIG. 7 illustrates a spacer 41 with a large protruding height. The spacer 41 with a large protruding height has its protruding tip surface in contact with the inner surface (alignment film) of the array substrate 21. In contrast, the spacer 41 with a small protruding height has a clearance between its protruding tip surface and the inner surface of the array substrate 21, and its protruding tip surface contacts the inner surface of the array substrate 21 only when one of the pair of substrates 20, 21 is bent inward due to the action of an external force. Such spacer 41 can maintain the distance (the thickness of liquid crystal layer 22, the cell gap) between the pair of substrates 20, 21. As shown in Fig. 5, the spacer 41 is arranged to overlap the gate electrode 27A of a specific TFT 27 (for example, the TFT 27 connected to the pixel electrode 28 constituting the blue pixel having the lowest luminosity factor) among the multiple TFTs 27 aligned along the X-axis direction.

[0036] Next, the planar shape of the first light-shielding portion 37 made of the first metal film will be described mainly with reference to FIG. 8. In FIG. 8, the configuration made of the first metal film and the third metal film (the first light-shielding portion 37 and the source wiring 26, etc.) is illustrated with different hatching patterns. As shown in FIG. 8, the first light-shielding portion 37 has a horizontally elongated strip shape extending along the X-axis direction, and is arranged so as to overlap the entire area of ​​the gate wiring 25 in a plan view. The width dimension of the first light-shielding portion 37 is made larger than the width dimension of the gate wiring 25, and both ends in the width direction (Y-axis direction) protrude from both side edges of the gate wiring 25. Therefore, it can be said that the first light-shielding portion 37 covers the entire area of ​​the non-low-resistance region 39 (channel region) of the semiconductor portion 27D, which is arranged so as to overlap the gate electrode 27A made of a part of the gate wiring 25, from the back side. This allows the first light-shielding portion 37 to efficiently block light traveling from the backlight device 12 toward the non-low resistance region 39, thereby suppressing fluctuations in the characteristics of the TFT 27 that may occur when light is irradiated onto the non-low resistance region 39. In addition, the portion (wide portion) of the first light-shielding portion 37 that overlaps with the spacer 41 is formed wider than the other portions.

[0037] Next, the planar shapes of the drain electrode 27C made of the first transparent electrode film and the pixel electrode 28 made of the second transparent electrode film will be described. As shown in FIG. 8, the drain electrode 27C and the pixel electrode 28 are both rectangular and elongated in the Y-axis direction. The pixel electrode 28 has a longer side dimension (dimension in the Y-axis direction) larger than the longer side dimension of the drain electrode 27C. In detail, the pixel electrode 28 has one end overlapping one of the two gate wirings 25 (lower side in FIG. 8) that sandwich the pixel electrode 28 in the Y-axis direction, whereas the other end is disposed at a distance in the Y-axis direction from the other gate wiring 25 (upper side in FIG. 8). The drain electrode 27C overlaps the pixel electrode 28 over its entirety, and is disposed unevenly toward the end of one of the pixel electrodes 28 (lower side in FIG. 8). One end of the drain electrode 27C (lower side in FIG. 8) overlaps one end of the pixel electrode 28 and the gate wiring 25 (gate electrode 27A), while the other end of the drain electrode 27C (upper side in FIG. 8) overlaps the other end (second low-resistance region 38B) of the semiconductor portion 27D described below. Note that one end of each of the pixel electrode 28 and the drain electrode 27C is also arranged to overlap the first light-shielding portion 37 and the non-low-resistance region 39 of the semiconductor portion 27D in addition to the gate wiring 25 (gate electrode 27A).

[0038] Next, the planar shape of the semiconductor portion 27D made of a semiconductor film will be described mainly with reference to FIG. 9. In FIG. 9, the configuration (gate wiring 25, gate electrode 27A, and semiconductor portion 27D) made of the second metal film and the semiconductor film is illustrated with different hatching. As shown in FIG. 9, the semiconductor portion 27D has a first extension portion 42 extending along a diagonal direction inclined with respect to both the extension direction (X-axis direction) of the gate wiring 25 and the extension direction (Y-axis direction) of the source wiring 26. The first extension portion 42 is disposed so as to cross the gate wiring 25. One end (lower side in FIG. 9) of the first extension portion 42 is located on the opposite side (lower side in FIG. 9) of the pixel electrode 28 to be connected across the gate wiring 25 in the Y-axis direction, and is disposed so as to overlap the source wiring 26. The other end (upper side in FIG. 9) of the first extending portion 42 is located on the pixel electrode 28 side (upper side in FIG. 9) to be connected across the gate wiring 25 in the Y-axis direction, and is arranged to overlap the drain electrode 27C. The first extending portion 42 extends from one end to the other end so as to move away from the source wiring 26 and approach the drain electrode 27C. The first extending portion 42 crosses the gate wiring 25 and extends to both sides in the Y-axis direction as viewed from the gate wiring 25, and thus includes the entire non-low resistance region 39 and parts of the first low resistance region 38A and the second low resistance region 38B. In detail, the part of the first extending portion 42 located on the source electrode 27B side (lower side in FIG. 9) with respect to the gate wiring 25 in the Y-axis direction is part of the first low resistance region 38A (part closer to the non-low resistance region 39 than the connection part with the source electrode 27B). Of the first extension portion 42, the portion located on the drain electrode 27C side (upper side in Figure 9) in the Y-axis direction relative to the gate wiring 25 is part of the second low-resistance region 38B (the portion closer to the non-low-resistance region 39 than the connection point with the drain electrode 27C).

[0039] As shown in Fig. 9, the semiconductor portion 27D includes a non-low resistance region 39 overlapping with the gate electrode 27A, a first low resistance region 38A located on the source electrode 27B side (lower side in Fig. 9) with respect to the non-low resistance region 39, and a second low resistance region 38B located on the drain electrode 27C side (upper side in Fig. 9) with respect to the non-low resistance region 39. One end of the semiconductor portion 27D, which is the first low resistance region 38A, is arranged to overlap with the source wiring 26 as shown in Fig. 7, and is connected to the source electrode 27B which is a part of the source wiring 26. A first contact hole CH1 is provided in the gate insulating film 32 and the first interlayer insulating film 33 interposed between the one end of the semiconductor portion 27D and the source electrode 27B at a position overlapping both the one end of the semiconductor portion 27D and the source electrode 27B. The first contact hole CH1 is provided in communication with the gate insulating film 32 and the first interlayer insulating film 33, and one end of the semiconductor portion 27D is connected to the source electrode 27B through the first contact hole CH1.

[0040] The other end of the semiconductor portion 27D, which is the second low resistance region 38B, is disposed so as to overlap the drain electrode 27C as shown in FIG. 7, and is connected to the drain electrode 27C. The gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 34 interposed between the other end of the semiconductor portion 27D and the other end of the drain electrode 27C are provided with a second contact hole CH2 at a position overlapping both the other end of the semiconductor portion 27D and the other end of the drain electrode 27C. The second contact hole CH2 is provided so as to communicate with the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 34, and the other end of the semiconductor portion 27D and the other end of the drain electrode 27C are connected through the second contact hole CH2. Further, the first planarization film 35 interposed between one end of the drain electrode 27C and one end of the pixel electrode 28 has a third contact hole CH3 provided at a position overlapping both one end of the semiconductor portion 27D and one end of the pixel electrode 28. One end of the semiconductor portion 27D is connected to one end of the pixel electrode 28 through this third contact hole CH3. The third contact hole CH3 is disposed so as to overlap the gate electrode 27A, the first light-shielding portion 37, the spacer 41, and the like.

[0041] As shown in Figs. 9 and 10, the semiconductor section 27D has a first overlapping section 43 that is arranged to overlap a part of each of the gate electrode 27A and the source wiring 26. In Fig. 10, the first overlapping section 43 is illustrated by being hatched. Since the first overlapping section 43 overlaps the gate electrode 27A, it is a part of the non-low resistance region 39 and also a part of the above-mentioned first extension section 42. In other words, it can be said that the first extension section 42 of the semiconductor section 27D is arranged such that a part of the non-low resistance region 39 that overlaps with the gate electrode 27A also overlaps a part of the source wiring 26. In detail, the first overlapping section 43 is constituted by an end portion of the non-low resistance region 39 on the first low resistance region 38A side (the lower side in Figs. 9 and 10). The first overlapping portion 43 is a triangular region (more specifically, a right-angled triangle) in a plan view, and the three sides defining the region are arranged to overlap one side edge of the source wiring 26 (the drain electrode 27C side in the X-axis direction), one side edge of the first extension portion 42 (the opposite side to the drain electrode 27C side in the X-axis direction), and one side edge of the gate wiring 25 (the source electrode 27B side in the Y-axis direction).

[0042] 9 and 10, the semiconductor portion 27D has the first overlapping portion 43 arranged to overlap a part of the gate electrode 27A and the source wiring 26, and therefore, compared to the conventional case where the semiconductor portion 27D is arranged not to overlap the source wiring 26, it is possible to reduce each parasitic capacitance generated between the first low-resistance region 38A, which is a part of the low-resistance region 38 that has the same potential as the source wiring 26, and other electrodes and wirings. In particular, in this embodiment, the first extension portion 42 including the first overlapping portion 43 extends along an oblique direction inclined with respect to both the gate wiring 25 and the source wiring 26, so that the area where the semiconductor portion 27D overlaps with the source wiring 26 is smaller than the case where the first extension portion extends in parallel with the source wiring 26 and is arranged to overlap with the source wiring 26. Therefore, the parasitic capacitance occurring between the second low-resistance region 38B, which is a portion from the other end (the end connected to the drain electrode 27C) of the low-resistance region 38 to the gate wiring 25, and the source wiring 26 is reduced. Since the second low-resistance region 38B has the same potential as the drain electrode 27C, the parasitic capacitance occurring between the drain electrode 27C and the source wiring 26 is reduced. Therefore, in this embodiment, it is possible to reduce each of the parasitic capacitances occurring between the first low-resistance region 38A and the gate wiring 25, the first light-shielding portion 37, and the pixel electrode 28, compared to the conventional case. This makes it possible to effectively reduce the load on the source wiring 26.

[0043] As shown in FIGS. 9 and 10, the semiconductor portion 27D has a second extension portion 44 extending in parallel to the source wiring 26 (Y-axis direction). The second extension portion 44 includes one end of the semiconductor portion 27D that is connected to the source electrode 27B, and is made of a part of the first low-resistance region 38A. The first low-resistance region 38A includes the entire second extension portion 44 and a part of the first extension portion 42. The second extension portion 44 is disposed so as to overlap the source wiring 26. The end of the second extension portion 44 opposite to the one end connected to the source electrode 27B is continuous with the end of the first extension portion 42. In this way, the area where the first low-resistance region 38A, which is a portion of the low-resistance region 38 that extends from one end connected to the source electrode 27B to the gate wiring 25, overlaps with the source wiring 26 becomes larger than if the semiconductor portion did not include the second extension portion 44 and the first extension portion included one end. Since the first low-resistance region 38A is at the same potential as the source wiring 26, it is possible to reduce parasitic capacitance generated between the first low-resistance region 38A, which is a portion of the low-resistance region 38 that is at the same potential as the source wiring 26, and other electrodes and wirings. This makes it possible to reduce the load on the source wiring 26.

[0044] As shown in Figs. 9 and 10, the other end of the semiconductor portion 27D connected to the drain electrode 27C extends in parallel to the Y-axis direction. In the low-resistance region 38, the second low-resistance region 38B, which is a portion from the other end connected to the drain electrode 27C to the gate wiring 25, is arranged so as not to overlap with the source wiring 26. The second low-resistance region 38B, which is a portion from the other end of the low-resistance region 38 to the gate wiring 25, is set to the same potential as the drain electrode 27C, and the second low-resistance region 38B and the source wiring 26 are not overlapped, so that the parasitic capacitance generated between the drain electrode 27C and the source wiring 26 is further reduced. This can further reduce the load on the source wiring 26.

[0045] Next, in order to verify the superiority of the array substrate 21 according to this embodiment, the following Comparative Experiment 1 was performed. In Comparative Experiment 1, the parasitic capacitance (electrostatic capacitance) associated with the source wiring 26 was calculated using the following Example 1 and Comparative Example 1. Example 1 is an array substrate 21 having the same configuration as that described before this paragraph. Comparative Example 1 is an array substrate having a different configuration from Example 1 in that it does not have a first overlapping portion 43 (see FIGS. 9 and 10). Specifically, as shown in FIG. 11, in the array substrate of Comparative Example 1, a portion of the semiconductor portion 27D-1 that crosses the gate wiring 25-1 extends in parallel with the source wiring 26-1 and is arranged so as not to overlap with the source wiring 26-1. Specifically, the semiconductor portion 27D-1 in the comparative example 1 extends straight along the Y-axis direction from the other end connected to the drain electrode 27C-1 toward the gate wiring 25-1, crosses the gate wiring 25-1, and is bent so as to extend obliquely in both the X-axis direction and the Y-axis direction, with one end connected to the source electrode 27B-1, which is a part of the source wiring 26-1. The comparative example 1 has almost the same configuration as the example 1, except for the configuration of the semiconductor portion 27D-1. The example 1 and the comparative example 1 have in common the resolution (pixel density) of 1728 ppi and the pixel arrangement pitch of 14.7 μm.

[0046] In Comparative Experiment 1, in the above-described Example 1 and Comparative Example 1, the parasitic capacitance Csd occurring between the source wiring and the pixel electrode, the parasitic capacitance Ctgs occurring between the source wiring and the gate wiring, and the parasitic capacitance Cbgs occurring between the source wiring and the first light-shielding portion were calculated. The calculation results of each of the parasitic capacitances Csd, Ctgs, and Cbgs are as shown in FIG. 12. The unit of each of the parasitic capacitances Csd, Ctgs, and Cbgs is "fF (femtofarad)". In addition to the calculation results of each of the parasitic capacitances Csd, Ctgs, and Cbgs, FIG. 12 shows the ratios obtained by dividing each of the parasitic capacitances Csd, Ctgs, and Cbgs of Example 1 by each of the parasitic capacitances Csd, Ctgs, and Cbgs of Comparative Example 1, as percentages.

[0047] The experimental results of Comparative Experiment 1 will be described. FIG. 12 shows that the parasitic capacitances Csd, Ctgs, and Cbgs of Example 1 are all lower than those of Comparative Example 1. In particular, it shows that the parasitic capacitance Csd generated between the source wiring 26 and the pixel electrode 28 of Example 1 is significantly lowered to 78% of that of Comparative Example 1. This is presumably because, in Example 1, as shown in FIG. 9, the second low-resistance region 38B of the low-resistance region 38 of the semiconductor portion 27D is arranged so as not to overlap with the source wiring 26 over the entire area, which contributes to the significant reduction in the parasitic capacitance Csd.

[0048] As described above, the array substrate 21 of the present embodiment includes the gate wiring (first wiring) 25, the source wiring (second wiring) 26 intersecting the gate wiring 25, the semiconductor portion 27D made of a semiconductor material, extending across the gate wiring 25 and having one end overlapping the source wiring 26, the gate insulating film (first insulating film) 32 interposed between the gate wiring 25 and the semiconductor portion 27D, and the gate electrode (first electrode) 27D consisting of a portion of the gate wiring 25 overlapping the semiconductor portion 27D via the gate insulating film 32. A source electrode (second electrode) 27B consisting of a portion of source wiring 26 overlapping semiconductor portion 27D and connected to semiconductor portion 27D, and a drain electrode (third electrode) 27C arranged overlapping the other end of semiconductor portion 27D and connected to semiconductor portion 27D, wherein semiconductor portion 27D has a low resistance region 38 in which the portion not overlapping with gate electrode 27A has a low resistance, and has a first overlapping portion 43 arranged overlapping a portion of gate electrode 27A and source wiring 26.

[0049] When a potential based on a signal transmitted by the gate wiring 25 is applied to the semiconductor portion 27D by the gate electrode 27A, which is a part of the gate wiring 25, a channel region is generated in a portion of the semiconductor portion 27D that overlaps with the gate electrode 27A via the gate insulating film 32. Then, a signal transmitted by the source wiring 26 is supplied from the source electrode 27B, which is a part of the source wiring 26, to the drain electrode 27C via the low-resistance region 38 and the channel region of the semiconductor portion 27D. Since the semiconductor portion 27D extends across the gate wiring 25 and has one end connected to the source electrode 27B and the other end connected to the drain electrode 27C, there is a concern that a parasitic capacitance generated between a portion of the low-resistance region 38 that has the same potential as the source wiring 26 and other electrodes or wirings will become large.

[0050] Here, the source wiring 26 intersects with the gate wiring 25, and a portion of the source wiring 26 overlaps with the gate wiring 25. On the other hand, the gate electrode 27A is made up of a portion of the gate wiring 25 that overlaps with the semiconductor portion 27D via the gate insulating film 32. The semiconductor portion 27D has a first overlapping portion 43 that is arranged to overlap with each of the gate electrode 27A and the source wiring 26. Therefore, compared to the conventional case where the semiconductor portion 27D is arranged not to overlap with the source wiring 26, it is possible to reduce the parasitic capacitance generated between the portion of the low resistance region 38 that has the same potential as the source wiring 26 and other electrodes and wirings. This reduces the load on the source wiring 26.

[0051] Moreover, the semiconductor portion 27D has a first extending portion 42 that extends along an oblique direction inclined with respect to both the gate wiring 25 and the source wiring 26 and crosses the gate wiring 25, and the first overlapping portion 43 is made of a part of the first extending portion 42. Since the first extending portion 42 including the first overlapping portion 43 extends along an oblique direction inclined with respect to both the gate wiring 25 and the source wiring 26, the area where the semiconductor portion 27D overlaps with the source wiring 26 is smaller than if the first extending portion extends in parallel with the source wiring 26 and is arranged overlapping with the source wiring 26. Therefore, the parasitic capacitance generated between the portion of the low resistance region 38 from the other end to the gate wiring 25 and the source wiring 26 can be reduced. The portion of the low-resistance region 38 from the other end to the gate wiring 25 is at the same potential as the drain electrode 27C, so that the parasitic capacitance between the drain electrode 27C and the source wiring 26 is reduced, thereby further reducing the load on the source wiring 26.

[0052] The semiconductor section 27D also has a second extension section 44 that includes one end and extends parallel to the source wiring 26, and the second extension section 44 is connected to the first extension section 42 and is arranged to overlap with the source wiring 26. In this way, the area where the portion of the low resistance region 38 from one end to the gate wiring 25 and the source wiring 26 overlap is larger than if the semiconductor section does not include the second extension section 44 and the first extension section includes one end. Since the portion of the low resistance region 38 from one end to the gate wiring 25 is at the same potential as the source wiring 26, the parasitic capacitance generated between the portion of the low resistance region 38 that is at the same potential as the source wiring 26 and other electrodes or wirings can be reduced. This can reduce the load on the source wiring 26.

[0053] Furthermore, the semiconductor portion 27D is arranged such that a portion of the low resistance region 38 from the other end to the gate wiring 25 does not overlap with the source wiring 26. The portion of the low resistance region 38 from the other end to the gate wiring 25 is at the same potential as the drain electrode 27C, and thus the non-overlapping of this portion with the source wiring 26 further reduces the parasitic capacitance generated between the drain electrode 27C and the source wiring 26. This further reduces the load on the source wiring 26.

[0054] Moreover, the liquid crystal display device (display device) 10 according to this embodiment includes the above-described array substrate 21 and a counter substrate 20 disposed to face the array substrate 21. According to such a liquid crystal display device 10, the load on the source wiring 26 is reduced, so that the signals transmitted by the source wiring 26 are less likely to be dulled. This leads to improved display quality.

[0055] <Embodiment 2> A second embodiment will be described with reference to Fig. 13 or 14. In this second embodiment, a case where the configurations of a color filter 129 and a second light-shielding portion 140 are changed is shown. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0056] The array substrate 121 according to this embodiment is provided with a color filter 129 as shown in FIG. 13. That is, the liquid crystal panel 111 according to this embodiment has a COA (Color Filter On Array) structure. The color filter 129 is disposed below the first planarization film 135. The source wiring 126 is disposed below the color filter 129 via the second interlayer insulating film 134, and is disposed so as to overlap the boundary (color boundary) of the color filters 129 that exhibit different colors. As shown in FIG. 14, the color filter 129 is disposed above the drain electrode 127C made of the first transparent electrode film. Therefore, the color filter 129 is disposed between one end of the drain electrode 127C and one end of the pixel electrode 128 together with the first planarization film 135. Accordingly, the third contact hole CH103 is provided in a form that communicates with the first planarization film 135 and the color filter 129. In manufacturing, after the drain electrode 127C is provided by patterning the first transparent electrode film, the color filter 129 and the first planarization film 135 are successively formed, and then the third contact hole CH103 is provided in communication with the color filter 129 and the first planarization film 135. The color filter 129 is made of a photosensitive resin material and has a thickness of, for example, about 1 μm. In contrast, the first planarization film 135 has a thickness of, for example, about 1 μm. In other words, the color filter 129 and the first planarization film 135 have approximately the same thickness, and the total thickness is approximately equal to the thickness (about 2 μm) of the first planarization film 35 described in the first embodiment.

[0057] As shown in FIG. 14, the array substrate 121 has an insulating portion 45 in the third contact hole CH103. The insulating portion 45 is made of a second planarization film located above the pixel electrode 128 made of the second transparent electrode film and below the third interlayer insulating film 136. The insulating portion 45 is provided to fill the third contact hole CH103. Therefore, the insulating portion 45 covers the drain electrode 127C and the pixel electrode 128 in the third contact hole CH103. The insulating portion 45 planarizes the pixel electrode 128, the third interlayer insulating film 136, the common electrode 130, and the alignment film located above the second planarization film. The insulating portion 45 is configured to be higher than the opening edge of the third contact hole CH103 in the first planarization film 135.

[0058] 13, the array substrate 121 according to this embodiment is provided with a second light-shielding portion 140 in addition to the above-mentioned color filters 129 and insulating portion 45. The second light-shielding portion 140 is disposed on the upper layer side of the common electrode 130 made of a third transparent electrode film, and is in direct contact with the common electrode 130. The second light-shielding portion 140 is made of a light-shielding film having the following configuration. The light-shielding film constituting the second light-shielding portion 140 is, for example, a light-shielding layer made of a metal material (e.g., Mo (molybdenum) etc.) and a light-transmitting resin material (e.g., SiN x The first transmission layer is made of a metal material (e.g., Mo), the second reflection / transmission layer is made of a light-transmitting resin material (e.g., SiN xand a second transmission layer made of a material such as a shading layer, a shading layer, etc. The shading layer has a function of blocking light irradiated from the backlight device 12. The thickness of the shading layer is preferably, for example, 30 nm or more in order to achieve the shading function. The first transmission layer has a function of reducing reflection of external light by utilizing thin film interference. The thickness of the first transmission layer is preferably, for example, in the range of 20 nm to 100 nm in order to achieve the above-mentioned function of reducing reflection of external light. The reflective-transmitting layer has a function of reducing reflection of external light and a function of re-reflecting light reflected by the shading layer. The thickness of the reflective-transmitting layer is preferably, for example, in the range of 3 nm to 20 nm in order to achieve each of the above-mentioned functions. The second transmission layer has a function of reducing reflection of external light by utilizing thin film interference. The thickness of the second transmission layer is smaller than the thickness of the first transmission layer. The shading film having such a configuration constitutes the second shading section 140. In addition to the above, the light-shielding film may be a single-layer structure or a multi-layer structure made of a metal material having light-shielding properties, or may be a single-layer structure or a multi-layer structure made of a light-shielding resin material. In this embodiment, the second light-shielding portion 140 is disposed on the upper layer side of the common electrode 130, that is, next to the alignment film on the array substrate 121, close to the liquid crystal layer 122, so that it can block a lot of light that may cause color mixing between pixels exhibiting different colors. This provides a high color mixing prevention function. Even with the configuration of this embodiment, it is possible to obtain the same actions and effects as those of the above-mentioned embodiment 1.

[0059] <Embodiment 3> A third embodiment will be described with reference to Fig. 15 to Fig. 17. In this third embodiment, a configuration of a semiconductor section 227D is changed from that of the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0060] As shown in FIG. 15, the semiconductor section 227D according to this embodiment has a third extension section 46 extending along the source wiring 226 (Y-axis direction). In FIG. 15, the configuration (gate wiring 225, gate electrode 227A, and semiconductor section 227D) consisting of the second metal film and the semiconductor film is illustrated with different hatching. The third extension section 46 includes one end of the semiconductor section 227D that is connected to the source electrode 227B, and is disposed across the gate wiring 225. The third extension section 46 that crosses the gate wiring 225 extends to both sides in the Y-axis direction as viewed from the gate wiring 225, and therefore includes the entire non-low resistance region 239, the entire first low resistance region 238A, and a part of the second low resistance region 238B. The third extension section 46 is disposed so as to overlap the source wiring 226. The width of the third extension 46 is larger than that of the source wiring 226, and both ends in the width direction (X-axis direction) protrude from both side edges of the source wiring 226. The gate electrode 227A, which is made up of a portion of the gate wiring 225 that overlaps with the semiconductor portion 227D, is arranged to overlap the third extension 46 and the source wiring 226. The semiconductor portion 227D also has a fourth extension 47 that extends along the gate wiring 225 (X-axis direction). The fourth extension 47 includes the other end connected to the drain electrode 227C of the semiconductor portion 227D, and the end opposite to the other end is connected to the end opposite to one end of the third extension 46 described above. The second low-resistance region 238B is composed of the entire area of ​​the fourth extension 47 and a part of the third extension 46.

[0061] In this embodiment, the third extension portion 46 extends along the Y-axis direction, crosses the gate wiring 225, and is arranged overlapping with the source wiring 226. Therefore, the first overlapping portion 243 is made of a part of the third extension portion 46 as shown in FIG. 16. In FIG. 16, the first overlapping portion 243 and the second overlapping portion 48 described below are illustrated with different hatching. The first overlapping portion 243 has a vertically elongated rectangular shape in a plan view, and its width dimension is equal to the width dimension of the source wiring 226 and its length dimension is equal to the width dimension of the gate wiring 225. The first overlapping portion 243 has a formation range that is approximately the same as that of the gate electrode 227A in a plan view. The first overlapping portion 243 according to this embodiment has a larger area than the first overlapping portion 43 (see FIG. 10) described in the first embodiment. The third extension portion 46 including the first overlapping portion 243 extends along the source wiring 226 and overlaps with the source wiring 226, so that the overlapping area between the non-low-resistance region 239 of the semiconductor portion 227D and the gate wiring 225 (gate electrode 227A) is smaller than that of the first extension portion 42 (see FIG. 10) described in the first embodiment. Therefore, it is possible to reduce the parasitic capacitance generated between the gate wiring 225 and the first low-resistance region 238A, which is a portion from one end of the low-resistance region 238 to the gate wiring 225. Since the first low-resistance region 238A is at the same potential as the source electrode 227B, the parasitic capacitance generated between the gate wiring 225 and the source wiring 226 is reduced, and the load on the source wiring 226 can be further reduced.

[0062] 16, the first light-shielding portion 237, which is wider than the gate wiring 225, has a second overlapping portion 48 that is arranged not overlapping with the gate wiring 225 but overlapping with a part of the third extending portion 46. The second overlapping portion 48 is a portion of the first light-shielding portion 237 that protrudes from the side edge of the gate wiring 225 and further overlaps with the third extending portion 46. According to this configuration, compared to the first extending portion 42 (see FIG. 10) described in the above-mentioned first embodiment, the third extending portion 46 extends straight along the Y-axis direction, and therefore the area where the third extending portion 46 and the first light-shielding portion 237 overlap is smaller. The first low-resistance region 238A, which is the portion from one end of the low-resistance region 238 to the gate wiring 225, is at the same potential as the source wiring 226, so that the parasitic capacitance generated between the source wiring 226 and the first light-shielding portion 237 is reduced, thereby further reducing the load on the source wiring 226.

[0063] Next, in order to verify the superiority of the array substrate 21 according to the present embodiment, the following Comparative Experiment 2 was performed. In Comparative Experiment 2, the parasitic capacitance (electrostatic capacitance) associated with the source wiring 226 was calculated using the following Example 2, similar to Comparative Experiment 1 described in the first embodiment. Example 2 is an array substrate 21 having the same configuration as that described before this paragraph. Note that, in Example 2, similar to Example 1 and Comparative Example 1 of Comparative Experiment 1, the resolution is set to 1728 ppi, and the pixel array pitch is set to 14.7 μm. In Comparative Experiment 2, in Example 2, the parasitic capacitance Csd generated between the source wiring 226 and the pixel electrode 228, the parasitic capacitance Ctgs generated between the source wiring 226 and the gate wiring 225, and the parasitic capacitance Cbgs generated between the source wiring 226 and the first light shielding portion 237 were calculated. The calculation results of the parasitic capacitances Csd, Ctgs, and Cbgs are as shown in FIG. 17. 17 shows the experimental results of Comparative Experiment 1 (the calculation results of Example 1 and Comparative Example 1) in addition to the calculation results of Example 2. The units of the parasitic capacitances Csd, Ctgs, and Cbgs are "fF". In addition to the calculation results of the parasitic capacitances Csd, Ctgs, and Cbgs, FIG. 17 shows the ratios, expressed as percentages, of the parasitic capacitances Csd, Ctgs, and Cbgs of Example 2 divided by the parasitic capacitances Csd, Ctgs, and Cbgs of Comparative Example 1.

[0064] The experimental results of the comparative experiment 2 will be described. According to FIG. 17, it can be seen that in Example 2, the parasitic capacitances Ctgs and Cbgs are both lower than those in Comparative Example 1, but the parasitic capacitance Csd is higher. The reason for this is presumed to be that in Example 2, most of the second low-resistance region 238B, which is a portion of the semiconductor portion 227D that includes the other end and has the same potential as the drain electrode 227C, overlaps with the source wiring 226, and the overlapping area is larger than those in Example 1 and Comparative Example 1. On the other hand, in Example 2, the parasitic capacitances Ctgs and Cbgs are both lower than those in Example 1. The reason for the lower parasitic capacitance Ctgs in Example 2 than that in Example 1 is presumed to be that the overlapping area between the first low-resistance region 238A, which is a portion of the semiconductor portion 227D that includes one end and has the same potential as the source electrode 227B, and the gate wiring 225 is smaller than that in Example 1. The reason why the parasitic capacitance Cbgs of Example 2 is lower than that of Example 1 is presumably because, in Example 2, the overlap area between the first low-resistance region 238A, which is a portion of the semiconductor portion 227D that includes one end and has the same potential as the source electrode 227B, and the first light-shielding portion 237 is smaller than that of Example 1.

[0065] As described above, according to this embodiment, the semiconductor portion 227D has the third extension portion 46 that extends along the source wiring 226 in a manner overlapping with the source wiring 226 and crosses the gate wiring 225, and the first overlapping portion 243 is made of a part of the third extension portion 46. The third extension portion 46 including the first overlapping portion 243 extends along the source wiring 226 and is arranged overlapping with the source wiring 226, so that the area where the semiconductor portion 227D and the gate wiring 225 (gate electrode 227A) overlap is smaller than when the third extension portion extends along an oblique direction inclined with respect to both the gate wiring 225 and the source wiring 226. Therefore, the parasitic capacitance generated between the gate wiring 225 and the portion from one end of the low resistance region 238 to the gate wiring 225 can be reduced. Since the portion of the low-resistance region 238 from one end to the gate wiring 225 is at the same potential as the source electrode 227B, the parasitic capacitance generated between the gate wiring 225 and the source wiring 226 is reduced, thereby further reducing the load on the source wiring 226.

[0066] Further, the semiconductor portion 227D includes a first light-shielding portion 237 that extends along the gate wiring 225 in a manner overlapping with the gate wiring 225 and is wider than the gate wiring 225, and the first light-shielding portion 237 has a second overlapping portion 48 that is arranged not overlapping with the gate wiring 225 and overlapping a part of the third extension portion 46. The first light-shielding portion 237 is wider than the gate wiring 225, so that light directed toward a portion of the semiconductor portion 227D that overlaps with the gate electrode 227A can be efficiently blocked. The first light-shielding portion 237 that is wider than the gate wiring 225 has the second overlapping portion 48 that is arranged not overlapping with the gate wiring 225 and overlapping with the third extension portion 46, so that the area where the third extension portion 46 and the first light-shielding portion 237 overlap is smaller than the case where the third extension portion extends along an oblique direction inclined with respect to both the gate wiring 225 and the source wiring 226. Since the portion of the low-resistance region 238 from one end to the gate wiring 225 is at the same potential as the source wiring 226, the parasitic capacitance generated between the source wiring 226 and the first light-shielding portion 237 is reduced, thereby further reducing the load on the source wiring 226.

[0067] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0068] (1) In the configurations described in the first and second embodiments, the inclination angle of the first extension portion 42 with respect to the Y-axis direction can be changed as appropriate to a value other than that shown in the drawings.

[0069] (2) In the configurations described in the first and second embodiments, the length of the second extension portion 44 in the Y-axis direction can be changed as appropriate to a length other than that shown in the drawings.

[0070] (3) In addition to the above (1) and (2), the specific planar shape of the semiconductor portion 27D, 227D can be appropriately changed to a shape other than that shown in the drawings. In addition, the specific planar shapes of the gate wiring 25, 225, the source wiring 26, 126, 226, the drain electrodes 27C, 127C, 227C, the pixel electrodes 28, 128, 228, the first light-shielding portion 37, 237, etc. can also be appropriately changed to a shape other than that shown in the drawings.

[0071] (4) In the configurations described in the first and third embodiments, the second light-shielding portion 140 described in the second embodiment may be additionally provided. In that case, the second light-shielding portion 40 may not be formed on the counter substrate 20.

[0072] (5) The configuration described in the second embodiment (COA structure) may be combined with the configuration described in the third embodiment (semiconductor portion 227D).

[0073] (6) The second light-shielding portions 40 may be arranged in a lattice pattern in a plan view so as to overlap both the gate lines 25, 225 and the source lines 26, 126, 226.

[0074] (7) In the configuration described in the second embodiment, the length of the second light-shielding portion 140 in the Y-axis direction may be approximately the same as that of the pixel electrodes 28, 128, and 228, and a plurality of second light-shielding portions 140 may be arranged at intervals in the Y-axis direction. In this case, the plurality of second light-shielding portions 140 arranged along the Y-axis direction are arranged at approximately the same arrangement pitch as the plurality of pixel electrodes 28, 128, and 228 arranged along the Y-axis direction.

[0075] (8) In the array substrate 21, 121, a bump that is higher than the surrounding area may be provided in the first planarization film 35, 135 at a position where the bump overlaps with the spacer.

[0076] (9) A source driver may be attached to the array substrate 21, 121 instead of the first circuit section 14A.

[0077] (10) A source driver may be attached to the flexible substrate 13 instead of the first circuit section 14A.

[0078] (11) A gate driver may be attached to the array substrate 21, 121 instead of the second circuit section 14B.

[0079] (12) The specific materials, film thicknesses, layered structures (single layer film, layered film), etc. used for the metal films, semiconductor films, insulating films, and transparent electrode films provided on the array substrates 21 and 121 can be changed as appropriate.

[0080] (13) The opposing substrate 20 may be provided with an overcoat film for planarization.

[0081] (14) The material of the first planarization films 35 and 135 may be a negative-type organic material having photosensitivity.

[0082] (15) The drain electrodes 27C, 127C, and 227C may be made of a metal film. In that case, a metal film may be formed in place of the first transparent electrode film and then patterned.

[0083] (16) The number of colors of the color filters 29 and 129 may be four or more. The additional color filters 29 and 129 may be yellow color filters that exhibit yellow color or transparent color filters that transmit light in all wavelength ranges.

[0084] (17) The structure of the TFT 27 may be a bottom gate type, a double gate type, or the like other than the top gate type shown in the drawing.

[0085] (18) Of the pixel electrodes 28, 128, 228 and the common electrodes 30, 130, the "upper electrode" that is the electrode located on the upper layer side may be the pixel electrodes 28, 128, 228, and the "lower electrode" that is the electrode located on the lower layer side may be the common electrode 30, 130. In this case, a slit is provided in the pixel electrodes 28, 128, 228 that are the "upper electrode".

[0086] (19) The alignment film may be subjected to an alignment treatment by rubbing.

[0087] (20) The semiconductor film may be an amorphous silicon thin film or a polycrystalline silicon thin film.

[0088] (21) The display mode of the liquid crystal panels 11, 111 may be VA mode, IPS mode, or the like other than FFS mode.

[0089] (22) The liquid crystal panels 11 and 111 may be of a reflective or semi-transmissive type other than a transmissive type. If the liquid crystal panels 11 and 111 are of a reflective type, the backlight device 12 can be omitted.

[0090] (23) In addition to the head mounted display 10 HMD, the present invention can be applied to devices such as head-up displays and projectors that use lenses to enlarge and display images displayed on the liquid crystal panels 11, 111. The present invention can also be applied to display devices that do not have a magnification function (such as television receivers, tablet terminals, and smartphones). [Explanation of symbols]

[0091] 10... liquid crystal display device (display device), 20... opposing substrate, 21, 121... array substrate, 25, 225... gate wiring (first wiring), 26, 126, 226... source wiring (second wiring), 27A, 227A... gate electrode (first electrode), 27B, 227B... source electrode (second electrode), 27C, 127C, 227C... drain electrode (third electrode), 27D, 227D... semiconductor portion, 32... gate insulating film (first insulating film), 37, 237... first light shielding portion, 38, 238... low resistance region, 42... first extension portion, 43, 243... first overlapping portion, 44... second extension portion, 46... third extension portion, 48... second overlapping portion

Claims

1. A first wiring; a second wiring that intersects with the first wiring; a semiconductor portion made of a semiconductor material, extending across the first wiring and having one end portion overlapping the second wiring; a first insulating film interposed between the first wiring and the semiconductor portion; a first electrode including a portion of the first wiring that overlaps with the semiconductor portion via the first insulating film; a second electrode formed from a portion of the second wiring that overlaps with the semiconductor portion and that is connected to the semiconductor portion; a third electrode disposed so as to overlap the other end of the semiconductor portion and connected to the semiconductor portion; The semiconductor portion is an array substrate having a first overlapping portion that is arranged to overlap a portion of the first electrode and a portion of the second wiring, the portion being a low-resistance region where the resistance is reduced, and the semiconductor portion is a low-resistance region where the portion not overlapping the first electrode and the second wiring is a low-resistance region.

2. the semiconductor portion has a first extension portion extending along a diagonal direction inclined with respect to both the first wiring and the second wiring and crossing the first wiring; The array substrate according to claim 1 , wherein the first overlapping portion is made up of a part of the first extending portion.

3. the semiconductor portion has a second extension portion that includes the one end portion and extends in parallel to the second wiring, The array substrate according to claim 2 , wherein the second extending portion is continuous with the first extending portion and is disposed so as to overlap the second wiring.

4. 4. The array substrate according to claim 2, wherein the semiconductor portion is arranged such that a portion of the low resistance region from the other end to the first wiring does not overlap with the second wiring.

5. the semiconductor portion has a third extension portion extending along the second wiring in a state overlapping with the second wiring and crossing the first wiring; The array substrate according to claim 1 , wherein the first overlapping portion is made up of a part of the third extending portion.

6. a first light-shielding portion extending along the first wiring in a manner overlapping with the first wiring and having a width greater than that of the first wiring; 6. The array substrate according to claim 5, wherein the first light shielding portion has a second overlapping portion that is arranged not overlapping with the first wiring but overlapping with a part of the third extending portion.

7. An array substrate according to any one of claims 1 to 6, a counter substrate disposed opposite the array substrate.

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