Semiconductor device

Abstract

To provide a semiconductor device in which switching tolerance can be improved.SOLUTION: In a semiconductor substrate 40, on an n+-type starting substrate 41 constituting an n+-type drain region 1, SiC layers 42, 43 constituting an n--type drift region 2 and a p-type base region 3, respectively, are stacked in this order. In the p-type base region 3, a p-type SiC part 51 comprising the p-type SiC layer 43 and a p-type polysilicon part 52 formed of p-type polysilicon are adjacent to each other in a depth direction. The p-type polysilicon part 52 is formed by filling a trench 53 formed in the p-type SiC layer 43 with p-type polysilicon. The trench 53 is formed to a depth where the p-type SiC layer 43 is not penetrated in a depth direction. For example, Al or B can be used as a p-type dopant to form the p-type polysilicon part 52.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes the use of aluminum (Al) as a p-type dopant in the formation of a p-type SiC region by epitaxial growth or ion implantation in a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) using silicon carbide (SiC) as a semiconductor material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-120072 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, because the band gap of SiC is relatively large, the sheet resistance of the p-type SiC region formed with Al as a p-type dopant increases at low temperatures of around -40° C. or -55° C. As a result, a depletion layer is likely to spread within the p-type SiC region, and the majority carriers in the p-type SiC region are depleted, making the depletion layer likely to reach the vicinity of the element surface, which may result in a high electric field being applied locally to the element structure and causing destruction.

[0005] An object of the present disclosure is to provide a semiconductor device that can more easily improve switching resistance. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the disclosure is as follows. An n-type region is provided inside a semiconductor substrate made of silicon carbide. A p-type region is provided inside the semiconductor substrate between a first main surface of the semiconductor substrate and the n-type region and in contact with the n-type region. A first electrode is electrically connected to the p-type region. A second electrode is electrically connected to the n-type region. At least a portion of the p-type region is a p-type polysilicon portion.

[0007] According to the above disclosure, the carrier concentration of the p-type polysilicon portion does not decrease even at low temperatures, so the depletion layer is unlikely to spread in the p-type region and the majority carriers in the p-type region are not depleted. Therefore, the depletion layer is unlikely to reach the vicinity of the first main surface of the semiconductor substrate, and local electric field concentration can be suppressed. Effect of the Invention

[0008] The semiconductor device according to the present disclosure has an effect of improving switching resistance. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view showing a layout of a semiconductor device according to a first embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing another example of the cross-sectional structure taken along line AA' in FIG. 1. [Figure 4] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a third embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 13 is a characteristic diagram showing the relationship between the sheet resistance and the bonding temperature of a p-type SiC region of a semiconductor device of a reference example. [Figure 8]1 is a cross-sectional view showing a structure of a semiconductor device of a reference example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Overview of the embodiment of the present disclosure> (1) A semiconductor device according to one aspect of the disclosure is as follows. An n-type region is provided inside a semiconductor substrate made of silicon carbide. A p-type region is provided inside the semiconductor substrate between a first main surface of the semiconductor substrate and the n-type region, in contact with the n-type region. A first electrode is electrically connected to the p-type region. A second electrode is electrically connected to the n-type region. At least a portion of the p-type region is a p-type polysilicon portion.

[0011] According to the above disclosure, the carrier concentration of the p-type polysilicon portion does not decrease even at low temperatures, so the depletion layer does not spread easily in the p-type region, and the majority carriers in the p-type region are not depleted. Therefore, the depletion layer does not easily reach the vicinity of the first main surface of the semiconductor substrate, and local electric field concentration can be suppressed. This improves the switching resistance, particularly the resistance to steep dV / dt.

[0012] (2) In the semiconductor device according to the present disclosure, in the above-mentioned (1), the remaining portion of the p-type region excluding the p-type polysilicon portion is a p-type silicon carbide portion.

[0013] According to the above disclosure, it is possible to obtain effects based on the material properties of silicon carbide in the p-type region.

[0014] (3) In the semiconductor device according to the present disclosure, in the above-mentioned (1), the entire p-type region may be the p-type polysilicon portion.

[0015] According to the above disclosure, for example, a p-type polysilicon portion can be easily formed by simply depositing a p-type polysilicon layer on the outermost surface of a semiconductor substrate.

[0016] (4) Furthermore, the semiconductor device according to the present disclosure, in the above-mentioned (1) or (2), further comprises an n-type partial region selectively provided inside the semiconductor substrate between a first main surface of the semiconductor substrate and the p-type region, and the entire n-type partial region is an n-type silicon carbide portion.

[0017] According to the above disclosure, it is possible to maintain the effects based on the material properties of silicon carbide in the n-type region.

[0018] (5) Furthermore, the semiconductor device according to the present disclosure, in the above-mentioned (2), may further include an n-type partial region selectively provided inside the semiconductor substrate between the first main surface of the semiconductor substrate and the p-type region, and a part of the n-type partial region may be an n-type polysilicon portion. The remaining part of the n-type partial region excluding the n-type polysilicon portion is an n-type silicon carbide portion. The n-type polysilicon portion is selectively provided inside the p-type polysilicon portion. The n-type silicon carbide portion is selectively provided inside the p-type silicon carbide portion.

[0019] According to the above disclosure, in a configuration in which a portion of the p-type region is a p-type polysilicon portion, an n-type partial region (an n-type polysilicon portion and an n-type silicon carbide portion) can be easily formed by simply ion implanting an n-type dopant.

[0020] (6) Furthermore, the semiconductor device according to the present disclosure, in the above-mentioned (3), may further include an n-type partial region selectively provided inside the semiconductor substrate between a first main surface of the semiconductor substrate and the p-type region, and the entire n-type partial region may be an n-type polysilicon portion.

[0021] According to the above disclosure, in a configuration in which the entire p-type region is a p-type polysilicon portion, an n-type partial region (n-type polysilicon portion) can be easily formed by only ion implantation of an n-type dopant.

[0022] (7) In the semiconductor device according to any one of (1) to (6) above, a predetermined element structure including a pn junction between the p-type region and the n-type region is provided in an active region of the semiconductor substrate, the first electrode is provided on a first main surface of the semiconductor substrate and is electrically connected to the element structure, and the second electrode is provided on a second main surface of the semiconductor substrate.

[0023] According to the above disclosure, the present invention is applicable to a vertical semiconductor device in which a current flows vertically between the first and second main surfaces of a semiconductor substrate through a pn junction.

[0024] (8) Furthermore, in the semiconductor device according to the present disclosure, in the above-mentioned (7), the semiconductor device may further include a termination region surrounding the active region and having a predetermined breakdown voltage structure disposed therein, and a plurality of the p-type regions may be provided inside the semiconductor substrate. A first p-type region of the plurality of p-type regions may be provided in the active region to form the element structure. A second p-type region of the plurality of p-type regions may be provided in the termination region to form the breakdown voltage structure.

[0025] According to the above disclosure, it is possible to suppress dielectric breakdown of the insulating layer covering the first main surface of the semiconductor substrate in the termination region.

[0026] (9) The semiconductor device according to the present disclosure, in the above-mentioned (8), further includes a boundary region between the active region and the termination region, and a wiring layer provided on the first main surface of the semiconductor substrate in the boundary region via an insulating layer. A third p-type region among the plurality of p-type regions may be electrically connected to the first electrode, provided in the boundary region, and facing the wiring layer in a depth direction via the insulating layer.

[0027] According to the above disclosure, it is possible to suppress dielectric breakdown of the insulating layer covering the first main surface of the semiconductor substrate in the boundary region.

[0028] (10) In addition, in the semiconductor device according to any one of (1) to (9) above, aluminum or boron may be introduced as a p-type dopant into the p-type polysilicon portion.

[0029] According to the above disclosure, a p-type polysilicon portion can be formed using a general p-type dopant with existing semiconductor manufacturing equipment.

[0030] (11) In addition, in the semiconductor device according to any one of (5) to (7) above, phosphorus, arsenic or nitrogen may be introduced into the n-type polysilicon portion as an n-type dopant.

[0031] According to the above disclosure, an n-type polysilicon portion can be formed using a general n-type dopant with existing semiconductor manufacturing equipment.

[0032] <Foundational knowledge of this disclosure> The problem with the semiconductor device of the reference example will be described. Fig. 8 is a cross-sectional view showing the structure of the semiconductor device of the reference example. The semiconductor device 110 of the reference example shown in Fig. 8 is a vertical SiC-MOSFET having a trench gate structure in the active region of a semiconductor substrate (semiconductor chip) 120 using silicon carbide (SiC) as a semiconductor material. The semiconductor substrate 120 is a n-type + On the starting substrate 121 - The SiC layers 122, 123 which become the p-type drift region 102 and the p-type base region 103 are epitaxially grown in this order.

[0033] n + The starting substrate 121 is n + The semiconductor substrate 120 has a main surface on the p-type SiC layer 123 side as a front surface, and an n-type + The main surface on the side of the starting substrate 121 is referred to as the back surface. - A p-type base region 103 is provided between the n-type drift region 102 and the p-type base region 103. + type source region 104, p ++The gate trench 105 is made up of a p-type contact region (not shown), a gate trench 105, a gate insulating film 106, and a gate electrode 107. + A mold area 108 is provided.

[0034] The p-type base region 103 is a p-type SiC layer 123 having an n + type source region 104 and p ++ The portion excluding the contact region is the front surface of the semiconductor substrate 120 and the n-type contact region. - The n-type drift region 102 is provided between the n-type drift region 102 and the n-type drift region 102. + type source region 104 and p ++ The n-type contact regions are selectively provided between the front surface of the semiconductor substrate 120 and the p-type base region 103. + type source region 104 and p ++ The p-type contact region is a diffusion region (SiC portion) formed in the surface region of the p-type SiC layer 123 by ion implantation.

[0035] The gate trench 105 is + through the p-type source region 104 and the p-type base region 103, - The gate electrode 107 is provided in the gate trench 105 via a gate insulating film 106. + The type region 108 is - The p-type base region 103 is a diffusion region formed by ion implantation inside the p-type SiC layer 122. ++ Type contact region and p + The p-type region 108 is formed using aluminum (Al) as a p-type dopant.

[0036] The interlayer insulating film 109 is provided on the entire front surface of the semiconductor substrate 120, and covers the gate electrode 107. The source electrode 113 is connected to the p-type base region 103 and the n-type base region 104 through a contact hole in the interlayer insulating film 109 via a barrier metal 112 and an ohmic electrode 111. + type source region 104 and p ++The back surface (n + The entire surface of the starting substrate 121 (the back surface of the starting substrate 121) is + Starting substrate 121(n + A drain electrode 114 is provided in contact with the n-type drain region 101).

[0037] As described above, in the semiconductor device 110 of the reference example, the p-type base region 103 and the p-type ohmic electrode 111 are electrically connected to each other. ++ p-type contact region for electric field relaxation + Al is used as a p-type dopant in forming p-type SiC regions such as the die region 108. Although not shown, the p-type SiC region disposed in the edge termination region surrounding the active region and constituting a breakdown voltage structure, and the p-type SiC region disposed in the boundary region (not shown) between the active region and the edge termination region are also formed by ion implantation using Al as the p-type dopant.

[0038] The inventors have confirmed through intensive research that when a p-type SiC region is formed using Al as a p-type dopant in this manner, the lower the junction temperature (temperature of the semiconductor substrate 120), the higher the sheet resistance of the p-type SiC region. The results of measuring the sheet resistance [Ω / □, ohms per square] for the n-type SiC region and multiple p-type SiC regions with different impurity concentrations of the semiconductor device 110 of the reference example while varying the temperature of the semiconductor substrate 120 are shown in Fig. 7. Fig. 7 is a characteristic diagram showing the relationship between the sheet resistance of the p-type SiC region of the semiconductor device of the reference example and the temperature of the semiconductor substrate 120.

[0039] n in Figure 7 + type region, p ++ type region, p + The n-type and p-type regions are shown in FIG. + type source region 104, p ++ Type contact area, p + 7. The p-type region 108 and the p-type base region 103 correspond to the p-type region 108 and the p-type base region 103 in FIG. -The type region corresponds to a p-type SiC region that is arranged in an edge termination region (not shown) of the semiconductor device 110 of the reference example and that constitutes a breakdown voltage structure such as a junction termination extension (JTE) structure or a field limiting ring (FLR).

[0040] From the results shown in FIG. 7, even if the temperature of the semiconductor substrate 120 changes, the n-type SiC region (n + The sheet resistance of the p-type SiC region (p ++ type region, p + type region, p-type region and p - 7 , the sheet resistance of the p-type SiC region increases as the temperature of the semiconductor substrate 120 decreases, and it has been confirmed that this tendency is the same regardless of the impurity concentration. Therefore, it can be said that the sheet resistance of all p-type SiC regions formed in the semiconductor substrate 120 using Al as a p-type dopant shows the same tendency as the p-type SiC region in FIG. 7 with respect to the temperature of the semiconductor substrate 120.

[0041] When the sheet resistance of the p-type SiC region increases due to a decrease in the temperature of the semiconductor substrate, the depletion layer spreads from the pn junction between the p-type SiC region and the n-type SiC region into the p-type SiC region with a width wider than the designed depletion layer width. The more abruptly the dV / dt (time rate of change of the drain-source voltage) changes when the SiC-MOSFET is off, the more the depletion layer spreads transiently into the p-type SiC region, causing the majority carriers (holes) in the p-type SiC region to be depleted, and the more likely the p-type SiC region will no longer function as a stopper to stop the spread of the depletion layer.

[0042] For example, the active region is usually a p-type base region 103 and an n-type - A depletion layer extending from the pn junction with the p-type drift region 102 into the p-type base region 103 is +However, when the temperature of the semiconductor substrate 120 becomes low and the sheet resistance of the p-type base region 103 becomes high, the carrier concentration (concentration of activated impurities) of the p-type base region 103 becomes lower than the design value, and the depletion layer is formed at both ends (the end in the p-type base region 103 and the n-type source region 104). - The potential difference (diffusion potential) at the end of the p-type drift region 102 spreads vertically in the p-type base region 103 faster than usual so as to balance out.

[0043] At this time, if the SiC-MOSFET is turned off at high speed to abruptly change dV / dt, the depletion layer that has spread in the p-type base region 103 will become n + When the SiC-MOSFET is turned off, the p-type base region 103 and the n-type source region 104 are punched through, resulting in local destruction of the device. - The depletion layer extends vertically from the pn junction with the p-type drift region 102 toward both main surfaces of the semiconductor substrate 120 (the end of the p-type base region 103 and the n - The depth position d according to the built-in potential at the end of the drift region 102 px ,d nx (where x is a positive number equal to or greater than 101: that is, in the p-type base region 103 and in the n - 10A and 10B are images of the equipotential line distribution of the depletion layer in the drift region 102, respectively, shown by fine and coarse dashed and dotted lines.

[0044] The p-type base region 103 and the n - The higher the voltage applied to the pn junction with the drift region 102, the greater the depth position d 100 Depth position d away from px ,d nx In FIG. 8, the depletion layer reaches the p-type base region 103 and the n - If the distance between the equipotential lines of the depletion layer in the p-type drift region 102 (the potential difference between the two-dot chain lines) is 100 V, - When the voltage applied to the pn junction with the p-type drift region 102 becomes 600 V or more, the end of the depletion layer extending vertically in the p-type base region 103 (depth position of the pn junction d100 Depth position d of the 6th and 7th lines p106 ,d p107 The equipotential lines of + 1 shows an example of reaching the mold source region 104.

[0045] The front surface of the semiconductor substrate 120 and - Even if only a p-type SiC region is disposed between the n-type drift region 102 and the p-type SiC region, if the temperature of the semiconductor substrate 120 is low, the steep dV / dt at the time of turning off the SiC-MOSFET may cause a breakdown between the p-type SiC region and the n-type drift region 102. - 7. A depletion layer spreading into the p-type SiC region from the pn junction with the p-type drift region 102 reaches the insulating layer on the front surface of the semiconductor substrate 120, where an electric field concentrates and dielectric breakdown occurs. Although not shown, even when the p-type SiC region is formed using boron (B) as the p-type dopant, it is estimated that the sheet resistance of the p-type SiC region will show the same tendency as the p-type SiC region in FIG. 7 with respect to the temperature of the semiconductor substrate.

[0046] Therefore, the problem to be solved in this embodiment is to improve the switching resistance of a SiC-MOSFET (semiconductor device), particularly the resistance to steep dV / dt, regardless of the temperature of the semiconductor substrate. The switching resistance indicates the resistance to dynamic destruction due to short circuit, turn-on, turn-off, dV / dt, etc.

[0047] Preferred embodiments of the semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions marked with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - added to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions not marked with them. In the following description of the embodiments and the accompanying drawings, the same reference numerals are used for similar configurations, and duplicated explanations will be omitted.

[0048] (Details of the first embodiment) A semiconductor device according to a first embodiment that solves the above-mentioned problems will be described below. FIG. 1 is a plan view showing a layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 2 is a cross-sectional view showing a cross-sectional structure along the cutting line A-A' in FIG. 1. FIG. 3 is a cross-sectional view showing another example of the cross-sectional structure along the cutting line A-A' in FIG. 1. A semiconductor device 10 according to the first embodiment shown in FIGS. 1 and 2 is a vertical SiC-MOSFET having a trench gate structure (element structure) in an active region 31 of a semiconductor substrate (semiconductor chip) 40 using silicon carbide (SiC) as a semiconductor material.

[0049] The active region 31 is a region through which a main current (drift current) flows when the MOSFET is on. The active region 31 has, for example, a substantially rectangular planar shape, and is disposed approximately in the center (chip center) of the semiconductor substrate 40. The effective region of the active region 31 is a region in which multiple MOSFET cells (functional units of an element) of the same structure are disposed adjacent to each other, and occupies most of the area of ​​the semiconductor substrate 40. The ineffective region of the active region 31 is a region of the active region 31 excluding the effective region, in which no MOSFET cells are disposed and which does not function as a MOSFET.

[0050] A boundary region 32 between the active region 31 and the edge termination region 33 surrounds the periphery of the active region 31 in a substantially rectangular shape. - When the MOSFET is off, the n-type drift region 2 and the n-type drift region 3 are in the n-type - A p-type peripheral region (not shown) is provided for extracting holes in the p-type drift region 2 to the source electrode 11. The edge termination region 33 is a region between the boundary region 32 and the edge (chip edge) of the semiconductor substrate 40, and surrounds the periphery of the boundary region 32 in a substantially rectangular shape. A predetermined voltage withstanding structure is disposed in the edge termination region 33.

[0051] Provided on the front surface of the semiconductor substrate 40 are electrode pads such as a source pad (source electrode 11) and a gate pad 12, metal wiring layers such as a gate runner 13, a gate ring 15 (solid thick line in FIG. 1) and a source ring 16 (solid dashed line in FIG. 1), a gate resistor 14 (hatched portion in FIG. 1) made of polysilicon (poly-Si), and a gate polysilicon wiring layer (not shown). The source electrode (first electrode) 11 is provided in the effective region of the active region 31 and covers substantially the entire effective region of the active region 31.

[0052] The gate pad 12, the gate runner 13, and the gate resistor 14, and the gate pad 12 and the gate runner 13 directly below (n + A gate polysilicon wiring layer on the side of the source and drain regions 1 (type drain region 1 side) is provided in an ineffective region of an active region 31. A gate ring 15, a source ring 16, and a gate polysilicon wiring layer directly below the gate ring 15 are provided in a boundary region 32. The gate electrodes 7 of all the cells of the MOSFET are electrically connected to the gate pad 12 via a gate resistor 14 and a gate runner 13.

[0053] The gate ring 15 surrounds the active region 31 in, for example, a substantially rectangular shape with a partial opening. The gate ring 15 is electrically connected to the gate electrode 7 via a gate polysilicon wiring layer directly below the gate ring 15 at a location away from the gate runner 13, and has the function of making the potential of the gate electrode 7 of all cells uniform. The source ring 16 is disposed outside the gate ring 15, and surrounds the active region 31 in a substantially rectangular shape. The source ring 16 is connected to the source electrode 11 at a partially open location of the gate ring 15, and is fixed to the potential of the source electrode 11.

[0054] The semiconductor substrate 40 is a n-type semiconductor substrate using SiC as a semiconductor material. + On the front surface of the starting mold substrate 41, - The SiC layers 42 and 43 that become the n-type drift region (n-type region) 2 and the p-type base region (p-type region, first p-type region) 3 are epitaxially grown in this order. The p-type base region 3 is formed by epitaxial growth, and the n- Alternatively, the n-type drift region 2 may be formed by ion implantation of aluminum (Al). The semiconductor substrate 40 has a first main surface on the p-type SiC layer 43 side as a front surface, and an n-type SiC layer 44 as a back surface. + The second main surface on the mold starting substrate 41 side is referred to as the back surface. + The starting substrate 41 is n + This is the n-type drain region 1. - The type SiC layer 42 is doped with an n-type dopant, such as phosphorus (P) or arsenic (As).

[0055] The p-type SiC layer 43 is doped with, for example, aluminum (Al) or boron (B) as a p-type dopant. The p-type region inside the semiconductor substrate 40 includes a p-type SiC part (corresponding to p-type SiC part 51 in FIG. 2) made of a diffusion region (SiC part in which an impurity of a predetermined conductivity type is diffused) formed by ion implantation inside the p-type SiC layer 43 itself or the SiC layers 42, 43, and a p-type polysilicon part (corresponding to p-type polysilicon part 52 in FIG. 2) made of p-type polysilicon containing, for example, Al or B as a p-type dopant.

[0056] n - The type SiC layer 42 is + The interface with the starting substrate 41 is + The upper surface of the mold region 21 (n + A layer up to the surface on the side of the p-type source region 4) + A layer from the upper surface of the mold region 21 to the interface with the p-type SiC layer 43 (a p + Alternatively, epitaxial growth may be performed in two stages, one in which the first layer is a layer where the mold connection portion 22 is provided, and the other in which the second layer is a layer where the mold connection portion 22 is provided. - The second layer of the type SiC layer 42 (p + The thickness of the portion where the die connecting portion 22 is provided is, for example, about 0.5 μm. The thickness of the p-type SiC layer 43 is, for example, about 1.1 μm.

[0057] Specifically, the trench gate structure includes a p-type base region 3, a n +The p-type base region 3 is formed of an n-type source region (n-type partial region) 4, a gate trench 5, a gate insulating film 6, and a gate electrode 7. The p-type base region 3 is formed on the front surface of the semiconductor substrate 40 and on the n-type - Between the n-type drift region 2, - The p-type base region 3 is provided in contact with the p-type drift region 2. The p-type base region 3 is provided in contact with the lower portion (n + A portion on the drain region 1 side: p-type SiC portion (p-type silicon carbide portion) 51 and an upper portion (hatched portion on the source electrode 11 side: p-type polysilicon portion) 52 made of p-type polysilicon are adjacent to each other in the depth direction.

[0058] The p-type SiC portion 51 and the p-type polysilicon portion 52 are adjacent to the gate trench 5 and contact the gate insulating film 6 on the side wall of the gate trench 5. A channel is formed in the portion of the p-type SiC portion 51 and the p-type polysilicon portion 52 along the side wall of the gate trench 5. + The portion excluding the p-type source region 4, the region where the p-type polysilicon portion 52 is formed (the portion removed by the formation of the trench 53 described later), and the portion removed by the formation of the gate trench 5 is the p-type SiC portion 51.

[0059] The p-type polysilicon portion 52 is formed by filling a trench 53 formed in the p-type SiC layer 43 with p-type polysilicon doped with a p-type dopant, or by ion-implanting a p-type dopant into undoped polysilicon filled in the trench 53. For example, Al or B can be used as the p-type dopant for forming the p-type polysilicon portion 52. The p-type polysilicon portion 52 has a lower surface (n + The surface (on the side of the drain region 1) of the trench 53 contacts the p-type SiC portion 51. The trench 53 is formed to a depth not penetrating the p-type SiC portion 51 (p-type SiC layer 43) in the depth direction.

[0060] The dose of the p-type dopant introduced into the p-type polysilicon portion 52 is approximately the same as the dose of the p-type dopant introduced into the p-type SiC portion 51. Since the band gap of polysilicon is smaller than that of SiC, the sheet resistance of the p-type polysilicon portion 52 does not vary much even when the junction temperature (temperature of the semiconductor substrate 40) becomes low, such as about -40°C or -55°C, or becomes high, such as about 175°C or higher, and is approximately constant regardless of the temperature of the semiconductor substrate 40. The sheet resistance of the p-type polysilicon portion 52 is approximately constant regardless of the temperature of the semiconductor substrate 40, as shown in FIG. 7 with respect to the temperature of the semiconductor substrate 40. + The trend is almost the same as that of the type region.

[0061] Therefore, the carrier concentration of the p-type polysilicon portion 52 is almost independent of the temperature of the semiconductor substrate 40, and even if the temperature of the semiconductor substrate 40 is low, majority carriers (positive holes) are abundantly present in the p-type polysilicon portion 52. Therefore, even if dV / dt changes sharply when the MOSFET (semiconductor device 10) is turned off, majority carriers in the p-type base region 3 are not depleted, and a depletion layer is unlikely to spread in the p-type base region 3. The p-type polysilicon portion 52 is connected to the p-type base region 3 (p-type SiC portion 51) and n-type polysilicon portion 52 when the MOSFET is turned off. - The depletion layer extending from the pn junction to the drift region 2 is + It functions as a stopper to prevent the source region 4 from being reached.

[0062] The p-type polysilicon portion 52 is + The p-type polysilicon portion 52 faces the entire lower surface of the n-type source region 4. As long as it can function as a stopper for the p-type polysilicon portion 52, the p-type polysilicon portion 52 may reach the front surface of the semiconductor substrate 40, may be disposed away from the front surface of the semiconductor substrate 40, or may be disposed at a distance from the front surface of the semiconductor substrate 40. + 4. + It may be located on the side of the drain region 1. When the p-type polysilicon portion 52 is away from the front surface of the semiconductor substrate 40, the area between the front surface of the semiconductor substrate 40 and the p-type polysilicon portion 52 becomes the p-type SiC portion 51.

[0063] Since the p-type polysilicon portion 52 may be disposed away from the front surface of the semiconductor substrate 40, it is also possible to provide a contact trench 8 with the source electrode 11 on the front surface of the semiconductor substrate 40 (see FIG. 3). In this case, the p-type polysilicon portion 52 is located n-type from the bottom surface of the contact trench 8. + The p-type polysilicon portion 52 is formed between the bottom surface of the contact trench 8 and the p-type drain region 1 and is exposed on the inner wall of the contact trench 8. ++ A mold contact area (not shown) may also be provided.

[0064] The depth position of the bottom surface of the p-type polysilicon portion 52 is n + The thickness of the n-type source region 4 may be twice or more, and preferably the n-type source region 4 may be + It is preferable that the thickness of the n-type source region 4 is three times or more. + The thickness of the n-type source region 4 is the thickness from the front surface of the semiconductor substrate 40 + The depth of p-type dopant in p-type polysilicon portion 52 and other p-type polysilicon portions described later can be activated simultaneously with activation of dopants in SiC layers 42 and 43 by laser annealing from the front surface of semiconductor substrate 40 or general heat treatment such as furnace annealing.

[0065] The p-type polysilicon portion 52 may be formed in a plurality of steps. That is, the trench 53 may be formed and the p-type polysilicon portion 52 may be embedded each time the p-type SiC layer 43 is epitaxially grown in a plurality of steps. For example, when the p-type polysilicon portion 52 reaches the front surface of the semiconductor substrate 40, the p-type SiC layer 43 is epitaxially grown in two steps. A trench 53 (53a) is formed to a predetermined depth in the first step of the p-type SiC layer 43, and the lower part of the p-type polysilicon portion 52 is embedded in the trench 53a.

[0066] A trench 53 (53b) is formed in the second stage of the p-type SiC layer 43 to a depth that reaches the lower part of the p-type polysilicon portion 52, and the upper part of the p-type polysilicon portion 52 is embedded in the trench 53b to connect the lower and upper parts of the p-type polysilicon portion 52. The lower part of the p-type polysilicon portion 52 is, for example, n + n type source region 4 + The upper portion of the p-type polysilicon portion 52 is a portion on the side of the p-type drain region 1. + This is the portion adjacent to the source region 4.

[0067] In this case, the portion of the first stage of the p-type SiC layer 43 that remains after the formation of the trench 53a becomes the p-type SiC portion 51. The portion of the second stage of the p-type SiC layer 43 between the p-type polysilicon portion 52 (trench 53b) and the gate trench 5 becomes the n-type SiC portion 52. + A source region 4 is formed. + The n-type source region 4 is a diffusion region formed by ion implantation in the surface region of the p-type SiC layer 43. + The p-type source region 4 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 3 in contact with the p-type base region 3 .

[0068] n + The n-type source region 4 is in contact with the ohmic electrode 17 on the front surface of the semiconductor substrate 40. + The p-type source region 4 is adjacent to the side wall of the gate trench 5 and contacts the gate insulating film 6 at the side wall of the gate trench 5. For example, when the gate trench 5 extends linearly in a direction parallel to the front surface of the semiconductor substrate 40, the p-type SiC portion 51, the p-type polysilicon portion 52 and the n-type SiC portion 53 are connected to each other. + The n-type source region 4 extends linearly in the longitudinal direction of the gate trench 5. + The source regions 4 may be interspersed in the longitudinal direction of the gate trench 5 .

[0069] Also, n + When the n-type source regions 4 are interspersed in the longitudinal direction of the gate trench 5, +The p-type source region 4 and the p-type base region 3 (or the p ++ The contact regions are alternately and repeatedly arranged adjacent to each other in the longitudinal direction of the gate trench 5. + When the n-type source regions 4 are interspersed in the longitudinal direction of the gate trench 5, the n-type source regions 4 adjacent to each of the side walls of the gate trench 5 are + The type source regions 4 may or may not face each other in the short direction of the gate trench 5.

[0070] n + The p-type source region 4 does not have to be provided between the gate trench 5 on the chip edge side and the boundary region 32. ++ A contact region (not shown) may be provided. ++ The contact region may be a diffusion region formed in the surface region of the p-type SiC layer 43 by ion implantation, or may be formed by increasing the impurity concentration in a part of the p-type polysilicon portion 52.

[0071] n + The n-type region (n + As an n-type dopant for forming a p-type channel stopper region, for example, P, As or nitrogen (N) can be used. ++ The p-type contact region and the p-type region (p-type peripheral region and p-type region constituting the breakdown voltage structure) provided outside the effective region of the active region 31 described later - As a p-type dopant for forming the p-type SiC portion and the p-type polysilicon portion constituting the p-type region, for example, Al or B can be used.

[0072] The gate trench 5 is formed from the front surface of the semiconductor substrate 40 to an n-type + The n-type source region 4, the p-type polysilicon portion 52, and the p-type SiC portion 51 are penetrated. -The gate trench 5 terminates inside the type-SiC layer 42. The gate trenches 5 extend linearly in a direction parallel to the front surface of the semiconductor substrate 40 (longitudinal direction: depth direction in FIG. 2) and are arranged in a stripe pattern adjacent to each other in the lateral direction (direction perpendicular to the longitudinal direction: lateral direction in FIG. 2). A gate electrode 7 is provided inside the gate trench 5 with a gate insulating film 6 interposed therebetween.

[0073] p-type base region 3 and n - Between the n-type drift region 2 and the bottom surface of the gate trench 5, + A p-type drain region 1 is formed at a deep position facing the bottom surface of the gate trench 5. + A mold area 21 is provided. + The type region 21 is p + The p-type base region 3 is connected to the p-type connection portion 22 and is fixed to the potential of the source electrode 11. + The mold region 21 may be in contact with the gate insulating film 6 at the bottom surface of the gate trench 5. + The type region 21 has a function of being depleted when the MOSFET is turned off, thereby reducing the electric field in the vicinity of the bottom surface of the gate trench 5 .

[0074] p + The width (width in the short side direction) of the mold region 21 is, for example, wider than the width (width in the short side direction) of the gate trench 5. + The mold connection portion 22 is formed along the side wall of the gate trench 5. + The p-type region 21 reaches the p-type base region 3. + The mold coupling parts 22 may be interspersed in the longitudinal direction of the gate trench 5, or may extend linearly in the longitudinal direction of the gate trench 5 only on one sidewall side of the gate trench 5. + Type region 21 and p + The type connecting portion 22 is n - This is a diffusion region formed inside the type SiC layer 42 by ion implantation.

[0075] p-type base region 3 and n - Between the n-type drift region 2 and the bottom surface of the gate trench 5, + A p-type base region 3 and an n-type drain region 1 are disposed deep on the side of the p-type- Type drift region 2, p + Type region 21 and p + An n-type current diffusion region (not shown) may be provided in contact with the type coupling portion 22. The n-type current diffusion region is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. - This is a diffusion region formed inside the type SiC layer 42 by ion implantation.

[0076] n - The p-type SiC layer 42 + type region 21, p + The p-type outer peripheral region (not shown) of the n-type coupling portion 22, the n-type current diffusion region, the invalid region of the active region 31 and the boundary region 32, which will be described later, and the edge termination region 33, which will be described later, constitute a breakdown voltage structure. - The part excluding the mold region (not shown) and the channel stopper region (not shown) described later is n - For example, the p-type SiC layer 43 is removed from the edge termination region 33, thereby forming an n - A layer of SiC 42 forms the front surface of semiconductor substrate 40 in edge termination region 33 .

[0077] The p-type peripheral region (third p-type region) is a region that is adjacent to the front surface of the semiconductor substrate 40 at the boundary region 32 and is - Between the n-type drift region 2 and the n-type drift region 3, - The p-type peripheral region is disposed in contact with the n-type drift region 2. The p-type peripheral region surrounds the periphery of the active region 31 and is in contact with the front surface of the semiconductor substrate 40 in the ineffective region of the active region 31. - The p-type peripheral region is fixed to the potential of the source electrode 11, and when the MOSFET is turned off, the p-type peripheral region extends to the entire region between the p-type drift region 2 and the n-type peripheral region 33. - It has the function of extracting holes in the type drift region 2 to the source electrode 11 or the source ring 16 .

[0078] Pressure-resistant structure - The n-type region (second p-type region) is connected to the front surface of the semiconductor substrate 40 in the edge termination region 33. -The transistor is selectively provided between the active region 31 and the drift region 2, and is concentrically arranged around the active region 31. - A field limiting ring (FLR) or a junction termination extension (JTE) structure may be arranged in the mold region.

[0079] The JTE structure consists of multiple p - The p-type region has a lower impurity concentration as it moves away from the center of the chip to the edge of the chip. - The channel stopper region is disposed adjacent to the active region 31 so as to be concentric with the active region 31. The channel stopper region is disposed on the outside of the breakdown voltage structure and adjacent to the front surface of the semiconductor substrate 40. - The channel stopper region is provided between the n-type drift region 2 and the breakdown voltage structure, and is exposed at the chip end (the side surface of the semiconductor substrate 40). + It may be of the type p + The p-type region may be a p-type region.

[0080] It is preferable that the p-type regions provided outside the effective regions of these active regions 31 have a structure in which a p-type SiC portion and a p-type polysilicon portion are adjacent to each other in the depth direction, similar to the p-type base region 3. The p-type polysilicon portion of this p-type region is also formed by burying a p-type polysilicon layer in a trench of a predetermined depth formed in the semiconductor substrate 40, similar to the p-type polysilicon portion 52 of the p-type base region 3. The p-type peripheral region of the boundary region 32 is, for example, a p + type region 21, p + It may have a laminated structure including p-type portions formed simultaneously with the mold connecting portion 22, the p-type SiC portion 51, and the p-type polysilicon portion 52.

[0081] The interlayer insulating film 9 is provided over almost the entire front surface of the semiconductor substrate 40, and covers all of the gate electrodes 7. The ohmic electrodes 17 are in ohmic contact with the semiconductor substrate 40 through contact holes in the interlayer insulating film 9, and are in ohmic contact with the p-type base region 3 and the n-type + Type source region 4(p++ When a p-type contact region is provided, ++ The ohmic electrode 17 is electrically connected to a semiconductor substrate 40 (a contact region). The ohmic electrode 17 is, for example, a nickel silicide (NixSiy, where x and y are positive numbers) film formed by silicidation with the semiconductor substrate 40.

[0082] Barrier metal 18 covers almost the entire surface of interlayer insulating film 9 and ohmic electrode 17 in active region 31. Barrier metal 18 has the function of preventing atomic diffusion and mutual reaction between source electrode 11 and semiconductor substrate 40. Source electrode 11 is provided on almost the entire surface of semiconductor substrate 40 in the effective region of active region 31, and is connected to p-type base region 3 and n-type base region 4 via barrier metal 18 and ohmic electrode 17. + Type source region 4(p ++ When a p-type contact region is provided, ++ The semiconductor device is electrically connected to the semiconductor substrate (type contact region).

[0083] A contact trench 8 may be provided on the front surface of the semiconductor substrate 40 (see FIG. 3). In this case, the inner wall of the contact trench 8 is + The p-type source region 4 and the p-type polysilicon portion 52 are exposed. ++ A type contact region may be provided. The barrier metal 18 and the ohmic electrode 17 are provided along the inner wall of the contact trench 8, and the source electrode 11 is provided on the barrier metal 18 so as to fill the contact trench 8.

[0084] The portion of the source electrode 11 exposed in the opening of the passivation film (not shown) functions as a source pad. The passivation film is a surface protection film that covers the outermost surface of the front surface of the semiconductor substrate 40 and protects the front surface of the semiconductor substrate 40. + A drain electrode (second electrode) 24 is provided on the entire back surface of the starting substrate 41. The drain electrode 19 is in ohmic contact with the back surface of the semiconductor substrate 40, and + Type drain region 1(n+ The mold is electrically connected to a starting substrate 41).

[0085] The entire front surface of the semiconductor substrate 40 in the invalid region of the active region 31, the boundary region 32 and the edge termination region 33 is covered with an insulating layer formed by laminating a field oxide film (not shown) and an interlayer insulating film 9 in this order. - The mold region is covered with the insulating layer. Between the field oxide film and the interlayer insulating film 9, a gate pad 12, a gate runner 13, and a gate polysilicon wiring layer immediately below the gate ring 15 (see FIG. 1), and a gate resistor 14 (see FIG. 1) are provided.

[0086] The entire surfaces of gate pad 12, gate runner 13, gate ring 15, the gate polysilicon wiring layer directly below them, and gate resistor 14 (see FIG. 1) face the p-type peripheral region via the field oxide film. Source ring 16 is electrically connected to the p-type peripheral region via interlayer insulating film 9 and a contact hole in the field oxide film. Gate pad 12, gate runner 13, gate ring 15, and source ring 16 are formed simultaneously with source electrode 11, for example, and are provided in the same layer as source electrode 11.

[0087] The operation of the semiconductor device 10 (MOSFET) according to the first embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 7 in a state where a positive voltage with respect to the source electrode 11 is applied to the drain electrode 19, the n-type SiC portion 51 and the p-type polysilicon portion 52 of the p-type base region 3 are + Type source region 4 and n - A channel (n-type inversion layer) is formed along the sidewall of the gate trench 5 between the n-type drift region 2 and the n ++ From the drain region 1, - Through the drift region 2 and the channel + A drift current (main current) flows toward the type source region 4, turning the MOSFET on.

[0088] On the other hand, when a voltage positive with respect to the source electrode 11 is applied to the drain electrode 19 and the voltage applied to the gate electrode 7 is less than the gate threshold voltage, the p-type base region 3, + Type region 21 and p + Type connecting portion 22 and n - Since the pn junction (main junction) with the type drift region 2 is reverse biased, the MOSFET maintains the off state. A depletion layer spreads vertically from the pn junction in the active region 31 toward both main surfaces of the semiconductor substrate 40, and also spreads horizontally from the effective region of the active region 31 toward the ineffective region of the active region 31 and the boundary region 32. - By depleting the type drift region 2, a predetermined breakdown voltage of the effective region of the active region 31 is ensured.

[0089] In addition, in the invalid region and boundary region 32 of the active region 31, the p-type peripheral region and the n - The pn junction with the drift region 2 is reverse biased, so that n - A depletion layer spreads laterally in the drift region 2. Furthermore, in the edge termination region 33, the p - Type domain and n - The pn junction with the drift region 2 is reverse biased, so that the n - The depletion layer spreads laterally outward in the n-type drift region 2. - The depletion layer extends outward in the type drift region 2, ensuring a predetermined breakdown voltage in the edge termination region 33 based on the dielectric breakdown field strength of the semiconductor material.

[0090] In addition, during the period when the MOSFET transitions from on to off, the p-type base region 3, + type region 21, p + a p-type connecting portion 22 and a p-type peripheral region, - The parasitic pn junction diode (body diode) formed by the pn junction of the drift region 2 and the n -Carriers (holes and electrons) are injected and stored in the n-type drift region 2. When the MOSFET is turned off from this state (reverse recovery of the body diode occurs), - Holes in the n-type drift region 2 are discharged to the source electrode 11 or source ring 16 through the p-type base region 3 of the active region 31 or the p-type peripheral region of the boundary region 32, and - The electrons in the type drift region 2 are discharged to the drain electrode 19, thereby turning off the MOSFET.

[0091] When the MOSFET is off, the p-type base region 3 and the n - The higher the voltage applied to the pn junction with the drift region 2, the greater the distance between the depth position d px ,d nx The depletion layer reaches the active region 31. When the MOSFET is off, the effective region of the active region 31 is the region between the p-type base region 3 and the n-type - The depletion layer that extends vertically from the pn junction with the n-type drift region 2 + The p-type polysilicon portion 52 is designed so as not to reach the n-type source region 4. Also, as described above, the sheet resistance of the p-type polysilicon portion 52 constituting the p-type base region 3 does not depend on the temperature of the semiconductor substrate, so that the carrier concentration of the p-type polysilicon portion 52 does not change even if the temperature of the semiconductor substrate is low, for example, at about -40°C or -55°C. Therefore, when the MOSFET is turned off, the depletion layer is unlikely to spread within the p-type polysilicon portion 52 of the p-type base region 3, regardless of the temperature of the semiconductor substrate, and the depletion layer is unlikely to spread within the n-type polysilicon portion 52 of the p-type base region 3 even if dV / dt changes sharply by turning off the MOSFET at high speed. + The source region 4 is not reached.

[0092] 2 and 3 show the p-type base region 3 and the n-type - The depletion layer extending vertically from the pn junction with the p-type drift region 2 (the end of the p-type base region 3 and the n - The depth position d according to the built-in potential at the end of the drift region 2 px ,d nx (where x is a positive number of 1 or more: that is, in the p-type base region 3 and in the n -The equipotential distribution of the depletion layer in the p-type drift region 2 is shown by a fine dashed double-dashed line and a coarse dashed double-dashed line (the same applies to Figs. 4 to 6). - If the distance between the equipotential lines of the depletion layer in the drift region 2 (the potential difference between the two-dot chain lines) is, for example, 100 V, - Even if the voltage applied to the pn junction with the type drift region 2 becomes about 600 V, the end of the depletion layer (the sixth depth position d from the pn junction depth position d p6 ) is n + 4 to 6. In FIG.

[0093] The front surface of the semiconductor substrate 40 in the invalid area of ​​the active region 31, the boundary region 32 and the edge termination region 33 and n - A p-type region (p-type peripheral region, p-type region constituting a breakdown voltage structure) is provided between the p-type drift region 2 and the - type region, p + By including a p-type polysilicon portion in each of the p-type regions (p-type channel stopper region), the depletion layer is less likely to spread vertically in the p-type region even if the temperature of the semiconductor substrate 40 is low. As a result, even if dV / dt changes sharply when the SiC-MOSFET is turned off, the depletion layer spreading in the p-type region does not reach the insulating layer on the front surface of the semiconductor substrate 40, so that insulation breakdown due to electric field concentration can be suppressed. In this way, by including a p-type polysilicon portion in each of the p-type regions in the semiconductor substrate 40, the spread of the depletion layer in the vertical direction can be suppressed almost as designed, regardless of the temperature of the semiconductor substrate 40.

[0094] When the MOSFET is off, the p-type base region 3 and the n - The depletion layer that spreads from the pn junction with the p-type drift region 2 to the p-type base region 3 is ++ There is no problem if the n-type contact region is reached. - The n-type impurity concentration of the n-type drift region 2 is lower than the p-type impurity concentration of the p-type base region 3, so that the p-type base region 3 and the n -The depletion layer that spreads from the pn junction with the p-type drift region 2 grows faster than the vertical expansion in the p-type base region 3. - The depletion layer extends vertically in the n-type drift region 2. - The faster the n - The electric field applied to the n-type drift region 2 can be reduced. - Even if the electrons rapidly spread vertically in the n-type drift region 2, the electrons are not directly in contact with the rear surface of the semiconductor substrate 40. - Between the n-type drift region 2 + Due to the presence of the type drain region 1, no problem arises.

[0095] Any n-type SiC region (n - Type drift region 2, n + 4, n-type source region, n-type current diffusion region, + In the n-type channel stopper region, the sheet resistance of the n-type SiC region is the same as that of the n-type SiC region in FIG. 7 with respect to the temperature of the semiconductor substrate 40, regardless of the impurity concentration. + The n-type region (reference structure shown in Figure 8) + 7 with respect to the temperature of the semiconductor substrate 40, regardless of the conductivity type. + The inventors have confirmed that this shows the same tendency as in the mold region.

[0096] As described above, according to the first embodiment, the p-type region provided in the effective region of the active region is composed of a p-type SiC portion and a p-type polysilicon portion. Since the sheet resistance of the p-type polysilicon portion is almost constant regardless of the temperature of the semiconductor substrate, the carrier concentration of the p-type polysilicon portion does not decrease even if the temperature of the semiconductor substrate is low, and majority carriers (positive holes) are abundant in the p-type polysilicon portion. For example, in a MOSFET, even if it is turned off at high speed under conditions where the temperature of the semiconductor substrate is low and dV / dt changes sharply, the depletion layer is unlikely to spread in the p-type base region, and the majority carriers in the p-type base region are not depleted. For this reason, the depletion layer is n +Therefore, it is possible to suppress punch-through due to the ion implantation reaching the source region.

[0097] Therefore, the switching resistance during switching of the MOSFET (semiconductor device), particularly the resistance to steep dV / dt, can be improved, and the electrical characteristics of the MOSFET can be prevented from fluctuating under conditions where the temperature of the semiconductor substrate is low. For example, when the temperature of the semiconductor substrate is low, such as about -40°C or -55°C, the inventors have confirmed through experiments that a switching resistance capable of blocking a hole current (reverse recovery current of the body diode) of about 5 times or more of the rated current is ensured against a steep dV / dt of about 50 kV / sec or 100 kV / sec. Also, when the temperature of the semiconductor substrate is high, such as about 175°C or 200°C, the switching resistance against steep dV / dt can be ensured to the same extent as when the temperature of the semiconductor substrate is low.

[0098] According to the first embodiment, the p-type region provided outside the effective region of the active region (the p-type peripheral region of the ineffective region and boundary region of the active region, and the p-type peripheral region of the edge termination region that constitutes the breakdown voltage structure) - type region, p + By forming a part of the p-type polysilicon portion for the p-type channel stopper region, the p-type polysilicon portion can function as a stopper that suppresses the spread of the depletion layer. This makes it possible to suppress the electric field concentration at a location where the electric field reaches the insulating layer on the front surface of the semiconductor substrate in a region other than the effective region of the active region. It is also possible to suppress the depletion layer from reaching the chip end in the lateral direction and becoming a reach-through. This makes it possible to further improve the switching tolerance of the MOSFET.

[0099] (Details of the second embodiment) A semiconductor device according to a second embodiment that solves the above-mentioned problems will be described below. FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. The layout of a semiconductor device 60 according to the second embodiment, as viewed from the front surface side of a semiconductor substrate 40, is the same as that of FIG. 1, with reference numeral 60 replacing reference numeral 10. FIG. 4 shows the cross-sectional structure taken along line A-A' in FIG. 1. The semiconductor device 60 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment (see FIG. 2) in that the semiconductor device 60 has p + Type region 21 is p + The p-type SiC portion (p-type silicon carbide portion) 61 and the p + The point is that it is constituted by a mold polysilicon portion 62 (hatched portion).

[0100] p + The type SiC portion 61 is - The p-type SiC layer 42 is a diffusion region formed by ion implantation. + Between the type SiC portion 61, + A mold polysilicon portion 62 is provided. + The polysilicon portion 62 is p + A trench 63 formed in the SiC portion 61 is doped with a p-type dopant. + The trench 63 is filled with p-type polysilicon or non-doped polysilicon filled in the trench 63 is ion-implanted with p-type dopants. + The polysilicon portion 62 is p-type on the entire inner wall of the trench 63. + The trench 63 is in contact with the SiC portion 61. + From the top surface of the mold SiC portion 61 + It is formed to a depth that does not penetrate through mold SiC portion 61 .

[0101] p + Since the p-type polysilicon portion 62 is made of polysilicon like the p-type polysilicon portion 52, the carrier concentration is almost independent of the temperature of the semiconductor substrate. + There are abundant majority carriers in the polysilicon portion 62. + When the MOSFET (semiconductor device 60) is turned off, the type polysilicon portion 62+ Type region 21 and n - Type drift region 2 and pn junction to p + The depletion layer extending into the p-type region 21 + The p-type region 21 is prevented from being completely depleted, and functions as a stopper that prevents the depletion layer from reaching the gate insulating film 6. + Type SiC section 61 and p + As a p-type dopant for forming the p-type polysilicon portion 62, for example, Al or B can be used.

[0102] p + The dose of the p-type dopant introduced into the p-type polysilicon portion 62 is p + The dose of the p-type dopant introduced into the p-type SiC portion 61 is approximately the same as that of the p-type dopant introduced into the p-type SiC portion 62. + The activation of the p-type dopant in the p-type polysilicon portion 62 can be performed simultaneously with the activation of the dopant in the SiC layers 42 and 43 by a general heat treatment such as laser annealing from the front surface of the semiconductor substrate 40 or furnace annealing. + The polysilicon portion 62 is formed on the gate insulating film 6 and the p + Mold connection part 22, n - It may be in contact with the drift region 2. + The width (width in the short side direction) of the mold polysilicon portion 62 may be, for example, equal to or greater than the width (width in the short side direction) of the gate trench 5.

[0103] The semiconductor device 60 according to the second embodiment may be provided with a contact trench similar to the contact trench 8 of the other example of the semiconductor device 10 according to the first embodiment shown in FIG.

[0104] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. + p in the type domain + The polysilicon part of the MOSFET provides p-type + Type domain and n - From the pn junction with the drift region +Since the depletion layer extending into the mold region can be made less likely to extend toward the gate trench, the effect of alleviating the electric field near the bottom of the gate trench can be improved.

[0105] (Details of the Third Embodiment) A semiconductor device according to a third embodiment that solves the above-mentioned problems will be described below. FIG. 5 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The layout of a semiconductor device 70 according to the third embodiment, as viewed from the front surface side of the semiconductor substrate 40, is the same as that of FIG. 1, except that reference numeral 10 is replaced with reference numeral 70. FIG. 5 shows the cross-sectional structure taken along the cutting line A-A' in FIG. 1. The semiconductor device 70 according to the third embodiment differs from the semiconductor device 10 according to the first embodiment (see FIG. 2) in that the portion in which the channel of the p-type base region 3 is formed is composed only of a p-type SiC portion 71.

[0106] In the third embodiment, of the p-type SiC portion 71 and the p-type polysilicon portion (hatched portion) 72 constituting the p-type base region 3, only the p-type SiC portion 71 is disposed adjacent to the gate trench 5 and contacts the gate insulating film 6 on the side wall of the gate trench 5. The p-type polysilicon portion 72 is formed by doping a p-type dopant into a trench 73 formed in the p-type SiC portion 71. + The trench 73 is formed by burying p-type polysilicon therein, or by ion-implanting p-type dopant into non-doped polysilicon buried in the trench 73 .

[0107] The p-type polysilicon portion 72 is disposed between the front surface of the semiconductor substrate 40 and the p-type SiC portion 71, and is spaced apart from the gate trench 5. The trench 73 is formed at a depth that does not penetrate the p-type SiC portion 71 (p-type SiC layer 43) from the front surface of the semiconductor substrate 40 in the depth direction, and is spaced apart from the gate trench 5. + The portion excluding the p-type source region 4, the region where the p-type polysilicon portion 72 is formed (the portion removed by the formation of the trench 73), and the portion removed by the formation of the gate trench 5 is the p-type SiC portion 71.

[0108] The p-type base region 3, n+ Type source region 4 (n + Type SiC part 74) and n - Only the p-type SiC portion 71 is arranged in a portion where a channel is formed between the p-type drift region 2. The configurations other than the arrangement of the p-type SiC portion 71 and the p-type polysilicon portion 72 are the same as the p-type SiC portion 51 and the p-type polysilicon portion 52 in the first embodiment. A space W1 between the p-type polysilicon portion 72 and the gate trench 5 is equal to or larger than the thickness of the channel in a direction perpendicular to the sidewall of the gate trench 5, and is preferably as narrow as possible.

[0109] When the temperature of the semiconductor substrate 40 is low, the carrier concentration of the p-type SiC portion 71 becomes lower than the carrier concentration of the p-type polysilicon portion 72. - The depletion layer that spreads from the pn junction with the drift region 2 into the p-type base region 3 spreads more easily in the p-type SiC portion 71 than in the p-type polysilicon portion 72, and extends between the p-type polysilicon portion 72 and the gate trench 5 in a curved, elongated protruding state along the bottom corner (the boundary between the bottom surface and the side surface) of the p-type polysilicon portion 72.

[0110] Between the p-type polysilicon portion 72 and the gate trench 5, + Type source region 4(n + The depletion layer extending toward the p-type SiC portion 74 is expanded laterally (in the short direction of the gate trench 5) into the p-type polysilicon portion 72 to form an n + It is preferable to make the interval W1 between the p-type polysilicon portion 72 and the gate trench 5 as narrow as possible so as not to allow the p-type polysilicon portion 72 to reach the source region 4. Specifically, it is preferable that the interval W1 between the p-type polysilicon portion 72 and the gate trench 5 is, for example, about 0.2 μm or less.

[0111] n + The source region 4 is an n + Type SiC section (n-type silicon carbide section) 74 and n + The insulating layer 75 may be made of a mold polysilicon portion 75. +The p-type SiC portion 74 is a diffusion region formed by ion implantation in the surface region of the p-type SiC layer 43. + The p-type SiC portion 74 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type SiC portion 71 in contact with the p-type SiC portion 71. + The type SiC portion 74 is adjacent to the gate trench 5 and contacts the gate insulating film 6 on the side wall of the gate trench 5. + The type SiC portion 74 may or may not be in contact with the ohmic electrode 17 .

[0112] n + The p-type polysilicon portion 75 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type polysilicon portion 72 in contact with the p-type polysilicon portion 72. + The polysilicon portion 75 is + On the opposite side of the gate trench 5 with respect to the type SiC portion 74, + It is provided adjacent to the mold SiC portion 74. + The mold polysilicon portion 75 contacts the ohmic electrode 17 on the front surface of the semiconductor substrate 40. + The depth of the polysilicon portion 75 is, for example, n + It is approximately the same as the depth of the mold SiC portion 74 .

[0113] n + The p-type polysilicon portion 75 is formed by converting a part of the p-type polysilicon portion 72 back to n-type by ion implantation of an n-type dopant. + The dose of the n-type dopant introduced into the n-type polysilicon portion 75 is n + The dose of the n-type dopant introduced into the n-type SiC portion 74 is approximately the same as that of the n-type dopant introduced into the n-type SiC portion 74. + The activation of the n-type dopant in the n-type polysilicon portion 75 can be performed simultaneously with the activation of the dopants in the SiC layers 42 and 43 by laser annealing from the front surface of the semiconductor substrate 40 or a general heat treatment such as furnace annealing.

[0114] n + The polysilicon portion 75 is, for example, n + It is formed at the same time as the mold SiC portion 74. +The source region 4 is partially + The configuration other than the mold polysilicon portion 75 is the same as that of the first embodiment. + The p-type polysilicon portion 75 is hatched differently from the p-type polysilicon portion 72 .

[0115] The semiconductor device 70 according to the third embodiment may be provided with a contact trench similar to the contact trench 8 of the other example of the semiconductor device 10 according to the first embodiment shown in FIG. + The p-type polysilicon portion 75 and the p-type polysilicon portion 72 are exposed. + The mold region 21 is formed by p + Type SiC section 61 and p + The polysilicon portion 62 is formed of p + It may be composed of only the mold SiC portion.

[0116] As described above, according to the third embodiment, the p-type polysilicon portion of the p-type base region can be disposed away from the gate trench, or the n + A part of the type source area is n + Even in the case where a mold polysilicon portion is used, the same effects as those in the first and second embodiments can be obtained.

[0117] (Details of the fourth embodiment) A semiconductor device according to a fourth embodiment that solves the above-mentioned problems will be described below. FIG. 6 is a cross-sectional view showing the structure of a semiconductor device according to the fourth embodiment. The layout of a semiconductor device 80 according to the fourth embodiment, as viewed from the front surface side of a semiconductor substrate 81, is the same as that of FIG. 1, with the reference numerals 10 and 40 replaced with the reference numerals 80 and 81, respectively. FIG. 6 shows the cross-sectional structure taken along the cutting line A-A' in FIG. 1. The semiconductor device 80 according to the fourth embodiment differs from the semiconductor device 10 according to the first embodiment (see FIG. 2) in that the p-type base region 3 and the n-type base region 4 are formed in a substantially rectangular shape. + The point is that the type source region 4 is made only of polysilicon (hatched portion).

[0118] In the fourth embodiment, the semiconductor substrate 81 is obtained by replacing the p-type SiC layer 43 of the semiconductor substrate 40 in the first embodiment with a p-type polysilicon layer 82 which becomes the p-type base region 3. The p-type polysilicon layer 82 is an n - The n-type SiC layer 42 may be formed by depositing a p-type polysilicon layer doped with a p-type dopant on the n-type SiC layer 42. - The p-type polysilicon layer 82 may be formed by ion-implanting a p-type dopant into a non-doped polysilicon layer deposited on the p-type SiC layer 42. + The portion (p-type polysilicon portion) 83 excluding the p-type polysilicon portion 84 becomes the p-type base region 3 .

[0119] n + The polysilicon portion 84 is + This is the n type source region 4. + The p-type polysilicon portion 84 is formed by converting a part of the p-type polysilicon layer 82 to n-type by ion implantation of an n-type dopant. + The source region 4 is all n + The configuration is the same as that of the first embodiment except that the p-type polysilicon portion 84 is used. + The activation of the dopants in the mold polysilicon portion 84 can be performed simultaneously with the activation of the dopants in the SiC layer 42 by laser annealing from the front surface of the semiconductor substrate 81 or a general heat treatment such as furnace annealing.

[0120] A contact trench may be provided in the semiconductor device 80 according to the fourth embodiment, similar to the contact trench 8 in the semiconductor device 10 according to the first embodiment shown in FIG. 3. In this case, the contact trench is formed to a depth that does not penetrate the p-type polysilicon layer 82 from the front surface of the semiconductor substrate 81, and the inner wall of the contact trench is provided with n-type polysilicon. + In this case, the p-type polysilicon portion 84 and the p-type polysilicon portion 83 are exposed. + The mold region 21 is formed by p + Type SiC section 61 and p + The polysilicon portion 62 is formed of p+ It may be composed of only the mold SiC portion.

[0121] The effect based on the material properties of SiC is reduced, but p + Type region 21 is p + Alternatively, the p-type polysilicon portion 62 may be formed only in the p-type region provided outside the effective region of the active region 31 (the ineffective region of the active region 31 and the p-type peripheral region of the boundary region 32, and the p-type polysilicon portion 63 forming the breakdown voltage structure in the edge termination region 33). - type region, p + The p-type channel stopper region may be made of only a p-type polysilicon portion. + The p-type region provided outside the effective region of the mold region 21 and the active region 31 may be composed of only a p-type polysilicon portion.

[0122] As described above, according to the fourth embodiment, the p-type base region and the n + Even if the type source region is made of only polysilicon, the effect based on the material properties of SiC is reduced, but the switching tolerance of the MOSFET when the temperature of the semiconductor substrate is low can be obtained in the same manner as in the first to third embodiments.

[0123] The present disclosure is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, in the above-mentioned embodiments, instead of the trench gate structure having a gate electrode extending in the depth direction from the front surface of the semiconductor substrate, a planar gate structure having a flat gate electrode extending along the front surface of the semiconductor substrate may be used. In addition, the present disclosure is not limited to MOSFETs, and can be applied to vertical semiconductor devices having pn junctions such as IGBTs (Insulated Gate Bipolar Transistors), BJTs (Bipolar Junction Transistors), and pin (p-intrinsic-n) diodes. [Industrial Applicability]

[0124] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present disclosure is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0125] 1,101 n + Type drain region 2,102 n - Type Drift Region 3,103 p-type base region 4,104 n + Type Source Area 5,105 Gate trench 6,106 Gate insulating film 7,107 Gate electrode 8 Contact Trench 9,109 Interlayer insulating film 10,60,70,80,110 Semiconductor device 11,113 Source electrode 12 Gate Pad 13 Gate Runner 14 Gate resistor 15 Gate Ring 16 Source Ring 17,111 Ohmic electrodes 18,112 Barrier metal 19,114 Drain electrode 21,108 p for electric field relaxation + type area 22 pages + mold connection part 31 Active area 32 Boundary area 33 Edge Termination Area 40,81,120 Semiconductor substrate 41,121 n + Starting substrate 42,122 n - type SiC layer 43,123 p-type SiC layer 51,71 p-type SiC part 52,72,83 p-type polysilicon section 53, 53a, 53b, 63, 73 Trench 61 pages + Type SiC part 62 pages + Polysilicon mold part 74 n + Type SiC part 75,84 n + Polysilicon mold part 82 p-type polysilicon layer d0,d100 p-type base region and n - Depth position of pn junction with the type drift region When the dnx MOSFET is off, the p-type base region and n - The depth position of the end of the depletion layer that spreads vertically from the pn junction with the p-type drift region into the p-type base region 3 When the dpx MOSFET is off, the p-type base region and n - The n-type drift region is vertically aligned from the pn junction. - Depth position of the edge of the depletion layer extending into the type drift region W1: Distance between the p-type polysilicon portion constituting the p-type base region and the gate trench

Claims

1. a semiconductor substrate made of silicon carbide; an n-type region provided within the semiconductor substrate; a p-type region provided inside the semiconductor substrate between the first main surface of the semiconductor substrate and the n-type region and in contact with the n-type region; a first electrode electrically connected to the p-type region; a second electrode electrically connected to the n-type region; Equipped with A semiconductor device, wherein at least a portion of the p-type region is a p-type polysilicon portion.

2. 2. The semiconductor device according to claim 1, wherein the remaining portion of said p-type region excluding said p-type polysilicon portion is a p-type silicon carbide portion.

3. 2. The semiconductor device according to claim 1, wherein the entire p-type region is the p-type polysilicon portion.

4. an n-type partial region selectively provided inside the semiconductor substrate between the first main surface of the semiconductor substrate and the p-type region; 2. The semiconductor device according to claim 1, wherein the entire n-type partial region is an n-type silicon carbide portion.

5. an n-type partial region selectively provided inside the semiconductor substrate between the first main surface of the semiconductor substrate and the p-type region; a part of the n-type partial region is an n-type polysilicon portion, a remaining portion of the n-type partial region excluding the n-type polysilicon portion is an n-type silicon carbide portion, the n-type polysilicon portion is selectively provided inside the p-type polysilicon portion, 3 . The semiconductor device according to claim 2 , wherein the n-type silicon carbide portion is selectively provided inside the p-type silicon carbide portion.

6. an n-type partial region selectively provided inside the semiconductor substrate between the first main surface of the semiconductor substrate and the p-type region; 4. The semiconductor device according to claim 3, wherein the entire n-type partial region is an n-type polysilicon portion.

7. an active region of the semiconductor substrate; a predetermined element structure provided in the active region, the element structure including a pn junction between the p-type region and the n-type region; a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the element structure; the second electrode provided on a second main surface of the semiconductor substrate; 2. The semiconductor device according to claim 1, further comprising:

8. a termination region surrounding the active region and having a predetermined breakdown voltage structure disposed therein; A plurality of the p-type regions are provided within the semiconductor substrate; a first p-type region among the plurality of p-type regions is provided in the active region to configure the element structure; 8. The semiconductor device according to claim 7, wherein a second p-type region of the plurality of p-type regions is provided in the termination region to constitute the breakdown voltage structure.

9. a boundary region between the active region and the termination region; a wiring layer provided on the first main surface of the semiconductor substrate in the boundary region via an insulating layer; Equipped with 9. The semiconductor device according to claim 8, wherein a third p-type region among the plurality of p-type regions is electrically connected to the first electrode, is provided in the boundary region, and faces the wiring layer in the depth direction via the insulating layer.

10. 2. The semiconductor device according to claim 1, wherein aluminum or boron is introduced into said p-type polysilicon portion as a p-type dopant.

11. 7. The semiconductor device according to claim 5, wherein the n-type polysilicon portion is doped with phosphorus, arsenic or nitrogen as an n-type dopant.

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