Printed wiring board, printed circuit board, electronic apparatus, and image forming device

Abstract

To provide a printed wiring board with which a memory interface can be accelerated, and a printed circuit board.SOLUTION: A printed wiring board can mount a memory controller having a plurality of first signal terminals and a memory device having a plurality of second signal terminals. The printed wiring board has a plurality of first wires, a plurality of second wires and a plurality of vias for electrically connecting the plurality of first signal terminals and the plurality of second signal terminals. The plurality of first wires and the plurality of second wires are connected through the plurality of vias provided at intersections of the plurality of first wires and the plurality of second wires in a planar view observed in a direction vertical to a principal surface of the printed wiring board. In the planar view, an angle θ formed by the plurality of first wires and the plurality of second wires is larger than 90° and smaller than 180°, and an angle φ formed by a first straight line passing through a center between mutually adjacent vias and a second straight line passing through the first wires is arctan (sinθ).SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a printed wiring board, a printed circuit board, an electronic device, and an image forming apparatus. [Background technology]

[0002] A memory system, which is an example of a printed circuit board, includes a memory controller having a plurality of transmitting terminals, a memory device having a plurality of receiving terminals, and a printed wiring board on which these are mounted. The transmitting terminals of the memory controller and the receiving terminals of the memory device are electrically connected by bus wiring on the printed wiring board. The memory controller controls the memory device by transmitting command signals and address signals to the memory device via the bus wiring. In addition, the memory controller and the memory device have data terminals for transmitting and receiving data signals, and the data terminals of the memory controller and the data terminals of the memory device are electrically connected by data signal lines on the printed wiring board.

[0003] High-performance electronic devices need to process large amounts of data at high speed. The electronic device described in Patent Document 1 is equipped with two memory devices, which makes it possible to process large amounts of data. The two memory devices described in Patent Document 1 are electrically connected to a memory controller by a bus wiring composed of fly-by wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-16867 A Summary of the Invention [Problem to be solved by the invention]

[0005] To process large volumes of data quickly, the communication speed of memory interfaces is increasing. Memory interfaces operate in synchronization with a clock signal. When the frequency of the clock signal increases due to the increase in speed, the period of the clock signal becomes shorter. An address signal operates in synchronization with this clock signal. Therefore, in order to achieve a higher communication speed in memory interfaces, it is necessary to reduce the variation in the time it takes for an address signal to be received by a memory device.

[0006] For high-frequency signals with transfer speeds exceeding 1 Gbps, the longer the wiring, the greater the loss of the electrical signal. This loss causes a drop in amplitude voltage and increases the rise and fall times of the signal waveform, which in turn reduces the voltage noise margin and timing margin, hindering faster speeds. Therefore, in order to achieve higher speeds, it is necessary to shorten the wiring in order to reduce the loss of electrical signals due to the wiring.

[0007] However, in a conventional printed wiring board, the first wiring drawn from the memory controller and the second wiring drawn to the memory device are arranged so that they are perpendicular to each other. Furthermore, vias are arranged at the intersections of the first wiring and the second wiring, and the first wiring and the second wiring are connected through the vias. In such a bus wiring structure, the variation in the length of the wiring can be reduced, but the wiring becomes long.

[0008] For example, a wiring structure in which the spacing between the second wirings is narrowed to shorten the wiring can be considered. With this structure, the wiring can be shortened, but the variation in wiring length, i.e., the variation in time, increases, hindering speed increases. Also, if an attempt is made to shorten the length by setting the angle between the first wiring and the second wiring to 45 degrees, the via and the wiring will interfere with each other, so the wiring must be detoured, and the variation in wiring length increases, hindering speed increases. In this way, there is a trade-off between the variation in wiring length and the wiring length.

[0009] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a printed wiring board and a printed circuit board that can realize a high speed memory interface. [Means for solving the problem]

[0010] According to one aspect of the present invention, there is provided a printed wiring board on which a memory controller having a plurality of first signal terminals and a memory device having a plurality of second signal terminals can be mounted, the printed wiring board having a plurality of first wirings, a plurality of second wirings, and a plurality of vias, the plurality of first wirings, the plurality of second wirings, and the plurality of vias are provided to electrically connect the plurality of first signal terminals and the plurality of second signal terminals, and the plurality of first wirings and the plurality of second wirings are arranged such that the plurality of first wirings and the plurality of second wirings are arranged in a plan view perpendicular to a main surface of the printed wiring board. a plurality of vias provided at intersections of the plurality of first wirings and a plurality of second wirings, an angle θ between the plurality of first wirings and the plurality of second wirings in the planar view, the angle θ on a side closer to the memory controller and the memory device being greater than 90° and smaller than 180°, and an angle φ between a first line passing through centers of the adjacent vias and a second line passing through the first wirings in the planar view, the angle φ on the same side as the angle θ with respect to the second line being arctan(sin θ).

[0011] According to another aspect of the present invention, there is provided a memory controller having a plurality of first signal terminals, a memory device having a plurality of second signal terminals, and a printed wiring board on which the memory controller and the memory device are mounted, the printed wiring board having a plurality of first wirings, a plurality of second wirings, and a plurality of vias, the plurality of first wirings, the plurality of second wirings, and the plurality of vias electrically connect the plurality of first signal terminals and the plurality of second signal terminals, and the plurality of first wirings and the plurality of second wirings are arranged in a front view in a plan view perpendicular to a main surface of the printed wiring board. The printed circuit board is provided with a plurality of first wirings and a plurality of second wirings connected through the plurality of vias arranged at the intersections of the plurality of first wirings and the plurality of second wirings, and in the planar view, an angle θ formed between the plurality of first wirings and the plurality of second wirings, the angle θ on the side closer to the memory controller and the memory device being greater than 90° and less than 180°, and an angle φ formed between a first line passing through the centers of the adjacent vias and a second line passing through the first wirings, the angle φ on the same side of the second line as the angle θ is arctan(sin θ). Effect of the Invention

[0012] According to the present invention, it is possible to realize a high-speed memory interface. [Brief description of the drawings]

[0013] [Figure 1] 1 is a perspective view illustrating an image forming apparatus as an example of an electronic device according to an embodiment. [Diagram 2] FIG. 2 is a plan view of a control module according to one embodiment. [Diagram 3] FIG. 2 is a cross-sectional view of a control module according to one embodiment. [Figure 4] FIG. 1 is a plan view illustrating a memory device according to an embodiment. [Diagram 5] FIG. 2 is a plan view showing command / address signal lines according to an embodiment. [Figure 6]1 is a plan view showing an area R1 including command / address signal lines according to an embodiment and its surroundings. FIG. [Figure 7] FIG. 2 is a plan view showing command / address signal lines according to the first embodiment. [Figure 8] FIG. 2 is a plan view showing the layout positions of ground vias in the first embodiment. [Figure 9] FIG. 11 is a plan view showing command / address signal lines according to a second embodiment. [Figure 10] FIG. 11 is a plan view showing command / address signal lines of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] [One embodiment] A printed wiring board and an electronic device according to an embodiment of the present invention will be described with reference to Figures 1 to 6. In this embodiment, an image forming apparatus will be described as an example of the electronic device.

[0015] 1 is a perspective view showing an image forming apparatus as an example of an electronic device according to the present embodiment. The image forming apparatus 100 is, but is not limited to, a digital device such as an X-ray flat panel detector.

[0016] 1, the image forming apparatus 100 includes an apparatus main body 101, a control module 200 that controls the apparatus main body 101, and a housing 102. The control module 200 is provided on the rear surface of the apparatus main body 101, and is disposed inside the housing 102 together with the apparatus main body 101. The apparatus main body 101 is a main body section that outputs image data corresponding to electromagnetic waves such as X-rays that are incident on the apparatus main body 101, and includes a scintillator, a photodiode, a thin film transistor array, an analog-to-digital converter, a low-noise amplifier, etc., which are not shown.

[0017] The control module 200 is an electronic module in the form of a printed circuit board. The control module 200 is connected to the device body 101 so as to be able to control the device body 101. The control module 200 also receives image data output by the device body 101. The control module 200 executes image processing on the input image data. Furthermore, the control module 200 transmits the image data to an external device via an interface such as a LAN (Local Area Network) or a USB (Universal Serial Bus).

[0018] FIG. 2 is an explanatory diagram of the control module 200 according to the present embodiment. As shown in FIG. 2, the control module 200 has a memory device 611 which is an example of a first element, a memory device 612 which is an example of a second element, and a memory controller 610 which is an example of a third element. The control module 200 also has a connector 301, a connector 302, a connector 303, a conversion chip 201, a resistor 613, and a printed wiring board 500. The memory device 611, the memory device 612, the memory controller 610, the connector 301, the connector 302, the connector 303, the conversion chip 201, and the resistor 613 are mounted on the printed wiring board 500. The printed wiring board 500 is, for example, a rigid board. The printed wiring board 500 has wirings 401 and 402, wirings 403 and 404, a command / address signal line 710, and data signal lines 711 and 712.

[0019] The memory device 611 and the memory device 612 are the same type of memory device. The memory devices 611 and 612 are, for example, DDR (Double Data Rate) 4 memories. Note that the memory devices 611 and 612 are not limited to DDR4 memories, and may be memories of other standards or other types.

[0020] The connectors 302 and 303 are connected to the device main body 101 via cables (not shown). Image data is input from the device main body 101 to the connectors 302 and 303 via those cables. The connectors 302 and 303 are also electrically connected to the memory controller 610 via wirings 401 and 402 of the printed wiring board 500. The image data input to the connectors 302 and 303 is transmitted to the memory controller 610 via the wirings 401 and 402, respectively.

[0021] The memory controller 610 stores image data in the memory devices 611 and 612 and reads out image data stored in the memory devices 611 and 612. The memory controller 610 is also electrically connected to the conversion chip 201 via the wiring 403 of the printed wiring board 500. The memory controller 610 transmits processed image data to the conversion chip 201 via the wiring 403.

[0022] The conversion chip 201 is electrically connected to the connector 301 via the wiring 404 of the printed wiring board 500. A cable 304 is connected to the connector 301. The conversion chip 201 converts the image data transmitted from the memory controller 610 into a format defined by a communication standard. Furthermore, the conversion chip 201 outputs the converted image data to the cable 304 via the wiring 404 and the connector 301. The cable 304 is connected to, for example, a computer for displaying images. The image data is input to the computer via the cable 304, and is subjected to processing such as display processing on a display and storage processing in a storage device in the computer.

[0023] The memory controller 610 and the memory devices 611, 612 are each configured as a single semiconductor package. The memory devices 611, 612 and the memory controller 610 are each electrically connected via data signal lines 711, 712 of the printed wiring board 500, which serve as transmission paths for data signals indicating image data. The data signal lines 711, 712 are each bus wirings consisting of a plurality of wirings.

[0024] Furthermore, the memory controller 610 and the memory devices 611 and 612 are electrically connected by a command / address signal line 710 of the printed wiring board 500, which serves as a transmission path for a command signal and an address signal. The command / address signal line 710 is a bus wiring consisting of a plurality of signal lines. The memory controller 610 transmits a command signal and an address signal to the two memory devices 611 and 612 by a parallel transmission method via the command / address signal line 710. The command signal and the address signal, which are parallel signals transmitted from the memory controller 610, are both received by the two memory devices 611 and 612 via the command / address signal line 710. The memory controller 610 controls the memory devices 611 and 612 by transmitting the command signal and the address signal to the memory devices 611 and 612 via the command / address signal line 710. Each of the memory devices 611 and 612 performs processes such as storing and erasing image data according to the command signal and the address signal.

[0025] As described above, a memory system is configured by the memory controller 610, the memory devices 611 and 612, and the printed wiring board 500. The memory system is configured as a printed circuit board.

[0026] FIG. 3 is a cross-sectional view showing the control module 200 according to this embodiment. The printed wiring board 500 has an insulating base material and a conductive conductor constituting wiring. The wiring is provided on the base material. The material of the base material is, for example, glass epoxy resin. The material of the conductor is, for example, copper. The printed wiring board 500 can mount a memory controller 610 and memory devices 611 and 612, and the memory controller 610 and the memory devices 611 and 612 are mounted on it. Note that the printed wiring board 500 can mount components other than the memory controller 610 and the memory devices 611 and 612, and other components may be mounted on it.

[0027] The printed wiring board 500 is a laminated board having a plurality of, for example, six conductor layers 501, 502, 503, 504, 505, and 506. The conductor layers 501 to 506 are arranged at intervals from each other in the Z direction, which is a direction perpendicular to the main surface of the printed wiring board 500 and is also the lamination direction. In addition, a base material, that is, an insulating layer, is provided between the conductor layers 501 to 506. The conductor layers 501 to 506 are arranged in the order of conductor layer 501, conductor layer 502, conductor layer 503, conductor layer 504, conductor layer 505, and conductor layer 506 from one side to the other in the Z direction. The conductor layers 501 and 506 are surface layers that are main surfaces, that is, mounting surfaces on which the memory controller 610, memory devices 611 and 612, etc. can be mounted. The conductor layers 502 to 505 between the conductor layer 501 and the conductor layer 506 are inner layers. In addition, a protective film such as a solder resist (not shown) may be disposed on the conductor layers 501 and 506 .

[0028] A conductor pattern 570, which is a conductor film constituting wiring, is formed on each of the conductor layers 501 to 506. Via conductors 560, 561, and 562 constituting wiring are arranged across the conductor layers 501 to 506. The via conductors 560, 561, and 562 are conductors formed in vias of a substrate. In this embodiment, the vias are through holes (penetrating vias), and the via conductors 560, 561, and 562 are provided in the through holes.

[0029] Note that FIG. 3 does not accurately depict the data signal lines 711, 712 and the command / address signal line 710 shown in FIG. 2, but merely illustrates a schematic cross section of printed wiring board 500 to explain conductor layers 501-506.

[0030] The memory controller 610 and the memory devices 611, 612 are both mounted on one conductor layer 501 of a pair of conductor layers 501, 506 which are surface layers. Components such as capacitors and resistors (not shown) are mounted on the conductor layers 501, 506. Conductor patterns that mainly serve as grounds are formed on the conductor layers 502, 505 adjacent to the conductor layers 501, 506 via insulating layers, respectively. The conductor layer 501 is the third conductor layer. The conductor layer 503 is the first conductor layer. The conductor layer 504 is the second conductor layer. The conductor layer 503 is relatively closer to the conductor layer 501 than the conductor layer 504. Conductor patterns that mainly serve as part of wiring such as data signal lines 711, 712 and command / address signal lines 710 are formed on the conductor layers 503, 504.

[0031] The memory controller 610 and the memory devices 611, 612 are joined to the printed wiring board 500 by soldering. The memory controller 610 and the memory devices 611, 612 each have a plurality of signal terminals, a plurality of power supply terminals, and a plurality of ground terminals. Of the plurality of signal terminals, for example, 16 are data terminals. The terminals of the memory controller 610 and the memory devices 611, 612 have a structure of, for example, a BGA (Ball Grid Array).

[0032] The arrangement of terminals in the memory devices 611 and 612 is shown in Fig. 4. Fig. 4 is a plan view showing the memory devices 611 and 612. Fig. 4 shows the memory devices 611 and 612 as viewed from the side opposite to the side on which the terminals are arranged. In Fig. 4, each terminal is indicated by a dashed line, which is a hidden line.

[0033] The memory devices 611 and 612 are DDR4-SDRAMs. As shown in Fig. 4, the terminals are provided in the first to third columns and the seventh to ninth columns of the 16 rows x 9 columns. There are no terminals in the fourth to sixth columns. The total number of terminals is 96.

[0034] In Fig. 4, among the multiple terminals, the terminals indicated by diagonal lines are command / address terminals A0 to A16, BA0, BA1, BG0, and ACT. The command / address terminals A0 to A16, BA0, BA1, BG0, and ACT are arranged in the 11th to 16th rows and the 2nd to 8th columns. The terminals indicated by a mesh are data terminals DQU0 to DQU7, data mask terminal DMU_n, data strobe terminals DQSU_c, DQSU_t, data terminals DQL0 to DQL7, data mask terminal DML_n, and data strobe terminals DQSL_c, DQSL_t. These data terminals, data mask terminals, and data strobe terminals are arranged in the 1st to 9th rows and the 2nd to 8th columns.

[0035] In general, the memory devices 611, 612 are arranged such that the data terminals of the memory devices 611, 612 face the memory controller 610. The data terminals of the memory devices 611, 612 and the data terminal of the memory controller 610 are electrically connected to each other via data signal lines 711, 712.

[0036] The command / address terminals of the memory devices 611 and 612 are disposed on the side farther from the memory controller 610. The command / address signal line 710 is a fly-by wiring structure composed of a plurality of wires functioning as a plurality of signal lines. The command / address terminals of the memory devices 611 and 612 and the command / address terminal of the memory controller 610 are electrically connected to each other by the command / address signal line 710. One end of the command / address signal line 710 is connected to a resistor 613. The resistor 613 is a termination element, and is a chip resistor that is pulled up and connected to a termination voltage. As shown in FIG. 2, the command / address signal line 710 is connected to the memory devices 611 and 612 by an L-shaped wire.

[0037] The memory interface operates in synchronization with a clock signal. When the frequency of the clock signal increases due to speedup, the period of the clock signal becomes shorter. In order to achieve high-speed memory interfaces, it is necessary to reduce the variation in the time it takes for the command / address signal output from the memory controller 610 to reach the memory devices 611 and 612. For example, the period of the address signal of a DDR3-800 memory interface is 2500 picoseconds. If the allowable value of the variation in the arrival time is 10% of the period, the allowable value is 250 picoseconds in time. If the wiring delay time in a 1 mm wiring is 7 picoseconds, a variation of about 35.7 mm of the command / address signal line is allowed. With the progress of speedup, the period of the address signal of a DDR4-3200 memory interface is 625 picoseconds. If the allowable value of the variation in the arrival time is 10% of the period, the allowable value is 62.5 picoseconds in time. In this case, the allowable variation of the command / address signal line is about 8.9 mm.

[0038] In order to realize a faster memory interface, it is required to suppress the variation in length of the multiple wirings constituting the command / address signal lines. In the arrangement of the command / address terminals of the memory devices 611 and 612 shown in FIG. 4, the terminal interval is, for example, 0.8 mm. In this case, for example, a variation in length of 4.8 mm occurs between the command / address terminal A5 in the 14th row and 8th column and the command / address terminal A6 in the 14th row and 2nd column. Therefore, when the terminal interval is narrower in this way, the tolerance of the variation in length of the command / address signal line 710 connecting between the memory controller 610 and the memory device 612 becomes smaller.

[0039] Meander wiring is a method for aligning the lengths of command / address signal lines. Meander wiring is a wiring structure that adjusts the length of the wiring by making the wiring longer through a meandering structure. When trying to align the lengths of the wiring using meander wiring, the length of the command / address signal bus wiring is adjusted to match the longest signal line, so the wiring becomes longer. As memory interface speeds increase, the effect of frequency loss of electrical signals due to wiring cannot be ignored. Frequency loss causes a drop in amplitude voltage and a longer rise and fall time of the signal waveform, reducing voltage noise margins and timing margins. For this reason, longer wiring is a cause of hindering the speedup of memory interfaces. Therefore, in order to achieve faster memory interfaces, it is necessary to shorten the wiring to reduce loss due to wiring.

[0040] Therefore, in this embodiment, by improving the wiring structure of the command / address signal lines 710, the variation in length of the multiple wires constituting the command / address signal lines 710 shown in Fig. 2 in plan view in the Z direction is suppressed to a small extent, and the length of the wires is shortened. Hereinafter, the wiring structure of the command / address signal lines 710 in the control module 200 according to this embodiment will be specifically described.

[0041] 5 is a plan view showing a part of the memory controller 610 and a part of the memory device 611 when the control module 200 according to the present embodiment is viewed in a plane, that is, when viewed in the Z direction which is a direction perpendicular to the main surface of the printed wiring board 500. As shown in FIG. 5, the memory controller 610 is disposed on the printed wiring board 500 at a distance from the memory device 611 in the Y direction perpendicular to the X direction and the Z direction. Note that the X direction and the Y direction are directions parallel to the main surface of the printed wiring board 500. In the following, for the sake of simplicity, a case will be described in which the command / address signal line 710 has three signal lines as shown in FIG. 5.

[0042] The memory controller 610 has a plurality of command / address terminals 610_1, 610_3, 610_5 which are a plurality of control signal terminals. The command / address terminals 610_1, 610_3, 610_5 are arranged to be aligned at a predetermined interval in the X direction. The memory device 611 has a plurality of command / address terminals 611_1, 611_3, 611_5 which are a plurality of control signal terminals. The command / address terminals 611_1, 611_3, 611_5 are arranged to be aligned at a predetermined interval in the Y direction.

[0043] A command / address terminal 610_1 of the memory controller 610 is electrically connected to a command / address terminal 611_1 of the memory device 611 through a via 561_1, a wiring 710_1, a via 560_1, a wiring 710_2, and a via 562_1. The via 561_1 is a via formed by the via conductor 561, and electrically connects the command / address terminal 610_1 and the wiring 710_1. The via 560_1 is a via formed by the via conductor 560, and electrically connects the wiring 710_1 and the wiring 710_2. The via 562_1 is a via formed by the via conductor 562, and electrically connects the wiring 710_2 and the command / address terminal 611_1. The via 561_1, the wiring 710_1, the via 560_1, the wiring 710_2, and the via 562_1 configure wiring that functions as one of a plurality of signal lines in the command / address signal line 710.

[0044] The command / address terminal 610_3 of the memory controller 610 is electrically connected to the command / address terminal 611_3 of the memory device 611 through a via 561_3, a wiring 710_3, a via 560_3, a wiring 710_4, and a via 562_3. The via 561_3 is a via formed by the via conductor 561, and electrically connects the command / address terminal 610_3 and the wiring 710_3. The via 560_3 is a via formed by the via conductor 560, and electrically connects the wiring 710_3 and the wiring 710_4. The via 562_3 is a via formed by the via conductor 562, and electrically connects the wiring 710_4 and the command / address terminal 611_3. The via 561_3, the wiring 710_3, the via 560_3, the wiring 710_4, and the via 562_3 configure wiring that functions as one of a plurality of signal lines in the command / address signal line 710.

[0045] The command / address terminal 610_5 of the memory controller 610 is electrically connected to the command / address terminal 611_5 of the memory device 611 through a via 561_5, a wiring 710_5, a via 560_5, a wiring 710_6, and a via 562_5. The via 561_5 is a via formed by the via conductor 561, and electrically connects the command / address terminal 610_5 and the wiring 710_5. The via 560_5 is a via formed by the via conductor 560, and electrically connects the wiring 710_5 and the wiring 710_6. The via 562_5 is a via formed by the via conductor 562, and electrically connects the wiring 710_6 and the command / address terminal 611_5. The via 561_5, the wiring 710_5, the via 560_5, the wiring 710_6, and the via 562_5 configure wiring that functions as one of a plurality of signal lines in the command / address signal line 710.

[0046] Thus, the command / address terminals 610_1, 610_3, 610_5 and the command / address terminals 611_1, 611_3, 611_5 are electrically connected by a plurality of wirings and a plurality of vias provided for electrically connecting them. The wirings for electrical connection include a plurality of wirings 710_1, 710_3, 710_5 and a plurality of wirings 710_2, 710_4, 710_6. The vias for electrical connection include vias 560_1, 560_3, 560_5, vias 561_1, 561_3, 561_5, and vias 562_1, 562_3, 562_5. In a plan view of the printed wiring board 500 seen in the Z direction, the vias 560_1, 560_3, and 560_5 are provided at intersections of the plurality of wirings 710_1, 710_3, and 710_5 and the plurality of wirings 710_2, 710_4, and 710_6, respectively. Similarly, in a plan view seen in the Z direction, the plurality of wirings 710_1, 710_3, and 710_5 are disposed closer to the memory controller 610 than the plurality of wirings 710_2, 710_4, and 710_6 with respect to the vias 560_1, 560_3, and 560_5.

[0047] In this embodiment, the plurality of wirings 710_1, 710_3, 710_5 and the plurality of wirings 710_2, 710_4, 710_6 are address bus wirings, but the present invention is not limited to this. The plurality of wirings 710_1, 710_3, 710_5 and the plurality of wirings 710_2, 710_4, 710_6 may be data bus wirings.

[0048] The plurality of wirings 710_1, 710_3, 710_5 are formed in a conductor layer, for example, conductor layer 504, far from the surface layer of one side of printed wiring board 500 on which memory controller 610 and memory devices 610, 612 are mounted. The plurality of wirings 710_2, 710_4, 710_6 are formed in a conductor layer, for example, conductor layer 503, close to the surface layer of one side of printed wiring board 500 on which memory controller 610 and memory devices 610, 612 are mounted. Conductor layer 504 is located farther from the surface layer of one side of printed wiring board 500 on which memory controller 610 and memory devices 610, 612 are mounted than conductor layer 503 is.

[0049] Conductive layer 502 is a ground layer located between conductor layer 503 and the surface layer of one side of printed wiring board 500 on which memory controller 610 and memory devices 610, 612 are mounted. Conductive layer 505 is a ground layer located farther from the surface layer of one side of printed wiring board 500 on which memory controller 610 and memory devices 610, 612 are mounted than conductor layer 504.

[0050] The region R1 shown in Fig. 5 is a rectangular region with the center of the via 560_1 and the center of the via 560_3 as vertices located diagonally from each other. Here, the intersection angle of the wiring and the arrangement position of the via that suppresses the variation in length of the wiring constituting the command / address signal line 710 as the address bus wiring will be described with reference to Fig. 6. Fig. 6 shows the region R1 and its surroundings. In Fig. 6, symbols are added to explain the angles and lengths of the line segments.

[0051] The wiring 710_1 and the wiring 710_2 are connected through a via 560_1. The center of the via 560_1 is A. The wiring 710_3 and the wiring 710_4 are connected through a via 560_3. The center of the via 560_3 is C. The region R1 is a rectangle with the center A and the center C as vertices located diagonally to each other. The remaining vertices located diagonally to each other in the region R1 are B and D. In addition, in a plan view seen in the Z direction, a point where the wiring 710_2 and the wiring 710_3 intersect is P. In addition, in a plan view seen in the Z direction, an angle formed between the wiring 710_1 and the wiring 710_2 is θ (theta). The angle θ is the angle on the side closer to the memory controller 610 and the memory device 611. In addition, in a plan view seen in the Z direction, a line passing through the centers of adjacent vias 560_1 and 560_3, i.e., center A of via 560_1 and center C of via 560_3, is defined as a line 800. In addition, in a plan view seen in the Z direction, a line passing through wiring 710_1 and overlapping wiring 710_1 is defined as a line 801. In addition, in a plan view seen in the Z direction, an angle (∠BAC) made by lines 800 and 801 is defined as φ (phi). In a plan view seen in the Z direction, angle φ is an angle on the same side as angle θ with respect to line 801.

[0052] It is considered that the wirings outside the region R1 have the same length. That is, the line segment AA′ and the line segment DD′ have the same length, and the line segment CC′ and the line segment PP′ have the same length. Here, point A′ is a point on the memory controller 610 side of the center A (vertex A) on the wiring 710_1 in a plan view seen in the Z direction. Point D′ is a point on the memory controller 610 side of the vertex D on the wiring 710_3 in a plan view seen in the Z direction. Point A′ and point D′ are equal in position to each other in the Y direction. Point C′ is a point on the memory device 611 side of the center C (vertex C) on the wiring 710_4 in a plan view seen in the Z direction. Point P′ is a point on the memory device 611 side of point P on the wiring 710_4 in a plan view seen in the Z direction. In order for the length of wiring A'P' (line segment A'A + line segment AP + line segment PP') and the length of wiring D'C' (line segment D'D + line segment DP + line segment PC + line segment CC') to be equal, the lengths of line segments AP and DC must be equal. Here, the length of line segment CB is L, the length of line segment AP is M, and the length of line segment AB is N. The length M of line segment AP can be calculated using the following equation 1.

number

[0053] Since the length of the line segment AP and the length of the line segment DC are equal to each other, the length N of the line segment AB can be calculated using the following equation 2.

number

[0054] The position where the via 560_3 is placed is a position shifted by N=L / sinθ in the Y direction and by L in the X direction with respect to the via 560_1. In this case, if an angle (∠BAC) between a line 800 passing through a center A of the via 560_1 and a center C of the via 560_3 and the wiring 710_1 is φ, the angle φ satisfies the following relational expression.

number

[0055] When the above equation is solved for the angle φ, the angle φ can be obtained by the following equation 3.

number

[0056] As described above, when the wiring 710_1 and the wiring 710_2 intersect at an angle θ in a plan view of the printed wiring board 500 seen in the Z direction, the via 560_3 is arranged so that the angle φ between the straight line 800 and the wiring 710_1 is arctan(sinθ). The via 560_3 is arranged at a position where the straight line 800 and the wiring 710_3 intersect in the plan view. By connecting the wiring 710_3 to the wiring 710_4 through the via 560_3 arranged in this way, it is possible to suppress the variation in length of the multiple wirings constituting the command / address signal line 710 and realize a command / address bus wiring structure with a short wiring length. According to this embodiment, it is possible to realize a high-speed memory interface.

[0057] As described above, according to this embodiment, it is possible to suppress variation in the length of the command / address bus wiring and realize a command / address bus wiring structure with a short wiring length, thereby enabling a high-speed memory interface.

[0058] In the present embodiment, the image forming apparatus 100 has been described as an example of an electronic device, but the electronic device according to the present embodiment is not limited to the image forming apparatus 100. The electronic device may be any electronic device that uses a printed circuit board including a printed wiring board having a wiring structure similar to that of the printed wiring board 500.

[0059] [Example] A more specific configuration of the printed wiring board 500 according to this embodiment will be described using Example 1, Example 2, and a comparative example.

[0060] Example 1 7 is a plan view showing the command / address signal lines 710 of the first embodiment when viewed in the Z direction. The memory controller 610 has command / address terminals 610_1, 610_3, and 610_5. The memory device 611 has command / address terminals 611_1, 611_3, and 611_5.

[0061] A command / address terminal 610_1 of the memory controller 610 and a command / address terminal 611_1 of the memory device 611 are electrically connected by wiring on the printed wiring board 500. Specifically, the command / address terminal 610_1 and the via 561_1 are connected by wiring 501_1 formed on the conductor layer 501. The via 561_1 and the via 560_1 are connected by wiring 710_1 formed on the conductor layer 504. The conductor layer 505 is a ground layer. The via 560_1 and the via 562_1 are connected by wiring 710_2 formed on the conductor layer 503. The conductor layer 502 is a ground layer. The via 562_1 and the command / address terminal 611_1 of the memory device 611 are connected by wiring 501_2 formed on the conductor layer 501. The angle between the wiring 710_1 and the wiring 710_2 is θ (90°<θ<180°).

[0062] The command / address terminal 610_3 of the memory controller 610 and the command / address terminal 611_3 of the memory device 611 are electrically connected by wiring on the printed wiring board 500. Specifically, the command / address terminal 610_3 and the via 561_3 are connected by a wiring 501_3 formed on the conductor layer 501. The via 561_3 and the via 560_3 are connected by a wiring 710_3 formed on the conductor layer 504. The via 560_3 and the via 562_3 are connected by a wiring 710_4 formed on the conductor layer 503. The via 562_3 and the command / address terminal 611_3 of the memory device 611 are connected by a wiring 501_4 formed on the conductor layer 501. The angle between the wiring 710_3 and the wiring 710_4 is θ (90°<θ<180°). The angle formed by a straight line 800 passing through the center of the via 560_1 and the center of the via 560_3 and the wiring 710_1 is φ.

[0063] When the angle θ is 135°, the angle φ is calculated by equation 3 and is approximately 35°. If the distance between the wires 710_1 and 710_3 in the X direction is 1 mm, then the length M of the line segment AP shown in FIG. 6 is √2 mm. The position of the via 560_3 for making the length M of the line segment AP equal to the length N of the line segment AB is a position shifted by √2 mm in the Y direction and 1 mm in the X direction relative to the via 560_1. Therefore, tanφ=L÷M=1÷√2, and φ≈35°.

[0064] The command / address terminal 610_5 of the memory controller 610 and the command / address terminal 611_5 of the memory device 611 are electrically connected by wiring on the printed wiring board 500. Specifically, the command / address terminal 610_5 and the via 561_5 are connected by wiring 501_5 formed on the conductor layer 501. The via 561_5 and the via 560_5 are connected by wiring 710_5 formed on the conductor layer 504. The via 560_5 and the via 562_5 are connected by wiring 710_6 formed on the conductor layer 503. The via 562_5 and the command / address terminal 611_5 of the memory device 611 are connected by wiring 501_6 formed on the conductor layer 501. The angle between the wiring 710_5 and the wiring 710_6 is θ (90°<θ<180°).

[0065] Thus, in a plan view of printed wiring board 500 seen in the Z direction, the plurality of wirings 710_1, 710_3, and 710_5 and the plurality of wirings 710_2, 710_4, and 710_6 intersect at an angle θ greater than 90° and smaller than 180°. Note that angle θ is preferably 135° in order to shorten the wirings.

[0066] The wiring constituting the command / address signal line 710 is switched from wiring 710_1, 710_3, 710_5 of the conductor layer 504 to wiring 710_2, 710_4, 710_6 of the conductor layer 503 by vias 560_1, 560_3, 560_5. Accordingly, it is desirable that the ground serving as the return path of the command / address signal is switched from the conductor layer 505 to the conductor layer 502. In this case, the conductor layer 502 as the ground layer and the conductor layer 505 as the ground layer are connected by a ground via 563 formed in the printed wiring board 500.

[0067] Fig. 8 is a plan view showing the arrangement position of the ground via 563. As shown in Fig. 8, the ground via 563 connecting the conductor layer 502 and the conductor layer 505 may be arranged at a position equal to the vias 560_1 and 560_3 in the command / address signal line 710 in a plan view seen in the Z direction. Specifically, the ground via 563 may be arranged at a position on a perpendicular bisector 803 with respect to a line segment 802 connecting the center A of the via 560_1 and the center C of the via 560_3 adjacent to each other in a plan view seen in the Z direction.

[0068] (Comparative Example) FIG. 10 is a plan view showing a command / address signal line 710a of the comparative example when viewed in the Z direction. The components of the comparative example will be described by adding "a" to the end of the reference numerals of the corresponding components of the first embodiment or before "_". However, some of the components to which "a" has been added are not shown. The memory controller 610a has command / address terminals 610a_1, 610a_3, and 610a_5. The memory device 611a has command / address terminals 611a_1, 611a_3, and 611a_5.

[0069] The command / address terminal 610a_1 of the memory controller 610a and the command / address terminal 611a_1 of the memory device 611a are electrically connected by wiring on the printed wiring board 500a. Specifically, the command / address terminal 610a_1 and the via 561a_1 are connected by wiring 501a_1 formed on the conductor layer 501a. The via 561a_1 and the via 560a_1 are connected by wiring 710a_1 formed on the conductor layer 504a. The conductor layer 505a is a ground layer. The via 560a_1 and the via 562a_1 are connected by wiring 710a_2 formed on the conductor layer 503a. The conductor layer 502a is a ground layer. The via 562a_1 and the command / address terminal 611a_1 of the memory device 611a are connected by wiring 501a_2 formed on the conductor layer 501a. The angle between the wiring 710a_1 and the wiring 710a_2 is 90°. The angle between a straight line 800a passing through the center of the via 560a_1 and the center of the via 560a_3 and a straight line 801a passing through the wiring 710a_1 and overlapping the wiring 710a_1 is 45°.

[0070] The command / address terminal 610a_3 of the memory controller 610a and the command / address terminal 611a_3 of the memory device 611a are electrically connected by wiring on the printed wiring board 500a. Specifically, the command / address terminal 610a_3 and the via 561a_3 are connected by wiring 501a_3 formed on the conductor layer 501a. The via 561a_3 and the via 560a_3 are connected by wiring 710a_3 formed on the conductor layer 504a. The via 560a_3 and the via 562a_3 are connected by wiring 710a_4 formed on the conductor layer 503a. The via 562a_3 and the command / address terminal 611a_3 of the memory device 611a are connected by wiring 501a_4 formed on the conductor layer 501a. The angle between the wiring 710a_3 and the wiring 710a_4 is 90°.

[0071] The command / address terminal 610a_5 of the memory controller 610a and the command / address terminal 611a_5 of the memory device 611a are electrically connected by wiring on the printed wiring board 500a. Specifically, the command / address terminal 610a_5 and the via 561a_5 are connected by wiring 501a_5 formed on the conductor layer 501a. The via 561a_5 and the via 560a_5 are connected by wiring 710a_5 formed on the conductor layer 504a. The via 560a_5 and the via 562a_5 are connected by wiring 710a_6 formed on the conductor layer 503a. The via 562a_5 and the command / address terminal 611a_5 of the memory device 611a are connected by wiring 501a_6 formed on the conductor layer 501a. The angle between the wiring 710a_5 and the wiring 710a_6 is 90°.

[0072] Thus, in a plan view of printed wiring board 500a seen in the Z direction, the plurality of wirings 710a_1, 710a_3, and 710a_5 and the plurality of wirings 710a_2, 710a_4, and 710a_6 intersect at 90° each other.

[0073] Here, the wiring length of the first embodiment and the comparative example are compared using a specific example. If the wiring length of the wiring 710a_3 of the comparative example is 6 mm and the wiring length of the wiring 710a_4 is 2 mm, the wiring length of the wirings 710a_3 and 710a_4 in the comparative example is 8 mm. On the other hand, the wiring length of the wiring 710_3 of the first embodiment is 4 mm, and the wiring 710_4 is 2√2 mm ≈ 2.8 mm, and the wiring length of the wirings 710_3 and 710_4 in the first embodiment is 6.8 mm. Therefore, the wiring length of the first embodiment is shorter by 1.2 mm (15%) than that of the comparative example.

[0074] As described above, according to the first embodiment, it is possible to suppress variation in the length of the wiring that constitutes the command / address signal line 710, and also possible to shorten the wiring.

[0075] Example 2 In practice, a suitable range of the angle φ can be derived by taking into account the width of the wiring, the diameter (via diameter) of the via, and the minimum interval between the wiring and the via. FIG. 9 is a plan view showing a case where the width of the wiring 710_2 is W and the interval 560s_3 between the center of the wiring 710_2 and the via 560_3 is Sr in a plan view seen in the Z direction. When the interval between the centers of the wiring 710_2 and the via 560_3 is Sr, the angle formed by the line segment 802 connecting the center of the via 560_1 and the center of the via 560_3 and the center line 710c_2 of the wiring 710_2 is ψ (psi). If the minimum interval (gap) between the wiring 710_2 and the via 560_3 is Dmin and the via diameter of the via 560_3 is Dv, then Sr=(Dv / 2)+Dmin. It is.

[0076] The condition for minimizing the distance between the center of the wiring 710_2 and the center of the via 560_3 is θ+φ+ψ≦180°. Therefore, it is preferable that the angles θ, φ, and ψ satisfy θ+φ+ψ≦180°. The angle ψ is calculated by the following formula 4.

number

[0077] The practically suitable range of angle φ between a line 800 (a line segment 802 connecting the centers) passing through the centers of vias 560_1 and 560_3 and a line 801 passing through wiring 710_1 and overlapping wiring 710_1 can be estimated taking into account the actual wiring width, via diameter, and minimum spacing.

[0078] For example, the width W of the wiring 710_2 is 200 μm, and the via diameter Dv is 250 μm. If the minimum interval Dmin between the wiring 710_2 and the via 560_3 is 100 μm, the interval Sr from the center of the via 560_3 to the end of the wiring 710_2 is 225 μm ((250 μm / 2)+100 μm). When the angle θ between the wiring 710_1 and the wiring 710_2 is 135°, the practically suitable range of the angle φ is 20° or more and 50° or less, and more preferably 20° or more and 35° or less. A more suitable specific angle φ is 35°. When the angle φ is 20° or more, the variation in the length of the wiring can be suppressed to a smaller value, which is suitable for a memory interface. When the angle φ is 35° or less, the minimum interval Sr between the wiring 710_2 and the via 560_3 can be reliably met.

[0079] In this manner, in the embodiment, when the angle θ between the wiring 710_1 and the wiring 710_2 is greater than 0° and less than 180°, the arrangement position of the via that can suppress the variation in the length of the wiring and shorten the wiring length is clarified. Also, in the embodiment, the practically suitable range of the angle φ that determines the arrangement position of the via is clarified.

[0080] It should be noted that the present invention is not limited to the above-described embodiments, and many modifications are possible within the technical concept of the present invention. Furthermore, the effects described in the embodiments are merely a list of the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

[0081] The disclosure of this embodiment includes the following configuration. (Configuration 1) A printed wiring board on which a memory controller having a plurality of first signal terminals and a memory device having a plurality of second signal terminals can be mounted, a plurality of first wirings, a plurality of second wirings, and a plurality of vias, the plurality of first wirings, the plurality of second wirings, and the plurality of vias being provided to electrically connect the plurality of first signal terminals and the plurality of second signal terminals; the plurality of first wirings and the plurality of second wirings are connected to each other through the plurality of vias provided at intersections between the plurality of first wirings and the plurality of second wirings in a plan view seen in a direction perpendicular to a main surface of the printed wiring board; an angle θ between the plurality of first wirings and the plurality of second wirings in the plan view, the angle θ on a side closer to the memory controller and the memory device being greater than 90° and smaller than 180°; In the plan view, an angle φ is formed between a first line passing through the center of the adjacent vias and a second line passing through the first wiring, and the angle φ on the same side as the angle θ with respect to the second line is arctan(sinθ). A printed wiring board comprising: (Configuration 2) In the plan view, the first wiring is arranged closer to the memory controller than the second wiring with respect to the via. 2. The printed wiring board according to configuration 1. (Configuration 3) the angle θ, the angle φ, and the angle ψ between the second wiring and the first straight line in the plan view satisfy θ+φ+ψ≦180° 3. The printed wiring board according to configuration 1 or 2. (Configuration 4) The angle θ is 135°. 4. The printed wiring board according to claim 1, wherein the printed wiring board is a printed wiring board having a first insulating layer and a second insulating layer. (Configuration 5) The angle φ is equal to or greater than 20° and equal to or less than 50°. 5. The printed wiring board according to claim 1, wherein the printed wiring board is a printed wiring board having a first insulating layer and a second insulating layer. (Configuration 6) The angle φ is 35°. 6. The printed wiring board according to configuration 5. (Configuration 7) a surface on which the memory controller and the memory device can be mounted; A first inner layer; a second inner layer located farther from the surface layer than the first inner layer; The first wiring is formed in the second inner layer, and the second wiring is formed in the first inner layer. 7. The printed wiring board according to any one of configurations 1 to 6. (Configuration 8) a first ground layer located farther from the first inner layer than the surface layer; a second ground layer located between the surface layer and the second inner layer; 8. The printed wiring board according to configuration 7. (Configuration 9) a ground via that connects the first ground layer and the second ground layer; In the plan view, the ground via is disposed at a position on a perpendicular bisector connecting centers of the adjacent vias. 9. The printed wiring board according to configuration 8. (Configuration 10) The first wiring and the second wiring are address bus wiring. 10. The printed wiring board according to any one of configurations 1 to 9. (Configuration 11) a memory controller having a plurality of first signal terminals; a memory device having a plurality of second signal terminals; a printed wiring board on which the memory controller and the memory device are mounted; the printed wiring board has a plurality of first wirings, a plurality of second wirings, and a plurality of vias, the plurality of first wirings, the plurality of second wirings, and the plurality of vias electrically connecting the plurality of first signal terminals and the plurality of second signal terminals; the plurality of first wirings and the plurality of second wirings are connected to each other through the plurality of vias provided at intersections between the plurality of first wirings and the plurality of second wirings in a plan view seen in a direction perpendicular to a main surface of the printed wiring board; an angle θ between the plurality of first wirings and the plurality of second wirings in the plan view, the angle θ on a side closer to the memory controller and the memory device being greater than 90° and smaller than 180°; In the plan view, an angle φ is formed between a first line passing through the center of the adjacent vias and a second line passing through the first wiring, and the angle φ on the same side as the angle θ with respect to the second line is arctan(sinθ). A printed circuit board comprising: (Configuration 12) In the plan view, the first wiring is arranged closer to the memory controller than the second wiring with respect to the via. 12. The printed circuit board of claim 11. (Configuration 13) the angle θ, the angle φ, and the angle ψ between the second wiring and the first straight line in the plan view satisfy θ+φ+ψ≦180° 13. The printed circuit board according to claim 11 or 12. (Configuration 14) The angle θ is 135°. 14. The printed circuit board according to any one of configurations 11 to 13. (Configuration 15) The angle φ is equal to or greater than 20° and equal to or less than 50°. 15. The printed circuit board according to any one of configurations 11 to 14. (Configuration 16) The angle φ is 35°. 16. The printed circuit board of claim 15. (Configuration 17) The printed wiring board comprises: a surface on which the memory controller and the memory device can be mounted; A first inner layer; a second inner layer located farther from the surface layer than the first inner layer; The first wiring is formed in the second inner layer, and the second wiring is formed in the first inner layer. 17. The printed circuit board according to any one of configurations 11 to 16. (Configuration 18) The printed wiring board comprises: a first ground layer located farther from the first inner layer than the surface layer; a second ground layer located between the surface layer and the second inner layer; 18. The printed circuit board of claim 17. (Configuration 19) the printed wiring board has a ground via that connects the first ground layer and the second ground layer; In the plan view, the ground via is disposed at a position on a perpendicular bisector connecting centers of the adjacent vias. 19. The printed circuit board of claim 18. (Configuration 20) The first wiring and the second wiring are address bus wiring. 20. The printed circuit board according to any one of claims 11 to 19. (Configuration 21) A housing and and a printed circuit board according to any one of configurations 11 to 20 disposed inside the housing. 1. An electronic device comprising: (Configuration 22) A housing and A main body section that is disposed inside the housing and outputs image data; and a printed circuit board according to any one of configurations 11 to 20, which is disposed inside the housing and performs image processing on the image data. 1. An image forming apparatus comprising: [Explanation of symbols]

[0082] 100 Image forming apparatus 101...Device body 102... Enclosure 200 Control module 201... Conversion chip 301, 302, 303... Connector 304···Cable 500 Printed wiring board 501, 502, 503, 504, 505, 506... Conductor layer 560...Via conductor 560_1, 560_3, 560_5...Via 561...Via conductor 561_1, 561_3, 561_5...Via 562 Via conductor 562_1, 562_3, 562_5...Via 563 Ground Via 610...Memory Controller 610_1, 610_3, 610_5 Command / Address terminal 611, 612: Memory devices 611_1, 611_3, 611_5 Command / Address terminals 613...Resistor 710 Address signal line 710_1,710_2,710_3,710_4,710_5,710_6...Wiring 711, 712 Data signal line

Claims

1. A printed wiring board on which a memory controller having a plurality of first signal terminals and a memory device having a plurality of second signal terminals can be mounted, a plurality of first wirings, a plurality of second wirings, and a plurality of vias, the plurality of first wirings, the plurality of second wirings, and the plurality of vias being provided to electrically connect the plurality of first signal terminals and the plurality of second signal terminals; the plurality of first wirings and the plurality of second wirings are connected to each other through the plurality of vias provided at intersections between the plurality of first wirings and the plurality of second wirings in a plan view seen in a direction perpendicular to a main surface of the printed wiring board; an angle θ between the plurality of first wirings and the plurality of second wirings in the plan view, the angle θ on a side closer to the memory controller and the memory device being greater than 90° and smaller than 180°; In the plan view, an angle φ is formed between a first line passing through the center of the adjacent vias and a second line passing through the first wiring, and the angle φ on the same side as the angle θ with respect to the second line is arctan(sin θ). A printed wiring board comprising:

2. In the plan view, the first wiring is arranged closer to the memory controller than the second wiring with respect to the via.

2. The printed wiring board according to claim 1.

3. the angle θ, the angle φ, and the angle ψ between the second wiring and the first straight line in the plan view satisfy θ+φ+ψ≦180°; 3. The printed wiring board according to claim 1 or 2.

4. The angle θ is 135°.

3. The printed wiring board according to claim 1 or 2.

5. The angle φ is equal to or greater than 20° and equal to or less than 50°.

3. The printed wiring board according to claim 1 or 2.

6. The angle φ is 35°.

6. The printed wiring board according to claim 5.

7. a surface on which the memory controller and the memory device can be mounted; A first inner layer; and a second inner layer located farther from the surface layer than the first inner layer; The first wiring is formed in the second inner layer, and the second wiring is formed in the first inner layer.

3. The printed wiring board according to claim 1 or 2.

8. a first ground layer located farther from the first inner layer than the surface layer; a second ground layer located between the surface layer and the second inner layer; 8. The printed wiring board according to claim 7.

9. a ground via that connects the first ground layer and the second ground layer; In the plan view, the ground via is disposed at a position on a perpendicular bisector connecting centers of the adjacent vias.

9. The printed wiring board according to claim 8.

10. The first wiring and the second wiring are address bus wiring.

3. The printed wiring board according to claim 1 or 2.

11. a memory controller having a plurality of first signal terminals; a memory device having a plurality of second signal terminals; a printed wiring board on which the memory controller and the memory device are mounted; the printed wiring board has a plurality of first wirings, a plurality of second wirings, and a plurality of vias, the plurality of first wirings, the plurality of second wirings, and the plurality of vias electrically connecting the plurality of first signal terminals and the plurality of second signal terminals; the plurality of first wirings and the plurality of second wirings are connected to each other through the plurality of vias provided at intersections between the plurality of first wirings and the plurality of second wirings in a plan view seen in a direction perpendicular to a main surface of the printed wiring board; an angle θ between the plurality of first wirings and the plurality of second wirings in the plan view, the angle θ on a side closer to the memory controller and the memory device being greater than 90° and smaller than 180°; In the plan view, an angle φ is formed between a first line passing through the center of the adjacent vias and a second line passing through the first wiring, and the angle φ on the same side as the angle θ with respect to the second line is arctan(sin θ). A printed circuit board comprising:

12. In the plan view, the first wiring is arranged closer to the memory controller than the second wiring with respect to the via.

12. The printed circuit board of claim 11.

13. the angle θ, the angle φ, and the angle ψ between the second wiring and the first straight line in the plan view satisfy θ+φ+ψ≦180°; 13. The printed circuit board according to claim 11 or 12.

14. The angle θ is 135°.

13. The printed circuit board according to claim 11 or 12.

15. The angle φ is equal to or greater than 20° and equal to or less than 50°.

13. The printed circuit board according to claim 11 or 12.

16. The angle φ is 35°.

16. The printed circuit board of claim 15.

17. The printed wiring board comprises: a surface on which the memory controller and the memory device can be mounted; A first inner layer; and a second inner layer located farther from the surface layer than the first inner layer; The first wiring is formed in the second inner layer, and the second wiring is formed in the first inner layer.

13. The printed circuit board according to claim 11 or 12.

18. The printed wiring board comprises: a first ground layer located farther from the first inner layer than the surface layer; a second ground layer located between the surface layer and the second inner layer; 20. The printed circuit board of claim 17.

19. the printed wiring board has a ground via that connects the first ground layer and the second ground layer; In the plan view, the ground via is disposed at a position on a perpendicular bisector connecting centers of the adjacent vias.

20. The printed circuit board of claim 18.

20. The first wiring and the second wiring are address bus wiring.

13. The printed circuit board according to claim 11 or 12.

21. A housing and and the printed circuit board according to claim 11 or 12, disposed inside the housing.

1. An electronic device comprising:

22. A housing and A main body section that is disposed inside the housing and outputs image data; and the printed circuit board according to claim 11 or 12, which is disposed inside the housing and performs image processing on the image data.

1. An image forming apparatus comprising:

Images