Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device in which optical degradation is suppressed.SOLUTION: A semiconductor device includes a gate electrode, a gate insulating layer on the gate electrode, an oxide semiconductor layer with a polycrystalline structure on the gate insulating layer, a source electrode and a drain electrode on the oxide semiconductor layer, and an interlayer insulating layer covering the source and gate electrodes and in contact with the oxide semiconductor layer, and an S value is equal to or more than 1.5 V / dec and equal to or less than 2.5 V / dec. The oxide semiconductor layer includes a first region superimposed on one of the source and drain electrodes and a second region in contact with the interlayer insulating layer, and the difference between the thickness of the first region and the thickness of the second region may be equal to or less than 5 nm.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device. In particular, an embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel. Also, an embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, development of semiconductor devices using oxide semiconductor films as channels instead of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single crystal silicon, etc. has been progressing (see, for example, Patent Documents 1 to 6). A semiconductor device including such an oxide semiconductor film can be formed with a simple structure and a low-temperature process, similar to a semiconductor device including an amorphous silicon film. A semiconductor device including an oxide semiconductor film is known to have a higher field-effect mobility than a semiconductor device including an amorphous silicon film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] Since an oxide semiconductor film transmits light in the visible light region, a semiconductor device including the oxide semiconductor film is less susceptible to photodegradation than a semiconductor device including a silicon semiconductor film. However, it is desired to further suppress photodegradation in a semiconductor device including an oxide semiconductor film.

[0005] An object of one embodiment of the present invention is to provide a semiconductor device in which photodegradation is suppressed. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device in which photodegradation is suppressed. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a gate electrode, a gate insulating layer on the gate electrode, an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer, a source electrode and a drain electrode on the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer, and has an S value of 1.5 V / dec or more and 2.5 V / dec or less.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a gate electrode, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer, depositing a conductive film on the oxide semiconductor layer, patterning the conductive film by etching to form source and drain electrodes, performing an annealing treatment on the oxide semiconductor layer whose surfaces are exposed from the source and drain electrodes after the formation of the source and drain electrodes, and forming an interlayer insulating layer that covers the source and drain electrodes and is in contact with the oxide semiconductor layer after the annealing treatment. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 3]1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 13] 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1 is a schematic plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 19]1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 20] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 21] 1 is a schematic cross-sectional view showing a configuration of a display device according to one embodiment of the present invention. [Figure 22] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 23] 1 is a schematic cross-sectional view showing a configuration of a display device according to one embodiment of the present invention. [Figure 24] 1 is a graph showing the correlation between the S value and the shift amount of threshold voltage and the field effect mobility in an NBTIS test. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, film thickness, shape, etc. of the components compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "upper" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "lower" or "lower". Thus, for convenience of explanation, the terms "upper" and "lower" are used in the explanation, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the figure. In addition, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. "Upper" and "lower" refer to the order of stacking in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a semiconductor device, the semiconductor device and the pixel electrode may overlap in a planar view. Note that the planar view refers to a view from a direction perpendicular to the surface of the substrate.

[0011] In this specification, unless otherwise specified, the expressions "α includes A, B, or C," "α includes any of A, B, and C," or "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other components.

[0012] In this specification and the like, the term "semiconductor device" refers to a device in general that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are included in one form of semiconductor device. The semiconductor device of the embodiment described below may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a transistor used in a memory circuit.

[0013] In this specification, the term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, in the embodiment, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified as the display device. However, the structure described in the embodiment can be applied to the display device including the other electro-optical layers described above.

[0014] In this specification and the like, the terms "film" and "layer" may be interchangeable in some cases.

[0015] In this specification, the term "S value" refers to the increase in gate voltage (Vg) required to increase the drain current (Id) by one digit. For example, the S value is calculated by taking the threshold voltage (Vth) at Id=10 nA from the Id-Vg curve when the voltage difference between the source electrode and the drain electrode is 10 V. _10nA ) and threshold voltage (Vth _1nA ) is calculated, and then the difference (Vth _10nA -Vth _1nA ) can be obtained by calculating

[0016] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0017] First Embodiment A semiconductor device 10 according to one embodiment of the present invention will be described with reference to FIGS.

[0018] [Configuration of semiconductor device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device 10 according to one embodiment of the present invention. Fig. 2 is a schematic plan view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. The cross-sectional view shown in Fig. 1 corresponds to a cross section taken along line A1-A2 shown in Fig. 2.

[0019] As shown in FIG. 1, the semiconductor device 10 is provided on a substrate 11. The semiconductor device 10 includes a gate electrode 12GE, gate insulating layers 14 and 16, an oxide semiconductor layer 26, a source electrode 32S, a drain electrode 32D, and interlayer insulating layers 34 and 38. When the source electrode 32S and the drain electrode 32D are not particularly distinguished from each other, they may be collectively referred to as a source electrode and a drain electrode 32. In addition, the gate electrode 12GE, the gate insulating layers 14 and 16, the oxide semiconductor layer 26, and the source electrode and the drain electrode 32 may be collectively referred to as a transistor. The semiconductor device 10 is a so-called bottom-gate transistor in which the gate electrode 12GE is provided below the oxide semiconductor layer 26.

[0020] In this embodiment, a bottom-gate transistor is illustrated as the semiconductor device 10, but the semiconductor device 10 is not limited to the bottom-gate transistor. For example, the semiconductor device 10 may be a dual-gate transistor in which gate electrodes are provided above and below the oxide semiconductor layer 26.

[0021] The gate electrode 12GE is provided on the substrate 11. The gate insulating layers 14 and 16 are provided on the substrate 11 and the gate electrode 12GE. The gate insulating layers 14 and 16 have a laminated structure, and the gate insulating layer 16 is provided on the gate insulating layer 14. The oxide semiconductor layer 26 is provided on the gate insulating layers 14 and 16. The source electrode 32S and the drain electrode 32D are provided on the oxide semiconductor layer 26. The interlayer insulating layers 34 and 38 are provided on the oxide semiconductor layer 26 and the source electrode 32S and the drain electrode 32D. The interlayer insulating layers 34 and 38 have a laminated structure, and the interlayer insulating layer 38 is provided on the interlayer insulating layer 34. That is, the interlayer insulating layers 34 and 38 cover the source electrode 32S and the drain electrode 32D, and the interlayer insulating layer 34 is in contact with the oxide semiconductor layer 26.

[0022] As shown in FIG. 2, in a plan view, the oxide semiconductor layer 26 overlaps with the gate electrode 12GE. The D1 direction is a direction connecting the source electrode 32S and the drain electrode 32D, and the D2 direction is a direction perpendicular to the D1 direction. In the semiconductor device 10, the channel length L corresponds to the length of a region (channel region) of the oxide semiconductor layer 26 between the source electrode 32S and the drain electrode 32D in the D1 direction, and the channel width W corresponds to the width of the channel region in the D2 direction. In a plan view, the region of the oxide semiconductor layer 26 overlapping with the source electrode 32S is the source region, and the region of the oxide semiconductor layer 26 overlapping with the drain electrode 32D is the drain region. That is, the channel region is located between the source region and the drain region.

[0023] The wiring 12W and the wiring 32W function as a gate wiring. The wiring 32W is electrically connected to the wiring 12W through a contact hole 15. Although the details will be described later, the wiring 12W is formed in the same layer as the gate electrode 12GE. The wiring 32W is also formed in the same layer as the source electrode 32S and the drain electrode 32D. Note that the wiring 32W may not be provided on the wiring 12W.

[0024] The oxide semiconductor layer 26 is transparent and has a polycrystalline structure including a plurality of crystal grains. Although details will be described later, the oxide semiconductor layer 26 having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. Therefore, hereinafter, the oxide semiconductor included in the oxide semiconductor layer 26 may be described as Poly-OS.

[0025] The Poly-OS contains two or more metal elements including indium, and the ratio of indium to the two or more metal elements is 50% or more. As the metal element other than the indium element, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid element is used. As the oxide semiconductor layer 26, an element other than the above may be used.

[0026] The crystal grains contained in the Poly-OS have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size can be obtained by, for example, SEM observation, TEM observation, or Electron Back Scattered Diffraction (EBSD) method of the oxide semiconductor layer 26.

[0027] As described above, the crystal grains contained in the Poly-OS have a grain size of 0.1 μm or more, and therefore, in the oxide semiconductor layer 26 having a thickness of 10 nm or more and 30 nm or less, there is a region that contains only one crystal grain along the film thickness direction.

[0028] Poly-OS has excellent etching resistance. As will be described later in detail, Poly-OS has excellent etching resistance against the etching solution or etching gas used in forming the source electrode 32S and the drain electrode 32D. Therefore, the oxide semiconductor layer 26 is hardly etched in the formation of the source electrode 32S and the drain electrode 32D. Therefore, the film thickness of the first region (i.e., the source region or the drain region) of the oxide semiconductor layer 26 overlapping with one of the source electrode 32S and the drain electrode 32D is substantially the same as the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 not overlapping with the source electrode 32S and the drain electrode 32D. In other words, the difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less, preferably 3 nm or less, and more preferably 1 nm or less.

[0029] The film thickness of the channel region affects the electrical characteristics of the semiconductor device. If the film thickness of the channel region varies greatly, it is not possible to provide a semiconductor device with stable electrical characteristics. In other words, the yield of the semiconductor device decreases. On the other hand, in the semiconductor device 10, since the film thickness of the channel region of the oxide semiconductor layer 26 can be controlled, the semiconductor device 10 has stable electrical characteristics. For example, in the semiconductor device 10, even if the gate insulating layers 14 and 16 have a large film thickness of 300 nm or more, the thickness of the channel region can be controlled within a range of 15 cm when the channel length L of the channel region is in the range of 2 μm to 10 μm and the channel width W of the channel region is in the range of 2 μm to 25 μm. 2 / Vs or more, even 20cm 2 Therefore, the semiconductor device 10 has improved voltage resistance and stable electrical characteristics even under high voltage.

[0030] Furthermore, the S value of the semiconductor device 10 is 1.5 V / dec or more and 2.5 V / dec or less. When the S value of the semiconductor device 10 is within the above range, the semiconductor device 10 has a 2While having a field effect mobility of 1.5V / dec or more, the shift amount of the threshold voltage in the NBTIS (Negative Bias Thermal Illumination Stress) test is reduced. That is, when the semiconductor device 10 has an S value within the above range, the photodegradation of the semiconductor device 10 is suppressed. In the case of the semiconductor device 10 having a Poly-OS, the amount of the threshold voltage in the NBTIS test decreases as the S value increases. Therefore, if the S value of the semiconductor device 10 is less than 1.5V / dec, the photodegradation of the semiconductor device 10 cannot be sufficiently suppressed. Also, if the S value of the semiconductor device 10 exceeds 2.5V / dec, the field effect mobility decreases. Therefore, in the semiconductor device 10, the S value is adjusted to be within the above range. Below, a method for manufacturing the semiconductor device 10 will be described, including a method for adjusting the S value of the semiconductor device 10.

[0031] [Method of Manufacturing Semiconductor Device 10] A method for manufacturing a semiconductor device 10 according to an embodiment of the present invention will be described with reference to Fig. 3 to Fig. 11. Fig. 3 is a flowchart for explaining a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figs. 4 to 11 are schematic cross-sectional views showing a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Each step of the flowchart shown in Fig. 3 will be described in order below.

[0032] In step S1001 ("GE formation") of FIG. 3, a gate electrode 12GE is formed on a substrate 11 (see FIG. 4).

[0033] As the substrate 11, a rigid substrate having light transmission properties, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 11 needs to be flexible, a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate, or a substrate containing a resin is used as the substrate 11. When a substrate containing a resin is used as the substrate 11, impurity elements may be introduced into the resin in order to improve the heat resistance of the substrate 11. When the semiconductor device 10 is used in an integrated circuit, a substrate not having light transmission properties, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, may be used as the substrate 11.

[0034] The gate electrode 12GE is formed by processing a conductive film formed by a sputtering method. A metal material is used for the gate electrode 12GE. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used for the gate electrode 12GE. The above metal materials may be used as a single layer or a multilayer structure for the gate electrode 12GE.

[0035] In step S1002 ("GI formation") in FIG. 3, gate insulating layers 14 and 16 are formed on the gate electrode 12GE (see FIG. 4). The gate insulating layers 14 and 16 are formed by a chemical vapor deposition (CVD) method or a sputtering method. An insulating material is used for the gate insulating layers 14 and 16. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) and other inorganic insulating materials are used. x N yis a silicon compound that contains a smaller ratio (x>y) of nitrogen (N) than oxygen (O). SiN x O y is a silicon compound that contains a smaller proportion of oxygen than nitrogen (x>y).

[0036] It is preferable that a gate insulating layer 14 using an insulating material containing nitrogen and a gate insulating layer 16 using an insulating material containing oxygen are formed in this order on the substrate 11. By using an insulating material containing nitrogen as the gate insulating layer 14, impurities diffusing from the substrate 11 toward the oxide semiconductor layer 26 can be blocked. In addition, by using an insulating material containing oxygen as the gate insulating layer 16, oxygen can be released by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 500° C. or less, 450° C. or less, or 400° C. or less. The insulating material containing oxygen may release oxygen when heated in any step of the manufacturing process of the semiconductor device 10.

[0037] The thickness of the gate insulating layer 14 is preferably larger than the thickness of the gate insulating layer 16. In this embodiment, for example, silicon nitride of 300 nm is formed as the gate insulating layer 14. For example, silicon oxide of 100 nm is formed as the gate insulating layer 16.

[0038] In step S1004 ("OS film formation") in Fig. 3, an oxide semiconductor film 22 is formed on the gate insulating layers 14 and 16 (see Fig. 5). The oxide semiconductor film 22 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 22 is 10 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0039] A metal oxide having semiconductor properties can be used as the oxide semiconductor film 22. For example, an oxide semiconductor containing two or more metal elements including indium (In) is used as the oxide semiconductor film 22. The ratio of indium to the two or more metal elements is 50% or more. As the metal element other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid element is used. It is preferable that the oxide semiconductor film 22 contains a Group 13 element. Note that elements other than the above may be used as the oxide semiconductor film 22.

[0040] When the oxide semiconductor film 22 is crystallized by OS annealing described later, the oxide semiconductor film 22 after deposition and before OS annealing preferably has an amorphous structure (for example, a structure with few crystalline components of the oxide semiconductor that is determined to be amorphous by XRD). That is, the oxide semiconductor film 22 is preferably formed under conditions that prevent the oxide semiconductor film 22 from crystallizing as soon as it is formed. For example, when the oxide semiconductor film 22 is formed by a sputtering method, the oxide semiconductor film 22 is formed while controlling the temperature of the object to be formed (the substrate 11 and the structure formed thereon).

[0041] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object rises during the film formation process. When the temperature of the target object rises during the film formation process, the oxide semiconductor film 22 contains microcrystals immediately after the film formation. When the oxide semiconductor film 22 contains microcrystals, the crystal grain size cannot be increased by the subsequent OS annealing. In order to control the temperature of the target object, for example, the target object can be cooled while the film is formed. For example, the target object can be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the film formation temperature of the oxide semiconductor film 22 is preferably 50°C or less. By forming the oxide semiconductor film 22 while cooling the substrate 11, it is possible to obtain the oxide semiconductor film 22 having a small amount of crystalline components immediately after the film formation.

[0042] In the sputtering process, the oxide semiconductor film 22 having an amorphous structure is formed under conditions of an oxygen partial pressure of 10% or less. If the oxygen partial pressure is high, the oxide semiconductor film 22 contains excess oxygen, which causes microcrystals to be included in the oxide semiconductor film 22 immediately after the film formation. Therefore, it is preferable to form the oxide semiconductor film 22 under conditions of a low oxygen partial pressure. The oxygen partial pressure is, for example, 1% to 5%, and preferably 2% to 4%. Under conditions of an oxygen partial pressure of less than 1%, the distribution of oxygen in the film formation apparatus tends to be non-uniform. As a result, the composition of oxygen in the oxide semiconductor film is also non-uniform, and an oxide semiconductor film containing many microcrystals is formed, or an oxide semiconductor film that does not crystallize even if a subsequent OS annealing process is performed is formed.

[0043] In step S1005 ("OS pattern formation") in FIG. 3, a pattern of the oxide semiconductor layer 24 is formed (see FIG. 6). The pattern of the oxide semiconductor layer 24 is formed by photolithography. For example, a resist mask (not shown) is formed on the oxide semiconductor film 22, and the oxide semiconductor film 22 is etched using the resist mask. For etching the oxide semiconductor film 22, wet etching or dry etching may be used. For wet etching, etching can be performed using an acidic etching solution. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, or hydrofluoric acid can be used as the etching solution. In this way, the oxide semiconductor layer 24 having a predetermined pattern can be formed. Thereafter, the resist mask is removed.

[0044] It is preferable that the oxide semiconductor layer 24 having a predetermined pattern is formed (i.e., the oxide semiconductor film 22 is patterned) before the OS annealing. The Poly-OS after the OS annealing has high etching resistance, and the patterning by etching becomes difficult. In addition, by performing the OS annealing after the formation of the oxide semiconductor layer 24, damage (e.g., oxygen defects in the oxide semiconductor layer 24) caused during the formation of the oxide semiconductor layer 24 can be repaired.

[0045] In step S1006 ("OS anneal") in FIG. 3, after the oxide semiconductor layer 24 is formed, the oxide semiconductor layer 24 is subjected to a heat treatment (OS anneal) to form the oxide semiconductor layer 26 (see FIG. 7). In the OS anneal, the oxide semiconductor layer 24 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. By performing the OS anneal, the oxide semiconductor layer 24 having an amorphous structure is crystallized to form the oxide semiconductor layer 26 having a polycrystalline structure. That is, the oxide semiconductor layer 26 including the Poly-OS is formed by the OS anneal.

[0046] 3, contact holes are formed in the gate insulating layers 14 and 16 (see FIG. 8). This exposes the upper surface of the wiring 12W. If there is no need to connect the wiring 32W and the wiring 12W, the process of step S1008 does not need to be performed.

[0047] In step S1009 ("SD formation") in FIG. 3, the source electrode 32S, the drain electrode 32D, and the wiring 32W are formed (see FIG. 9). The source electrode 32S, the drain electrode 32D, and the wiring 32W are formed by patterning a conductive film formed by a sputtering method through etching. The source electrode 32S and the drain electrode 32D are made of a conductive material similar to that of the gate electrode 12GE. The source electrode 32S, the drain electrode 32D, and the wiring 32W may be made of a single layer or a multilayer of conductive materials. In this embodiment, a multilayer structure of MoW alloy, Al, and MoW alloy (MoW / Al / MoW structure), a single layer structure of MoW alloy (MoW structure), a single layer structure of Ti (Ti structure), and a multilayer structure of Ti, Al, and Ti (Ti / Al / Ti structure) are exemplified.

[0048] To form the source electrode 32S, the drain electrode 32D, and the wiring 32W, patterning is performed using wet etching or dry etching. In wet etching, an etching solution is used. For example, a solution containing at least two selected from the group consisting of phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, and oxalic acid can be used as the etching solution. Specifically, a mixed acid etching solution containing phosphoric acid, acetic acid, and nitric acid as main components can be used as the etching solution. Also, a mixed solution of hydrogen peroxide water and ammonia water (hereinafter referred to as "H2O2 / NH3 solution") can be used as the etching solution. In dry etching, an etching gas is used. For example, a gas containing fluorine such as sulfur hexafluoride gas (SF6) (hereinafter referred to as "fluorine-based gas") or a gas containing chlorine such as chlorine gas (Cl2) (hereinafter referred to as "chlorine-based gas") is used as the etching gas.

[0049] Poly-OS has excellent etching resistance. Specifically, the etching rate of the poly-OS is very small with respect to the etching solution or etching gas used in forming the source electrode 32S and the drain electrode 32D. This means that the poly-OS is hardly etched by the etching solution or etching gas. Therefore, in the semiconductor device 10, even if a conductive film is formed directly on the oxide semiconductor layer 26 and the conductive film is patterned to form the source electrode 32S and the drain electrode 32D, the channel region of the oxide semiconductor layer 26 is hardly etched.

[0050] For example, the etching rate of the oxide semiconductor layer 26 with respect to the etching solution used in forming the source electrode 32S and the drain electrode 32D is 0.1 nm / sec or less, or 0.01 nm / sec or less. Also, the etching rate of the oxide semiconductor layer 26 with respect to the etching gas used in forming the source electrode 32S and the drain electrode 32D is 0.5 nm / sec or less, or 0.1 nm / sec or less. For example, the etching rate of the oxide semiconductor layer 26 with respect to a chlorine-based gas is 0.1 nm / sec or less.

[0051] In a semiconductor device using an oxide semiconductor that does not have a polycrystalline structure, such as IGZO, as the oxide semiconductor layer, when a source electrode and a drain electrode are formed on the oxide semiconductor, the oxide semiconductor layer is also etched by etching the source electrode and the drain electrode. Specifically, the etching rate of IGZO with respect to a gas containing chlorine is 1.0 nm / sec, and it is necessary to form a thick oxide semiconductor film in advance, taking into consideration that the channel region is etched at this etching rate. For example, when manufacturing a semiconductor device in which the thickness of the channel region of the oxide semiconductor layer is 40 nm or less, it is necessary to form an oxide semiconductor film having a thickness of about 65 nm, and adjust the etching time in forming the source electrode and the drain electrode so that the thickness of the channel region is 40 nm or less. However, when the etching rate is high, it is difficult to precisely control the thickness of the channel region by the etching time. In this case, the variation in the thickness of the channel region becomes large.

[0052] Furthermore, when the thickness of the channel region is significantly reduced, a recess is formed on the upper surface of the oxide semiconductor layer. The interlayer insulating layer provided on the oxide semiconductor layer is formed so as to cover the recess, but if the recess is deep, the interlayer insulating layer cannot cover the recess sufficiently. That is, a gap may be generated between the oxide semiconductor layer and the interlayer insulating layer, or between the source electrode and the drain electrode and the interlayer insulating layer. This may cause variations in not only the electrical characteristics of the semiconductor device but also the reliability.

[0053] In contrast, the oxide semiconductor layer 26 containing Poly-OS can have an etching rate of 0.00 nm / sec to 0.1 nm / sec, preferably 0.00 nm / sec to 0.06 nm / sec, regardless of whether the etching is performed by dry etching or wet etching. That is, the oxide semiconductor layer 26 containing Poly-OS has a lower etching rate and higher etching resistance than the oxide semiconductor layer containing IGZO. Therefore, the thickness of the channel region can be controlled without considering the reduction in the thickness of the oxide semiconductor layer caused by etching. Therefore, the oxide semiconductor film can be formed to a thickness of 10 nm to 30 nm. In addition, the selectivity of conductive materials that can be used for the source electrode 32S, the drain electrode 32D, and the wiring 32W is improved. For example, even when the source electrode 32S and the drain electrode 32D are formed by wet etching a conductive film using a MoW / Al / MoW stacked structure or a MoW structure, the reduction in the thickness of the oxide semiconductor layer 26 can be suppressed.

[0054] As described above, the etching rate of the oxide semiconductor layer 26 with respect to the etching solution used in forming the source electrode 32S and the drain electrode 32D is very small. Therefore, the film thickness of the first region (i.e., the source region or the drain region) of the oxide semiconductor layer 26 overlapping with one of the source electrode 32S and the drain electrode 32D is substantially the same as the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 not overlapping with the source electrode 32S and the drain electrode 32D. In other words, the difference between the film thickness of the first region and the film thickness of the second region can be controlled to be 5 nm or less, preferably 3 nm or less, and more preferably 1 nm. That is, the variation in the film thickness of the channel region is suppressed.

[0055] In step S1010 ("BCH plasma treatment") in FIG. 3, a plasma treatment is performed on the oxide semiconductor layer 26, the source electrode 32S, and the drain electrode 32D using a predetermined gas. In practice, the plasma treatment may be performed on the surface of the oxide semiconductor layer 26 exposed from the source electrode 32S and the drain electrode 32D (hereinafter, sometimes referred to as "back channel"). As the predetermined gas, an inert gas such as argon gas or nitrogen gas may be used, but argon gas is preferable. The predetermined gas may be not only one type of gas, but also two or more types of gases. In addition, in the BCH plasma treatment, not only one plasma treatment but also multiple plasma treatments using different gases may be performed. The time of the plasma treatment is 5 seconds or more and 300 seconds or less, preferably 10 seconds or more and 150 seconds or less, and more preferably 15 seconds or more and 90 seconds or less.

[0056] When the SD formation in step S1009 is performed, impurities may adhere to the back channel due to the etching solution or etching gas. Therefore, BCH plasma processing is performed to remove the impurities adhered to the back channel. For example, if the impurities adhered to the back channel are mainly organic matter, the organic matter adhered to the back channel can be removed by plasma processing using argon gas.

[0057] In step S1011 ("BCH anneal") of FIG. 3, the oxide semiconductor layer 26, the source electrode 32S, and the drain electrode 32D are annealed. In practice, the back channel may be annealed. In the BCH anneal, the anneal is performed in an air atmosphere. The anneal temperature is 200° C. or more and 400° C. or less, preferably 200° C. or more and 300° C. or less, and more preferably 200° C. or more and 250° C. or less. The anneal time is 15 minutes or more and 150 minutes or less, preferably 30 minutes or more and 120 minutes or less, and more preferably 30 minutes or more and 90 minutes or less.

[0058] The BCH plasma and BCH annealing adjust the S value of the semiconductor device 10. By performing plasma processing of the back channel with BCH plasma, the S value of the semiconductor device 10 can be increased. On the other hand, by performing annealing processing of the back channel with BCH annealing, the S value of the semiconductor device 10 can be decreased. Therefore, the S value of the semiconductor device 10 can be adjusted to 1.5 V / dec or more and 2.5 V / dec or less by BCH plasma and BCH annealing. In order to adjust the S value of the semiconductor device 10 to the above range, at least one of the BCH plasma and the BCH annealing may be performed. The S value of the semiconductor device 10 can also be adjusted by the processing time in the BCH plasma or the temperature and time in the BCH annealing.

[0059] In step S1012 ("SiOx formation") in FIG. 3, an interlayer insulating layer 34 is formed on the oxide semiconductor layer 26, the source electrode 32S, and the drain electrode 32D. It is preferable to use an insulating material containing oxygen for the interlayer insulating layer 34. For example, silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) is preferably used. It is also preferable to use an insulating film with few defects as the interlayer insulating layer 34. For example, when the oxygen composition ratio in the interlayer insulating layer 34 is compared with the oxygen composition ratio in an insulating film having the same composition as the interlayer insulating layer 34 (hereinafter referred to as "another insulating film"), the oxygen composition ratio in the interlayer insulating layer 34 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating film. However, when silicon oxide (SiO x When a silicon oxide (SiO2) is used, it is preferable that the gate insulating layer 16 has a composition ratio closer to the stoichiometric ratio of silicon oxide (SiO2) than the interlayer insulating layer 34. As the interlayer insulating layer 34, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used.

[0060] The interlayer insulating layer 34 can be formed by using the same film formation method as the gate insulating layers 14, 16. In order to increase the composition ratio of oxygen in the interlayer insulating layer 34, the film may be formed at a relatively low temperature (for example, a film formation temperature of less than 350° C.). In order to form an insulating film with few defects as the interlayer insulating layer 34, the interlayer insulating layer 34 may be formed at a film formation temperature of 350° C. or higher. Furthermore, after forming the interlayer insulating layer 34, a process of implanting oxygen into a part of the interlayer insulating layer 34 may be performed.

[0061] The thickness of the interlayer insulating layer 34 is 10 nm or more and 300 nm or less, 40 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less.

[0062] 3, a metal oxide film 36 is formed on the interlayer insulating layer 34 (see FIG. 10). The metal oxide film 36 is formed by sputtering or atomic layer deposition (ALD).

[0063] A metal oxide containing aluminum as a main component is used as the metal oxide film 36. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. A metal oxide film containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide film 36 is 1% or more of the entire metal oxide film 36. The ratio of aluminum contained in the metal oxide film 36 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide film 36. The above ratio may be a mass ratio or a weight ratio.

[0064] The thickness of the metal oxide film 36 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less. Aluminum oxide is preferably used as the metal oxide film 36. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. Here, the barrier properties refer to a function of suppressing the permeation of gases such as oxygen and hydrogen through aluminum oxide. In other words, it means that gases such as oxygen and hydrogen in a layer provided under the aluminum oxide film are not allowed to move to a layer provided on the aluminum oxide film. Or, it means that gases such as oxygen and hydrogen in a layer provided on the aluminum oxide film are not allowed to move to a layer provided under the aluminum oxide film.

[0065] Note that a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide film 36. For example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like may be used as the metal oxide film 36.

[0066] 3 ("oxidation anneal"), a heat treatment is performed (see FIG. 10) on the oxide semiconductor layer 26 with the interlayer insulating layer 34 and the metal oxide film 36 formed thereon. As a result, oxygen released from the interlayer insulating layer 34 is supplied to the oxide semiconductor layer 26. The metal oxide film 36 is provided so as to cover the substrate 11, so that the oxygen released from the interlayer insulating layer 34 can be prevented from being released to the outside of the metal oxide film 36.

[0067] During the process from when the oxide semiconductor layer 26 is formed until when the interlayer insulating layer 34 is formed on the oxide semiconductor layer 26, many oxygen defects are generated in the oxide semiconductor layer 26. However, by the oxidation annealing in step S1014, oxygen released from the interlayer insulating layer 34 is supplied to the oxide semiconductor layer 26, and the oxygen defects are repaired.

[0068] 3, the metal oxide film 36 is removed (see FIG. 11). For example, the metal oxide film 36 may be removed using diluted hydrofluoric acid (DHF).

[0069] 3, an interlayer insulating layer 38 is formed on the interlayer insulating layer 34. It is preferable to use an insulating material containing nitrogen for the interlayer insulating layer 38. For example, silicon nitride (SiN x ) or silicon oxynitride (SiN x O y The interlayer insulating layer 38 can be formed by the same film formation method as that for the gate insulating layers 14 and 16.

[0070] Through the steps described above, the semiconductor device 10 shown in FIG. 1 can be manufactured.

[0071] In the semiconductor device 10 manufactured by the above-mentioned manufacturing method, the S value can be adjusted to 1.5 V / dec or more and 2.5 V / dec or less. 2 It is possible to suppress light degradation of the semiconductor device 10 while having a field effect mobility of 1.5 V or more.

[0072] <Second embodiment> A semiconductor device 10A according to one embodiment of the present invention will be described with reference to Figures 12 to 17. Note that when the components of the semiconductor device 10A are similar to those of the semiconductor device 10, the description of the components of the semiconductor device 10A may be omitted.

[0073] [Configuration of semiconductor device 10A] Fig. 12 is a cross-sectional view showing a schematic configuration of a semiconductor device 10A according to one embodiment of the present invention, which corresponds to a cross section taken along line A1-A2 shown in Fig. 2.

[0074] As shown in Fig. 12, the semiconductor device 10A is provided on a substrate 11. The semiconductor device 10A includes a gate electrode 12GE, gate insulating layers 14 and 16, a metal oxide layer 28, an oxide semiconductor layer 26, a source electrode 32S, a drain electrode 32D, and interlayer insulating layers 34 and 38. That is, unlike the semiconductor device 10, the semiconductor device 10A includes a metal oxide layer 28. Note that the gate electrode 12GE, the gate insulating layers 14 and 16, the metal oxide layer 28, the oxide semiconductor layer 26, and the source electrode and drain electrode 32 may be referred to as a transistor.

[0075] The metal oxide layer 28 is provided on the gate insulating layer 16. In addition, the oxide semiconductor layer 26 is provided on the metal oxide layer 28. An end face of the metal oxide layer 28 is approximately aligned with an end face of the oxide semiconductor layer 26.

[0076] In the semiconductor device 10A, the metal oxide layer 28 controls the crystallinity of the Poly-OS in the oxide semiconductor layer 26, and also controls the thickness of the channel region of the oxide semiconductor layer 26 containing the Poly-OS, so that the semiconductor device 10A has more stable electrical characteristics. For example, in the semiconductor device 10A, even when the gate insulating layers 14 and 16 have a large thickness of 300 nm or more, the semiconductor device 10A can achieve a thickness of 20 cm or less when the channel length L of the channel region is in the range of 2 μm to 4 μm and the channel width W of the channel region is in the range of 2 μm to 25 μm. 2 / Vs or more, even 30cm 2 Therefore, the semiconductor device 10A has improved voltage resistance and stable electrical characteristics even under high voltage.

[0077] In addition, the S value of the semiconductor device 10A is 1.5 V / dec or more and 2.5 V / dec or less. When the S value of the semiconductor device 10A is within the above range, the semiconductor device 10A has a 2 3. It is possible to suppress light degradation of the semiconductor device 10A while having a field effect mobility of 1.0 V or more.

[0078] [Manufacturing Method of Semiconductor Device 10A] A method for manufacturing a semiconductor device 10A according to one embodiment of the present invention will be described with reference to Figs. 13 to 17. Fig. 13 is a flowchart for explaining a method for manufacturing a semiconductor device 10A according to one embodiment of the present invention. Figs. 14 to 17 are schematic cross-sectional views showing a method for manufacturing a semiconductor device 10A according to one embodiment of the present invention. Each step of the flowchart shown in Fig. 13 will be described in order below, but some of the steps described in the first embodiment will not be described.

[0079] 13, a metal oxide film 18 is formed on the gate insulating layers 14 and 16 (see FIG. 14). The metal oxide film 18 is formed by sputtering or atomic layer deposition (ALD).

[0080] Metal oxide containing aluminum as a main component is used as the metal oxide film 18. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), or aluminum nitride (AlN x ) is used. A metal oxide containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide is 1% or more. Specifically, the ratio of aluminum contained in the metal oxide film 18 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide film 18. The above ratio may be a mass ratio or a weight ratio.

[0081] The thickness of the metal oxide film 18 is, for example, 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. In this embodiment, aluminum oxide is used as the metal oxide film 18. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. In other words, the barrier properties refer to a function of suppressing the permeation of gases such as oxygen and hydrogen through aluminum oxide. That is, even if gases such as oxygen or hydrogen exist from a layer provided below the aluminum oxide film, they are not allowed to move to a layer provided above the aluminum oxide film. Or, even if gases such as oxygen or hydrogen exist from a layer provided above the aluminum oxide film, they are not allowed to move to a layer provided below the aluminum oxide film.

[0082] In step S1004 ("OS film formation") in FIG. 13, an oxide semiconductor film 22 is formed on the metal oxide film 18 (see FIG. 14).

[0083] In step S1005 ("OS pattern formation") of FIG. 13, a pattern of the oxide semiconductor layer 24 is formed (see FIG. 15).

[0084] In step S1006 ("OS anneal") in FIG. 13, after the oxide semiconductor layer 24 is formed, heat treatment (OS anneal) is performed on the oxide semiconductor layer 24 to form the oxide semiconductor layer 26 (see FIG. 16).

[0085] In step S1007 ("MO pattern formation") in FIG. 13, the metal oxide film 18 is patterned to form a metal oxide layer 28 (see FIG. 17). The oxide semiconductor layer 26 sufficiently crystallized by the heat treatment has high etching resistance. Therefore, when the metal oxide film 18 is patterned using the crystallized oxide semiconductor layer 26 as a mask, it is possible to suppress the oxide semiconductor layer 26 from disappearing. The metal oxide film 18 is etched using the oxide semiconductor layer 26 patterned in the above process as a mask. For etching the metal oxide film 18, wet etching may be used or dry etching may be used. For example, diluted hydrofluoric acid (DHF) is used for wet etching. By etching the metal oxide film 18 using the oxide semiconductor layer 26 as a mask, the photolithography process can be omitted.

[0086] Steps S1008 to S1016 in FIG. 13 are similar to steps S1008 to S1016 in FIG. 3, and therefore will not be described here.

[0087] Through the steps described above, the semiconductor device 10A shown in FIG. 13 can be manufactured.

[0088] In the semiconductor device 10A manufactured by the above-mentioned manufacturing method, the S value can be adjusted to 1.5 V / dec or more and 2.5 V / dec or less. 2 It is possible to suppress light degradation of the semiconductor device 10 while having a field effect mobility of 1.5 V or more.

[0089] <Third embodiment> 18 to 21, a display device 20 using a semiconductor device 10 according to one embodiment of the present invention will be described. In the embodiment shown below, a configuration in which the semiconductor device 10 described in the first embodiment is applied to the circuitry of a liquid crystal display device will be described.

[0090] [Outline of the display device 20] Fig. 18 is a schematic plan view showing an overview of a display device 20 according to an embodiment of the present invention. As shown in Fig. 18, the display device 20 has an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. In a liquid crystal region 220 surrounded by the seal portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 220 is an area that overlaps with a liquid crystal element 311 described later in a plan view.

[0091] The seal area 240 in which the seal portion 310 is provided is a region surrounding the liquid crystal region 220. The FPC 330 is provided in the terminal area 260. The terminal area 260 is a region in which the array substrate 300 is exposed from the counter substrate 320, and is provided outside the seal area 240. The outside of the seal area 240 means the outside of the region in which the seal portion 310 is provided and the region surrounded by the seal portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0092] [Circuit configuration of display device 20] Fig. 19 is a block diagram showing a circuit configuration of a display device 20 according to an embodiment of the present invention. As shown in Fig. 19, a source driver circuit 302 is provided at a position adjacent to the liquid crystal region 220 in which the pixel circuits 301 are arranged in the second direction D2 (column direction), and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal region 220 in the first direction D1 (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the above-mentioned sealing region 240. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 240, and may be any region outside the region in which the pixel circuits 301 are provided.

[0093] A source line 304 extends from the source driver circuit 302 in the second direction D2 and is connected to the plurality of pixel circuits 301 arranged in the second direction D2. A gate electrode 12GE extends from the gate driver circuit 303 in the first direction D1 and is connected to the plurality of pixel circuits 301 arranged in the first direction D1.

[0094] A terminal section 306 is provided in the terminal region 260. The terminal section 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connection wiring 307. By connecting the FPC 330 to the terminal section 306, an external device to which the FPC 330 is connected is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0095] The semiconductor device 10 according to the first embodiment is used as a transistor included in a pixel circuit 301, a source driver circuit 302, and a gate driver circuit 303.

[0096] [Pixel circuit 301 of display device 20] Fig. 20 is a circuit diagram showing a pixel circuit 301 of a display device 20 according to an embodiment of the present invention. As shown in Fig. 20, the pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 12GE, an oxide semiconductor layer 26, a source electrode 32S, and a drain electrode 32D. The gate electrode 12GE is connected to a gate wiring 305. The source electrode 32S is connected to a source wiring 304. The drain electrode 32D is connected to the storage capacitor 350 and the liquid crystal element 311.

[0097] [Configuration of display device 20] Fig. 21 is a schematic cross-sectional view of a display device 20 according to one embodiment of the present invention. The display device 20 shown in Fig. 21 uses the semiconductor device 10.

[0098] 21, a gate electrode 12GE is provided on a substrate 11. Gate insulating layers 14 and 16 are provided on the gate electrode 12GE. An oxide semiconductor layer 26 is provided on the gate insulating layers 14 and 16. A source electrode 32S and a drain electrode 32D are provided on the oxide semiconductor layer 26.

[0099] Interlayer insulating layers 34 and 38 are provided on the source electrode 32S and the drain electrode 32D. An insulating layer 39 is provided on the interlayer insulating layers 34 and 38. The insulating layer 39 is provided to reduce unevenness caused by the semiconductor device 10. A contact hole is formed in the interlayer insulating layers 34 and 38 and the insulating layer 39 so as to expose the upper surface of the source electrode 32S. A common electrode 42C that is provided in common to a plurality of pixels is provided on the insulating layer 39. An insulating layer 44 is provided on the common electrode 42C. The insulating layer 44 is provided inside the contact hole. By forming the insulating layer 44 from a silicon nitride film, it is possible to suppress the intrusion of moisture from the contact hole through the insulating layer 44. A pixel electrode 46P is provided on the insulating layer 44 and inside the contact hole. The pixel electrode 46P is connected to the drain electrode 32D.

[0100] Furthermore, a wiring 12C is provided on the substrate 11 and is connected to a wiring 32C through a contact hole provided in the gate insulating layers 14 and 16. The wiring 12C and the wiring 32C function as a capacitance wiring. Furthermore, an electrode 46C is provided on the insulating layer 39 and inside the opening. A storage capacitor 350 is formed by the common electrode 42C, the insulating layer 44, and the electrode 46C.

[0101] In this embodiment, a configuration in which the semiconductor device 10 is used in the pixel circuit 301 is illustrated as an example, but the semiconductor device 10 may also be used in a peripheral circuit including a source driver circuit 302 and a gate driver circuit 303 .

[0102] <Fourth embodiment> A display device 20 using the semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 22 and Fig. 23. In this embodiment, a configuration in which the semiconductor device 10 described in the first embodiment is applied to the circuit of an organic EL display device will be described. The outline and circuit configuration of the display device 20 are similar to those shown in Fig. 18 and Fig. 19, and therefore description thereof will be omitted.

[0103] [Pixel circuit 301 of display device 20] FIG. 22 is a circuit diagram showing a pixel circuit of a display device 20 according to an embodiment of the present invention. As shown in FIG. 22, a pixel circuit 301 includes elements such as a driving transistor 110, a selection transistor 120, a storage capacitor 210, and a light-emitting element DO. The driving transistor 110 and the selection transistor 120 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 120 is connected to a signal line 211, and the gate electrode of the selection transistor 120 is connected to a gate line 212. The source electrode of the driving transistor 110 is connected to an anode power line 213, and the drain electrode of the driving transistor 110 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to a cathode power line 214. The gate electrode of the driving transistor 110 is connected to the drain electrode of the selection transistor 120. The storage capacitor 210 is connected to the gate electrode and drain electrode of the driving transistor 110. A grayscale signal that determines the light-emitting intensity of the light-emitting element DO is supplied to the signal line 211. A signal that selects a pixel row to which the above grayscale signal is written is supplied to the gate line 212.

[0104] [Cross-sectional structure of the display device 20] Fig. 23 is a schematic cross-sectional view showing the configuration of a display device 20 according to one embodiment of the present invention. The configuration of the display device 20 shown in Fig. 23 is similar to that of the display device 20 shown in Fig. 21, but the structure above the insulating layer 39 of the display device 20 shown in Fig. 23 is different from the structure above the insulating layer 39 of the display device 20 shown in Fig. 21. Hereinafter, a description of the configuration of the display device 20 shown in Fig. 23 that is similar to that of the display device 20 shown in Fig. 21 will be omitted, and only the differences between the two will be described.

[0105] As shown in FIG. 23, the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating layer 39. The pixel electrode 390 is provided on the insulating layer 39 and inside a contact hole formed in the interlayer insulating layers 34, 38 and the insulating layer 39. An insulating layer 362 is provided on the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to a light-emitting region. That is, the insulating layer 362 defines a pixel. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common to a plurality of pixels. The light-emitting layer 392 is made of different materials depending on the display color of the pixel.

[0106] In the second and third embodiments, the semiconductor device 10 described in the first embodiment is applied to a liquid crystal display device and an organic EL display device. However, the semiconductor device 10 may be applied to a display device other than these display devices (for example, a self-luminous display device other than an organic EL display device or an electronic paper display device). The semiconductor device 10 can be applied to a variety of display devices, from small and medium-sized display devices to large display devices, without any particular limitations. Even when manufactured using a large-area substrate, the shape of the oxide semiconductor layer 26 in the semiconductor device 10 varies little. Therefore, when the semiconductor device 10 is applied to the display device 20, display unevenness can be reduced. Furthermore, the yield rate when manufacturing the display device 20 can be improved. EXAMPLES

[0107] [Sample Preparation] Five semiconductor devices (samples 1 to 5) were fabricated using the manufacturing method for the semiconductor device 10A described in the second embodiment.

[0108] Table 1 shows different fabrication conditions for Samples 1 to 5. Fabrication conditions other than those shown in Table 1 are common to Samples 1 to 5. Specifically, a gate electrode 12GE was formed on a glass substrate, and gate insulating layers 14 and 16 were formed on the gate electrode 12GE. A metal oxide film 18 (aluminum oxide) having a thickness of 3 nm and an oxide semiconductor film 22 having a thickness of 30 nm were formed on the gate insulating layers 14 and 16. The oxide semiconductor film 22 was processed to form an oxide semiconductor layer 24, and an OS annealing process was performed at a controlled temperature in the range of 350° C. to 450° C. to form an oxide semiconductor layer 26 (Poly-OS) having a polycrystalline structure. In addition, the metal oxide film 18 was patterned using the oxide semiconductor layer 26 as a mask to form a metal oxide layer 28.

[0109] A conductive film was formed on the oxide semiconductor layer 26, and a source electrode 32S and a drain electrode 32D were formed by wet etching. Next, a silicon oxide layer was formed as an interlayer insulating layer 34, and then a metal oxide film 36 (aluminum oxide) of 10 nm was formed. After oxidation annealing, the metal oxide film 36 was removed. Finally, an interlayer insulating layer 38 was formed on the interlayer insulating layer 34.

[0110] [Table 1]

[0111] Regarding the differences in the fabrication conditions in Table 1, Sample 1 and Sample 2 differ in the materials of the source electrode and drain electrode 32. Also, BCE annealing and BCE plasma were not performed in Sample 1 and Sample 2, whereas BCE annealing was performed in Samples 3 to 5. Also, BCH plasma was not performed in Sample 3, whereas BCH plasma was performed in Samples 4 and 5. Note that, in the implementation of BCH plasma in Sample 4 and Sample 5, plasma treatment was performed using argon gas (Ar gas) in Sample 4, whereas plasma treatment was performed using chlorine gas (Cl gas) in Sample 5.

[0112] [Sample evaluation] To evaluate the fabricated Samples 1 to 5, electrical characteristics were measured and an NBTIS test was performed. In order to perform the NBTIS test as an accelerated test, the samples were heated to 85° C. and irradiated with light from the back channel side that was not blocked by the gate electrode 12GE. The evaluation results of Samples 1 to 5 are shown in Table 2.

[0113] [Table 2]

[0114] The "field effect mobility" in Table 2 is the linear field effect mobility when the gate voltage is 20 V. Also, the "shift amount" in Table 2 is the shift amount of the threshold voltage after the stress time (1000 seconds) has elapsed in the NBTIS test.

[0115] Fig. 24 is a graph showing the correlation between the S value and the threshold voltage shift amount and field effect mobility in the NBTIS test. In addition to plotting the threshold voltage shift amount (circles) and field effect mobility (triangles), Fig. 24 also shows an approximation curve (solid line) of the threshold voltage shift amount versus the S value.

[0116] As shown in Fig. 24, as the S value increases, the shift of the threshold voltage decreases, and photodegradation is suppressed. 2A field effect mobility of 1000 .ANG. / Vs or more can be obtained. However, the S value cannot be increased significantly by simply changing the material of the source electrode and the drain electrode 32 (Sample 1 and Sample 2). In contrast, the S value can be changed significantly by performing BCH annealing or BCH plasma (Sample 3 to Sample 5). Specifically, the S value increases when BCH annealing is performed, and decreases when BCH plasma is performed using argon gas (Sample 3 and Sample 4). In addition, the S value increases when BCH plasma is performed using chlorine gas (Sample 5). However, if the S value is too large, the field effect mobility decreases significantly (Sample 5).

[0117] As can be seen from the evaluation results shown in Fig. 24, if the S value is less than 1.5 V / dec, photodegradation cannot be sufficiently suppressed, and if the S value exceeds 2.5 V / dec, the field-effect mobility decreases. Therefore, in the semiconductor device 10A (or the semiconductor device 10), one or both of BCH plasma and BCH annealing are performed to adjust the S value range to 1.5 V / dec or more and 2.5 V / dec or less. This makes it possible to obtain the semiconductor device 10A (or the semiconductor device 10) having high field-effect mobility while suppressing photodegradation.

[0118] The above-mentioned embodiments and modifications of the present invention may be combined as appropriate as long as they are not mutually inconsistent. In addition, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits processes or modifies conditions, based on the semiconductor device and display device of each embodiment and modification are included in the scope of the present invention as long as they include the gist of the present invention.

[0119] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0120] 10, 10A: semiconductor device, 20: display device, 11: substrate, 12C: wiring, 12GE: gate electrode, 12W: wiring, 14: gate insulating layer, 15: contact hole, 16: gate insulating layer, 18: metal oxide film, 22: oxide semiconductor film, 24: oxide semiconductor layer, 26: oxide semiconductor layer, 28: metal oxide layer, 32C: wiring, 32D: drain electrode, 32S: source electrode, 32W: wiring, 34: interlayer insulating layer, 36: metal oxide film, 38: interlayer insulating layer, 39: insulating layer, 42C: common electrode, 44: insulating layer, 46C: electrode, 46P: pixel electrode, 110: driving transistor, 120: selection transistor, 210: storage capacitor, 211: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 220: liquid crystal region, 240: sealing region, 260: terminal region, 300: array substrate, 301: pixel circuit, 302: source driver circuit, 303: gate driver circuit, 304: source wiring, 305: gate wiring, 306: terminal section, 307: connection wiring, 310: sealing section, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit board, 340: chip, 350: storage capacitor, 362: insulating layer, 363: opening, 390: pixel electrode, 392: light-emitting layer, 394: common electrode

Claims

1. A gate electrode; a gate insulating layer on the gate electrode; an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer; A semiconductor device having an S value of 1.5 V / dec or more and 2.5 V / dec or less.

2. The oxide semiconductor layer is a first region overlapping one of the source electrode and the drain electrode; a second region in contact with the interlayer insulating layer; 2. The semiconductor device according to claim 1, wherein a difference between a thickness of said first region and a thickness of said second region is 5 nm or less.

3. the oxide semiconductor layer contains indium and at least one metal element other than indium, 2. The semiconductor device according to claim 1, wherein a ratio of said indium to said at least one metal element is 50% or more.

4. The semiconductor device according to claim 1 , further comprising a metal oxide layer between the gate insulating layer and the oxide semiconductor layer.

5. 5. The semiconductor device according to claim 4, wherein the metal oxide layer has a thickness of 10 nm or less.

6. The semiconductor device according to claim 4 , wherein an end face of the metal oxide layer is substantially aligned with an end face of the oxide semiconductor layer.

7. The field effect mobility is 20 cm ２ 6. The semiconductor device according to claim 5, wherein the Vref is greater than or equal to 1 Vs.

8. forming a gate electrode; forming a gate insulating layer on the gate electrode; forming an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer; forming a conductive film on the oxide semiconductor layer; patterning the conductive film by etching to form a source electrode and a drain electrode; After the source electrode and the drain electrode are formed, an annealing treatment is performed on the oxide semiconductor layer whose surface is exposed from the source electrode and the drain electrode; forming, after the annealing treatment, an interlayer insulating layer that covers the source electrode and the drain electrode and is in contact with the oxide semiconductor layer.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein an S value of the semiconductor device is not less than 1.5 V / dec and not more than 2.5 V / dec.

10. The oxide semiconductor layer is a first region overlapping one of the source electrode and the drain electrode; a second region in contact with the interlayer insulating layer; 9. The method for manufacturing a semiconductor device according to claim 8, wherein a difference between a film thickness of said first region and a film thickness of said second region is 5 nm or less.

11. the oxide semiconductor layer contains indium and at least one metal element other than indium, 9. The method for manufacturing a semiconductor device according to claim 8, wherein a ratio of said indium to said indium and said at least one metal element is 50% or more.

12. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the annealing treatment is performed in an air atmosphere.

13. The method for manufacturing a semiconductor device according to claim 8 , further comprising the step of: performing a plasma treatment on the oxide semiconductor layer, the surface of which is exposed, using a predetermined gas, before the annealing treatment.

14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the predetermined gas is argon gas or nitrogen gas.

15. moreover, forming a metal oxide film on the gate insulating layer; 9. The method for manufacturing a semiconductor device according to claim 8, further comprising: patterning the metal oxide film by etching using the oxide semiconductor layer as a mask to form a metal oxide layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the metal oxide layer has a thickness of 10 nm or less.

17. The field effect mobility of the semiconductor device is 20 cm ２ The method for manufacturing a semiconductor device according to claim 15, wherein the voltage Vcc is greater than or equal to 1 Vs.

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