Display device and manufacturing method for display device

Abstract

To provide a high-definition display device.SOLUTION: A display device includes an oxide semiconductor layer including a polycrystal structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a source wire provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wire and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer. The gate electrode has a channel length of 2.0 μm or less.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device and a method for manufacturing the display device. In particular, one embodiment of the present invention relates to a display device using a transistor having an oxide semiconductor and a method for manufacturing the display device. [Background technology]

[0002] Recently, development of transistors using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single crystal silicon has been progressing (for example, Patent Document 1 and Patent Document 2). Transistors using oxide semiconductors for the channel have a simple structure and are formed by a low-temperature process, similar to transistors using amorphous silicon for the channel. Transistors using oxide semiconductors for the channel are known to have higher mobility and very low off-current than transistors using amorphous silicon for the channel.

[0003] In recent years, display devices have been required to have higher definition, and pixel sizes are being reduced. Along with the reduction in pixel size, reductions in wiring width and transistor size are being considered. However, there is a limit to these reductions, and the aperture ratio is reduced due to the arrangement of metal layers and semiconductor layers that constitute the pixel circuit. Therefore, development is being carried out to use transistors in pixel circuits that use an oxide semiconductor layer for the channel, which can provide sufficient characteristics for driving the pixel circuit even if the transistor size is small. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-146819 A [Patent Document 2] JP 2015-159315 A Summary of the Invention [Problem to be solved by the invention]

[0005] It is known that a transistor using an oxide semiconductor is significantly affected by hydrogen contained in an insulating film provided around the oxide semiconductor. As the pixel size of a display device becomes smaller, the size (channel length L) of the transistor must also be reduced. If the channel length L is 2.0 μm or less, hydrogen is likely to penetrate not only into the source region and drain region but also into the channel region, which may cause the transistor to fail to function.

[0006] An object of one embodiment of the present invention is to provide a high-definition display device. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, and the channel length of the gate electrode is 2.0 μm or less.

[0008] A display device according to one embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a silicon oxide layer provided in contact with the first silicon nitride layer, a source wiring provided on and in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the silicon oxide layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein the channel length of the gate electrode is 2.0 μm or less, and the film thickness of the silicon oxide layer is smaller than the film thickness of the first silicon nitride layer, the film thickness of the second silicon nitride layer, and the film thickness of the third silicon nitride layer.

[0009] A method for manufacturing a display device according to one embodiment of the present invention includes forming an oxide semiconductor layer including a polycrystalline structure, depositing a gate insulating layer on the oxide semiconductor layer, forming a gate electrode facing the oxide semiconductor layer on the gate insulating layer, depositing a first silicon nitride layer in contact with the gate electrode, forming a source wiring in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, depositing a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer, forming a first transparent conductive layer in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and depositing a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of a channel region overlapping with the gate electrode in the oxide semiconductor layer is 2.0 μm or less, and the deposition temperatures of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are 150° C. or more and 250° C. or less. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic plan view showing a configuration of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a circuit configuration of a display device according to an embodiment of the present invention. [Diagram 3] 1 is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Diagram 5] 1 is a plan view showing a configuration of a pixel of a display device according to an embodiment of the present invention; [Figure 6] 1 is a plan view showing a configuration of a pixel of a display device according to an embodiment of the present invention; [Figure 7] FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 8] FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 9] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 10] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 13] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 14] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 15] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 17] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 18] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Figure 19] FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 20] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 21] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 22] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Figure 23] 5A to 5C are cross-sectional views illustrating a manufacturing method of a display device according to one embodiment of the present invention. [Figure 24] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Diagram 25] FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 26] FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, film thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, the same symbols are used for configurations similar to those described above with respect to the previous figures, and detailed explanations may be omitted as appropriate.

[0012] The term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. The semiconductor device of the following embodiment may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a transistor used in a memory circuit.

[0013] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0014] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". In this way, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is different from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the stacking order in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0015] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0016] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0017] First Embodiment A display device 10 according to one embodiment of the present invention will be described with reference to FIGS.

[0018] <1. Overview of the display device> An overview of the display device 10 will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic plan view showing the configuration of the display device 10. Fig. 2 is a schematic plan view showing the circuit configuration of the display device 10. The display device 10 is, as an example, a liquid crystal display device.

[0019] 1 or 2, the display device 10 includes an array substrate 100, a seal portion 200, a counter substrate 190, a flexible printed circuit board (FPC) 300, and an IC chip 400. The array substrate 100 and the counter substrate 190 are attached together by the seal portion 200.

[0020] The display device 10 also includes a display area 122 and a peripheral area 121 surrounding the periphery of the display area 122. The peripheral area 121 includes a sealing area 124 and an outside of the sealing area 124 surrounding the sealing area 124. The outside of the sealing area 124 includes an exposed area 126.

[0021] A plurality of pixels 180 arranged in a matrix in a first direction D1 and a second direction D2 are arranged in the display region 122. The display region 122 is a region overlapping with a liquid crystal layer (not shown) containing liquid crystal molecules in a plan view.

[0022] A light shielding portion 192 overlapping with the array substrate 100 and the counter substrate 190 is disposed in the peripheral region 121. A seal portion 200 is disposed in the seal region 124. The seal region 124 is a region that overlaps with the seal portion 200 in a plan view.

[0023] The exposed area 126 is an area where the array substrate 100 is exposed from the counter substrate 190. The FPC terminal section 150 is disposed in the exposed area 126. Also disposed in the exposed area 126 are the FPC 300, the IC chip 400, and a part of the routed wiring section 115.

[0024] In the display device 10, the sealing region 124, the area outside the sealing region 124, and the exposed region 126 may be collectively referred to as a frame region.

[0025] The FPC terminal portion 150 includes a plurality of FPC terminals. The wiring portion 115 includes a plurality of data signal supply lines 116. The light shielding portion 192 overlaps with the seal portion 200, the first drive circuit 110, the second drive circuit 120, a portion of the wiring portion 115, and the common wiring 145, and has a function of hiding the seal portion 200, the first drive circuit 110, the second drive circuit 120, a portion of the wiring portion 115, the common wiring 145, etc.

[0026] A case will be described in which the shape of the array substrate 100 and the shape of the display area 122 of the display device 10 are octagonal. Note that the shapes of the array substrate 100 and the display area 122 of the display device 10 are not limited to octagonal, and may be rectangular or circular.

[0027] 2. Circuit configuration of display device 10 Next, the circuit configuration of the display device 10 will be described with reference to Fig. 2. Configurations that are the same as or similar to those in Fig. 1 will be described as necessary.

[0028] 2, the FPC terminal portion 150 connected to the FPC 300 is connected to the IC chip 400 and the second driving circuit 120 by connection wiring 141. The IC chip 400 is connected to the first driving circuit 110 using a plurality of data signal supply lines 116.

[0029] The first driving circuit 110 is provided parallel to a first direction D1 of the display region 122. The second driving circuit 120 is provided parallel to a second direction D2 of the display region 122. The first driving circuit 110 and the second driving circuit 120 overlap with a sealing region 124 (FIG. 1) in a plan view. The region where the sealing region 124 overlaps with the first driving circuit 110 and the second driving circuit 120 is an example and is not limited to the sealing region 124 shown in FIG. 1. The region where the sealing region 124 overlaps with the first driving circuit 110 and the second driving circuit 120 may be any region outside the region where the pixel circuits 182 of the multiple pixels 180 (see FIG. 3) are provided.

[0030] The first driving circuit 110 is, for example, a source driver, and includes a plurality of multiplexer circuits 111 that select a data signal. The multiplexer circuit 111 includes a plurality of analog switches (ASW) 112. The multiple ASWs 112 are electrically connected between a plurality of data signal lines 131 and a plurality of data signal supply lines 116, and each has a function of electrically connecting the corresponding data signal line 131 and data signal supply line 116. For convenience of explanation, the number of ASWs 112 in the multiplexer circuit 111 shown in FIG. 2 is two, as an example. The number of ASWs 112 included in the multiplexer circuit 111 may be more than two.

[0031] The second driving circuit 120 is, for example, a gate driver circuit. The IC chip 400 also supplies, for example, a control signal for driving the pixel circuit 182 to at least one of the first driving circuit 110 and the second driving circuit 120.

[0032] Each of the pixels 180 may correspond to, for example, sub-pixel R, sub-pixel G, and sub-pixel B. The pixel 180 is the smallest unit constituting a part of an image reproduced in the display region 122. Each of the pixels 180 is provided with one display element. In the example shown in FIG. 1, the display element is a liquid crystal element 170 (see FIG. 3). The color corresponding to the sub-pixel is determined by the characteristics of the liquid crystal element 170 or a color filter (not shown) provided in the sub-pixel. The color filter may be provided on the counter substrate 190 or on the array substrate 100.

[0033] For example, sub-pixel R may have a red color filter that emits red color, sub-pixel G may have a green color filter that emits green color, and sub-pixel B may have a blue color filter that emits blue color.

[0034] A plurality of data signal lines including a data signal line 131 extend from the first driving circuit 110 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. A plurality of scanning signal lines including a scanning signal line 129 extend from the second driving circuit 120 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0035] The common wiring 145 overlaps with the peripheral area 121, for example, and is provided inside the periphery of the peripheral area 121. A common voltage is supplied to the common wiring 145 from an external device. The common voltage may be, for example, a voltage between the voltage of the positive voltage amplitude of the data signal and the voltage of the negative voltage amplitude of the data signal, a voltage that is a reference voltage amplitude, 0V, a ground voltage, or a ground voltage. The common wiring 145 may be electrically connected to a common electrode (not shown) formed on the counter substrate 190 via a plurality of connection parts 143, or may be electrically connected to a common electrode 146 (see FIG. 3) using various wiring layers.

[0036] By connecting the FPC 300 to the FPC terminal portion 150, the display device 10 is connected to an external device (not shown) connected to the FPC 300, and signals from the external device are supplied to, for example, the IC chip 400, the first drive circuit 110, the second drive circuit 120, and each pixel 180. The display device 10 drives each pixel circuit 182 provided in the display device 10 using the signals from the external device and control signals generated by the IC chip 400, the first drive circuit 110, and the second drive circuit 120.

[0037] 3. Configuration of the pixel circuit 182 of the pixel 180 The configuration of the pixel circuit 182 will be described with reference to Fig. 3. Fig. 3 is a schematic circuit diagram showing the configuration of the pixel circuit 182 of the pixel 180 in the display device 10. Configurations that are the same as or similar to those in Figs. 1 and 2 will be described as necessary.

[0038] The pixel circuit 182 includes, for example, a transistor 160, a liquid crystal element 170, and a capacitance element 168. Details will be described later, but for example, a first electrode of the capacitance element 168 is a pixel electrode PTCO, and a second electrode of the capacitance element 168 is grounded. Like the capacitance element 168, a first electrode of the liquid crystal element 170 is a pixel electrode PTCO, and a second electrode of the liquid crystal element 170 is a common electrode CTCO. Note that the first electrode and the second electrode of the capacitance element 168 are interchangeable. The first electrode and the second electrode of the liquid crystal element 170 are interchangeable. The second electrode of the liquid crystal element 170 is the common electrode 146. Note that the second electrode of the capacitance element 168 may be the common electrode CTCO or may be the common electrode 146. The transistor 160 includes a first gate electrode 161, a first source electrode 163, and a first drain electrode 164. The first gate electrode 161 is connected to the scanning signal line 129. The first source electrode 163 is connected to the data signal line 131. The first drain electrode 164 is connected to a first electrode of the capacitance element 168 and a first electrode of the liquid crystal element 170. For convenience of explanation, in this specification and the like, the first source electrode 163 is referred to as a source electrode and the first drain electrode 164 is referred to as a drain electrode, but depending on the voltage supplied (applied) to the source electrode and the drain electrode of the transistor 160, the function of each electrode as a source and the function as a drain may be interchanged.

[0039] An arbitrary signal (voltage or current) is supplied to each pixel circuit 182 of the three sub-pixels of the display device 10, and the display device 10 can display an image. For example, the IC chip 400, the first driving circuit 110, the second driving circuit 120, and an external device can change the alignment state of the liquid crystal molecules included in the liquid crystal element 170 by supplying a current or voltage to each of the pixel electrode and the common electrode 146 included in the pixel circuit 182. As a result, the display device 10 can display an image.

[0040] 4. Configuration of the display device 10 An overview of a display device 10 according to an embodiment of the present invention will be described with reference to FIGS. 4 to 6. FIG. 4 is a cross-sectional view showing a configuration of a display device 10 according to an embodiment of the present invention. The cross-sectional view shown in FIG. 4 shows a transistor Tr2 in a peripheral region 121 and a transistor Tr1 in a pixel circuit 182, which are adjacent to each other. In reality, the pixel circuit 182 is included in the display region 122, and the peripheral circuit is included in the peripheral region 121. Therefore, it goes without saying that the pixel circuit and the peripheral circuit shown adjacent to each other in FIG. 4 are provided separately in the display device 10. In addition, the cross-sectional view shown in FIG. 4 shows the periphery of the opening of the pixel 180 and a part of a transmission region (opening region) that contributes to displaying an image. The transistor Tr2 and the transistor Tr1 are, for example, thin film transistors. Configurations that are the same as or similar to those in FIGS. 1 to 3 will be described as necessary.

[0041] 5 and 6 are plan views showing the configuration of a pixel of a display device 10 according to an embodiment of the present invention. Fig. 5 shows a layout from the light-shielding layer LS to the passivation layer PAS3, and Fig. 6 shows a layout from the passivation layer PAS3 to the common electrode CTCO.

[0042] As shown in FIG. 4, each layer included in the display device 10 is provided above the substrate SUB1 (third direction D3). The display device 10 has a transistor Tr1, a transistor Tr2, a wiring group W including a plurality of wirings, a connection electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation for transparent conductive oxide. The transistor Tr1 is a transistor included in a pixel circuit 182 of a pixel 180 of the display device 10. The transistor Tr2 is a transistor included in a peripheral circuit such as the first drive circuit 110 or the second drive circuit 120. The wiring group W includes, for example, a wiring W1, a wiring W2, and a wiring W3.

[0043] <4-1. Structure of transistor Tr1> As shown in FIG. 4, the transistor Tr1 is provided above the substrate SUB1. The transistor Tr1 includes at least an oxide semiconductor layer POS, a first gate insulating layer GI1, a gate wiring GL1 (also referred to as a gate electrode), a passivation layer PAS1, a wiring W3, a passivation layer PAS2, and a connection electrode ZTCO (also referred to as a connection electrode). The transistor Tr1 may further include a passivation layer PAS3 on the connection electrode ZTCO. The transistor Tr1 may further include a second insulating layer IL2 and a light-shielding layer LS between the oxide semiconductor layer POS and the substrate SUB1. The transistor Tr1 may further include a metal oxide layer MO1 mainly composed of aluminum provided in contact with the oxide semiconductor layer POS between the oxide semiconductor layer POS and the second insulating layer IL2. In FIG. 4, an example in which the metal oxide layer MO1 is provided under the oxide semiconductor layer POS will be described, but an embodiment of the present invention is not limited thereto, and the oxide semiconductor layer POS may be in contact with the second insulating layer IL2 (see FIG. 24).

[0044] The gate wiring GL1 faces the oxide semiconductor layer POS. The first gate insulating layer GI1 is provided between the oxide semiconductor layer POS and the gate wiring GL1. In this embodiment, a top-gate transistor in which the oxide semiconductor layer POS is provided closer to the substrate SUB1 than the gate wiring GL1 is illustrated as the transistor Tr1, but a bottom-gate transistor in which the positional relationship between the gate wiring GL1 and the oxide semiconductor layer POS is reversed may also be used. Note that the configuration from the substrate SUB1 to the passivation layer PAS3 may be referred to as a semiconductor device.

[0045] The oxide semiconductor layer POS has a polycrystalline structure including a plurality of crystal grains. Although the details will be described later, the oxide semiconductor layer POS having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. Hereinafter, an oxide semiconductor having a polycrystalline structure may be referred to as a Poly-OS.

[0046] As will be described in detail later, the oxide semiconductor layer POS contains two or more metal elements including indium, and the ratio of indium in the two or more metal elements is 50% or more. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides are used. However, the oxide semiconductor layer POS only needs to contain Poly-OS, and may contain metal elements other than the above.

[0047] The oxide semiconductor layer POS includes a channel region OS1 and a low-resistance region OS2. The channel region OS1 is an oxide semiconductor layer in a region overlapping with the gate wiring GL1 in a planar view. The channel region OS1 is switched between a conductive state and a non-conductive state depending on a voltage supplied to the gate wiring GL1. The low-resistance region OS2 is a region having a lower resistance than the channel region OS1. The low-resistance region OS2 functions as a source region or a drain region. For example, the low-resistance region OS2 is made low-resistance by ion-implanting an impurity into the oxide semiconductor layer POS.

[0048] As shown in FIG. 5, the gate wiring GL1 is arranged along the first direction D1. A region of the gate wiring GL1 that overlaps with the oxide semiconductor layer POS is called a gate electrode. The oxide semiconductor layer POS is arranged to intersect with the gate wiring GL1. A region of the oxide semiconductor layer POS that overlaps with the gate wiring GL1 is a channel region OS1. In FIG. 5, in the channel region OS1, the width (length in the second direction D2) of the gate wiring GL1 corresponds to the channel length L. In the channel region OS1, the oxide semiconductor layer POS (length in the first direction D1) corresponds to the channel width W. In this embodiment, the width (channel length L) of the gate wiring GL1 is 2.0 μm or less, preferably 1.5 μm or less.

[0049] A first gate insulating layer GI1 is provided on the oxide semiconductor layer POS. A passivation layer PAS1 is provided on the first gate insulating layer GI1. A wiring W3 is provided on the passivation layer PAS1. As shown in FIG. 5, in a plan view, the wiring W3 is arranged along the second direction D2 and functions as a source wiring. The wiring W3 is connected to the low resistance region OS2 through an opening SCON1 provided in the first gate insulating layer GI1 and the passivation layer PAS1. A passivation layer PAS2 is provided on the passivation layer PAS1 and the wiring W3. A connection electrode ZTCO is provided on the passivation layer PAS2. The connection electrode ZTCO is connected to the low resistance region OS2 through an opening ZCON provided in the first gate insulating layer GI1 and the passivation layers PAS1 and PAS2. The connection electrode ZTCO is in contact with the low resistance region OS2 at the bottom of the opening ZCON. The region where the connection electrode ZTCO and the low resistance region OS2 are in contact is called a contact region CON1.

[0050] A second insulating layer IL2 and a light-shielding layer LS are provided between the oxide semiconductor layer POS and the substrate SUB1. As shown in FIG. 5, in a plan view, the light-shielding layer LS is disposed along the first direction D1 and is provided in a region overlapping with the gate wiring GL1. The light-shielding layer LS is also provided so as to intersect with the oxide semiconductor layer POS. That is, in a plan view, the light-shielding layer LS is provided in a region overlapping with the channel region OS1. The light-shielding layer LS prevents light incident from the substrate SUB1 side from reaching the channel region OS1. When a conductive layer is used as the light-shielding layer LS, a voltage may be applied to the light-shielding layer LS to control the channel region OS1. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate wiring GL1 may be electrically connected. In a plan view, the contact region CON1 is provided in a region not overlapping with the light-shielding layer LS.

[0051] When a high light transmittance is required for the display device 10, one of the source electrode and the drain electrode may be formed from a metal conductive layer, and the other may be formed from a transparent conductive layer. For example, if a transparent conductive layer such as ITO is formed in contact with a silicon layer, the surface of the silicon layer is oxidized by process gases and oxygen ions during the ITO film formation. Since the oxide layer formed on the surface of the silicon layer has high resistance, the contact resistance between the silicon layer and the transparent conductive layer increases. As a result, poor electrical contact occurs between the silicon layer and the transparent conductive layer. On the other hand, even if the transparent conductive layer is formed in contact with the oxide semiconductor layer, the high resistance oxide layer as described above is not formed on the surface of the oxide semiconductor layer. Therefore, poor electrical contact does not occur between the oxide semiconductor layer and the transparent conductive layer.

[0052] To realize a high-definition display device 10, it is necessary that the width (channel length L) of the gate electrode of a transistor using an oxide semiconductor layer is 2 μm or less. Considering the variation in the width of the gate electrode caused by the photolithography process and etching in the manufacturing process of the display device 10, it is necessary to make it possible to operate the transistor even with a width of 1.5 μm or less.

[0053] It is known that oxygen defects occur in oxide semiconductors due to processing damage such as etching. When hydrogen is trapped in the oxygen defects, the resistance of the oxide semiconductor is reduced, allowing it to function as a conductor. On the other hand, by supplying oxygen to the oxygen defects to increase the resistance of the oxide semiconductor, it is possible to allow it to function as a semiconductor. That is, in order to operate satisfactorily as a transistor, it is preferable to increase the resistance of the oxide semiconductor in the channel region by supplying oxygen to the oxygen defects, and to decrease the resistance of the oxide semiconductor in the source or drain region by supplying hydrogen to the oxygen defects.

[0054] The characteristics of a transistor using an oxide semiconductor are significantly affected by hydrogen and oxygen contained in an insulating film provided around the oxide semiconductor. When oxygen is excessively supplied to the oxide semiconductor, a defect level different from oxygen defects is formed by the excess oxygen, which reduces the reliability of the transistor and reduces the field-effect mobility. Furthermore, when hydrogen is excessively supplied to the oxide semiconductor and reaches the channel region, the transistor is depressed and does not operate.

[0055] Therefore, in order to miniaturize a transistor using an oxide semiconductor, it is necessary to appropriately supply oxygen and hydrogen to the channel region OS1 having a channel length of 2.0 μm or less and the low-resistance region OS2.

[0056] In one embodiment of the present invention, hydrogen is appropriately supplied to the oxide semiconductor layer POS, thereby reducing the resistance of the low-resistance region OS2 functioning as a source region and a drain region and suppressing the diffusion of hydrogen into the channel region OS1.

[0057] In this embodiment, silicon nitride layers are used as the passivation layers PAS1 to PAS3. Silicon nitride layers contain more hydrogen than silicon oxide. Hydrogen contained in silicon nitride layers diffuses when heat exceeding 250°C is applied. Therefore, silicon nitride layers are formed as the passivation layers PAS1 to PAS3 at a temperature of 150°C to 250°C. This makes it possible to prevent a large amount of hydrogen contained in the silicon nitride layers from diffusing, and to prevent excessive hydrogen from being supplied to the low resistance region OS2. This makes it possible to prevent the transistor Tr1 from being depressed. The configuration of the passivation layers PAS1 to PAS3 will be described in detail later.

[0058] <4-2. Structure of transistor Tr2> The transistor Tr2 has a p-type transistor Tr2-1 and an n-type transistor Tr2-2. When the transistor Tr2 is not distinguished, the transistor included in the peripheral region 121 is expressed as the transistor Tr2. When the transistor Tr2 is distinguished, the transistor Tr2 is expressed as a p-type transistor Tr2-1, an n-type transistor Tr2-2, etc.

[0059] Both the p-type transistor Tr2-1 and the n-type transistor Tr2-2 have a gate electrode GL2, a second gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 faces the semiconductor layer S. The second gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. As an example, the transistor Tr2 of the display device 10 is a top-gate transistor in which the gate electrode GL2 is provided above the semiconductor layer S. The transistor Tr2 may be a bottom-gate transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed.

[0060] The first insulating layer IL1 is provided on the substrate SUB1. The first insulating layer IL1 functions as a base layer. By providing the first insulating layer IL1, it is possible to prevent impurities from the substrate SUB1 from penetrating into the semiconductor layer S.

[0061] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a semiconductor in a region that overlaps with the gate electrode GL2 in a planar view. The semiconductor layer S1 functions as a channel region of the transistor Tr2-1. The semiconductor layer S2 functions as a conductor. The semiconductor layer S3 functions as a conductor having a higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers that invade toward the semiconductor layer S1.

[0062] A second insulating layer IL2 and a first gate insulating layer GI1 are provided on the gate electrode GL2. A wiring W2 is provided on these insulating layers. The wiring W2 functions as a source electrode and a drain electrode of the transistor Tr2. The wiring W2 is connected to the semiconductor layer S through an opening SCON2 provided in the second insulating layer IL2, the first gate insulating layer GI1, and the second gate insulating layer GI2. The wiring W2 is also connected to the wiring W1 through an opening WC1 provided in the second insulating layer IL2 and the first gate insulating layer GI1. A passivation layer PAS1 is provided on the wiring W2. A wiring W3 is provided on the passivation layer PAS1. The wiring W3 is connected to the wiring W2 through an opening WC2 provided in the passivation layer PAS1.

[0063] The gate electrode GL2 is formed in the same layer as the wiring W1 and the light-shielding layer LS. The wiring W2 is formed in the same layer as the gate wiring GL1. The term "same layer" means that a single layer is patterned to form a plurality of components.

[0064] <4-3. Other configurations of the display device> Next, the layer structure provided on the transistors Tr1 and Tr2 will be described. In the display region 122, a color filter CF is provided on the passivation layer PAS3. By providing the color filter CF on the substrate SUB1 side, it is possible to suppress misalignment between the color filter CF and the pixel circuit. In addition, a third insulating layer IL3 is provided on the color filter CF and the passivation layer PAS3. Since the color filter CF is not provided in the peripheral region 121, the third insulating layer IL3 is provided on the passivation layer PAS3. The third insulating layer IL3 functions as a planarization film.

[0065] In the display region 122, a pixel electrode PTCO is provided on the third insulating layer IL3. The pixel electrode PTCO is connected to the connection electrode ZTCO through an opening PCON provided in the third insulating layer IL3. As shown in Figures 5 and 6, the pixel electrode PTCO overlaps with the gate line GL1, the oxide semiconductor layer POS, and the connection electrode ZTCO between two adjacent lines W3. The pixel electrode PTCO contacts the connection electrode ZTCO at the opening PCON that overlaps with the gate line GL1.

[0066] A fourth insulating layer IL4 is provided in the display region 122 and the peripheral region 121. In the display region 122, the fourth insulating layer IL4 is provided so as to cover the pixel electrode PTCO and the third insulating layer IL3. In the peripheral region 121, the fourth insulating layer IL4 is provided on the third insulating layer IL3. In addition, at the end of the peripheral region 121 (the end of the substrate SUB1), the fourth insulating layer IL4 is in contact with the third insulating layer IL3. This makes it possible to seal in moisture contained in the third insulating layer IL3.

[0067] In the display area 122, a common auxiliary electrode CMTL and a common electrode CTCO are provided on the fourth insulating layer IL4. As shown in FIG. 6, the common auxiliary electrode CMTL and the common electrode CTCO are arranged in a lattice pattern so as to overlap the gate wiring GL and the wiring W3. That is, the common auxiliary electrode CMTL is provided in common for a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is provided so as to expose the pixel electrode PTCO. The pattern of the opening OP is provided inside the pattern of the pixel electrode PTCO. Note that the region where the opening OP is provided corresponds to the opening of the pixel. That is, the opening ZCON (first contact region CON1) is included in the opening of the pixel. Note that the opening of the pixel means a region where the user can see the light from the pixel. For example, a region that is shielded by a metal layer and where the user cannot see the light is not included in the opening of the pixel. That is, the opening of the pixel may be called a "light-transmitting region". Also, a region extending along the D1 direction of the common auxiliary electrode CMTL overlaps with the opening PCON. In the display region 122, the common auxiliary electrode CMTL also functions as a black matrix. The common auxiliary electrode CMTL and the common electrode CTCO are also provided in the opening PCON. In FIG. 4, a case where the common electrode CTCO is provided on the common auxiliary electrode CMTL is described, but the common auxiliary electrode CMTL may be disposed on the common electrode CTCO. Here, as shown in FIG. 4, the pixel electrode PTCO overlaps with the common electrode CTCO via a fourth insulating layer IL4. The area where the pixel electrode PTCO overlaps with the common electrode CTCO via the fourth insulating layer IL4 functions as a storage capacitor.

[0068] A spacer SP is provided on the common electrode CTCO so as to fill the opening PCON. The spacer SP protrudes toward the counter substrate SUB2. The spacer SP of the liquid crystal layer LC is provided not only in the display region 122 but also in the peripheral region 121 by the spacer SP. In the display region 122 and the peripheral region 121, an alignment film OF1 is provided on the third insulating layer IL3, the common electrode CTCO, and the spacer SP.

[0069] In the peripheral region 121, a black matrix BM is provided on the counter substrate SUB2. An overcoat layer OC is provided in the peripheral region 121 and the display region 122. An alignment film OF2 is provided so as to cover the overcoat layer OC. The substrate SUB1 and the counter substrate SUB2 are disposed so that the alignment films OF1 and OF2 face each other, and are bonded together by a seal portion 200 provided in the peripheral region 121. A liquid crystal layer LC is provided in the region surrounded by the seal portion 200.

[0070] 5. Method for manufacturing the display device 10 A method for manufacturing the display device 10 according to one embodiment of the present invention will be described. Fig. 7 and Fig. 8 are sequence diagrams for explaining the method for manufacturing the display device 10 according to one embodiment of the present invention. Fig. 9 to Fig. 17 are cross-sectional views for explaining the method for manufacturing the display device 10 according to one embodiment of the present invention.

[0071] First, a first insulating layer IL1, a semiconductor layer S, and a second gate insulating layer GI2 are formed on a substrate SUB1 (see step S1001 shown in FIG. 7 and FIG. 9).

[0072] As the substrate SUB1, a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used. When the substrate SUB1 needs to be flexible, a substrate containing an organic resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used as the substrate SUB1. When a substrate containing an organic resin is used as the substrate SUB1, an impurity element may be introduced into the organic resin in order to improve the heat resistance of the substrate SUB1.

[0073] The first insulating layer IL1 is formed by a chemical vapor deposition (CVD) method or a sputtering method. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x Oy ) and other inorganic insulating materials are used. x N y is a silicon compound that contains a smaller ratio (x>y) of nitrogen (N) than oxygen (O). SiN x O y is a silicon compound containing oxygen at a ratio (x>y) smaller than that of nitrogen. The first insulating layer IL1 may have a single layer structure using the above inorganic insulating material, or may have a multilayer structure.

[0074] Moreover, polysilicon is used as the semiconductor layer S. Moreover, the second gate insulating layer GI2 is formed by the same film formation method and using the same inorganic insulating material as the first insulating layer IL1.

[0075] Next, a light-shielding layer LS is formed on the gate insulating layer GI2 (see step S1002 shown in FIG. 7 and FIG. 9).

[0076] The light-shielding layer LS is formed by processing a conductive layer formed by, for example, a sputtering method. A general metal material is used as the light-shielding layer LS. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as the light-shielding layer LS. The light-shielding layer LS may have a single-layer structure using the above-mentioned materials, or may have a multilayer structure.

[0077] Next, the second insulating layer IL2 is formed on the light-shielding layer LS (see step S1003 shown in FIG. 7 and FIG. 9). The second insulating layer IL2 is formed by the same film formation method and using the same inorganic insulating material as the first insulating layer IL1.

[0078] The second insulating layer IL2 may have a single-layer structure using the inorganic insulating material described above, or may have a laminated structure. When the second insulating layer IL2 has a laminated structure, it is preferable that the insulating material containing nitrogen and the insulating material containing oxygen are formed in this order from the substrate SUB1. By using the insulating material containing nitrogen, for example, it is possible to block impurities diffusing from the substrate SUB1 side toward the oxide semiconductor layer POS. By using the insulating material containing oxygen, it is possible to release oxygen by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the insulating material containing oxygen releases oxygen at a heat treatment temperature performed in the manufacturing process of the display device when a glass substrate is used as the substrate SUB1. In this embodiment, for example, silicon nitride is formed as the insulating material containing nitrogen. For example, silicon oxide is formed as the insulating material containing oxygen.

[0079] Next, a metal oxide layer MO1 containing aluminum as a main component is formed on the second insulating layer IL2 (see step S1004 shown in FIG. 7 and FIG. 10).

[0080] The metal oxide layer MO1 is formed by a sputtering method. The metal oxide layer MO1 mainly composed of aluminum is, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) and other inorganic insulating materials are used. x N y is an aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). AlN x O y is an aluminum compound that contains a smaller proportion of oxygen than nitrogen (x>y).

[0081] "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer MO1 is 1% or more of the entire metal oxide layer MO1. The ratio of aluminum contained in the metal oxide layer MO1 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer MO1. The above ratio may be a mass ratio or a weight ratio.

[0082] The thickness of the metal oxide layer MO1 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, aluminum oxide is used as the metal oxide layer MO1. Aluminum oxide has high gas barrier properties.

[0083] Next, an amorphous oxide semiconductor layer AOS is formed on the metal oxide layer MO1 (see step S1005 shown in FIG. 7 and FIG. 10).

[0084] The oxide semiconductor layer AOS is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor layer AOS is, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0085] A metal oxide having semiconductor properties can be used as the oxide semiconductor layer AOS. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer AOS. The ratio of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid is used as the oxide semiconductor layer AOS. An element other than the above may be used as the oxide semiconductor layer AOS. In this embodiment, a metal oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer AOS.

[0086] When the oxide semiconductor layer AOS is crystallized by an OS annealing process described later, the oxide semiconductor layer AOS after deposition and before the OS annealing process is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the oxide semiconductor layer AOS is preferably deposited under conditions that prevent the oxide semiconductor layer AOS from crystallizing as much as possible immediately after deposition. For example, when the oxide semiconductor layer AOS is deposited by a sputtering method, the oxide semiconductor layer AOS is deposited while controlling the temperature of the deposition target (the substrate SUB1 and the structure formed thereon).

[0087] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object rises with the film formation process. If the temperature of the target object rises during the film formation process, the oxide semiconductor layer AOS contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing process is inhibited. In order to control the temperature of the target object as described above, for example, the target object may be cooled while the film is formed. For example, the target object may be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer AOS while cooling the target object, the oxide semiconductor layer AOS having a small amount of crystalline components immediately after the film formation can be formed.

[0088] Next, a pattern of the oxide semiconductor layer AOS is formed (see step S1006 shown in FIG. 7). Although not shown, a resist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the resist mask. For etching the oxide semiconductor layer AOS, wet etching or dry etching may be used. For wet etching, etching may be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid may be used as the etchant.

[0089] It is preferable that the oxide semiconductor layer AOS is patterned before the OS annealing treatment. If the oxide semiconductor layer AOS is crystallized by the OS annealing treatment, it tends to be difficult to etch. In addition, even if the oxide semiconductor layer AOS is damaged by etching, the damage can be repaired by the OS annealing treatment, which is preferable.

[0090] After the patterning of the oxide semiconductor layer AOS, a heat treatment (OS annealing treatment) is performed on the oxide semiconductor layer AOS (see step S1007 shown in FIG. 7 and FIG. 11). In the OS annealing treatment, the oxide semiconductor layer AOS is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. By performing the OS annealing treatment, the oxide semiconductor layer AOS is crystallized, and an oxide semiconductor layer POS having a polycrystalline structure is formed.

[0091] Next, a pattern of the metal oxide layer MO1 is formed using the oxide semiconductor layer POS as a mask (see step S1008 shown in FIG. 7 and FIG. 12). The metal oxide layer MO1 is etched using the crystallized oxide semiconductor layer POS as a mask. The metal oxide layer MO1 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching. The crystallized oxide semiconductor layer POS has etching resistance to diluted hydrofluoric acid compared to the amorphous oxide semiconductor layer AOS. Therefore, the metal oxide layer MO1 can be etched using the oxide semiconductor layer POS as a mask. This makes it possible to omit a photolithography process.

[0092] Next, a first gate insulating layer GI1 is formed on the oxide semiconductor layer POS (see step S1009 shown in FIG. 7 and FIG. 13).

[0093] For the method of forming the first gate insulating layer GI1 and the insulating material, see the description of the second insulating layer IL2. The thickness of the first gate insulating layer GI1 is, for example, 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.

[0094] It is preferable to use an insulating material containing oxygen as the first gate insulating layer GI1. It is also preferable to use an insulating layer with few defects as the first gate insulating layer GI1. For example, when the oxygen composition ratio in the first gate insulating layer GI1 is compared with the oxygen composition ratio in an insulating layer having the same composition as the second gate insulating layer GI2 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the first gate insulating layer GI1 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x ) is used, the composition ratio of oxygen in the silicon oxide used as the first gate insulating layer GI1 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the second gate insulating layer GI2. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the first gate insulating layer GI1.

[0095] In order to form an insulating layer with few defects as the first gate insulating layer GI1, the first gate insulating layer GI1 may be formed at a film formation temperature of 350° C. or higher. In addition, after the first gate insulating layer GI1 is formed, a process of implanting oxygen into a part of the first gate insulating layer GI1 may be performed. In this embodiment, in order to form an insulating layer with few defects as the first gate insulating layer GI1, silicon oxide is formed at a film formation temperature of 350° C. or higher.

[0096] Next, a metal oxide layer MO2 containing aluminum as a main component is formed on the first gate insulating layer GI1 (see step S1010 shown in FIG. 7 and FIG. 13).

[0097] The description of the metal oxide layer MO1 may be referred to for the deposition method and insulating material of the metal oxide layer MO2. Oxygen is implanted into the first gate insulating layer GI1 by deposition of the metal oxide layer MO2. The film thickness of the metal oxide layer MO2 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer MO2. Aluminum oxide has high barrier properties against gas. In this embodiment, the aluminum oxide used as the metal oxide layer MO2 suppresses outward diffusion of oxygen implanted into the first gate insulating layer GI1 during deposition of the metal oxide layer MO2.

[0098] For example, when the metal oxide layer MO2 is formed by sputtering, the process gas used in the sputtering remains in the film of the first gate insulating layer GI1. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the first gate insulating layer GI1. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the first gate insulating layer GI1.

[0099] A first gate insulating layer GI1 is formed on the oxide semiconductor layer POS, and a metal oxide layer MO2 is formed on the first gate insulating layer GI1. In this state, a heat treatment (oxidation annealing treatment) is performed to supply oxygen to the oxide semiconductor layer POS (see step S1011 shown in FIG. 7).

[0100] During the process from when the oxide semiconductor layer POS is formed until the first gate insulating layer GI1 is formed on the oxide semiconductor layer POS, many oxygen defects are generated on the upper surface and side surface of the oxide semiconductor layer POS. Therefore, the number of oxygen defects formed near the upper surface of the oxide semiconductor layer POS is greater than the number of oxygen defects formed near the lower surface of the oxide semiconductor layer POS. In other words, the oxygen defects in the oxide semiconductor layer POS are not uniformly present in the thickness direction of the oxide semiconductor layer POS, but are non-uniformly distributed in the thickness direction of the oxide semiconductor layer POS. Specifically, the number of oxygen defects in the oxide semiconductor layer POS is fewer on the lower surface side of the oxide semiconductor layer POS and more on the upper surface side of the oxide semiconductor layer POS.

[0101] When a uniform oxygen supply process is performed on the oxide semiconductor layer POS having the above-mentioned oxygen defect distribution, if an amount of oxygen required to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer POS is supplied, an excess of oxygen is supplied to the lower surface side of the oxide semiconductor layer POS. As a result, a defect level different from the oxygen defects is formed on the lower surface side due to the excess oxygen. As a result, phenomena such as characteristic fluctuation in reliability tests or a decrease in field-effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layer POS while suppressing the supply of oxygen to the lower surface side of the oxide semiconductor layer POS.

[0102] Oxidation annealing is performed in a state where a metal oxide layer MO1 is provided under the oxide semiconductor layer POS and a metal oxide layer MO2 is provided on the oxide semiconductor layer POS. In this manner, oxygen implanted into the first gate insulating layer GI1 in the above-mentioned oxidation annealing process is blocked by the metal oxide layer MO2, and is therefore prevented from being released into the atmosphere. In addition, oxygen released from the second insulating layer IL2 is supplied to the upper and side surfaces of the oxide semiconductor layer POS. In addition, the metal oxide layer MO1 can prevent excessive oxygen from being supplied below the oxide semiconductor layer POS. This allows the oxygen to be efficiently supplied to the oxide semiconductor layer POS, and oxygen defects can be repaired.

[0103] Next, after the oxidation annealing treatment, the metal oxide layer MO2 is etched (removed) (see step S1012 shown in FIG. 7 and FIG. 14). For etching the metal oxide layer MO2, wet etching or dry etching may be used. For example, diluted hydrofluoric acid (DHF) is used for wet etching. By this etching, the metal oxide layer MO2 formed on the entire surface is removed. In other words, the metal oxide layer MO2 is removed without using a mask. In further other words, by this etching, all the metal oxide layer MO2 in the region overlapping with the oxide semiconductor layer POS formed in a certain pattern is removed, at least in a plan view.

[0104] Next, the gate line GL1 is formed on the first gate insulating layer GI1 (see step S1013 shown in FIG. 7 and FIG. 15). For the film formation method and conductive material of the gate line GL, refer to the description of the light-shielding layer LS.

[0105] Next, impurities are added to the oxide semiconductor layer POS using the gate line GL1 as a mask (see step S1014 shown in FIG. 7 and FIG. 15). In this embodiment, the case where the impurities are added by ion implantation will be described, but the addition may be performed by ion doping.

[0106] Specifically, impurity elements are added to the oxide semiconductor layer POS by ion implantation through the first gate insulating layer GI1, forming a low resistance region OS2. A region of the oxide semiconductor layer POS that overlaps with the gate wiring GL1 becomes a channel region OS1. For example, argon (Ar), phosphorus (P), or boron (B) may be used as the impurity element. When boron (B) is added by ion implantation, the acceleration energy is set to 20 keV to 40 keV, and the amount of boron (B) implanted is set to 1×10 14 cm -2 More than 1×10 16 cm -2 The following would suffice.

[0107] The concentration of impurity elements contained in the low-resistance region OS2 is 1×10 18 cm -3 More than 1×10 21 cm -3 It is preferable that the low resistance region OS2 is 1×10 18 cm -3 More than 1×10 21 cm -3 If the following is present, it is presumed that impurity elements have been intentionally added by ion implantation or doping.

[0108] By ion-implanting an impurity element into the oxide semiconductor layer POS, oxygen defects are formed in the low-resistance region OS2, and defects are also formed in the metal oxide layer MO1 and the second insulating layer IL2 provided under the low-resistance region OS2. In a subsequent process, hydrogen is supplied to the oxygen defects, thereby further reducing the resistance of the low-resistance region OS2. For example, a silicon nitride layer is used as a passivation layer to supply hydrogen to the oxygen defects. Since the silicon nitride layer contains a large amount of hydrogen during film formation, the resistance of the low-resistance region OS2 can be further reduced by trapping the hydrogen contained in the silicon nitride layer in the oxygen defects in the low-resistance region OS2. In addition, by trapping hydrogen in the defects formed by ion implantation in the metal oxide layer MO1 and the second insulating layer IL2, it is possible to suppress the supply of hydrogen to the channel region OS1 more than necessary. However, if a large amount of hydrogen is diffused during the film formation of the silicon nitride layer, the oxygen defects in the low-resistance region OS2 and the defects in the metal oxide layer MO1 and the second insulating layer IL2 cannot trap all the hydrogen. If too much hydrogen is supplied to the oxygen vacancies in the low-resistance region OS2, hydrogen is supplied from the low-resistance region OS2 to the channel region OS1, causing the transistor to enter depletion.

[0109] In order to prevent excessive hydrogen from being supplied to the low resistance region OS2, silicon oxide can be used in combination as a passivation layer, but when forming the silicon oxide film, deposition waste (particles) may be generated by the reaction gas. It is difficult to remove the deposition waste, and it becomes an obstacle to the subsequent manufacturing process, so it is not very desirable to use a thick silicon oxide as a passivation layer.

[0110] Therefore, in this embodiment, silicon nitride layers are used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1, and the silicon nitride layers are deposited at a temperature of 150° C. to 250° C. This prevents a large amount of hydrogen from diffusing during deposition of the silicon nitride layer, and prevents excessive hydrogen from being supplied to the low resistance region OS2. As a result, it is possible to prevent the transistor Tr1 from becoming depressed. Hereinafter, a method for depositing the passivation layers PAS1 to PAS3 will be described in detail.

[0111] Next, a passivation layer PAS1 is formed on the first gate insulating layer GI1 and the gate wiring GL1 (see step S1015 shown in FIG. 8 and FIG. 16). The passivation layer PAS1 is formed using a silicon nitride layer. The thickness of the passivation layer PAS1 is 200 nm or more and 600 nm or less. In addition, the thickness of the passivation layer PAS1 is preferably thicker than the thicknesses of the passivation layers PAS2 and PAS3. This makes it possible to reduce the parasitic capacitance generated in the wiring W3. The raw material gas used for forming the silicon nitride layer contains a large amount of hydrogen. Therefore, if the film formation temperature exceeds 250° C., hydrogen diffuses and penetrates into the oxide semiconductor layer POS. Therefore, when a silicon nitride layer is formed as the passivation layer PAS1, it is preferable to form the film at a film formation temperature of 150° C. or more and 250° C. or less.

[0112] Next, an opening SCON1 is formed in the passivation layer PAS1 so as to reach the low-resistance region OS2. After that, a wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low-resistance region OS2 through the opening SCON1 (see step S1016 shown in FIG. 8 and FIG. 16). For the film formation method and conductive material of the wiring W3, refer to the description of the light-shielding layer LS. The film formation temperature of the wiring W3 is preferably a temperature that does not exceed the film formation temperature of the passivation layer PAS1. This is because, if the film is formed at a temperature that greatly exceeds the film formation temperature of the wiring W3, hydrogen is released from the passivation layer PAS1 and diffuses into the channel region OS1. In this way, the film formation temperature of the wiring, electrodes, and insulating layers formed on the passivation layer PAS1 is preferably not higher than the film formation temperature of the passivation layer PAS1.

[0113] Next, a passivation layer PAS2 is formed on the passivation layer PAS1 and the wiring W3 (see step S1017 shown in FIG. 8 and FIG. 16). The passivation layer PAS2 is formed using a silicon nitride layer. The thickness of the passivation layer PAS2 is 50 nm or more and 350 nm or less. As with the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS2 is preferably formed at a film formation temperature of 150° C. or more and 250° C. or less. This makes it possible to suppress the diffusion of hydrogen contained in the source gas during the formation of the passivation layer PAS2, and also to suppress the diffusion of hydrogen contained in the silicon nitride layer of the passivation layer PAS1.

[0114] Next, an opening ZCON is formed in the passivation layer PAS2 so as to reach the low resistance region OS2. After that, a connection electrode ZTCO is formed on the passivation layer PAS2, and the connection electrode ZTCO is connected to the low resistance region OS2 through the opening ZCON (see step S1018 shown in FIG. 8 and FIG. 16).

[0115] The connection electrode ZTCO is formed by processing a transparent oxide conductive layer formed by a sputtering method. A transparent conductive material such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used as the connection electrode ZTCO. A transparent conductive material other than the above may also be used as the connection electrode ZTCO.

[0116] Next, a passivation layer PAS3 is formed using a silicon nitride layer on and in contact with the connection electrode ZTCO (see step S1019 shown in FIG. 8 and FIG. 17). The passivation layer PAS3 is formed using a silicon nitride layer. The thickness of the passivation layer PAS3 is 50 nm or more and 300 nm or less. As with the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS3 is preferably formed at a film formation temperature of 150° C. or more and 250° C. or less. This makes it possible to suppress the diffusion of hydrogen contained in the source gas during the formation of the passivation layer PAS3, and also to suppress the diffusion of hydrogen contained in the silicon nitride layers of the passivation layers PAS1 and PAS2.

[0117] In addition, by forming the silicon nitride layer as the passivation layer PAS3 at 150°C or more and 250°C or less, it is possible to suppress the reduction of the connection electrode ZTCO during the film formation. This makes it possible to suppress the occurrence of irregularities on the surface of the connection electrode ZTCO. It is possible to suppress short circuits of the connection electrode ZTCO and a decrease in light transmittance caused by the irregularities occurring on the surface of the connection electrode ZTCO.

[0118] As described above, in this embodiment, silicon nitride layers are used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1, and the film formation temperature of the silicon nitride layers is set to 150° C. or more and 250° C. or less. This makes it possible to suppress excessive diffusion of hydrogen during the film formation of the passivation layers PAS1 to PAS3, and therefore hydrogen can be appropriately supplied to the low resistance region OS2. In addition, since silicon oxide is not used as the passivation layers PAS1 to PAS3, the influence of film formation dust can be reduced. In addition, since the passivation layers PAS1 to PAS3 are formed only with silicon nitride layers, the mutual adhesion of the passivation layers PAS1 to PAS3 can be improved. Furthermore, by forming the silicon nitride layers as the passivation layers PAS1 to PAS3 at 150° C. or more and 250° C. or less, the generation of compressive stress in the silicon nitride layers can be suppressed. This makes it possible to suppress peeling of the silicon nitride layers and the connection electrodes ZTCO, and warping of the substrate SUB1.

[0119] Next, color filters CF are formed on the passivation layer PAS3 (see step S1020 in FIG. 8 and FIG. 4). In this embodiment, the color filters CF have red, green, and blue colors. The color filters CF of each color are arranged along the second direction D2.

[0120] Next, a third insulating layer IL3 is formed on the color filter CF (see step S1021 shown in FIG. 8 and FIG. 4). The third insulating layer IL3 is formed using an organic resin material. By forming the third insulating layer IL3 on the color filter CF, it is possible to reduce unevenness caused by the color filter CF and the transistor Tr1 formed thereunder.

[0121] In a high-definition display device, since it is difficult to align the color filter formed on the counter substrate with the pixel circuit of the array substrate, it is preferable to provide the color filter on the array substrate side. Also, in order to flatten the surface on which the liquid crystal is driven, a planarization film is provided on the color filter. The color filter and the planarization film are made of an organic insulating material, but the organic insulating material contains a large amount of moisture. If this large amount of moisture penetrates into the oxide semiconductor layer, it will have a significant effect on the operation of the transistor, so it is necessary to suppress the moisture from penetrating into the oxide semiconductor layer.

[0122] In this embodiment, the passivation layers PAS1 to PAS3 are silicon nitride layers formed at a temperature of 150° C. to 250° C. The silicon nitride layers can prevent moisture contained in the color filter CF and the third insulating layer IL3 from penetrating into the oxide semiconductor layer POS.

[0123] Next, an opening PCON is formed in the third insulating layer IL3 and the color filter CF, reaching the connection electrode ZTCO. After that, a pixel electrode PTCO is formed on the third insulating layer IL3, and the pixel electrode PTCO is connected to the connection electrode ZTCO through the opening PCON (see step S1022 shown in FIG. 8 and FIG. 4). The pixel electrode PTCO is formed using the inorganic insulating material and film formation method described for the connection electrode ZTCO.

[0124] Next, a fourth insulating layer IL4 is deposited on the third insulating layer IL3 and the pixel electrode PTCO (see step S1023 shown in FIG. 8 and FIG. 4). The fourth insulating layer IL4 is deposited using the inorganic insulating material and deposition method described for the first insulating layer IL1. Since the fourth insulating layer IL4 functions as the capacitance of the capacitive element 168, it is preferable that the fourth insulating layer IL4 is deposited using, for example, a silicon nitride layer.

[0125] Next, the common auxiliary electrode CMTL is formed on the fourth insulating layer IL4 (see step S1024 shown in FIG. 8 and FIG. 4). For the film formation method and conductive material of the common auxiliary electrode CMTL, refer to the description of the light-shielding layer LS. After forming a conductive film on the fourth insulating layer IL4, the conductive film is processed so as to cover the gate wiring GL1 and the wiring W3, thereby forming the common auxiliary electrode CMTL arranged in a lattice pattern.

[0126] Next, a common electrode CTCO is formed on the common auxiliary electrode CMTL (see step S1025 shown in FIG. 8 and FIG. 4). For the film formation method and transparent conductive material of the common electrode CTCO, refer to the description of the connection electrode ZTCO. After forming a transparent conductive film on the fourth insulating layer IL4 and the common auxiliary electrode CMTL, the transparent conductive film is processed so as to overlap with the common auxiliary electrode CMTL, thereby forming the common electrode CTCO arranged in a lattice shape. The common electrode CTCO and the common auxiliary electrode CMTL function as a common wiring. The common electrode CTCO has high resistance because it is formed of a transparent conductive material, but the resistance can be reduced by providing the common auxiliary electrode CMTL in contact with it. In addition, the common auxiliary electrode CMTL has a light-shielding property, and therefore also functions as a black matrix.

[0127] Next, spacers SP are formed in the openings PCON (see step S1026 shown in FIG. 8 and FIG. 4). The spacers SP are formed using organic resin so that the organic resin protrudes from the substrate surface. Spacers SP do not have to be formed in all openings PCON. If spacers SP are not formed, the openings PCON are simply filled with organic resin, and the organic resin does not have to protrude from the surface.

[0128] Next, an alignment film OF1 is formed on the substrate SUB1, a sealant 200 is applied so as to surround the display region 122, and liquid crystal is dropped on it. An opposing substrate SUB2 on which a black matrix BM and the like are formed is bonded to the substrate SUB1 so as to face each other, and the sealant 200 is cured. Through the above steps, the display device 10 can be manufactured.

[0129] In this embodiment, silicon nitride layers are used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1. Therefore, the passivation layer PAS2 is in contact with the passivation layers PAS1 and PAS3. The wiring W3 is sandwiched between the passivation layers PAS1 and PAS2, and the connection electrode ZTCO is sandwiched between the passivation layers PAS2 and PAS3. This improves the adhesion of the passivation layers PAS1 to PAS3. In addition, the passivation layers PAS1 to PAS3 are formed at a low temperature of 150°C or higher and 250°C or lower. This makes it possible to prevent hydrogen contained in the raw material gas and hydrogen contained in the silicon nitride layer from diffusing due to heat applied during the formation of the passivation layers PAS1 to PAS3. In addition, since silicon oxide is not used for the passivation layers PAS1 to PAS3, it is possible to suppress film formation waste during film formation.

[0130] 6. Crystal structure of oxide semiconductor layer The oxide semiconductor layer POS described in this embodiment includes a Poly-OS. The crystal grains included in the Poly-OS observed from the top surface of the oxide semiconductor layer POS (or the thickness direction of the oxide semiconductor layer POS) have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained, for example, by cross-sectional SEM observation, cross-sectional TEM observation, or an electron backscattered diffraction (EBSD) method.

[0131] In the Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of the Poly-OS can be identified by an electron beam diffraction method, an XRD method, or the like. That is, the crystal structure of the oxide semiconductor layer POS can be identified by an electron beam diffraction method, an XRD method, or the like.

[0132] The crystal structure of the oxide semiconductor layer POS is preferably a cubic crystal. The cubic crystal structure has high symmetry, and even if oxygen defects are generated in the oxide semiconductor layer POS, structural relaxation is unlikely to occur, and the crystal structure is stable. As described above, by increasing the ratio of the indium element, the crystal structure of each of the multiple crystal grains is controlled, and the oxide semiconductor layer POS having a cubic crystal structure can be formed.

[0133] In the transistor Tr1 including the oxide semiconductor layer POS manufactured by the above manufacturing method, good transistor characteristics can be obtained even if the channel length L of the channel region OS1 is set to 0.5 μm or more and 2.0 μm or less. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. This makes it possible to provide a high-definition display device 10.

[0134] In the transistor Tr including the oxide semiconductor layer POS manufactured by the above manufacturing method, when the channel length L of the channel region OS1 is in the range of 0.5 μm to 2 μm and the channel width of the channel region OS1 is in the range of 1 μm to 25 μm, the mobility is 50 [cm 2 / Vs] or more, 55[cm 2 / Vs] or more, or 60 [cm 2 / Vs] or more can be obtained. The mobility in this embodiment means the field effect mobility in the saturation region of the transistor, and refers to the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage (Vg) supplied to the gate electrode.

[0135] <7. Variation 1> Next, a first modified example of the display device 10 will be described with reference to Figs. 18 to 21. In the present embodiment, a configuration in which only silicon nitride layers are used as the passivation layers PAS1 to PAS3, without using silicon oxide, has been described. In this modified example, a case in which a silicon oxide layer SO is formed on the passivation layer PAS1 will be described.

[0136] Fig. 18 is a cross-sectional view showing an overview of a display device 10A according to one embodiment of the present invention. The display device 10A shown in Fig. 18 differs from the display device 10 shown in Fig. 4 in that a silicon oxide layer SO is provided between a passivation layer PAS1 and a wiring W3.

[0137] 19 is a sequence diagram illustrating a manufacturing method of a display device 10A according to an embodiment of the present invention. In this modification, steps S1027 and S1016, which are different from the sequence diagrams illustrated in FIGS. 7 and 8, will be described in more detail.

[0138] A silicon oxide layer SO is formed on the passivation layer PAS1 (see step S1027 shown in FIG. 19 and FIG. 20). As described above, since film-forming waste is generated when the silicon oxide layer is formed, it is preferable that the film thickness T1 of the silicon oxide layer SO is smaller than the film thicknesses of the passivation layers PAS1 to PAS3, and is preferably formed to a thickness of, for example, 10 nm to 50 nm, or 10 nm to 30 nm. This makes it possible to suppress the generation of film-forming waste during film formation. In addition, by setting the temperature at which the silicon oxide layer SO is formed to 150° C. to 250° C., it is possible to suppress the diffusion of hydrogen contained in the passivation layer PAS1.

[0139] Next, an opening SCON1 is formed in the passivation layer PAS1 so as to reach the low-resistance region OS2. After that, a wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low-resistance region OS2 through the opening SCON1 (see step S1016 shown in FIG. 8 and FIG. 21). For the film formation method and conductive material of the wiring W3, refer to the description of the light-shielding layer LS. The wiring W3 can be formed by processing a conductive film, but the passivation layer PAS1 may also be etched when processing the conductive film. By forming a thin silicon oxide layer SO on the passivation layer PAS1, the silicon oxide layer SO can function as an etching stopper.

[0140] In this modification, the silicon oxide layer SO exposed from the wiring W3 is entirely removed by etching. Therefore, as shown in FIG. 21, the silicon oxide layer SO is provided between the passivation layer PAS1 and the wiring W3. The silicon oxide layer SO is masked by the wiring W3, and therefore has the same thickness as when it was formed. Therefore, the thickness T1 of the silicon oxide layer SO shown in FIG. 21 is 10 nm to 50 nm, or 10 nm to 30 nm. Then, a silicon nitride layer is formed as the passivation layer PAS2 on the passivation layer PAS1, thereby improving the adhesion between the passivation layer PAS1 and the passivation layer PAS2. Therefore, in this modification, in addition to obtaining the effects described in the manufacturing process of FIGS. 7 to 8, the passivation layer PAS1 can be prevented from being etched more than necessary when the wiring W3 is processed.

[0141] <8. Variation 2> Next, a second modified example of the display device 10 will be described with reference to Figs. 22 and 23. In the first modified example, a silicon oxide layer SO is formed on the passivation layer PAS1, and then the silicon oxide layer SO exposed from the wiring W3 during the formation of the wiring W3 is entirely removed. In this modified example, a case will be described in which the wiring W3 is processed so that the silicon oxide layer SO remains. Therefore, the sequence diagram for explaining the manufacturing method of the display device 10B is generally similar to that in Fig. 19.

[0142] 22 is a cross-sectional view showing an overview of a display device 10B according to an embodiment of the present invention. In this modification, a silicon oxide layer SO is provided between a passivation layer PAS1 and a passivation layer PAS2. The silicon oxide layer SO has a thickness T1 in a first region overlapping with the wiring W3 that is greater than a thickness T2 in a second region not overlapping with the wiring W3.

[0143] In this modification, the process of step S1016 in the sequence diagram shown in FIG. 19 is different from that of modification 1. The silicon oxide layer SO is formed to a thickness of 10 nm to 50 nm, preferably 10 nm to 30 nm, so that the thickness T1 is the thickness of the silicon oxide layer SO after it is formed. On the other hand, the region exposed from the wiring W3 is removed by etching, so that the thickness T2 is smaller than the thickness T1. The thickness T2 may be greater than 0 nm and less than 10 nm. The conductive film is etched to form the wiring W3 so that the silicon oxide layer SO remains.

[0144] By providing a thin silicon oxide layer SO between the passivation layers PAS1 and PAS2, it is possible to suppress the diffusion of hydrogen contained in the layers above the passivation layer PAS2. In addition, since the thickness of the silicon oxide layer SO is smaller than the thicknesses of the passivation layers PAS1 to PAS3, it is also possible to reduce the influence of film-forming dust during film formation.

[0145] <9. Variation 3> Next, a third modified example of the display device 10 will be described with reference to Fig. 24 and Fig. 25. In this modified example, a manufacturing method that is partially different from the manufacturing method of the display device 10 will be described.

[0146] Fig. 24 is a cross-sectional view showing an overview of a display device 10C according to one embodiment of the present invention. As shown in Fig. 24, the configuration of the transistor Tr1 is different from the configuration of the transistor Tr1 shown in Fig. 4. In Fig. 24, the metal oxide layer MO1 formed under the oxide semiconductor layer POS is omitted.

[0147] FIG. 25 is a sequence diagram for explaining a manufacturing method of a display device 10C according to an embodiment of the present invention. The sequence diagram shown in FIG. 25 is partially different from the sequence diagram shown in FIG. 7. As shown in FIG. 25, the process of forming the metal oxide layer MO1 on the second insulating layer IL2 (step S1004 shown in FIG. 7) and the process of patterning the metal oxide layer MO1 (step S1008 shown in FIG. 7) are omitted. Note that the process from step S1014 shown in FIG. 25 onwards is similar to the process shown in FIG. 8, so detailed description is omitted. In this modification, the metal oxide layer MO1 is omitted, but the first gate insulating layer GI1 is capped by the metal oxide layer MO2. As a result, oxygen released from the second insulating layer IL2 and the first gate insulating layer GI1 by the subsequent oxidation annealing is capped by the metal oxide layer MO2, so that it is supplied to the upper and lower surfaces of the oxide semiconductor layer POS, and oxygen defects are repaired. Therefore, oxygen can be efficiently supplied to the oxygen defects of the oxide semiconductor layer POS.

[0148] <10. Variation 4> Next, a fourth modified example of the display device 10 will be described with reference to Fig. 26. In this modified example, a manufacturing method that is partially different from the manufacturing method of the display device 10 will be described. Note that the cross-sectional structure of the display device according to this modified example is similar to the cross-sectional structure of the display device 10C shown in Fig. 24, and therefore is not shown in the figures.

[0149] FIG. 26 is a sequence diagram for explaining a manufacturing method of a display device according to an embodiment of the present invention. The sequence diagram shown in FIG. 26 is partially different from the sequence diagram shown in FIG. 7. As shown in FIG. 26, the process of forming the metal oxide layer MO2 on the first gate insulating layer GI1 (step S1010 shown in FIG. 7) and the process of removing the metal oxide layer MO2 (step S1012 shown in FIG. 7) are omitted. Note that the process from step S1014 shown in FIG. 26 onwards is similar to the process shown in FIG. 8, so detailed description is omitted. In this modification, the metal oxide layer MO2 is omitted, but the lower side of the oxide semiconductor layer POS is capped by the metal oxide layer MO1. As a result, oxygen released from the second insulating layer IL2 by the subsequent oxidation annealing is supplied to the upper and lower surfaces of the oxide semiconductor layer POS, and oxygen defects are repaired. In addition, oxygen released from the second insulating layer IL2 is blocked by the metal oxide layer MO1, and is prevented from being supplied in large amounts to the lower surface of the oxide semiconductor layer POS, so that the formation of defect levels can be suppressed. Therefore, oxygen can be efficiently supplied to the oxygen defects in the oxide semiconductor layer POS.

[0150] As described in Modification 3 and Modification 4, by performing annealing in a state in which the metal oxide layer MO1 or the metal oxide layer MO2 is formed on at least one of the lower surface and the upper surface of the oxide semiconductor layer POS, oxygen can be supplied to the oxygen vacancies in the oxide semiconductor layer POS.

[0151] In the manufacturing method of the display device 10 according to the present modification 3 and modification 4, in the transistor Tr1 including the oxide semiconductor layer POS, even if the channel length L of the channel region OS1 is set to 0.5 μm or more and 2 μm or less, good transistor characteristics can be obtained. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. As a result, a high-definition display device 10 can be provided.

[0152] The manufacturing method of the display device 10C according to the present modification 3 and modification 4 also makes it possible to form an oxide semiconductor layer POS having a good polycrystalline structure. In the transistor Tr including the oxide semiconductor layer POS manufactured in the present modification 3 and modification 4, the mobility is 30 cm when the channel length L of the channel region OS1 is in the range of 0.5 μm to 2 μm and the channel width of the channel region OS1 is in the range of 1 μm to 25 μm. 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 Electrical characteristics of at least / Vs can be obtained.

[0153] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. In addition, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits processes or modifies conditions, based on the semiconductor device and display device of each embodiment are included in the scope of the present invention as long as they include the gist of the present invention.

[0154] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those which are clear from the description in this specification or which can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0155] 10, 10A to 10C: display device, 100: array substrate, 110: first driving circuit, 111: multiplexer circuit, 112: analog switch, 115: wiring section, 116: data signal supply line, 120: second driving circuit, 121: peripheral area, 122: display area, 124: sealing area, 126: exposed area, 129: scanning signal line, 131: data signal line, 141: connection wiring, 143: connection section, 145: common wiring, 146: common electrode, 150: terminal section, 1 60: transistor, 161: first gate electrode, 163: first source electrode, 164: first drain electrode, 168: capacitance element, 170: liquid crystal element, 180: pixel, 182: pixel circuit, 190: opposing substrate, 192: light shielding portion, 200: sealing portion, 300: flexible printed circuit board, 400: IC chip, AOS: oxide semiconductor layer, B: subpixel, BM: black matrix, CF: color filter, CMTL: common auxiliary electrode, CON1: contact region, CTCO: common electrode, G: subpixel, GI1: first gate insulating layer, GI2: second gate insulating layer, GL1: gate wiring, GL2: gate electrode, IL1: first insulating layer, IL2: second insulating layer, IL3: third insulating layer, IL4: fourth insulating layer, LC: liquid crystal layer, LS: light-shielding layer, MO1, MO2: metal oxide layer, OC: overcoat layer, OF1, OF2: alignment film, OS1: channel region, OS2: low-resistance region, PAS1 to PAS3: passivation layers , PCON: opening, POS: oxide semiconductor layer, PTCO: pixel electrode, R: subpixel, S: semiconductor layer, S1: semiconductor layer, S2: semiconductor layer, S3: semiconductor layer, SCON1: opening, SCON2: opening, SO: silicon oxide layer, SP: spacer, SUB1: substrate, SUB2: opposing substrate, Tr, Tr1, Tr2, Tr2-1, Tr2-2: transistors, W: wiring group, W1 to W3: wiring, WC1, WC2: opening, ZCON: opening, ZTCO: connecting electrode

Claims

1. an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer provided on the oxide semiconductor layer; a gate electrode on the gate insulating layer and facing the oxide semiconductor layer; a first silicon nitride layer provided in contact with the gate electrode; a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer; A display device, wherein the channel length of the gate electrode is 2.0 μm or less.

2. The display device according to claim 1 , further comprising a silicon oxide layer between the source wiring and the first silicon nitride layer.

3. The display device according to claim 2 , wherein the silicon oxide layer has a thickness of 10 nm or more and 50 nm or less.

4. The display device according to claim 1 , further comprising an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer.

5. The display device according to claim 1 , wherein the oxide semiconductor layer contains two or more metal elements including indium, and a ratio of indium to the two or more metal elements is 50% or more.

6. an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer provided on the oxide semiconductor layer; a gate electrode on the gate insulating layer and facing the oxide semiconductor layer; a first silicon nitride layer provided in contact with the gate electrode; a silicon oxide layer provided in contact with the first silicon nitride layer; a source wiring provided on and in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer provided in contact with the source wiring and the silicon oxide layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer; The channel length of the gate electrode is 2.0 μm or less; A display device, wherein a thickness of the silicon oxide layer is smaller than a thickness of the first silicon nitride layer, a thickness of the second silicon nitride layer, and a thickness of the third silicon nitride layer.

7. 7. The display device according to claim 6, wherein a thickness of a first region of the silicon oxide layer overlapping the source wiring is greater than a thickness of a second region of the silicon oxide layer not overlapping the source wiring.

8. The display device according to claim 7 , wherein the first region of the silicon oxide layer has a thickness of 10 nm or more and 50 nm or less.

9. The display device according to claim 7 , wherein the thickness of the second region of the silicon oxide layer is greater than 0 nm and less than 10 nm.

10. The display device according to claim 6 , further comprising an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer.

11. The display device according to claim 6 , wherein the oxide semiconductor layer contains two or more metal elements including indium, and a ratio of indium to the two or more metal elements is 50% or more.

12. forming an oxide semiconductor layer having a polycrystalline structure; forming a gate insulating layer on the oxide semiconductor layer; forming a gate electrode on the gate insulating layer so as to face the oxide semiconductor layer; forming a first silicon nitride layer in contact with the gate electrode; forming a source wiring in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; forming a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer; forming a first transparent conductive layer in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; depositing a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer; a channel length of a channel region overlapping with the gate electrode in the oxide semiconductor layer is 2.0 μm or less; A method for manufacturing a display device, wherein the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are each formed at a temperature of 150° C. or higher and 250° C. or lower.

Images