Display driver circuit and display system

Abstract

To shorten lock time of a PLL circuit at re-training a clock, in a configuration for receiving data from a display control circuit by clock embedded type high-speed serial transmission system.SOLUTION: A PLL circuit 15 includes a VCO 25 for generating a signal at an oscillation frequency according to inputted control voltage Vctrl and outputting it as a clock signal 102. The PLL circuit 15 generates the clock signal 102 synchronized with a reference clock included in a clock training period of the data signal by the VCO 25 and output it, during the clock training period of the data signal received from a display controller through an amplifier circuit 11. A control voltage holding circuit 40 holds a voltage value of the control voltage Vctrl when the PLL circuit 15 becomes lock state, and supplies a voltage based on the hold voltage value to the control voltage Vctrl when the PLL circuit 15 becomes unlock state from the lock state.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a display driver circuit for receiving a data signal from a display control circuit (display controller) and driving a display device such as an LCD display device, and to a display system including the display driver circuit. [Background technology]

[0002] In an image processing system equipped with a display driver circuit for receiving data signals from a display control circuit (display controller) and driving a display device such as an LCD display device, high-speed signal transmission is required between the display control circuit and the display driver circuit. In particular, in recent years, the amount of video data to be transmitted has increased with the increase in resolution and refresh rate of display devices, and the signal transmission speed has become faster and faster.

[0003] As a signal transmission method between such a display control circuit and a display driver circuit, a clock-embedded high-speed serial transmission method is sometimes used (see, for example, Patent Document 1).

[0004] In this clock-embedded high-speed serial transmission method, a display control circuit on the sending side superimposes a clock onto data and serially transmits the data to a display driver circuit on the receiving side, which uses a PLL (Phase Locked Loop) circuit to regenerate a clock signal from the received data and receive the data. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2022-037647 A Summary of the Invention [Problem to be solved by the invention]

[0006] In such a clock-embedded high-speed serial transmission method, it is necessary to use a PLL circuit to generate a clock signal synchronized with a reference clock superimposed on a data signal within a determined period called a clock training period.

[0007] However, as described above, the amount of video data to be transmitted is increasing along with the increase in resolution and refresh rate of display devices, and signal transmission speeds are becoming faster and faster, so there is a tendency for this clock training period to become shorter.

[0008] Even if the PLL circuit is in a locked state and generates a clock signal, if the PLL circuit cannot maintain the locked state, it is necessary to perform re-clock training to lock the PLL circuit again. Therefore, when a display defect occurs due to some cause and the display state is to be restored to the original normal state, re-clock training to lock the PLL circuit again is necessary. If the lock time of the PLL circuit during this re-clock training can be shortened, the time to restore the normal display state can also be shortened. In addition, since re-clock training is performed many times during tests such as at the time of shipment to check the operation of the display driver circuit, the inspection cost at the time of shipment can be reduced by shortening the time for re-clock training.

[0009] An object of the present invention is to provide a display driver circuit capable of shortening the lock time of a PLL circuit during re-clock training in a configuration in which data is received from a display control circuit using a clock-embedded high-speed serial transmission method. [Means for solving the problem]

[0010] In order to solve the above problems, a display driver circuit of the present invention is a display driver circuit for receiving a data signal from a display control circuit and driving a display device, comprising: a PLL circuit having a voltage controlled oscillator which generates a signal having an oscillation frequency according to an input control voltage and outputs the signal as a clock signal, and which generates and outputs a clock signal synchronized with a reference clock included in a clock training period of a data signal received from the display control circuit by using the voltage controlled oscillator during the clock training period of the data signal; a drive circuit that drives a display device using the clock signal generated by the PLL circuit; The PLL circuit includes a control voltage holding circuit that holds the voltage value of the control voltage when the PLL circuit is in a locked state, and supplies a voltage based on the held voltage value to the control voltage when the PLL circuit goes from a locked state to an unlocked state.

[0011] In the display driver circuit of the present invention, the control voltage holding circuit includes a converter that converts the control voltage into a digital value when the PLL circuit is in a locked state; A holding circuit that holds the digital value converted by the converter, The converter may be configured to convert the digital value held in the holding circuit into an analog value and supply the analog value as the control voltage when the PLL circuit changes from a locked state to an unlocked state.

[0012] In the display driver circuit of the present invention, the control voltage holding circuit includes a switch element connected to the converter for switching between output and non-output of the control voltage; a timing signal generating circuit that generates a timing signal to control the converter, the holding circuit, and the switch element; The timing signal generating circuit may be configured to output the timing signal for controlling the switch element to a closed state during a period in which the control voltage is output, when the PLL circuit changes from a locked state to an unlocked state.

[0013] In order to achieve the above object, a display system of the present invention includes any one of the display driver circuits described above; a display control circuit that transmits the data signal, on which a reference clock is superimposed together with display data, to the display driver circuit; a display device to which the display data is supplied from the display driver circuit. Effect of the Invention

[0014] According to the present invention, it is possible to provide a display driver circuit capable of shortening the lock time of a PLL circuit during re-clock training in a configuration in which data is received from a display control circuit using a high-speed serial transmission method based on a clock-embedded system. [Brief description of the drawings]

[0015] [Figure 1] 1 is a block diagram showing a configuration of a display driver circuit 10 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of a PLL circuit 115 as a comparative example. [Diagram 3] 3 is a diagram showing operational waveforms in the PLL circuit 115 of the comparative example shown in FIG. 2. [Figure 4] 2 is a diagram showing a circuit configuration of a PLL circuit 15 in one embodiment of the present invention. [Diagram 5] 5 is a block diagram for explaining the configuration of a control voltage hold circuit 40 shown in FIG. [Figure 6] 4 is a flowchart for explaining the operation of the PLL circuit 15 according to one embodiment of the present invention. [Figure 7] 5 is a diagram showing operational waveforms in the PLL circuit 15 of the embodiment of the present invention shown in FIG. 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0017] The configuration of a display driver circuit 10 according to one embodiment of the present invention is shown in the block diagram of Figure 1. As shown in Figure 1, a display system 1 is made up of the display driver circuit 10, a display controller 20, and an LCD display device 30.

[0018] As shown in FIG. 1, the display driver circuit 10 of this embodiment is made up of an amplifier circuit 11, a deserializer 12, a logic circuit 13, an amplifier 14, and a PLL circuit 15.

[0019] The display driver circuit 10 is configured to receive data signals from a display controller 20, which is a display control circuit, and drive an LCD display device 30.

[0020] The data signal (DATA / CLK) from the display controller 20 is a clock-embedded serial signal in which a reference clock is superimposed during a preset clock training period, along with display data for driving the LCD display device 30.

[0021] The amplifier circuit 11 amplifies a data signal (DATA / CLK) input from the display controller 20, and supplies the amplified signal to the deserializer 12 and the PLL circuit 15.

[0022] During the clock training period of the data signal (DATA / CLK) supplied from the amplifier circuit 11, the PLL circuit 15 generates and outputs a clock signal 102 synchronized with a reference clock included in the clock training period of this data signal.

[0023] Furthermore, the PLL circuit 15 outputs a signal indicating whether or not the current state is a locked state as a locked state signal 101. Specifically, when the PLL circuit 15 is in a locked state, a high-level (hereinafter abbreviated as H level) locked state signal 101 is output, and when the PLL circuit 15 is in an unlocked state, a low-level (hereinafter abbreviated as L level) locked state signal 101 is output.

[0024] The deserializer 12 operates based on the clock signal 102 generated by the PLL circuit 15, obtains data to be displayed on the LCD display device 30 from the data signal (DATA / CLK) supplied from the amplifier circuit 11, converts the obtained data from serial format to parallel format, and outputs the data.

[0025] The logic circuit 13 operates based on a clock signal 102 generated by the PLL circuit 15, and outputs the parallel data from the deserializer 12 as display data for driving the LCD display device 30. A lock state signal 101 is input to the logic circuit 13, and the logic circuit 13 operates while grasping the lock state of the PLL circuit 15. A control signal is input to the logic circuit 13 from the display controller 20, and the display controller 20 is configured to be able to control the operation of the logic circuit 13.

[0026] The amplifier 14 amplifies the display data output from the logic circuit 13 and outputs it to the LCD display device 30 .

[0027] As described above, the deserializer 12 and the logic circuit 13 constitute a drive circuit that drives the LCD display device 30 using the clock signal 102 generated by the PLL circuit 15.

[0028] Next, a description will be given of the PLL circuit 15, which is a characteristic component of the display driver circuit 10 of this embodiment. However, before describing the PLL circuit 15 in the display driver circuit 10 of this embodiment, a circuit configuration of a general PLL circuit 115 will be described as a comparative example.

[0029] Fig. 2 is a diagram showing a circuit configuration of the comparative example PLL circuit 115. Fig. 2 shows a circuit configuration in the case where this PLL circuit 115 is applied to the display driver circuit 10 in place of the PLL circuit 15 in this embodiment.

[0030] As shown in FIG. 2, the comparative example PLL circuit 115 includes a phase comparator 21, a phase frequency comparator 22, a charge pump 23, an LPF (loop filter) 24, a VCO (Voltage Controlled Oscillator) 25, a frequency divider 26, and a lock detection circuit 27.

[0031] The PLL circuit 115 has a VCO 25 that generates a signal with an oscillation frequency according to the input control voltage Vctrl and outputs it as a clock signal 102. The PLL circuit 115 has a circuit configuration in which, during the clock training period of the data signal received from the display controller 20 via the amplifier circuit 11, the VCO 25 generates and outputs the clock signal 102 synchronized with a reference clock included in the clock training period of the data signal.

[0032] During the clock training period, the PLL circuit 115 performs the following operations.

[0033] Next, the phase frequency comparator 22 compares the frequency of the signal divided by the frequency divider 26 with the frequency of the data signal from the amplifier circuit 11, and if the frequency of the signal divided by the frequency divider 26 is lower than the frequency of the data signal from the amplifier circuit 11, it outputs an up pulse signal to the charge pump 23. If the frequency of the signal divided by the frequency divider 26 is higher than the frequency of the data signal from the amplifier circuit 11, the phase frequency comparator 22 outputs a down pulse signal to the charge pump 23.

[0034] The charge pump 23 increases or decreases the output voltage based on an up-pulse signal or a down-pulse signal. Specifically, the charge pump 23 increases the output voltage when an up-pulse signal is input, and decreases the output voltage when a down-pulse signal is input.

[0035] The LPF 24 is a filter circuit that smoothes the output voltage from the charge pump 23 and outputs the smoothed voltage to the VCO 25 as a control voltage Vctrl.

[0036] Due to the circuit configuration as described above, when the phase frequency comparator 22 outputs an up pulse signal, the control voltage Vctrl increases, and when the phase frequency comparator 22 outputs a down pulse signal, the control voltage Vctrl decreases.

[0037] The VCO 25 generates a clock signal 102 having an oscillation frequency according to the control voltage Vctrl input from the LPF 24 .

[0038] The frequency divider 26 divides the frequency of the clock signal 102 generated by the VCO 25 by a set division ratio, and outputs the divided signal to the phase frequency comparator 22 .

[0039] During the clock training period, PLL circuit 115 performs the above-mentioned operation to generate and output clock signal 102 having a frequency that is the frequency of the reference clock during the clock training period multiplied by the division ratio of frequency divider 26. For example, when the division ratio of frequency divider 26 is 2 and the frequency of the reference clock during the clock training period is 200 MHz, PLL circuit 115 generates and outputs clock signal 102 of 400 MHz.

[0040] The lock detection circuit 27 monitors the clock signal 102 output from the VCO 25, and outputs a locked state signal 101 that is at H level when the PLL circuit 115 is in a locked state and at L level when the PLL circuit 115 is in an unlocked state.

[0041] During the clock training period, the PLL circuit 115 is in an unlocked state, and the locked state signal 101 is at L level. When the clock training period ends and the data acquisition period begins, the PLL circuit 115 is in a locked state, and the locked state signal 101 is at H level.

[0042] The phase frequency comparator 22 operates only when the locked state signal 101 is at the L level, and the phase comparator 21 operates only when the locked state signal 101 is at the H level. In other words, the phase frequency comparator 22 operates during the clock training period, and the phase comparator 21 operates during the data acquisition period after the PLL circuit 115 enters the locked state and the clock signal 102 of the set frequency is generated.

[0043] Then, the phase comparator 21 compares the phase of the clock signal 102 with the phase of the data signal from the amplifier circuit 11, and outputs an up pulse signal or a down pulse signal to the charge pump 23 depending on the phase difference between the clock signal 102 and the data signal from the amplifier circuit 11.

[0044] In other words, during the clock training period, the PLL circuit 115 operates such that the phase frequency comparator 22 operates to generate a clock signal 102 having a frequency synchronized with the reference clock, and during the subsequent data acquisition period, the phase comparator 21 operates to maintain the generated clock signal 102.

[0045] Next, FIG. 3 shows the operation waveforms in the PLL circuit 115 of the comparative example shown in FIG.

[0046] 3, it can be seen that at time T1, power is supplied to the display driver circuit 10, and the display driver circuit 10 is in a power-on state. Then, during the initial clock training period after the power-on state, the PLL circuit 115 goes through the steps of resetting the control voltage Vctrl, restarting the VCO 25, reproducing the frequency, and stabilizing the phase, and is then in a locked state.

[0047] Then, in FIG. 3, it can be seen that at time T2, an unlocking occurs for some reason, causing the PLL circuit 115 to go from a locked state to an unlocked state, and during the re-training period in which the clock signal 102 of the set frequency is generated, the PLL circuit 115 goes through the steps of resetting the control voltage Vctrl, restarting the VCO 25, reproducing the frequency, and stabilizing the phase again, before entering the locked state.

[0048] That is, in the PLL circuit 115 of the comparative example, the time it takes for the PLL circuit 115 to transition from an unlocked state to a locked state is substantially equal between the initial clock training period and the re-clock training period.

[0049] That is, in the PLL circuit 115 of this comparative example, every time an unlocking occurs, it is necessary to execute the process of transitioning from the unlocked state to the locked state again through the same procedure.

[0050] Next, a circuit configuration of the PLL circuit 15 in one embodiment of the present invention is shown in FIG.

[0051] The PLL circuit 15 of this embodiment shown in Fig. 4 has a configuration in which a control voltage holding circuit 40 is added to the PLL circuit 115 of the comparative example shown in Fig. 2. Note that in Fig. 4, the same components as those shown in Fig. 2 are given the same reference numerals, and the description of their operation will be omitted.

[0052] The control voltage holding circuit 40 is configured to hold the voltage value of the control voltage Vctrl when the PLL circuit 15 enters a locked state, and to supply a voltage based on the held voltage value to the control voltage Vctrl when the PLL circuit 15 goes from a locked state to an unlocked state.

[0053] The configuration of the control voltage holding circuit 40 shown in FIG. 4 will be described with reference to the block diagram of FIG.

[0054] The control voltage holding circuit 40 is made up of a timing signal generating circuit 41, an AD (Analog-Digital) converter 42, a digital value holding circuit 43, and a changeover switch 44.

[0055] The changeover switch 44 is a switch element that is connected to the AD converter 42 and switches between outputting and not outputting the control voltage Vctrl.

[0056] The AD converter 42 converts the control voltage Vctrl when the PLL circuit 15 is in a locked state into a digital value.

[0057] The digital value holding circuit 43 is a holding circuit that holds the digital value converted by the AD converter 42 .

[0058] Furthermore, when the PLL circuit 15 changes from a locked state to an unlocked state, the AD converter 42 converts the digital value held in the digital value holding circuit 43 into an analog value and supplies the analog value as the control voltage Vctrl.

[0059] That is, the AD converter 42 operates as an A / D converter or a D / A converter.

[0060] The timing signal generating circuit 41 generates and outputs a timing signal for controlling the AD converter 42 , the digital value holding circuit 43 , and the changeover switch 44 based on the lock state signal 101 .

[0061] Specifically, when the lock state signal 101 changes from the unlocked state to the locked state, the timing signal generating circuit 41 closes the change-over switch 44 for a preset control voltage holding period, converts the voltage value of the control voltage Vctrl into a digital value by the AD converter 42, and holds it in the digital value holding circuit 43.

[0062] When the lock state signal 101 changes from a locked state to an unlocked state, the timing signal generating circuit 41 closes the change-over switch 44 for a preset control voltage output period, converts the digital value held in the digital value holding circuit 43 into an analog voltage value by the AD converter 42, and outputs it as the control voltage Vctrl.

[0063] Next, the operation of the PLL circuit 15 of this embodiment will be described with reference to the flowchart of FIG.

[0064] First, in the PLL circuit 15 of this embodiment, when the PLL circuit 15 is in an unlocked state, clock training is performed to generate a clock signal 102 synchronized with a reference clock included in a data signal (step S101).

[0065] Then, when clock training is performed, the PLL circuit 15 enters a locked state and the clock signal 102 is generated, the control voltage Vctrl in the locked state is held by the control voltage holding circuit 40 (step S102).

[0066] After that, a data acquisition period begins in which the generated clock signal 102 is used to acquire data contained in the data signal of the display controller 20 (step S103).

[0067] Then, the locked state is maintained in the PLL circuit 15, and the process of step S103 continues while the locked state signal 101 is at H level (while yes is returned in step S104).

[0068] Then, when the locked state is released in the PLL circuit 15 for some reason and the locked state signal 101 becomes the L level (no in step S104), the control voltage holding circuit 40 outputs the held voltage value to the control voltage Vctrl (step S105).

[0069] Then, clock training is executed again in step S101. Here, in the first clock training, the PLL circuit 15 was in a locked state through the procedure of resetting the control voltage Vctrl, restarting the VCO 25, reproducing the frequency, and stabilizing the phase. However, in the re-clock training period after the PLL circuit 15 has once been in a locked state, the control voltage holding circuit 40 outputs the voltage in the previous locked state as the control voltage Vctrl. Therefore, the time until the PLL circuit 15 is in a locked state through the procedure of restarting the VCO 25, reproducing the frequency, and stabilizing the phase is shortened compared to the case where the control voltage Vctrl is reset without holding the control voltage Vctrl.

[0070] Next, FIG. 7 shows operational waveforms in the PLL circuit 15 according to the embodiment of the present invention shown in FIG.

[0071] 7, it can be seen that at time T3, power is supplied to the display driver circuit 10 and the display driver circuit 10 is in a power-on state. Then, during the initial clock training period after the power-on state, the PLL circuit 15 goes through the steps of resetting the control voltage Vctrl, restarting the VCO 25, reproducing the frequency, and stabilizing the phase, and the PLL circuit 15 is in a locked state.

[0072] Then, at time T4, when the PLL circuit 15 enters a locked state and the locked state signal 101 changes from L level to H level, the timing signal generation circuit 41 outputs a timing signal instructing to hold the control voltage to the AD converter 42, the digital value hold circuit 43, and the changeover switch 44. Therefore, the voltage value of the control voltage Vctrl in the locked state is held in the digital value hold circuit 43.

[0073] Then, at time T5, when an unlock occurs for some reason and the PLL circuit 15 changes from a locked state to an unlocked state, the timing signal generation circuit 41 outputs a timing signal instructing the output of a control voltage to the AD converter 42, the digital value hold circuit 43, and the change-over switch 44. Therefore, a voltage based on the voltage value held in the digital value hold circuit 43 during the locked state is output as the control voltage Vctrl.

[0074] 7, it can be seen that the change range of the control voltage Vctrl in the re-clock training period is smaller than the change range of the control voltage Vctrl in the initial clock training period, and that the reset procedure of the control voltage Vctrl is omitted in the re-clock training period.

[0075] That is, the time taken for the PLL circuit 15 to transition to the locked state in the re-clock training period is shorter than the time taken for the PLL circuit 15 to transition to the locked state in the initial clock training period.

[0076] Therefore, according to the display driver circuit 10 of this embodiment, in a configuration in which data is received from the display controller 20 using a high-speed serial transmission method based on a clock-embedded method, it is possible to shorten the lock time of the PLL circuit 15 during re-clock training. [Explanation of symbols]

[0077] 1 Display System 10 Display driver circuit 11 Amplification circuit 12 Deserializer 13 Logic Circuits 14 Amplifier 15 PLL circuit 20 Display Controller 21 Phase comparator 22 Phase Frequency Detector 23 Charge Pump 24 LPF 25 VCO 26 frequency divider 27 Lock detection circuit 30 LCD display device 40 Control voltage holding circuit 41 Timing signal generation circuit 42 AD converter 43 Digital value holding circuit 44 Changeover switch 101 Lock status signal 102 Clock Signal 115 PLL circuit

Claims

1. A display driver circuit for receiving a data signal from a display control circuit and driving a display device, a PLL circuit having a voltage controlled oscillator which generates a signal having an oscillation frequency according to an input control voltage and outputs the signal as a clock signal, and which generates and outputs a clock signal synchronized with a reference clock included in a clock training period of a data signal received from the display control circuit by using the voltage controlled oscillator during the clock training period of the data signal; a drive circuit that drives a display device using the clock signal generated by the PLL circuit; the PLL circuit includes a control voltage holding circuit that holds a voltage value of the control voltage when the PLL circuit is in a locked state, and that supplies a voltage based on the held voltage value to the control voltage when the PLL circuit is in an unlocked state from a locked state. Display driver circuit.

2. the control voltage holding circuit includes a converter that converts the control voltage into a digital value when the PLL circuit is in a locked state; A holding circuit that holds the digital value converted by the converter, the converter converts the digital value held in the holding circuit into an analog value and supplies the analog value to the control voltage when the PLL circuit changes from a locked state to an unlocked state.

2. The display driver circuit of claim 1.

3. The control voltage holding circuit includes a switch element connected to the converter for switching between output and non-output of the control voltage; a timing signal generating circuit that generates a timing signal to control the converter, the holding circuit, and the switch element; 3. The display driver circuit according to claim 2, wherein the timing signal generating circuit outputs the timing signal that controls the switch element to a closed state during a period in which the control voltage is output when the PLL circuit changes from a locked state to an unlocked state.

4. A display driver circuit according to any one of claims 1 to 3; a display control circuit that transmits the data signal, on which a reference clock is superimposed together with display data, to the display driver circuit; a display device to which the display data is supplied from the display driver circuit; A display system comprising:

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