Processor and control method of processor

Abstract

To synchronize different kinds of computing apparatuses included in a processor, thereby improving the performance of the processor.SOLUTION: A processor includes a first computing apparatus that executes a first command, and a second computing apparatus that executes a second command and a third command. The first computing apparatus calculates first data by executing the first command. The second computing apparatus executes the third command using the first data, based on first synchronization information issued by the first computing apparatus, after the execution of the third command is stopped based on the second command which is a command to wait for issuance of the first synchronization information.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a processor and a method for controlling a processor. [Background technology]

[0002] For example, in a processor having different types of arithmetic units with different functions, the processing performance of the processor can be improved by synchronizing the different types of arithmetic units with each other and having one arithmetic unit execute processing that cannot be executed by the other arithmetic unit. Summary of the Invention [Problem to be solved by the invention]

[0003] In the present disclosure, the processing performance of a processor is improved by operating different types of arithmetic units included in the processor in synchronization with each other. [Means for solving the problem]

[0004] A processor according to an embodiment of the present invention has a first arithmetic unit that executes a first instruction and a second arithmetic unit that executes a second instruction and a third instruction, wherein the first arithmetic unit calculates first data by executing the first instruction, and the second arithmetic unit stops execution of the third instruction based on the second instruction, which is an instruction to wait for the issuance of first synchronization information, and then executes the third instruction that uses the first data based on the issuance of the first synchronization information by the first arithmetic unit. [Brief description of the drawings]

[0005] [Figure 1] FIG. 2 is a block diagram showing an example of a configuration of a processor according to an embodiment of the present invention. [Diagram 2] 2 is a timing diagram showing an example of a synchronization method between a PE and a CPU in the processor of FIG. 1. [Diagram 3] 1. FIG. 4 is a diagram illustrating an example of data movement between a PE and a CPU unit by tag synchronization in the processor of FIG. [Figure 4]FIG. 11 is a block diagram showing an example of a configuration of a processor according to another embodiment of the present invention. [Diagram 5] 5 is a diagram illustrating an example of an operation of a processor when the PE in FIG. 4 is caused to selectively execute a plurality of processes. [Figure 6] FIG. 11 is a block diagram showing an example of a configuration of a processor according to another embodiment of the present invention. [Figure 7] 7 is a diagram illustrating an example of an operation of a processor when the PE in FIG. 6 is caused to selectively execute a plurality of processes. [Figure 8] 7 is a diagram illustrating another example of the instruction supply circuit of FIG. 4 or FIG. 6. [Figure 9] 9 is a diagram illustrating an example of the operation of the processor when the instruction supply circuit of FIG. 4 includes the instruction buffer IBUFb of FIG. 8. [Figure 10] FIG. 11 is a block diagram showing an example of a configuration of a processor according to another embodiment of the present invention. [Figure 11] 11 is a diagram illustrating an example of an operation of a processor when the PE in FIG. 10 is caused to selectively execute a plurality of processes. [Figure 12] 11 is a diagram illustrating another example of the operation of the processor when the PE in FIG. 10 is caused to selectively execute a plurality of processes. [Figure 13] 2 is a block diagram showing an example of a hardware configuration of a computer on which the processor shown in FIG. 1 is installed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Although not limited to this, the processor described below may be installed in a computer such as a server and execute a program (instruction) to perform, for example, a convolution operation in training or inference of a deep neural network. The processor described below may also be used for scientific and technical calculations.

[0007] FIG. 1 is a block diagram showing an example of a configuration of a processor in an embodiment of the present invention. The processor 100 shown in FIG. 1 may be mounted on a board such as a server (not shown) together with an external memory 200. A plurality of processors 100 may be mounted on one board. In this case, the external memory 200 may be provided for each of the plurality of processors 100, or may be provided commonly to the plurality of processors 100. The external memory 200 is an example of a storage device. The processor 100 may be connected to a host system 300 via the board. Note that the arrows shown in FIG. 1 mainly indicate the transfer paths of data, and the transfer paths of control signals may be omitted.

[0008] The processor 100 may be, for example, a single instruction multiple data (SIMD) processor or a single instruction multiple threads (SIMT) processor. The processor 100 may include an external interface circuit 101, an instruction supply circuit 102, an instruction distribution circuit 103, a data movement synchronization circuit 104, a network on chip (NoC) 105, a network interface 106, a shared memory 107, a memory controller 108, a plurality of processor elements (PEs) 110, and a central processing unit (CPU) unit 120. The processor 100 may include a single PE 110. The PE 110, the instruction supply circuit 102, and the instruction distribution circuit 103 are examples of a first arithmetic device, and the instruction supply circuit 102 and the instruction distribution circuit 103 are examples of an instruction supply control circuit. The CPU unit is an example of a second arithmetic device. The processor 100 may be configured as a single chip, or may be configured as a plurality of chips.

[0009] Each PE 110 may include an arithmetic unit 111, a register file 112, a local memory 113, and an NoC interface 114. The arithmetic unit 111 may include an arithmetic logic unit (ALU) and a floating point unit (FPU). The ALU and the FPU are examples of a first arithmetic unit.

[0010] The CPU unit 120 may include a synchronization circuit 121, a CPU 122, a local memory 123, and an NoC interface 124. The CPU 122 may include a plurality of types of arithmetic units EX and a register file RF. For example, the CPU unit 120 can execute a process that is difficult to execute in the PE 110. The PE 110 and the CPU unit 120 have a function of synchronizing the execution of instructions with each other.

[0011] The PE 110 and the CPU unit 120 have different processing performances and functions. For example, the PE 110 can perform high-speed calculations on a large amount of data by executing in parallel calculation instructions supplied from the host system 300 using a large number of arithmetic units. The CPU unit 120 can execute not only calculation instructions but also branch instructions such as conditional branch instructions by fetching and executing instructions held in the local memory 123.

[0012] In addition, the CPU unit 120 may have a GPU (Graphics Processing Unit), a GPGPU (General Purpose Computing on GPU), a DSP (Digital Signal Processor), an ISP (Image Signal Processor), custom hardware, or a PE of a different type from the PE 110 instead of the CPU 122.

[0013] The external interface circuit 101 may be connected to the host system 300 via, for example, a PCIe (Peripheral Component Interconnect express) bus or the like. The external interface circuit 101 may control communication with the host system 300.

[0014] Of the sequence of instructions read from the system memory 310 of the host system 300, the data movement instruction and the operation instruction executed by the CPU 122 may be transferred to the local memory 123 of the CPU unit 120 via the external interface circuit 101, the NoC 105, and the NoC interface 124. Of the instructions read from the system memory 310 of the host system 300, the instructions other than the instruction executed by the CPU 122 may be transferred to the instruction supply circuit 102 via the external interface circuit 101. For example, the instructions transferred to the instruction supply circuit 102 may include the operation instruction executed by the PE 110, and the wait instruction and the data movement instruction issued by the host system 300. The system memory 310 is an example of a storage device.

[0015] Hereinafter, the arithmetic instruction, data movement instruction, and wait instruction executed by the CPU 122 are also referred to as CPU instructions. The arithmetic instruction executed by the PE 110, and the wait instruction and data movement instruction issued by the host system 300 are also referred to as host instructions.

[0016] An arithmetic instruction executed by the PE 110 may be supplied to the arithmetic unit 111 via the instruction supply circuit 102 and the instruction distribution circuit 103, and executed by an arithmetic unit in the arithmetic unit 111. The arithmetic instruction supplied to the PE 110 may be executed by an arithmetic unit in the arithmetic unit 111 without any conditions. An instruction executed by the CPU 122 may be stored in the local memory 123 via the NoC 105 and the NoC interface 124, and then executed by the CPU 122 by fetching the instruction held in the local memory 123.

[0017] For example, instructions read from system memory 310 may include a multiplication instruction, an addition instruction, a data movement instruction, a wait instruction, a stop instruction, etc., which will be described later. The multiplication instruction and the addition instruction may each be a fixed point instruction or a floating point instruction. The data movement instruction may include an instruction that includes a tag for instruction synchronization and an instruction that does not include a tag. The wait instruction may include a tag for instruction synchronization. Instruction synchronization control using tags will be described in FIG. 2 and FIG. 3.

[0018] The instruction supply circuit 102 may supply the operation instruction for the PE 110 supplied from the external interface circuit 101 to the instruction distribution circuit 103. The instruction supply circuit 102 may have a DMAC (Direct Memory Access Controller). The DMAC functions as a data movement circuit. The DMAC operates based on a data movement instruction issued from the host system 300, and may move data from a transfer source to a transfer destination. Here, the data movement instruction issued from the host system 300 is different from the data movement instruction transferred to the local memory 123 and executed by the CPU 122. The DMAC may be activated by the CPU 122. The DMAC may be disposed between the external interface circuit 101 and the NoC 105, or may be disposed within the NoC 105.

[0019] The instruction distribution circuit 103 may output the arithmetic instruction for the PE 110 received from the instruction supply circuit 102 to each of the arithmetic units 111 of the multiple PEs 110 in parallel. The arithmetic units (ALUs, etc.) in the arithmetic units 111 of the multiple PEs 110 may execute the received arithmetic instructions in parallel. Furthermore, the arithmetic units in the arithmetic units 111 of the multiple PEs 110 may execute the arithmetic instruction unconditionally when they receive the arithmetic instruction. However, when the instruction distribution circuit 103 receives a wait instruction, it may suppress the output of the arithmetic instruction following the wait instruction to the PE 110 until it receives the same tag as the tag included in the wait instruction from the data movement synchronization circuit 104. The data movement synchronization circuit 104 may output the tag received from the NoC 105 to the instruction distribution circuit 103.

[0020] The NoC 105 can transfer data between the shared memory 107, the external memory 200, or the network, and the local memory 113 or the local memory 123. The NoC 105 can also transfer data between the register file 112 of the PE 110 and the local memory 123 of the CPU unit 120, or between the local memory 113 of the PE 110 and the register file RF of the CPU 122.

[0021] NoC 105 may output the tag to data movement synchronization circuit 104 when data is moved from CPU unit 120 to PE 110 by a data movement instruction including a tag executed by CPU unit 120. NoC 105 may also output the tag to synchronization circuit 121 of CPU unit 120 when data is moved from PE 110 to CPU unit 120 by a data movement instruction including a tag issued by host system 300.

[0022] Furthermore, when the CPU unit 120 executes a data movement instruction to input or output data to the system memory 310, the NoC 105 may transfer the access request and write data to the system memory 310 or transfer read data from the system memory 310 to the CPU unit 120. When the DMAC inputs or outputs data to the system memory 310 based on a data movement instruction, the NoC 105 may transfer the access request and write data to the system memory 310 or transfer read data from the system memory 310 to a write destination of the data.

[0023] The PE 110 may execute an operation instruction issued by the host system 300 and transferred from the instruction distribution circuit 103. For this reason, the PE 110 does not need to have a function for fetching an operation instruction, and does not need to have a program counter.

[0024] In the PE 110, each arithmetic unit in the arithmetic unit 111 may read data to be operated on from the register file 112 based on an arithmetic instruction supplied from the instruction distribution circuit 103. Each arithmetic unit may perform an operation using the read data and store the data resulting from the operation in the register file 112. The register file 112 may have a plurality of registers used by the arithmetic unit 111. A register number or an address may be assigned to each of the plurality of registers, and each register may be identified by the register number or the address.

[0025] The local memory 113 may be, for example, a static random access memory (SRAM). The local memory 113 may hold data used in the arithmetic unit 111 and the results of arithmetic operations in the arithmetic unit 111 via the register file 112. Since the PE 110 does not have a function to fetch instructions, instructions do not need to be stored in the local memory 123. The NoC interface 114 may control the movement of data between the register file 112 or the local memory 113 and the NoC 105.

[0026] In the CPU unit 120, the CPU 122 may fetch an instruction held in the local memory 123 and execute the fetched instruction. If the fetched instruction is an arithmetic instruction, the CPU 122 may perform an arithmetic operation using data read from the built-in register file RF and store the data resulting from the arithmetic operation in the built-in register file RF. If the fetched instruction is a data movement instruction, the CPU 122 may move the data by executing the data movement instruction. However, if the CPU 122 fetches a wait instruction including a tag, the CPU 122 may suppress the execution of the fetched instruction until the tag is received from the synchronization circuit 121.

[0027] The synchronization circuit 121 may inhibit the CPU 122 from executing an instruction following the wait instruction until the CPU 122 receives from the NoC 105 a tag included in the wait instruction fetched from the local memory 123. When the synchronization circuit 121 receives from the NoC 105 a tag included in the wait instruction, the synchronization circuit 121 may permit the CPU 122 to execute an instruction following the wait instruction.

[0028] The local memory 123 may hold instructions (programs) executed by the CPU and data used by the instructions. The NoC interface 124 may control the movement of data between the register file or the local memory 123 in the CPU 122 and the NoC 105.

[0029] The network interface 106 may connect the processor 100 to a network. When a source address or a destination address included in a data movement command indicates a storage area of ​​a memory (not shown) located on the network, the NoC 105 may output a memory access request to the network via the network interface 106.

[0030] The shared memory 107 may be, for example, an SRAM. The shared memory 107 may hold data used by the arithmetic unit 111 or the arithmetic unit EX, and arithmetic results of the arithmetic unit 111 or the arithmetic unit EX. When the NoC 105 accesses the shared memory 107, the NoC 105 may output a memory access request to the shared memory 107.

[0031] The memory controller 108 may control access to the external memory 200. For example, the external memory 200 may be a main storage device such as a dynamic random access memory (DRAM), without being limited thereto. The external memory 200 may be a non-volatile memory such as a flash memory in which data can be electrically rewritten, or a non-volatile storage device that stores data magnetically or by resistance. For example, the memory controller 108 may have a queue that holds a plurality of memory access requests received from the NoC 105, and may issue the memory access requests held in the queue to the external memory 200 in sequence.

[0032] Fig. 2 is a timing diagram showing an example of a synchronization method between the PE 110 and the CPU 122 in the processor 100 of Fig. 1. Fig. 2 shows an example of a control method of the processor 100. Fig. 2 shows an example in which the CPU 122 executes a process 2 using a result of a process 1 executed by the PE 110, and the PE 110 executes a process 3 using a result of the process 2. For this reason, the process 2 needs to be synchronized with the process 1, and the process 3 needs to be synchronized with the process 2.

[0033] A wait instruction including a tag may be used to cause CPU 122 to wait until completion of process 1 before starting process 2. Synchronization circuit 121 of CPU unit 120 may cause CPU 122 to refrain from starting process 2 until the tag included in the wait instruction is received from NoC 105. After PE 110 completes process 1, NoC 105 may transfer the result of process 1 to CPU unit 120 based on a data movement instruction including the tag from host system 300, and send the tag included in the data movement instruction to synchronization circuit 121.

[0034] If the received tag is the same as the tag included in the wait command, the synchronization circuit 121 may permit the CPU 122 to execute the process 2, and the CPU 122 may start executing the process 2 based on the permission. This allows the CPU 122 to start the process 2 in synchronization with the completion of the process 1 by the arithmetic unit 111.

[0035] For example, the instruction distribution circuit 103 may receive a wait command including a tag for synchronizing the processes 2 and 3, and an operation command for the process 3 following the wait command, from the host system 300 via the instruction supply circuit 102. The instruction distribution circuit 103 may refrain from supplying the operation command for the process 3 to the operation unit 111 until the tag included in the wait command is received from the data movement synchronization circuit 104.

[0036] The CPU 122 may execute, for example, a data movement instruction including a tag after completing the process 2. The NoC 105 may transfer the result of the process 2 to the PE 110 based on the data movement instruction, and may transmit the tag included in the data movement instruction to the data movement synchronization circuit 104.

[0037] The data movement synchronization circuit 104 may output the received tag to the instruction distribution circuit 103. When the tag received from the data movement synchronization circuit 104 is the same as the tag included in the wait instruction, the instruction distribution circuit 103 may output an operation instruction following the wait instruction to the arithmetic unit 111. This allows the arithmetic unit 111 to start process 3 in synchronization with the completion of process 2 by the CPU.

[0038] Fig. 3 is a diagram showing an example of data movement between the PE 110 and the CPU unit 120 by tag synchronization in the processor 100 of Fig. 1. Fig. 3 shows an example of a control method for the processor 100. Fig. 3 shows an example of data movement from the PE 110 to the CPU unit 120 by tag synchronization corresponding to the synchronization processing between the processes 1 and 2 of Fig. 2, and an example of data movement from the CPU unit 120 to the PE 110 by tag synchronization corresponding to the synchronization processing between the processes 2 and 3 of Fig. 2.

[0039] 3 may be generated in advance by a compiler or the like and then stored in the system memory 310 of the host system 300. The instructions stored in the system memory 310 may then be supplied to the instruction distribution circuit 103 via the external interface circuit 101 and the instruction supply circuit 102, or may be stored in the local memory 123 of the CPU unit 120 via the external interface circuit 101, the NoC 105, and the NoC interface 124.

[0040] The tag is indicated as tag#n (n is an identification number) in the description of the instruction. The arrows shown in the instruction indicate the data movement direction in the data movement instruction mv, and the movement direction of the operation result in the operation instruction. In the instructions, the symbol cpu indicates the CPU unit 120, and the symbol pe indicates the PE 110. The symbol lm indicates local memory, and the symbol r indicates a register. The symbol adr indicates an address.

[0041] "CPU instruction" refers to an instruction that is transferred from system memory 310 to local memory 123 of CPU unit 120 before synchronization processing, and is fetched and processed by CPU 122. "Host instruction" refers to an instruction issued from host system 300, and includes an arithmetic instruction processed by PE 110, a data movement instruction processed by DMAC, and a wait instruction used to control instruction distribution circuit 103.

[0042] When moving data from PE 110 to CPU unit 120 by tag synchronization, first, the arithmetic unit 111 of PE 110 may calculate the product of the values ​​of registers r0 and r1 of register file 112 based on a multiplication instruction mult from the instruction distribution circuit 103, and store the calculation result in register r2 of register file 112.

[0043] Next, the instruction supply circuit 102 may transfer data stored in the register r2 of the register file 112 to an area indicated by the address adr#0 of the local memory 123 of the CPU unit 120 based on a data movement instruction mv(tag#01) including tag#01 received from the host system 300 via the external interface circuit 101. The data transfer may be executed by a DMAC. The instruction supply circuit 102 may output tag#01 to the synchronization circuit 121 of the CPU unit 120A via the NoC 105 based on the data transfer by the data movement instruction mv(tag#01). The tag#01 included in the data movement instruction mv(tag#01) used for data movement from the PE 110 to the CPU unit 120 is an example of first synchronization information.

[0044] The CPU unit 120 may sequentially fetch a wait instruction wait(tag#01) including tag#01, a data movement instruction mv, and an add instruction add. Based on the wait instruction wait(tag#01), the CPU unit 120 may suppress the execution of the subsequent data movement instruction mv and add instruction add until tag#01 is received.

[0045] Based on the reception of tag#01, the synchronization circuit 121 of the CPU unit 120 may permit the CPU 122 to execute the data movement instruction mv following the wait instruction wait(tag#01). By using tag#01, the CPU unit 120A can wait for the branch condition, which is the multiplication result by the PE 110, to be stored in the local memory 123.

[0046] Then, the CPU 122 may execute a data movement instruction mv to store the data (multiplication result) transferred from the PE 110 and held at the address adr#0 of the local memory 123 in a register r0 of the register file RF. The CPU 122 may also use an addition instruction add to calculate the sum of the registers r0 and r1 of the register file RF and store the sum in a register r2.

[0047] As a result, the CPU 122 can execute the addition instruction "add" using the calculation result by the PE 110 after the calculation result by the PE 110 is stored in the local memory 123 of the CPU unit 120. That is, the completion of the processing by the PE 110 and the start of the processing by the CPU unit 120 can be synchronized, and the processing performance of the processor can be improved. Furthermore, by using tags, processing involving data dependency in the PE 110 and the CPU unit 120 can be executed without malfunction.

[0048] In data movement from the CPU unit 120 to the PE 110 by tag synchronization, the CPU unit 120 may sequentially fetch an addition instruction "add" and a data movement instruction "mv(tag#01)" including tag#01. The CPU 122 may calculate the sum of the values ​​of registers r0 and r1 of the register file RF based on the fetched addition instruction "add" and store the calculation result in register r2 of the register file RF.

[0049] Furthermore, based on the fetched data movement instruction mv(tag#01), the CPU 122 may store the data (addition result) stored in register r2 of the register file RF in an area indicated by address adr#0 in the local memory 113 of the PE 110, and output tag#01 to the NoC 105. The tag#01 included in the data movement instruction mv(tag#01) used to move data from the CPU unit 120 to the PE 110 is an example of second synchronization information.

[0050] The instruction supply circuit 102 may receive a wait instruction wait(tag#01) including tag#01 and a data movement instruction mv from the host system 300 via the external interface circuit 101. When the wait instruction wait(tag#01) is received, the instruction supply circuit 102 may suppress execution of the data movement instruction mv following the wait instruction wait(tag#01) until the data movement synchronization circuit 104 receives tag#01 from the CPU unit 120 via the NoC 105.

[0051] When the data movement synchronization circuit 104 receives tag#01, the instruction supply circuit 102 may cause the DMAC to execute data movement based on the data movement instruction mv. For example, the DMAC may store data (the result of addition by the CPU 122) held in a storage area at address adr#0 of the local memory 113 of the PE 110 in the register r0 of the register file 112.

[0052] The instruction supply circuit 102 may supply a multiplication instruction mult received from the host system 300 via the external interface circuit 101 to the instruction distribution circuit 103 in order to execute the data movement instruction mv. The instruction distribution circuit 103 may supply the multiplication instruction mult from the instruction supply circuit 102 to the arithmetic unit 111. The arithmetic unit 111 may then calculate the product of the values ​​of registers r0 and r1 in the register file 112 based on the multiplication instruction mult, and store the calculation result in register r2 in the register file 112.

[0053] This allows the PE 110 to execute the multiplication instruction mult using the result of the calculation by the CPU 122 after the result of the calculation by the CPU unit 120 is stored in the local memory 113 of the PE 110. That is, the completion of the process by the CPU unit 120 and the start of the process by the PE 110 can be synchronized, improving the processing performance of the processor. Furthermore, by using tags, processes involving data dependency in the PE 110 and the CPU unit 120 can be executed without malfunction.

[0054] 1 to 3, the different types of PEs 110 and CPU units 120 mounted on the processor 100 can be synchronized with each other using tags to execute multiple processes in cooperation with each other. This allows the PEs 110 and CPU units 120, which have different processing capabilities and functions, to execute the processes that they are best suited to, thereby improving the processing performance of the processor 100 compared to when each executes a process independently.

[0055] Also, instead of waiting for reception of a tag by a wait command, a polling command may be entered instead of the wait command for both the PE 110 and the CPU unit 120. By using the polling command, for example, the CPU unit 120 may periodically check with the PE 110 whether a necessary operation has been completed, or the PE 110 may periodically check with the CPU unit 120 whether a necessary operation has been completed, and when it is confirmed that the necessary operation has been completed, the subsequent command may be processed.

[0056] FIG. 4 is a block diagram showing an example of a configuration of a processor in another embodiment of the present invention. The same or similar circuits as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The processor 100A shown in FIG. 4 has the same configuration and function as the processor 100 in FIG. 1, except that it has a CPU unit 120A instead of the CPU unit 120 in FIG. 1. The CPU unit 120A has the same configuration and function as the CPU unit 120 in FIG. 1, except that it has an instruction entry address register 125A. The instruction entry address register 125A may be allocated to a part of the local memory 123. The instruction entry address register 125A may have a queue structure (FIFO structure) including a plurality of entries. The instruction entry address register 125A is an example of an address register that holds a read address indicating the source of an instruction read from a storage device.

[0057] For example, the instruction entry address register 125A may hold a top address of a storage area in the system memory 310 that holds an instruction sequence to be executed by the PE 110. For example, the CPU unit 120A may store one of a plurality of top addresses in the instruction entry address register 125A based on the result of the operation by the arithmetic unit 111 of the PE 110. Then, the CPU unit 120A may transfer an operation instruction of a predetermined size to the PE 110 from a storage area in the system memory 310 whose top address is the address stored in the instruction entry address register 125A. In this case, the CPU unit 120A may wait for reception of the operation result from the PE 110 by using a wait instruction "wait".

[0058] Alternatively, the CPU unit 120A may store one of a plurality of leading addresses in the instruction entry address register 125A based on the calculation by the CPU 122. Then, the CPU unit 120A may transfer a predetermined size of calculation instruction to the PE 110 from a storage area of ​​the system memory 310 starting from the address stored in the instruction entry address register 125A. In this case, since it is not necessary to transmit and receive the calculation result between the PE 110 and the CPU unit 120A, the wait instruction "wait" is not used. However, even in this case, while the calculation by the CPU 122 and the calculation instruction by the CPU unit 120A are being transferred, the PE 110 may be made to perform a calculation using another instruction sequence, and the wait instruction "wait" may be used to wait for the transfer of the calculation instruction.

[0059] As described above, it is possible to selectively determine the next operation instruction to be executed by the PE 110 based on the operation result of the PE 110 or the operation result of the CPU unit 120A, and to cause the PE 110 to execute the selected operation instruction.

[0060] Fig. 5 is a diagram showing an example of the operation of the processor 100A when the PE 110 in Fig. 4 is caused to selectively execute a plurality of processes. Fig. 5 shows an example of a control method for the processor 100A. Detailed description of instructions that are the same as or similar to the instructions shown in Fig. 3 will be omitted.

[0061] 5, when the branch destination of an instruction executed by the PE 110 is determined based on the calculation result of the PE 110, the PE 110 may first execute a multiplication instruction mult, which multiplies the values ​​of registers r1 and r2 of the register file 112 by the calculation unit 111 and stores the multiplication result in register r0 of the register file 112. This multiplication instruction corresponds to an instruction for determining a branch condition that is executed before a conditional branch instruction in a normal CPU or the like.

[0062] Next, the instruction supply circuit 102 may transfer data (branch condition) stored in the register r0 of the register file 112 to an area indicated by the address adr#0 of the local memory 123 of the CPU unit 120A based on a data movement instruction mv(tag#01) received from the host system 300 via the external interface circuit 101. The data transfer may be executed by a DMAC. The instruction supply circuit 102 may output tag#01 to the synchronization circuit 121 of the CPU unit 120A via the NoC 105 based on the data transfer by the data movement instruction mv(tag#01). The tag#01 included in the data movement instruction mv(tag#01) used for data movement from the PE 110 to the CPU unit 120 is an example of third synchronization information.

[0063] The CPU unit 120A may execute a wait instruction wait(tag#01) including tag#01, and suppress execution of subsequent instructions until tag#01 is received. The synchronization circuit 121 of the CPU unit 120 may permit the CPU 122 to execute a data movement instruction mv following the wait instruction wait(tag#01) based on the reception of tag#01. Using tag#01, the CPU unit 120A can wait for the branch condition, which is the multiplication result by the PE 110, to be stored in the local memory 123.

[0064] For example, the CPU unit 120A may execute a data movement instruction mv that moves a branch condition stored in the local memory 123 to a register r0 of the register file RF. Next, the CPU unit 120A may execute a data movement instruction mv that stores an address selected according to the value of the register r0 in the instruction entry address register 125A, and a data movement instruction mv that transfers a predetermined size of data from a storage area of ​​the system memory 310 indicated by the address stored in the instruction entry address register 125A to the PE 110. For example, the CPU unit 120A may issue a data transfer request to the DMAC and cause the DMAC to transfer data from the system memory 310 to the PE 110.

[0065] 5, when the value of register r0 is equal to or greater than "0", 1024 bytes of data (e.g., 1024 instructions) are transferred from a storage area at address 0x1000 (0x indicates hexadecimal) of system memory 310 to PE 110. When the value of register r0 is less than "0", 1024 bytes of data are transferred from a storage area at address 0x2000 of system memory 310 to PE 110. Note that any of three or more addresses may be selected depending on the value of register r0, and the data transfer size may be other than 1024 bytes.

[0066] The instruction transferred from address 0x1000 or address 0x2000 of the system memory 310 may be supplied to the instruction supply circuit 102. If the received instruction is an arithmetic instruction or a wait instruction "wait", the instruction supply circuit 102 may output the received instruction to the instruction distribution circuit 103. If the received instruction is a data movement instruction "mv", the instruction supply circuit 102 may cause the DMAC to execute data transfer. Then, the PE 110 may sequentially execute the instructions transferred from the system memory 310.

[0067] As described above, depending on the branch condition obtained by the operation by the PE 110, the CPU unit 120 can selectively transfer the operation instruction to be executed next by the PE 110 from the system memory 310 to the PE 110. As a result, the PE 110, which does not have an instruction fetch function and does not have a branch instruction execution function, can efficiently execute branch processing similar to that of a conditional branch instruction.

[0068] 5, when the branch destination of the instruction executed by the PE 110 is determined based on the calculation result of the CPU unit 120A, the CPU unit 120A may execute an add instruction "add" that adds the values ​​of registers r1 and r2 of the register file RF and stores the addition result in register r0 of the register file RF by the CPU 122. This add instruction corresponds to an instruction that determines the branch condition and is executed before a normal conditional branch instruction.

[0069] 5, the CPU unit 120A may execute a data movement instruction mv for storing an address selected according to the value of register r0 in the instruction entry address register 125A, and a data movement instruction mv for transferring a predetermined size of data (instruction) from a storage area of ​​the system memory 310 indicated by the address stored in the instruction entry address register 125A to the PE 110. The PE 110 may then sequentially execute the instructions transferred from the system memory 310.

[0070] As a result, CPU unit 120A can selectively transfer the next calculation instruction to be executed by PE 110 from system memory 310 to PE 110 depending on the branch condition for PE 110 obtained by calculation, thereby enabling PE 110 to efficiently perform branch processing similar to that of a conditional branch instruction.

[0071] As described above, in the embodiment shown in Figures 4 and 5, as in the embodiment shown in Figures 1 to 3, the heterogeneous PEs 110 and CPU units 120A mounted on the processor 100A can be synchronized with each other using tags, thereby enabling multiple processes to be executed in cooperation with each other, thereby improving the processing performance of the processor 100A.

[0072] Furthermore, in the embodiment shown in FIGS. 4 and 5, the PE 110 does not have an instruction fetch function and does not have a branch instruction execution function, so that branch processing similar to that of a conditional branch instruction can be efficiently performed.

[0073] Also, the CPU unit 120A may input a polling command instead of a wait command to wait for reception of a tag. By using the polling command, for example, the CPU unit 120A may periodically check with the PE 110 whether a necessary operation has been completed, and may process the subsequent command when it is confirmed that the necessary operation has been completed.

[0074] Fig. 6 is a block diagram showing an example of a processor configuration in another embodiment of the present invention. Circuits that are the same as or similar to those in Fig. 1 and Fig. 4 are given the same reference numerals, and detailed description is omitted. The processor 100B shown in Fig. 6 has the same configuration and function as the processor 100 in Fig. 1, except that it has an external interface circuit 101B, NoC 105B, and a CPU unit 120A instead of the external interface circuit 101, NoC 105, and CPU unit 120 in Fig. 1. The CPU unit 120A may be the same as the CPU unit 120A in Fig. 4.

[0075] NoC105B has the same configuration and function as NoC105 in Fig. 1, except that it has a function of transferring instructions to instruction supply circuit 102. Instruction supply circuit 102 has the same configuration and function as instruction supply circuit 102 in Fig. 1, except that it receives instructions from NoC105B.

[0076] The external interface circuit 101B may output to the NoC 105B all of the instructions read from the system memory 310 of the host system 300. In other words, the external interface circuit 101B may output to the NoC 105B the arithmetic instructions to be executed by the PE 110, and the wait instructions and data movement instructions issued by the host system 300.

[0077] However, in this embodiment, the instructions that NoC 105B receives from the host system 300 may be stored in advance in the external memory 200. That is, the instructions supplied to the instruction supply circuit 102 may be transferred from the external memory 200. For this reason, NoC 105B may have a transfer path for transferring the instructions received from the external memory 200 to the instruction supply circuit 102.

[0078] Fig. 7 is a diagram showing an example of the operation of the processor 100B when the PE 110 in Fig. 6 is caused to selectively execute a plurality of processes. Fig. 7 shows an example of a control method for the processor 100B. Detailed description of instructions that are the same as or similar to the instructions shown in Fig. 5 will be omitted. As described above, the processor 100B may read instructions to be executed by the PE 110 from the external memory 200.

[0079] The operation shown in Fig. 7 is similar to the operation shown in Fig. 5, except that in the last data movement instruction mv of the CPU instructions, data is transferred from the external memory 200 to the PE 110 via the memory controller 108. Therefore, in the example shown in Fig. 7, addresses 0x1000 and 0x2000 are addresses assigned to the external memory 200. Note that the CPU unit 120A may specify the external memory 200 as the transfer source address and issue a data transfer request to the DMAC.

[0080] When the value of register r0 is equal to or greater than "0", 1024 bytes of data may be transferred from a storage area at address 0x1000 in external memory 200 to PE 110. When the value of register r0 is less than "0", 1024 bytes of data may be transferred from a storage area at address 0x2000 in external memory 200 to PE 110. Note that any one of three or more addresses may be selected depending on the value of register r0, and the data transfer size does not have to be 1024 bytes.

[0081] For example, when the DMAC receives a data transfer request from the CPU unit 120A, it may issue a memory access request to the memory controller 108 and transfer data output from the external memory 200 (for example, an arithmetic instruction for the PE 110) to the PE 110.

[0082] As described above, in the embodiment shown in Figures 6 and 7, similarly to the embodiment shown in Figures 1 to 5, the different types of PE 110 and CPU unit 120A mounted on the processor 100B can be synchronized with each other using tags, thereby enabling a plurality of processes to be executed in cooperation with each other, thereby improving the processing performance of the processor 100B. Also, the PE 110, which does not have an instruction fetch function and does not have a branch instruction execution function, can efficiently execute branch processing similar to a conditional branch instruction.

[0083] Furthermore, even in the case shown on the right side of Fig. 7, while the calculation by the CPU 122 and the calculation instruction by the CPU unit 120A are being transferred, similarly to Fig. 4 and Fig. 5, the PE 110 may be caused to perform calculation using another instruction sequence, and the transfer of the calculation instruction may be waited for using the wait instruction. Also, the CPU unit 120A may not wait for the reception of a tag by the wait instruction, but may input a polling instruction instead. For example, the CPU unit 120A may periodically check with the PE 110 whether the necessary calculation has been completed by the polling instruction, and may process the subsequent instruction when it is confirmed that the necessary calculation has been completed.

[0084] Fig. 8 is a diagram showing another example of the instruction supply circuit 102 of Fig. 4 or Fig. 6. For example, the instruction supply circuit 102 shown in Fig. 4 and Fig. 6 may include an instruction buffer IBUFa or an instruction buffer IBUFb.

[0085] The instruction buffer IBUFa may have one FIFO (First-In First-Out) that can hold N+1 instructions. The instruction buffer IBUFb may have M+1 FIFOs that can hold a smaller number of instructions than the instruction buffer IBUFa, an input selector that selects the FIFO that stores instructions, an output selector that selects the FIFO from which instructions are taken out, and a selection register that operates the input selector and the output register. The input selector, output selector, and selection register are examples of a selection control circuit that selects the FIFO to input / output instructions into / from.

[0086] By providing either the instruction buffer IBUFa or IBUFb having a FIFO in the instruction supply circuit 102, it is possible to hold the branch destination instruction in advance. Therefore, it is possible to supply the instruction to the PE 110 more quickly than in the case where the instruction is transferred from the system memory 310 after the branch destination of the instruction is determined.

[0087] Furthermore, by providing the instruction supply circuit 102 with an instruction buffer IBUFb having multiple smaller sized FIFOs, it is possible to set the instruction buffer IBUFb to hold in advance the branch destination instructions of the number of instructions corresponding to the number of FIFOs. This reduces the probability that the branch destination instructions are not stored in the instruction buffer IBUFb even when there are multiple branch destinations of instructions. Note that in the instruction buffer IBUFb, the control of storing instructions in the FIFOs by the selection register and the control of taking out instructions from the FIFOs may be performed by the CPU unit 120A.

[0088] In the processor 100C shown in Fig. 10, the PE 110C has an instruction memory 115C that holds an instruction sequence, so that the instruction can be transferred in advance from the system memory 310. Therefore, even if the processor 100C does not have instruction buffers IBUFa and IBUFb, it is possible to suppress delays in supplying instructions to the PE 110C when the instruction branches. However, a FIFO-type instruction buffer may be provided in the instruction supply circuit 116C in Fig. 10.

[0089] FIG. 9 is a diagram showing an example of the operation of the processor when the instruction supply circuit 102 in FIG. 4 includes the instruction buffer IBUFb in FIG. 8. FIG. 9 shows an example of a control method for the processor 100 in FIG. 4 and the processor 100B in FIG. 6. Detailed explanations of instructions that are the same as or similar to the instructions shown in FIG. 5 are omitted. In the instructions shown in FIG. 9, the symbol ibuf.X indicates the X-th FIFO of the instruction buffer IBUFb, and the symbol ibuf.sel indicates a selection register for selecting the FIFO in the instruction buffer IBUFb. Also, "stop tag#X" indicates that tag#X is output to the synchronization circuit 121 of the CPU unit 120A when the stop instruction is executed. Other instructions are the same as those shown in FIG. 3, FIG. 5, and FIG. 11.

[0090] 9, when the branch destination of the instruction executed by PE110 is determined based on the calculation result of PE110, CPU unit 120A may execute a data movement instruction mv to transfer 64 instructions from the beginning of addresses 0x1000 and 0x2000, which are the branch destinations of the instruction by PE110, from system memory 310 of host system 300 to FIFO(0) and FIFO(1) of instruction buffer IBUFb, respectively, and cause the DMAC to execute the data transfer. After that, CPU unit 120A may execute a wait instruction wait(tag#01) to wait for reception of tag#01 from PE110.

[0091] The PE 110 may start executing instructions from address 0x0000, execute a multiplication instruction mult, and obtain a multiplication result that is a branch condition that determines a branch destination of the instruction executed by the PE 110. The instruction supply circuit 102 may transfer the multiplication result of the PE 110 to the local memory 123 of the CPU unit 120A using a data movement instruction mv(tag#01), and output tag#01 to the synchronization circuit 121 of the CPU unit 120A.

[0092] The CPU unit 120A, which has received tag#01 via the synchronization circuit 121, may execute the data movement instruction mv to move the multiplication result of the PE 110 held in the local memory 123 to the register r0. At this time, since the instruction sequence being executed by the PE 110 has not been completed, the CPU unit 120A may execute the wait instruction wait(tag#02) to wait for the execution of the instruction sequence by the PE 110 to be completed.

[0093] The PE 110 may execute a stop command stop(tag#02) based on the completion of the execution of the sequence of instructions to stop the execution of the instructions, and output tag#02 to the synchronization circuit 121 of the CPU unit 120A.

[0094] The synchronous circuit 121 of the CPU unit 120A may cancel the wait command wait(tag#02) based on the reception of tag#02. Then, the CPU unit 120A may store information for selecting a FIFO that will be the supply source of the next command to the PE 110 in a selection register of the command buffer IBUFb according to the multiplication result by the PE 110 held in the register r0.

[0095] Furthermore, the CPU unit 120A may execute a data movement instruction mv to store in the instruction entry address register 125A the start addresses of the remaining 960 instructions, excluding the 64 (0x40) instructions stored in the FIFO first, of the entire 1024 instructions in the instruction sequence executed by the PE 110, according to the multiplication result by the PE 110 held in the register r0. Then, the CPU unit 120A may execute a data movement instruction mv to transfer the remaining 960 instructions, excluding the 64 instructions stored in the FIFO first, of the entire 1024 instructions in the instruction sequence, from the system memory 310 of the host system 300 to the instruction supply circuit 102.

[0096] The instruction supply circuit 102 may sequentially supply the 960 instructions transferred from the system memory 310 to the currently selected FIFO according to the multiplication result. Here, the data movement command "mv pe" indicates that an instruction is to be supplied to the currently selected FIFO. As soon as it is confirmed that an instruction is stored in the currently selected FIFO, the instruction supply circuit 102 may resume the supply of instructions to the PE 110 that was stopped by the stop command stop(tag#02).

[0097] On the other hand, as shown on the right side of Figure 9, when the branch destination of the instruction executed by PE110 is determined based on the calculation result of CPU unit 120A, similar to the case where the branch destination is determined based on the calculation result of PE110, CPU unit 120A may transfer 64 instructions from the beginning of addresses 0x1000 and 0x2000, which are the branch destinations of the instruction by PE110, to FIFO(0) and FIFO(1) of instruction buffer IBUFb, respectively.

[0098] Thereafter, the CPU unit 120A may execute, for example, an addition instruction "add" to obtain a multiplication result that is a branch condition that determines the branch destination of the instruction executed by the PE 110. Then, the CPU unit 120A may execute a wait instruction "wait(tag#01)" to wait for reception of tag#01 from the PE 110.

[0099] The PE 110 may execute a stop command stop(tag#01) based on the completion of the execution of the sequence of instructions to stop the execution of the instructions, and output tag#01 to the synchronization circuit 121 of the CPU unit 120A.

[0100] The CPU unit 120A, which has received tag#01 via the synchronous circuit 121, may store information for selecting the FIFO that will be the source of the next instruction to the PE 110 in the selection register of the instruction buffer IBUFb, depending on the addition result held in the register r0.

[0101] Furthermore, the CPU unit 120A may execute a data movement instruction mv to store the leading addresses of the remaining 960 instructions, excluding the 64 (0x40) instructions stored in the FIFO first, of the entire 1024 instructions in the instruction sequence executed by the PE 110, in the instruction entry address register 125A according to the addition result (branch condition) held in the register r0. Then, the CPU unit 120A may execute a data movement instruction mv to transfer the remaining 960 instructions, excluding the 64 instructions stored in the FIFO first, of the entire 1024 instructions in the instruction sequence, from the system memory 310 of the host system 300 to the instruction supply circuit 102.

[0102] The instruction supply circuit 102 may sequentially supply the 960 instructions transferred from the system memory 310 to the currently selected FIFO according to the multiplication result. As soon as it is confirmed that an instruction is stored in the currently selected FIFO, the instruction supply circuit 102 may resume the supply of instructions to the PE 110 that was stopped by the stop command stop(tag#01).

[0103] In addition, by changing "host.sys_mem" in the instruction sequence shown in FIG. 9 to "mem.adr", it is possible to obtain an instruction sequence that indicates the operation when the instruction buffer IBUFb in FIG. 8 is provided in the instruction supply circuit 102 of the processor 100B in FIG.

[0104] Also, the CPU unit 120A may input a polling command instead of a wait command to wait for reception of a tag. By using the polling command, for example, the CPU unit 120A may periodically check with the PE 110 whether a necessary operation has been completed, and may process the subsequent command when it is confirmed that the necessary operation has been completed.

[0105] Fig. 10 is a block diagram showing an example of a processor configuration in another embodiment of the present invention. Circuits that are the same as or similar to those in Fig. 1 and Fig. 4 are given the same reference numerals, and detailed description will be omitted. The processor 100C shown in Fig. 10 may have an NoC 105C and multiple PEs 110C instead of the NoC 105 and PE 110 in Fig. 1. The processor 100C may also have multiple CPU units 120.

[0106] The processor 100C may have each PE 110C have the functions of the instruction supply circuit 102, the instruction distribution circuit 103, and the data movement synchronization circuit 104 of Fig. 1. The processor 100C may have a plurality of groups GR each including a PE 110C and a CPU unit 120. The PE 110C is an example of a first arithmetic unit. The instruction supply circuit 102 is an example of an instruction supply control circuit.

[0107] The connections between the external interface circuit 101, the network interface 106, the shared memory 107, and the memory controller 108 and the NoC 105C may be the same as those in Fig. 1. Instructions executed by the PE 110C and the CPU unit 120 may be transferred from the system memory 310 of the host system 300 or the external memory 200.

[0108] Each PE 110C includes an arithmetic unit 111, a register file 112, a local memory 113, an NoC interface 114, an instruction memory 115C, an instruction supply circuit 116C, a synchronization circuit 117C, and an instruction entry address register 118C. The instruction entry address register 118C may include an address area for holding the top address of a memory area of ​​the instruction memory 115C that holds an instruction sequence executed by the PE 110C, and a tag area for holding a tag. The instruction entry address register 118C may also have a queue structure (FIFO structure) including a plurality of entries having an address area and a tag area in which a pair of an address and a tag is held. Furthermore, the instruction entry address register 118C may be allocated to a part of the local memory 113. The instruction entry address register 118C is an example of an address register for holding a read address indicating the source of an instruction read from the instruction memory 115C.

[0109] For example, even if an address is stored in the instruction entry address register 118C, the instruction supply circuit 116C may continue to suppress reading of an instruction from the instruction memory 115C until the tag stored in the instruction entry address register 118C together with the address is received from the synchronization circuit 117C. Note that, if the tag number stored in the instruction entry address register 118C indicates that it is not necessary to wait for the tag to be received from the synchronization circuit 117C (for example, tag#00), the instruction supply circuit 116C may start reading of an instruction from the instruction memory 115C based on the address being stored in the instruction entry address register 118C. tag#00 is an example of invalid synchronization information. A tag other than tag#00 is an example of valid synchronization information.

[0110] The instruction memory 115C may hold in advance an instruction sequence (e.g., instruction sequence A and instruction sequence B, etc.) transferred from outside the PE 110C via the NoC 105C and the NoC interface 114. The instruction sequence A and the instruction sequence B may include an operation instruction to be executed by the operation unit 111.

[0111] When an address and an invalid tag are stored in the instruction entry address register 118C, the instruction supply circuit 116C may sequentially read out instructions included in the instruction sequence from a storage area of ​​the instruction memory 115C having the address stored in the instruction entry address register 118C as a top address. When an address and a valid tag are stored in the instruction entry address register 118C, the instruction supply circuit 116C may sequentially read out instructions included in the instruction sequence from a storage area of ​​the instruction memory 115C having the address stored in the instruction entry address register 118C as a top address, based on receiving a tag the same as the valid tag from the synchronization circuit 117C. The instruction supply circuit 116C may supply the read out instructions to the arithmetic unit 111 to execute the arithmetic operation.

[0112] 1, the instruction supply circuit 116C may suppress the supply of an arithmetic instruction following a wait instruction corresponding to a tag to the arithmetic unit 111 until the tag is received from the synchronization circuit 117C. The instruction supply circuit 116C may have a function of executing a data movement instruction, or may have a DMAC (not shown) having a function of executing a data movement instruction. The instruction supply circuit 116C may transmit a tag to the synchronization circuit 121 of the CPU unit 120 when the execution of a data movement instruction including a tag is completed.

[0113] The synchronization circuit 117C may output a tag received from the CPU unit 120 via the NoC 105C to the instruction supply circuit 116C, similar to the data movement synchronization circuit 104 in Fig. 1. The synchronization circuit 117C may also execute synchronization processing using a tag included in the instruction entry address register 118C. The operation using the tag included in the instruction entry address register 118C is described in Fig. 12.

[0114] Fig. 11 is a diagram showing an example of the operation of the processor 100C when the PE 110C in Fig. 10 is made to selectively execute a plurality of processes. Fig. 11 shows an example of a control method for the processor 100C. Detailed explanations of instructions that are the same as or similar to the instructions shown in Fig. 3 and Fig. 5 will be omitted. Note that before the operation of Fig. 11 is executed, an instruction may be stored in advance in the instruction memory 115C from the system memory 310 of the host system 300 or the external memory 200.

[0115] 11 shows an example in which the tag area of ​​the instruction entry address register 118C is not used and the instruction supply circuit 116C reads an instruction from the instruction memory 115C based on an address stored in the instruction entry address register 118C. When the tag area is not used, invalid tag information (tag#00) may be stored in the tag area of ​​the instruction entry address register 118C. An example in which the tag area of ​​the instruction entry address register 118C is used is shown in FIG.

[0116] As shown on the left side of FIG. 11, when the branch destination of the instruction executed by PE110C is determined based on the calculation result of PE110C, PE110C starts executing the instruction from address 0x0000, for example. PE110C may sequentially execute the multiplication instruction mult, the data movement instruction mv(tag#01), and the stop instruction stop held from address 0x0000 in the instruction memory 115C. For example, the multiplication instruction mult and the data movement instruction mv(tag#01) are the same as the multiplication instruction mult and the data movement instruction mv(tag#01) shown in FIG. 5. The tag#01 included in the data movement instruction mv(tag#01) used for data movement from PE110C to the CPU unit 120 is an example of first synchronization information.

[0117] The instruction supply circuit 116C may have a function of executing the data movement instruction mv read from the instruction memory 115C. The data movement instruction mv read from the instruction memory 115C by the instruction supply circuit 116C may be executed by a DMAC provided in each group GR.

[0118] The instruction supply circuit 116C may transfer the branch condition, which is the multiplication result held in register r0 of the register file 112, to the local memory 123 of the CPU unit 120 by the data movement instruction mv(tag#01), and transfer tag#01 to the synchronization circuit 121 of the CPU unit 120. The multiplication result and tag#01 may be transferred to the CPU unit 120 via the NoC interface 114 and NoC 105C. After this, the instruction supply circuit 116C may stop the execution of the instruction by the stop instruction stop.

[0119] 5, the CPU unit 120 may wait for reception of tag#01 from PE110C by a wait instruction wait(tag#01) including tag#01, and then execute a data movement instruction mv for reading the multiplication result (branch condition) by PE110C from local memory 123, and a data movement instruction mv for storing an address corresponding to the multiplication result by PE110C in the instruction entry address register 118C of PE110C. The two data movement instructions mv store the address of the branch destination corresponding to the branch condition in the instruction entry address register 118C.

[0120] The instruction supply circuit 116C may read an address from the instruction entry address register 118C based on the address stored in the instruction entry address register 118C. The instruction supply circuit 116C may sequentially read instructions from a storage area of ​​the instruction memory 115C having the read address as a top address, and supply the instructions to the arithmetic unit 111. For example, when the address is 0x1000, the instruction supply circuit 116C may supply a multiplication instruction mult included in the instruction sequence A held in the instruction memory 115C to the arithmetic unit 111 and have the arithmetic unit 111 execute the instruction. When the address is 0x2000, the instruction supply circuit 116C may supply an addition instruction add included in the instruction sequence B held in the instruction memory 115C to the arithmetic unit 111 and have the arithmetic unit 111 execute the instruction.

[0121] On the other hand, as shown on the right side of Figure 11, when the branch destination of the instruction executed by PE110C is determined based on the calculation result of the CPU unit 120, as in Figure 5, the CPU unit 120 may execute an addition instruction add, and execute a data movement instruction mv to store an address selected according to the branch condition for PE110C, which is the addition result, in the instruction entry address register 118C of PE110C.

[0122] The PE 110C may operate in the same manner as the operation shown on the left side of Fig. 11. For example, the PE 110C may start executing instructions from address 0x0000 and then stop the operation by a stop instruction stop. After that, the instruction supply circuit 116C may sequentially read instructions held at address 0x1000 or address 0x2000 of the instruction memory 115C based on the storage of the address in the instruction entry address register 118C by the CPU unit 120, and cause the arithmetic unit 111 to execute them.

[0123] As a result, the PE110C can selectively execute instructions without the CPU unit 120 transferring instructions from outside the processor 100C to the PE110C each time the instructions are executed by the PE110C. By providing the instruction memory 115C for holding instructions in the PE110C, the time from when an address is stored in the instruction entry address register 118C to when an instruction is supplied to the instruction supply circuit 116C can be significantly reduced compared to the case where the instruction memory 115C is not provided. As a result, even when the CPU unit 120 is used to selectively execute instructions by the PE110C, it is possible to suppress a decrease in the performance of the PE110C in executing instructions.

[0124] Also, the CPU unit 120 may input a polling command instead of a wait command to wait for reception of a tag. By using the polling command, for example, the CPU unit 120 may periodically check with the PE 110C whether a necessary operation has been completed, and may process the subsequent command when it is confirmed that the necessary operation has been completed.

[0125] Fig. 12 is a diagram showing another example of the operation of the processor 100C when the PE 110C in Fig. 10 is made to selectively execute a plurality of processes. Fig. 12 shows an example of a control method of the processor 100C. Detailed description of instructions that are the same as or similar to the instructions shown in Figs. 3, 5, and 11 will be omitted. In Fig. 12 as well, an instruction may be stored in advance in the instruction memory 115C from the system memory 310 of the host system 300 or the external memory 200 before the operation in Fig. 12 is executed.

[0126] Fig. 12 also shows an example in which the CPU unit 120 determines an instruction sequence to be executed by the PE 110C, as in Fig. 11. Fig. 12 also shows an example in which a tag held in the instruction entry address register 118C is used to delay the start of an operation by the PE 110C until data used in the operation of the PE 110C is transferred from the CPU unit 120 to the PE 110C.

[0127] 12, when using the tag of the instruction entry address register 118C, for example, the PE 110C may first start executing instructions from address 0x0000 and stop the execution of the instructions by a stop command stop. In this embodiment, the instruction supply circuit 116C of the PE 110C continues to inhibit reading of instructions from address 0x1000 of the instruction memory 115C until a valid tag is received from the synchronization circuit 117C, even if an address is stored in the instruction entry address register 118C.

[0128] After determining the instruction sequence to be executed by the PE 110C, the CPU unit 120 may execute the data movement instruction mv and store the address 0x1000 of the instruction memory 115C where the determined instruction sequence is held in the instruction entry address register 118C. The CPU unit 120 may also execute the data movement instruction mv and store the tag number 0x01 in the tag area of ​​the instruction entry address register 118C.

[0129] Thereafter, the CPU unit 120 may sequentially execute the addition instruction add and a data movement instruction mv(tag#01) for transferring the addition result to the local memory 113 of the PE 110C, and transfer the tag#01 to the synchronization circuit 117C of the PE 110C via the NoC 105C. The tag#01 included in the data movement instruction mv(tag#01) used for data movement from the CPU unit 120 to the PE 110C is an example of second synchronization information.

[0130] The instruction supply circuit 116C of the PE 110C may sequentially read instructions from address 0x1000 of the instruction memory 115C and execute the read instructions based on receiving tag#01 that is the same as tag#01 held in the instruction entry address register 118C via the synchronization circuit 117C. For example, the instruction supply circuit 116C may execute a data movement instruction mv that moves data transferred from the CPU unit 120 to address adr#0 of the local memory 113 to register r1 of the register file 112, and then execute a multiplication instruction mult.

[0131] On the other hand, as shown on the right side of FIG. 12, when the instruction entry address register 118C has a queue structure, for example, the PE 110C may first start executing instructions from address 0x0000, and stop the execution of the instructions by a stop instruction stop.

[0132] After determining the instruction sequence to be executed by the PE 110C as the first branch destination, the CPU unit 120 may sequentially execute the push instruction "push" and store the address 0x1000 and tag#00 of the instruction memory 115C in which the determined instruction sequence is held in the instruction entry address register 118C. The push instruction "push" is an instruction that stores an address and a tag in the instruction entry address register 118C of the queue structure. The tag#00 is an invalid tag indicating that the instruction supply circuit 116C does not wait for a tag from the synchronization circuit 117C.

[0133] After determining the instruction sequence to be executed by the PE 110C as the next branch destination, the CPU unit 120 may execute the push instruction "push" in sequence and store the address 0x2000 of the instruction memory 115C where the determined instruction sequence is held and tag#01 in the instruction entry address register 118C. tag#01 is a valid tag indicating that the instruction supply circuit 116C should inhibit reading of instructions from the instruction memory 115C until it receives tag#01 from the synchronization circuit 117C.

[0134] The PE 110C may start executing an instruction from address 0x0000, and stop the execution of the instruction by a stop instruction stop. After that, the PE 110C immediately reads an instruction from a storage area of ​​the instruction memory 115C having the address 0x1000 held in the instruction entry address register 118C as a top address, based on the storage of the address 0x1000 and tag#00 indicating no tag wait in the instruction entry address register 118C by the CPU unit 120. The PE 110C may execute the read instruction (for example, a multiplication instruction mult), and then stop the operation by a stop instruction stop.

[0135] The CPU unit 120 may sequentially execute the addition instruction add and a data movement instruction mv(tag#01) for transferring the addition result to the local memory 113 of the PE 110C, and transfer the tag#01 to the synchronous circuit 117C of the PE 110C via the NoC 105C.

[0136] Although not shown in the figure, when tag tag#01 held in pair with address 0x2000 in instruction entry address register 118C matches tag#01 received via synchronization circuit 117C, PE110C may sequentially read instructions from a memory area of ​​instruction memory 115C whose top address is address 0x2000 held in instruction entry address register 118C, and execute the read instructions.

[0137] As described above, in FIG. 12, the execution of an instruction to be executed by PE110C can be delayed by using not only the tag included in the data movement instruction mv but also the tag stored in the instruction entry address register 118C, and PE110C can be selectively executed from a sequence of multiple instructions held in the instruction memory 115C.

[0138] As described above, in the embodiment shown in Figures 10 to 12, similarly to the embodiment shown in Figures 1 to 7, the different types of PE 110C and CPU unit 120 mounted on the processor 100C can be synchronized with each other using tags, thereby enabling a plurality of processes to be executed in cooperation with each other, thereby improving the processing performance of the processor 100C. Also, the PE 110C, which does not have an instruction fetch function and does not have a branch instruction execution function, can efficiently execute branch processing similar to a conditional branch instruction.

[0139] 10 to 12, even when the instruction entry address register 118C is provided in the PE 110C, the PE 110C and the CPU unit 120 can execute a plurality of processes in cooperation with each other, and the PE 110C can efficiently execute branch processes similar to those of a conditional branch instruction. Also, by providing a tag area in which a valid tag or an invalid tag is stored in the instruction entry address register 118C, it is possible to execute an instruction from a branch destination not only after waiting for a tag, but also without waiting for a tag.

[0140] Fig. 13 is a block diagram showing an example of a hardware configuration of a computer equipped with the processor 100 shown in Fig. 1. The processor 100 shown in Fig. 13 may be replaced with the processor 100A shown in Fig. 4, the processor 100B shown in Fig. 6, or the processor 100C shown in Fig. 10. In Fig. 13, the computer may be realized as a computer 500 including the processor 100, a main storage device 30 (memory), an auxiliary storage device 40 (memory), a network interface 50, and a device interface 60, which are connected via a bus 510. For example, the main storage device 30 may be the external memory 200 shown in Fig. 1.

[0141] The computer 500 in FIG. 13 includes one of each component, but may include multiple of the same components. Although one computer 500 is shown in FIG. 13, the software may be installed in multiple computers, and each of the multiple computers may execute the same or different parts of the software. In this case, a distributed computing form may be used in which each computer communicates via a network interface 50 or the like to execute the process. In other words, a system may be configured in which one or multiple computers 500 execute instructions stored in one or multiple storage devices to realize a function. Also, a configuration may be used in which information transmitted from a terminal is processed by one or multiple computers 500 provided on a cloud, and the processing results are transmitted to the terminal.

[0142] Various calculations may be executed in parallel using one or more processors 100 mounted on the computer 500, or using multiple computers 500 via a network. Various calculations may be distributed to multiple computing cores in the processor 100 and executed in parallel. Some or all of the processes, means, etc. disclosed herein may be realized by at least one of a processor and a storage device provided on a cloud that can communicate with the computer 500 via a network. In this way, each device in the above-mentioned embodiment may be in the form of parallel computing using one or more computers.

[0143] The processor 100 may be an electronic circuit (processing circuit, processing circuitry, CPU, GPU, FPGA, ASIC, etc.) that at least controls a computer or performs calculations. The processor 100 may be a general-purpose processor, a dedicated processing circuit designed to perform a specific calculation, or a semiconductor device that includes both a general-purpose processor and a dedicated processing circuit. The processor 100 may include an optical circuit, or may include a calculation function based on quantum computing.

[0144] The processor 100 may perform arithmetic processing based on data or software input from each device or the like in the internal configuration of the computer 500, and may output arithmetic results or control signals to each device or the like. The processor 100 may control each component constituting the computer 500 by executing the OS (Operating System) of the computer 500, applications, or the like.

[0145] The main memory device 30 may store instructions executed by the processor 100 and various data, and information stored in the main memory device 30 may be read by the processor 100. The auxiliary memory device 40 is a memory device other than the main memory device 30. Note that these memory devices refer to any electronic components capable of storing electronic information, and may be semiconductor memories. The semiconductor memories may be either volatile or non-volatile memories. A memory device for saving various data, etc. in the computer 500 may be realized by the main memory device 30 or the auxiliary memory device 40, or may be realized by an internal memory built into the processor 100.

[0146] When the computer 500 is configured with at least one storage device (memory) and at least one processor 100 connected (coupled) to the at least one storage device, at least one processor 100 may be connected to one storage device. At least one storage device may be connected to one processor 100. A configuration may also be included in which at least one processor 100 of the multiple processors 100 is connected to at least one storage device of the multiple storage devices. This configuration may also be realized by storage devices and processors 100 included in multiple computers 500. Furthermore, a configuration may also be included in which a storage device is integrated with the processor 100 (for example, a cache memory including an L1 cache and an L2 cache).

[0147] The network interface 50 is an interface for connecting to the communication network 600 wirelessly or by wire. The network interface 50 may be an appropriate interface, such as one conforming to an existing communication standard. The network interface 50 may exchange information with an external device 710 connected via the communication network 600. The communication network 600 may be any one of a wide area network (WAN), a local area network (LAN), a personal area network (PAN), etc., or a combination thereof, as long as information is exchanged between the computer 500 and the external device 710. An example of a WAN is the Internet, an example of a LAN is IEEE802.11 or Ethernet (registered trademark), and an example of a PAN is Bluetooth (registered trademark) or Near Field Communication (NFC).

[0148] The device interface 60 is an interface such as a USB that directly connects to an external device 720 .

[0149] The external device 710 is a device connected to the computer 500 via a network. The external device 720 is a device connected directly to the computer 500.

[0150] The external device 710 or the external device 720 may be, for example, an input device. The input device is, for example, a device such as a camera, a microphone, a motion capture device, various sensors, a keyboard, a mouse, a touch panel, or the like, and provides acquired information to the computer 500. Alternatively, the input device may be a device equipped with an input unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0151] Moreover, the external device 710 or the external device 720 may be, for example, an output device. The output device may be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) panel, or may be a speaker that outputs sound or the like. Alternatively, the output device may be a device including an output unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0152] Furthermore, the external device 710 or the external device 720 may be a storage device (memory). For example, the external device 710 may be a network storage or the like, and the external device 720 may be a storage device such as an HDD.

[0153] Furthermore, the external device 710 or the external device 720 may be a device having some of the functions of the components of the computer 500. In other words, the computer 500 may transmit some or all of the processing results to the external device 710 or the external device 720, or may receive some or all of the processing results from the external device 710 or the external device 720.

[0154] In this specification (including the claims), when the expression "at least one of a, b, and c" or "at least one of a, b, or c" (including similar expressions) is used, it includes any of a, b, c, ab, ac, bc, or abc. It may also include multiple instances of any element, such as aa, abb, aabbcc, etc. Furthermore, it also includes the addition of elements other than the enumerated elements (a, b, and c), such as having d, as in abcd.

[0155] In this specification (including claims), when expressions such as "using data as input / based on / according to / in response to data" (including similar expressions) are used, unless otherwise specified, this includes the use of data itself or data that has been processed in some way (e.g., data with noise added, normalized, feature values ​​extracted from data, intermediate representations of data, etc.). In addition, when it is stated that a result is obtained "using data as input / based on / according to / in response to data" (including similar expressions), unless otherwise specified, this includes the use of the result based only on the data, or the use of the result influenced by other data, factors, conditions, and / or states other than the data. In addition, when it is stated that "data is output" (including similar expressions), unless otherwise specified, this includes the use of data itself as output, or data that has been processed in some way (e.g., data with noise added, normalized, feature values ​​extracted from data, intermediate representations of various data, etc.) as output.

[0156] In this specification (including the claims), the terms "connected" and "coupled" are intended as open-ended terms including any of direct connection / coupling, indirect connection / coupling, electrically connection / coupling, communicatively connection / coupling, functionally connection / coupling, physically connection / coupling, etc. The terms should be interpreted appropriately depending on the context in which the terms are used, but any connection / coupling form that is not intentionally or naturally excluded should be interpreted as being included in the terms without any restriction.

[0157] In this specification (including the claims), when the expression "A configured to B" is used, it may include that the physical structure of element A has a configuration capable of performing operation B, and that the permanent or temporary setting / configuration of element A is configured / set to actually perform operation B. For example, when element A is a general-purpose processor, it is sufficient that the processor has a hardware configuration capable of performing operation B, and is configured to actually perform operation B by setting a permanent or temporary program (instruction). Also, when element A is a dedicated processor, dedicated arithmetic circuit, etc., it is sufficient that the circuit structure, etc. of the processor is implemented to actually perform operation B, regardless of whether control instructions and data are actually attached.

[0158] In this specification (including the claims), when terms implying containing or possessing (e.g., "comprising / including," "having," etc.) are used, they are intended to be open-ended terms that include cases in which the term contains or possesses things other than the object indicated by the object of the term. When the object of such terms implying containing or possessing does not specify a quantity or suggests a singular number (such as an expression using the article "a" or "an"), the expression should be construed as not being limited to a specific number.

[0159] In this specification (including the claims), even if expressions such as "one or more" and "at least one" are used in some places and expressions that do not specify a quantity or suggest a singular number (expressions using the articles "a" or "an") are used in other places, the latter expressions are not intended to mean "one." In general, expressions that do not specify a quantity or suggest a singular number (expressions using the articles "a" or "an") should be interpreted as not necessarily being limited to a specific number.

[0160] In this specification, when a particular advantage / result is described as being obtained from a particular configuration of an embodiment, it should be understood that the same effect can also be obtained from one or more other embodiments having the same configuration, unless there is a reason to the contrary. However, it should be understood that the presence or absence of the effect generally depends on various factors, conditions, and / or states, and that the effect is not necessarily obtained by the configuration. The effect is merely obtained by the configuration described in the embodiment when various factors, conditions, and / or states are satisfied, and the effect is not necessarily obtained in the invention according to the claim that specifies the configuration or a similar configuration.

[0161] In this specification (including claims), when a plurality of pieces of hardware perform a predetermined process, each piece of hardware may cooperate to perform the predetermined process, or a portion of the hardware may perform all of the predetermined process. Also, a portion of the hardware may perform a portion of the predetermined process, and another piece of hardware may perform the remainder of the predetermined process. In this specification (including claims), when an expression such as "one or more pieces of hardware perform a first process, and the one or more pieces of hardware perform a second process" (including similar expressions) is used, the hardware performing the first process and the hardware performing the second process may be the same or different. In other words, it is sufficient that the hardware performing the first process and the hardware performing the second process are included in the one or more pieces of hardware. The hardware may include an electronic circuit, a device including an electronic circuit, and the like.

[0162] In this specification (including the claims), when multiple storage devices (memories) store data, each of the multiple storage devices may store only a portion of the data, or may store the entire data. Also, a configuration in which only some of the multiple storage devices store data may be included.

[0163] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-mentioned individual embodiments. Various additions, modifications, replacements, partial deletions, etc. are possible within the scope of the conceptual idea and intent of the present invention derived from the contents defined in the claims and their equivalents. For example, in the above-mentioned embodiments, when numerical values ​​or formulas are used for explanation, these are shown for illustrative purposes and do not limit the scope of the present disclosure. In addition, the order of each operation shown in the embodiment is also illustrative and does not limit the scope of the present disclosure. [Explanation of symbols]

[0164] 30 Main memory 40 Auxiliary storage 50 Network Interface 60 Device Interfaces 100, 100A, 100B, 100C Processors 101, 101B External interface circuit 102 Instruction supply circuit 103 Instruction distribution circuit 104 Data transfer synchronous circuit 105, 105B, 105C NoC 106 Network Interface 107 Shared Memory 108 Memory Controller 110, 110C PE 111 Calculation Unit 112 Register File 113 Local Memory 114 NoC Interface 115C Instruction Memory 116C instruction supply circuit 117C synchronous circuit 118C Instruction Entry Address Register 120, 120A CPU unit 121 Synchronous Circuit 122 CPU 123 Local Memory 124 NoC Interface 125A Instruction Entry Address Register 200 External Memory 300 Host System 310 System Memory 500 Computers 510 Bus 600 Communication Network 710, 720 External device GR Group IbUFa, IBUFb Instruction buffer

Claims

1. a first processor that executes a first instruction; a second arithmetic unit that executes a second instruction and a third instruction, the first calculation unit executes the first instruction to calculate first data; the second arithmetic unit executes the third instruction using the first data based on the issuance of the first synchronization information by the first arithmetic unit after suspending the execution of the third instruction based on the second instruction which is an instruction to wait for the issuance of first synchronization information. Processor.

2. The first arithmetic unit has an instruction supply control circuit, the second calculation unit calculates second data by executing the third instruction; the instruction supply control circuit stops supplying a fifth instruction to the first arithmetic unit based on a fourth instruction that is an instruction to wait for issuance of second synchronization information, and then supplies the fifth instruction, which uses the second data, to the first arithmetic unit based on the issuance of the second synchronization information. The processor of claim 1 .

3. The first arithmetic unit has an instruction supply control circuit, the second calculation unit has an address register for holding a read address of an instruction from a storage device; the second calculation unit stores an address selected according to the first data in the address register based on the issuance of the first synchronization information; the instruction supply control circuit reads a fourth instruction from a memory area of ​​the memory device indicated by the address stored in the address register; the instruction supply control circuit supplies the fourth instruction read from the memory area to the first arithmetic unit; The processor of claim 1 .

4. The first arithmetic unit has an instruction supply control circuit, the second calculation unit has an address register for holding a read address of an instruction from a storage device; the second calculation unit stores an address selected according to third data calculated by the calculation in the address register; the instruction supply control circuit reads a fourth instruction from a memory area of ​​the memory device indicated by the address stored in the address register; the instruction supply control circuit supplies the fourth instruction read from the memory area to the first arithmetic unit; The processor of claim 1 .

5. the instruction supply control circuit has an instruction buffer including a FIFO for holding instructions read from the storage device; A processor according to claim 3 or claim 4.

6. the instruction supply control circuit has an instruction buffer including a plurality of FIFOs for holding instructions read from the storage device, and a selection control circuit for selecting a FIFO for inputting and outputting instructions; A processor according to claim 3 or claim 4.

7. the second command is a wait command or a polling command; A processor according to any one of claims 1 to 4.

8. a first arithmetic unit including an instruction memory, a first arithmetic unit that executes a first instruction stored in the instruction memory, an instruction supply control circuit that supplies the first arithmetic unit with the first instruction, and an address register that holds a read address of an instruction from the instruction memory; a second arithmetic unit that executes a second instruction and a third instruction, the first calculation unit calculates first data by executing the first instruction; the second arithmetic unit stores an address selected according to the first data in the address register based on the issuance of the first synchronization information after stopping the execution of the third instruction based on the second instruction which is an instruction to wait for the issuance of first synchronization information; the instruction supply control circuit reads the first instruction from a memory area of ​​the instruction memory indicated by the address stored in the address register based on the address stored in the address register, and supplies the read first instruction to the first arithmetic unit; Processor.

9. the address register has an area for storing synchronization information; the instruction supply control circuit, based on reception of synchronization information that matches the synchronization information held in the address register, reads an instruction from a storage area of ​​the instruction memory indicated by an address stored in the address register, and supplies the read instruction to the first arithmetic unit; The processor of claim 8.

10. The address register has a FIFO structure having a plurality of areas for storing addresses and synchronization information. The processor of claim 8.

11. A method for controlling a processor having a first arithmetic unit that executes a first instruction and a second arithmetic unit that executes a second instruction and a third instruction, comprising: the first calculation unit executes the first instruction to calculate first data; the second arithmetic unit executes the third instruction that uses the first data based on the issuance of the first synchronization information by the first arithmetic unit after suspending execution of the third instruction based on a second instruction that is an instruction to wait for issuance of first synchronization information; How the processor is controlled.

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