Memory system and host device

Abstract

To simplify logical-physical conversion processing by a memory controller to improve read performance.SOLUTION: When an area designating command, with one or more contiguous local addresses and a data size added, is received from a host device, a controller according to an embodiment sets a designated area for the data size having contiguous physical addresses in the storage area of memory, and causes a storage unit to store first address conversion information in which the beginning physical address of the contiguous physical addresses is linked to the beginning logical address of the contiguous logical addresses and the data size. When a read command, with the logical addresses corresponding to data in the designated area added, is received from the host device, the physical addresses offset from the beginning physical address of the first address conversion information are identified as physical addresses corresponding to the logical addresses added to the read command on the basis of the logical addresses added to the read command.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a memory system and a host device. [Background technology]

[0002] The memory system includes, for example, a non-volatile semiconductor memory and a memory controller that controls the semiconductor memory. When the memory controller receives a read command with a logical address from a host device, the memory controller refers to a logical-physical conversion table to convert the logical address from the host device into a physical address of the data to be read, and identifies the read destination in the semiconductor memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-237668 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a memory system and a host device capable of improving read performance by simplifying logical-physical conversion processing by a memory controller. [Means for solving the problem]

[0005] The memory system of the embodiment comprises a non-volatile memory, and a controller having a host interface and a storage unit and controlling the memory. When the controller receives an area designation command from a host device, which is assigned one or more consecutive logical addresses and a data size, the controller sets a designated area of ​​the data size having consecutive physical addresses within the storage area of ​​the memory, and stores first address conversion information in the storage unit, in which the first physical address of the consecutive physical addresses is linked to the first logical address of the consecutive logical addresses and the data size. When the controller receives a read command from the host device, which is assigned a logical address corresponding to data in the designated area, the controller identifies a physical address offset from the first physical address of the first address conversion information based on the logical address assigned to the read command as the physical address corresponding to the logical address assigned to the read command. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an information processing system according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of one block included in the memory cell array according to the first embodiment. [Diagram 3] 4 is a schematic diagram showing an example of a correspondence relationship between data in a logical address space and data in a physical address space in the memory system according to the first embodiment; [Figure 4] FIG. 2 is a schematic diagram for explaining an example of the operation of the information processing system according to the first embodiment. [Diagram 5] FIG. 2 is a schematic diagram for explaining an example of the operation of the information processing system according to the first embodiment. [Figure 6] FIG. 2 is a schematic diagram for explaining an example of the operation of the information processing system according to the first embodiment. [Figure 7] FIG. 2 is a schematic diagram for explaining an example of the operation of the information processing system according to the first embodiment. [Figure 8] FIG. 2 is a schematic diagram for explaining an example of the operation of the information processing system according to the first embodiment. [Figure 9] FIG. 2 is a schematic diagram for explaining an example of the operation of the information processing system according to the first embodiment. [Figure 10] FIG. 4 is a sequence diagram showing an example of a processing procedure in the information processing system according to the first embodiment. [Figure 11] FIG. 4 is a flowchart showing an example of a procedure of a write process of the memory controller according to the first embodiment. [Figure 12] FIG. 4 is a flowchart showing an example of a procedure of a read process of the memory controller according to the first embodiment. [Figure 13] FIG. 11 is a schematic diagram for explaining an example of the operation of the information processing system according to the second embodiment. [Figure 14] FIG. 11 is a schematic diagram for explaining an example of the operation of the information processing system according to the second embodiment. [Figure 15] FIG. 11 is a schematic diagram for explaining an example of the operation of the information processing system according to the second embodiment. [Figure 16] FIG. 11 is a sequence diagram showing an example of a processing procedure in the information processing system according to the second embodiment. [Figure 17] FIG. 11 is a flowchart showing an example of a procedure for setting a designated area of ​​a memory controller according to the second embodiment. [Figure 18] FIG. 13 is a flowchart showing an example of a procedure for setting a designated area of ​​a memory controller according to a first modification of the second embodiment; [Figure 19] FIG. 13 is a sequence diagram showing an example of a processing procedure in an information processing system according to a second modification of the second embodiment. [Figure 20] FIG. 13 is a sequence diagram showing another example of the processing procedure in the information processing system according to the second modification of the second embodiment. [Figure 21] FIG. 11 is a schematic diagram for explaining an example of the operation of the information processing system according to the third embodiment. [Figure 22] FIG. 11 is a schematic diagram for explaining an example of the operation of the information processing system according to the third embodiment. [Diagram 23] FIG. 11 is a sequence diagram showing an example of a processing procedure in an information processing system according to a third embodiment. [Figure 24]FIG. 11 is a flowchart showing an example of a procedure for setting a designated area of ​​a memory controller according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, configurations according to the embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0008] [Embodiment 1] Hereinafter, the first embodiment will be described in detail with reference to the drawings.

[0009] (Configuration example of memory system and host device) 1 is a diagram showing an example of a configuration of an information processing system 1000 according to the first embodiment. The information processing system 1000 according to the first embodiment includes a memory system 1 and a host device 2.

[0010] The memory system 1 is connected to a host device 2 and functions as an external storage device for the host device 2. The host device 2 can issue access commands to the memory system 1. The access commands include write commands that request writing of data and read commands that request reading of data. The host device 2 issues these access commands to the memory system 1 by adding a logical address, which is data location information, to the access commands.

[0011] Any interface standard can be adopted as the communication interface standard between the memory system 1 and the host device 2. Examples of interface standards that can be adopted include the UFS UFS Host Performance Booster (HPB) standard applied to UFS (Universal Flash Storage), the SCSI (Small Computer System Interface) standard, the SAS (Serial Attached SCSI) standard, the PCI Express standard, and the SATA (Serial ATA) standard.

[0012] The memory system 1 and the host device 2 may have a one-to-one correspondence as in the example of Fig. 1, or may have a multi-to-one correspondence. In other words, a plurality of memory systems 1 may be connected to the host device 2.

[0013] The memory system 1 includes a memory controller 10 and a NAND memory 11, which is a NAND type flash memory. The NAND memory 11 functions as a storage. However, as the storage, a type of memory other than the NAND type flash memory can also be adopted. Examples of memories other than the NAND type include a NOR type flash memory, a ReRAM (Resistance Random Access Memory), an MRAM (Magnetoresistive Random Access Memory), and a magnetic disk.

[0014] The NAND memory 11 includes a memory cell array 16. The memory cell array 16 includes a plurality of blocks that are units for erasing data. Each block includes a plurality of pages that are units for writing and reading data. The detailed configuration of the NAND memory 11 will be described later.

[0015] The memory controller 10 executes control of all operations of the memory system 1, including data transfer between the host device 2 and the NAND memory 11. The memory controller 10 includes an interface (I / F) unit 12, a processing unit 13, a NAND control unit 14, and a storage unit 15. Some or all of the I / F unit 12, the processing unit 13, and the NAND control unit 14 can be realized by software, hardware, or a combination thereof. "A component is realized by software" means that in a computer having a CPU (Central Processing Unit) and a memory that stores a program in advance, the CPU realizes the functions of the component according to the program.

[0016] The I / F unit 12 controls communication between the host device 2 and the memory controller 10. For example, the I / F unit 12 transfers an access command from the host device 2 to the NAND control unit 14, and performs operation settings of the memory controller 10 in response to a setting request from the host device 2. The above functions of the I / F unit 12 are realized, for example, by an I / F circuit that operates under the control of a CPU that is executing a program.

[0017] The NAND control unit 14 executes access to the NAND memory 11 in response to an access command received from the I / F unit 12. Specifically, the NAND control unit 14 writes data to the NAND memory 11 in response to a write command. Also, the NAND control unit 14 reads data from the NAND memory 11 in response to a read command.

[0018] As described above, the host device 2 assigns logical addresses to the data and issues these access commands to the memory controller 10. Meanwhile, the memory controller 10 assigns physical addresses to the storage areas of the NAND memory 11 to manage the data in the NAND memory 11.

[0019] The processing unit 13 performs a logical-physical conversion process to convert these logical addresses and physical addresses into each other and identify the data. For example, when specific data is written to the NAND memory 11 in accordance with a write command, the processing unit 13 manages the logical address given to the write command in association with the physical address of the data write destination in the NAND memory 11. The processing unit 13 also converts the logical address given to the read command into a physical address and identifies the data read destination in the NAND memory 11.

[0020] The logical-physical conversion process by the processing unit 13 is executed by referring to a logical-physical conversion table 111 that has a one-to-one correspondence between logical addresses and physical addresses. The logical-physical conversion table 111 is generated, for example, for each page. Therefore, the logical-physical conversion table 111 may have a large capacity because it contains information corresponding to a wide area spanning multiple pages of the storage area of ​​the NAND memory 11, and is stored, for example, in the memory cell array 16 of the NAND memory 11. When writing and reading data, the memory controller 10 appropriately loads the logical-physical conversion table 111 from the NAND memory 11 and performs processing.

[0021] However, for some read commands, address conversion information 101 having a smaller capacity than the logical-physical conversion table 111 may be referenced instead of the logical-physical conversion table 111. Since the address conversion information 101 has a sufficiently small capacity, it is stored in the storage unit 15 of the memory controller 10. The detailed configuration of the address conversion information 101 will be described later.

[0022] The processing unit 13 is, for example, the above-mentioned CPU, that is, a processor, and the above-mentioned functions of the processing unit 13 are realized, for example, by the CPU executing a program.

[0023] The storage unit 15 is composed of a register or a memory. Any type of memory can be used as the storage unit 15. For example, a dynamic random access memory (DRAM) or a static random access memory (SRAM) can be used as the memory of the storage unit 15. The address conversion information 101 described above is held in a constantly expanded state on the storage unit 15, which is a DRAM or an SRAM.

[0024] The host device 2 is a computer such as a personal computer, a server, a portable information device, or an AV device. For example, an OS (Operating System) and one or more applications are executed in the host device 2. The host device 2 includes an I / F unit 22, a processing unit 23, an access unit 24, and a storage unit 25. Some or all of the I / F unit 22, the processing unit 23, the access unit 24, and the storage unit 25 can be realized by software, hardware, or a combination thereof.

[0025] The I / F unit 22 controls communication between the memory system 1 and the host device 2. For example, the I / F unit 22 transmits an access command from the host device 2 to the memory controller 10, and enables data exchange between the host device 2 and the memory controller 10. The above functions of the I / F unit 22 are realized by an I / F circuit that operates under the control of a CPU that is executing a program, for example. The CPU here is a CPU provided in the host device 2 configured as a computer, for example.

[0026] The host device 2 of the first embodiment can issue an area designation command to the memory controller 10 in addition to a write command, a read command, etc. The area designation command is a command for causing the memory controller 10 to reserve a predetermined area in the storage area of ​​the NAND memory 11. That is, the area designation command allows the host device 2 to designate a predetermined area in the NAND memory 11 via the memory controller 10. The area designation command may be included in the access command. The I / F unit 22 transmits the area designation command from the host device 2 to the memory controller 10.

[0027] The processing unit 23 manages logical addresses to be assigned to access commands such as write commands and read commands. The logical addresses are assigned as serial numbers to management units for managing data in units of a predetermined size, such as 4 kB. As described above, the logical address is location information used by the host device 2 to specify the location of data in the memory system 1. The address space realized by the logical addresses is also called the logical address space. The logical address space is provided from the memory system 1 to the host device 2.

[0028] As described above, a physical address is location information that the memory controller 10 uses to specify the location of data in the NAND memory 11, and an address space realized by the physical address is also called a physical address space.

[0029] The processing unit 23 also manages logical addresses to be assigned to area designation commands. The area designation commands are assigned logical addresses corresponding to data that occupies a wide area of ​​the address space and is not frequently rewritten, such as an OS, or data that requires high-speed access. Occupying a wide area of ​​the address space means large-capacity data in gigabyte units, for example. The processing unit 23 determines the timing of issuing the area designation command and selects the logical address to be assigned to the area designation command.

[0030] The processing unit 23 is, for example, a CPU, that is, a processor, of the host device 2, and the above-mentioned functions of the processing unit 23 are realized, for example, by the CPU executing a program.

[0031] The storage unit 25 is configured by a register or a memory. Any type of memory can be adopted as the storage unit 25. As the memory of the storage unit 25, for example, a volatile memory such as a DRAM or an SRAM can be adopted.

[0032] Next, a detailed configuration of the memory cell array 16 of the NAND memory 11 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the configuration of one block included in the memory cell array 16 according to the first embodiment.

[0033] As shown in FIG. 2, each block includes (q+1) NAND strings arranged in order along the X direction, where q is an integer equal to or greater than 0. The select transistor ST1 included in each of the (q+1) NAND strings has a drain connected to one of the bit lines BL0 to BLp and a gate commonly connected to a select gate line SGD, where p is an integer equal to or greater than 1. The select transistor ST2 has a source commonly connected to a source line SL and a gate commonly connected to a select gate line SGS.

[0034] Each memory cell transistor MT is composed of, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a stacked gate structure formed on a semiconductor substrate. The stacked gate structure includes a charge storage layer (e.g., a nitride film (SiN) or a floating gate, etc.) formed on the semiconductor substrate with a tunnel oxide film interposed therebetween, and a control gate electrode formed on the charge storage layer with an inter-gate insulating film interposed therebetween. The threshold voltage of the memory cell transistor MT changes depending on the number of electrons stored in the charge storage layer, and data is stored depending on the difference in this threshold voltage. That is, the memory cell transistor MT holds an amount of charge corresponding to the data in the charge storage layer, which is a floating gate, etc.

[0035] Specifically, the memory cell transistor MT is charged with electrons by a peripheral circuit (not shown) included in the NAND memory 11 so that the threshold voltage reaches a target value according to data. The peripheral circuit includes a charge pump, a row decoder, a sense amplifier, and a column decoder. The memory cell transistor MT may be configured to store one bit of data, or may be configured to store multi-value data of two or more bits.

[0036] In each NAND string, the (q+1) memory cell transistors MT are arranged such that their current paths are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. Then, starting from the memory cell transistor MT located closest to the drain, the control gate electrodes are connected to the word lines WL0 to WLq, respectively. Therefore, the drain of the memory cell transistor MT connected to the word line WL0 is connected to the source of the select transistor ST1, and the source of the memory cell transistor MT connected to the word line WLq is connected to the drain of the select transistor ST2.

[0037] The word lines WL0 to WLq commonly connect the control gate electrodes of the memory cell transistors MT between the NAND strings in a block. That is, the control gate electrodes of the memory cell transistors MT in the same row in a block are connected to the same word line WL. The (p+1) memory cell transistors MT connected to the same word line WL are treated as one or more pages, and data is written and read for each page.

[0038] That is, for example, according to a storage method in which 2 bits are stored in a memory cell transistor MT, (p+1) memory cell transistors MT connected to the same word line WL are treated as two pages, an upper page and a lower page.

[0039] Consecutive physical addresses are assigned to one page, and consecutive physical addresses are assigned to the pages contained in one block.

[0040] Next, the correspondence between data in the logical address space 200 and the physical address space 100 will be described with reference to Fig. 3. Fig. 3 is a schematic diagram showing an example of the correspondence between data in the logical address space 200 and data in the physical address space 100 in the memory system 1 according to the first embodiment.

[0041] 3, a predetermined area L of the logical address space 200 is assumed to be an area having consecutive logical addresses. The data specified by these consecutive logical addresses may be distributed across a plurality of areas P having mutually discontinuous physical addresses in the physical address space 100. This is because the block to which the data is written is determined regardless of the logical address given to the write command, and writing is performed in ascending page order.

[0042] As a result, when writing and reading data, the memory controller 10 performs each process by loading the logical-physical conversion table 111 from the NAND memory 11 as described above. The logical-physical conversion table 111 stores logical addresses and physical addresses corresponding to the logical addresses in a 1:1 association.

[0043] When writing data, the memory controller 10 associates the physical address of the newly written data with the logical address specified by the host device 2 and stores them in the logical-physical conversion table 111. When reading data, the memory controller 10 refers to the logical-physical conversion table 111 loaded from the NAND memory 11, converts the logical address specified by the host device 2 into the physical address of the data read destination, and specifies the data to be read.

[0044] On the other hand, in the above-mentioned address translation information 101 stored in the memory controller 10, instead of making logical addresses correspond one-to-one with physical addresses, a different data structure is adopted to reduce the capacity. An operation example of the information processing system 1000 according to the first embodiment will be shown below, and the detailed structure of the address translation information 101 will be described.

[0045] (Example of operation of information processing system) 4 to 9 are schematic diagrams illustrating an example of the operation of the information processing system 1000 according to the first embodiment.

[0046] 4, when issuing, for example, a write command, the host device 2 issues an area designation command to the memory system 1. The area designation command includes one or more logical addresses, which are consecutive logical addresses (X0, X1, X2, . . . X n-1 ,X n ) and the data size required for the specified area. Here, n is an integer equal to or greater than 3. Note that, for convenience of explanation, the area specification command is issued prior to the write command, but the area specification command may be issued simultaneously with the write command.

[0047] As shown in FIG. 5, when the processing unit 13 of the memory controller 10 receives an area specification command from the host device 2, the processing unit 13 stores, in the physical address space 100 of the NAND memory 11, consecutive physical addresses (Y0, Y1, Y2, . . . Y) that have the data size specified by the area specification command and correspond 1:1 to the logical addresses given to the area specification command. n-1 ,Y n ) is set as a designated area RA. The designated area RA may be set via the NAND control unit 14, for example.

[0048] In addition, the processing unit 13 generates address conversion information 101 that links the data size assigned to the area specification command, the first logical address (X0) of the logical addresses, and the first physical address (Y0) of the specified area RA, and stores it in the memory unit 15 within the memory controller 10.

[0049] As shown in Fig. 6, the host device 2 issues a write command to the memory system 1 by adding predetermined data indicated by the logical address added to the area designation command in Fig. 4. The data corresponding to the above logical address exists, for example, in a predetermined area LA in the logical address space 200. When the write command is issued after the above-mentioned area designation command, the same logical address as the logical address added to the area designation address in Fig. 4 is added to the write command in order to identify the above data.

[0050] When the processing unit 13 of the memory controller 10 receives an area designation command from the host device 2, it writes the data from the host device 2 into a designated area RA set in the physical address space 100 of the NAND memory 11 via, for example, the NAND control unit 14.

[0051] As shown in FIG. 7, the memory controller 10 transmits a completion response to the host device 2 upon completion of the data write process.

[0052] As shown in FIG. 8, the host device 2 issues a read command to the memory system 1 by assigning one or more logical addresses that specify any data in the designated area RA. m .....) are the logical addresses mentioned above (X0, X1, X2... X n-1 ,X n )

[0053] When the processing unit 13 of the memory controller 10 receives a read command with a logical address that specifies data in the specified area RA, the processing unit 13 refers to the address conversion information 101 expanded in the memory unit 15 and performs a logical-to-physical conversion process to convert the logical address specified in the read command into a physical address.

[0054] More specifically, the processing unit 13 refers to the address conversion information 101 to convert the above-mentioned logical addresses (X0, X1, X2, . . . X n-1 ,X n ) and read the logical address (X m In addition, the processing unit 13 refers to the address conversion information 101 to identify the head physical address (Y0) of the designated area RA, and subtracts it from the above logical address (X0, X m ) is added to the first physical address (Y0). This results in the logical address (X m ) corresponding to the physical address (Y mIf a plurality of logical addresses are specified in the read command, the above logical-physical conversion process is repeated.

[0055] As shown in FIG. 9, the memory controller 10 reads out data specified by the physical address obtained by the above logical-physical conversion process from the NAND memory 11, and transmits the data to the host device 2.

[0056] In this way, by setting a designated area RA that corresponds to a logical address and has a consecutive physical address within the physical address space 100 of the NAND memory 11, it becomes possible to manage the data within the designated area RA using small-capacity address conversion information 101.

[0057] When a rewrite command is issued from the host device 2 to the data in the designated area RA set in the NAND memory 11, the data to be rewritten is rewritten to a predetermined area outside the designated area RA in the physical address space 100. In this case, the management method of the data can be returned to the management by the logical-physical conversion table 111 described above.

[0058] On the other hand, if there are frequent rewrite instructions for the data in the designated area RA, the address conversion information 101 will not function. Therefore, as described above, the host device 2 of the first embodiment can select data whose rewrite frequency is equal to or less than a predetermined value and write it to the designated area RA. In addition, since the address conversion information 101 can simplify the logical-physical conversion process, data that requires high-speed access may be written to the designated area RA.

[0059] An example of data that is rewritten infrequently is data that occupies a large area of ​​address space, such as an OS. Data related to the OS often requires high-speed access. An example of a case in which OS data is rewritten is when updating the OS.

[0060] In this way, by setting large-sized data such as OS data as the write target in the designated area RA, the configuration of the first embodiment is preferably applied in which a part of the large-sized logical-physical conversion table 111 is replaced with the small-sized address conversion information 101. At this time, the address conversion information 101 covers a wide area spanning multiple pages of the address space.

[0061] The designated area RA may be set for multiple areas. In this case, the host device 2 may issue an area designation command each time, and the memory controller 10 may set the designated area RA one by one, or the host device 2 may designate multiple areas with one area designation command. The number of designated areas RA that can be designated may be limited to the total capacity of the address translation information 101 corresponding to these designated areas RA within the size that can be stored in the memory unit 15 in the memory controller 10.

[0062] (Example of processing by information processing system) Next, a processing example of the information processing system 1000 according to the first embodiment will be described with reference to FIGS.

[0063] First, an example of the overall processing of the information processing system 1000 will be described with reference to Fig. 10. Fig. 10 is a sequence diagram showing an example of the procedure of the processing in the information processing system 1000 according to the first embodiment.

[0064] 10, the host device 2 issues an area designation command with one or more consecutive logical addresses and a data size to the memory controller 1 (step S1). At the same time, the host device 2 may issue a write command with data corresponding to the logical addresses.

[0065] Upon receiving an area designation command from the host device 2, the processing unit 13 of the memory controller 10 sets a designated area RA within the physical address space 100 of the NAND memory 11, generates address conversion information 101 linking the first physical address of the designated area RA with the first address and data size of the logical address assigned to the area designation command from the host device 2, and stores the information in the memory unit 15 (step S2).

[0066] Furthermore, the NAND control unit 14 of the memory controller 10 requests the NAND memory 11 to write the data attached to the write command to the already set designated area RA according to the write command received from the host device 2 (step S3). After writing the data to the designated area RA, the NAND memory 11 transmits a write response to the memory controller 10 (step S4). In response to this, the memory controller 10 transmits a completion response to the host device 2 (step S5).

[0067] Thereafter, the host device 2 transmits, at a predetermined timing, to the memory controller 1 a read command to which is added a logical address corresponding to the data in the designated area RA (step S6).

[0068] The processing unit 13 of the memory controller 10 performs logical-physical conversion processing based on the address conversion information 101 in the storage unit 15 to convert the logical address given to the read command into a physical address (step S7).

[0069] The NAND control unit 14 of the memory controller 10 requests the NAND memory 11 to read data by specifying the physical address derived by the processing unit 13 (step S8). The NAND memory 11 transmits a read response together with the read data to the memory controller 10 (step S9). The memory controller 10 transmits the data read from the NAND memory 11 to the host device 2 (step S10).

[0070] This completes the processing of the information processing system 1000 according to the first embodiment.

[0071] Next, a write process by the memory controller 10 of the first embodiment will be described with reference to Fig. 11. Fig. 11 is a flow diagram showing an example of a procedure of a write process by the memory controller 10 according to the first embodiment. Fig. 11 also describes a case where an area designation command is issued simultaneously with a write command.

[0072] As shown in FIG. 11, the I / F unit 12 of the memory controller 10 receives a write command from the host device 2 (step S101).

[0073] If the I / F unit 12 receives an area designation command accompanying the write command (step S102: Yes), the processing unit 13 of the memory controller 10 sets a designated area RA in the storage area of ​​the NAND memory 11 (step S103).

[0074] The NAND control unit 14 writes the data attached to the write command from the host device 2 into the designated area RA of the NAND memory 11 (step S104).

[0075] In addition, the processing unit 13 generates address conversion information 101 in which the first logical address and data size among the logical addresses assigned to the area designation command are linked to the first physical address of the set designated area RA, and stores the information in the memory unit 15 (step S105).

[0076] On the other hand, if an area designation command accompanying the write command has not been received (step S102: No), the NAND control unit 14 writes the data attached to the write command from the host device 2 to a predetermined area of ​​the NAND memory 11 (step S106). The data write destination at this time is determined in ascending order from among the free pages to which data has not been written. The processing unit 13 loads, for example, the logical-physical conversion table 111 from the NAND memory 11 to specify the page to which data is to be written next.

[0077] The processing unit 13 also associates the physical address of the data write destination with the logical address assigned to the write command and stores them in the logical-physical conversion table 111 loaded from the NAND memory 11 (step S107). The logical-physical conversion table 111 thus updated is stored again in a predetermined area of ​​the NAND memory 11.

[0078] When any of the above processes is completed, the memory controller 10 transmits a completion response to the host device 2.

[0079] With the above, the write process by the memory controller 10 of the first embodiment is completed.

[0080] When a write command and an area designation command are received simultaneously, the address conversion information 101 may be generated after the designated area RA is set and before data is written to the designated area RA.

[0081] Next, a read process by the memory controller 10 of the first embodiment will be described with reference to Fig. 12. Fig. 12 is a flow diagram showing an example of a procedure of a read process by the memory controller 10 according to the first embodiment.

[0082] 12, the I / F unit 12 of the memory controller 10 receives a read command from the host device 2 (step S111). The processing unit 13 of the memory controller 10 determines whether the read destination specified by the read command is within the specified area RA (step S112).

[0083] Whether or not a read command specifies the designated area RA as the read destination can be determined, for example, by referring to the address conversion information 101 in which the logical address assigned to the read command is expanded in the memory unit 15 of the memory controller 10.

[0084] That is, the processing unit 13 refers to the address conversion information 101 in the storage unit 15, and identifies logical addresses from the beginning to the end corresponding to the designated area RA from the first logical address (X0) included in the address conversion information 101 and corresponding to the designated area RA and the data size of the designated area RA. The processing unit 13 also determines whether or not the logical address to be assigned to the read command is included in the logical addresses identified in this way. That is, the first logical address (X0)≦logical address of the read command (X m ) ≦ Last logical address (X n ), it can be seen that the logical address of the read command designates the designated area RA, where m is an integer equal to or greater than 0.

[0085] If the read destination specified by the read command is the specified area RA (step S112: Yes), the processing unit 13 refers to the address conversion information 101 in the storage unit 15 and derives a physical address from the logical address given to the read command (step S113).

[0086] More specifically, the processing unit 13 derives a physical address corresponding to the logical address of the read command by offsetting the difference between the first logical address corresponding to the specified area RA and the logical address assigned to the read command from the first physical address of the specified area RA. That is, the corresponding physical address (Y m ) = Starting physical address (Y0) + (logical address of read command (X m ) - the first logical address (X0)) to determine the physical address to read from.

[0087] On the other hand, if the read destination specified by the read command is not the specified area RA (step S112: No), the processing unit 13 loads the logical-physical conversion table 111 from the NAND memory 11 via, for example, the NAND control unit 14 (step S114). Also, the processing unit 13 refers to the logical-physical conversion table 111 to derive the physical address of the read destination (step S115).

[0088] The NAND control unit 14 reads data from a storage area of ​​the NAND memory 11 specified by the physical address derived from the address conversion information 101 or the logical-physical conversion table 111 (step S116). The I / F unit 12 transmits the read data to the host device 2 (step S117).

[0089] This completes the read process by the memory controller 10 of the first embodiment.

[0090] (Overview) In NAND type flash memory, data is written in pages and erased in blocks. Data cannot be written to a page that already has data written to it, and data is written in ascending page order regardless of the logical address given to the write command.

[0091] For this reason, a logical-physical conversion table that associates a logical address specified by a host device with a physical address that specifies a predetermined position in a storage area in a NAND memory is used for data management in the memory controller. Since the logical-physical conversion table can be as large as 1 / 500 to 1 / 1000 of the storage capacity of a memory system, it is not practical to keep it constantly deployed in an SRAM or the like in a memory controller, and it is stored in, for example, a NAND memory and loaded into the memory controller when data is read out and used.

[0092] However, it takes a certain amount of time to load the logical-physical conversion table from the NAND memory, which causes a delay in the operation of the memory system due to the need to load the logical-physical conversion table every time data is read, resulting in a decrease in the read performance of the memory system.

[0093] According to the memory system 1 of embodiment 1, when the memory controller 10 receives an area designation command from the host device 2 with one or more consecutive logical addresses and a data size attached thereto, it sets a designated area RA with consecutive physical addresses for the above data size within the memory area of ​​the NAND memory 11, and stores in the memory unit 15 address conversion information 101 in which the first logical address of the above consecutive logical addresses and the above data size are linked to the first physical address of the above consecutive physical addresses.

[0094] As a result, the address conversion information 101 that can be used for logical-to-physical conversion processing can be obtained with a significantly smaller amount of information than, for example, the logical-to-physical conversion table 111. Therefore, the address conversion information 101 can be constantly expanded in, for example, the storage unit 15 in the memory controller 10.

[0095] According to the memory system 1 of embodiment 1, when the memory controller 10 receives from the host device 2 a read command assigned with a logical address corresponding to data in the specified area RA, the memory controller 10 identifies a physical address offset from the first physical address of the address conversion information 101 based on the logical address assigned to the read command as the physical address corresponding to the logical address assigned to the read command.

[0096] In this way, when reading data from the specified area RA, it is possible to perform logical-physical conversion processing by referring to the address conversion information 101 expanded in the storage unit 15, and therefore it is possible to omit the processing of loading the logical-physical conversion table 111 from the NAND memory 11. This allows the logical-physical conversion processing by the memory controller 10 to be simplified, thereby reducing delays in reading data and improving the reading performance of the memory system 1.

[0097] According to the memory system 1 of the first embodiment, the memory controller 10 offsets the difference between the logical address assigned to the read command and the first logical address from the first physical address, and identifies the physical address corresponding to the logical address assigned to the read command. By using the address conversion information 101, it is possible to derive the physical address corresponding to the logical address with a simple offset calculation in this manner.

[0098] According to the host device 2 of the first embodiment, the logical address to be assigned to the area designation command is determined based on whether the rewrite frequency of the data specified by the logical address is equal to or less than a predetermined value. That is, the area designation command is assigned a logical address that specifies data whose rewrite frequency is equal to or less than a predetermined value.

[0099] As described above, when the host device 2 issues a rewrite command to data in the designated area RA, the data is rewritten to a specified area outside the designated area RA, and is placed under management again using the logical-physical conversion table 111. By applying the area designation command to data whose rewrite frequency is equal to or less than a specified value, it is possible to prevent the generated address conversion information 101 from failing in a short period of time.

[0100] Furthermore, as described above, by targeting data that is extensive and frequently read, such as OS data in gigabyte units, the above configuration in which part of the information in the logical-physical conversion table 111 is carried by the address conversion information 101 can be utilized more effectively.

[0101] [Embodiment 2] In the above-described first embodiment, for example, data that is rewritten infrequently is targeted for logical-physical management using the address translation information 101. However, even such data may be rewritten, albeit infrequently, and if this occurs repeatedly, the functionality of the address translation information 101 will be impaired.

[0102] In the second embodiment, based on the configuration of the above-mentioned first embodiment, an information processing system capable of recovering the function of the address translation information 101 when it is impaired will be described.

[0103] The information processing system of the second embodiment will be described below with reference to Figures 13 to 18. In the following drawings, the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0104] (Example of operation of information processing system) 13 to 15 are schematic diagrams illustrating an example of the operation of the information processing system according to the second embodiment.

[0105] 13, the information processing system of the second embodiment includes a host device 2a and a memory system 1a, and the memory system 1a includes a memory controller 10a and a NAND memory 11. A designated area RA is set in a physical address space 100 of the NAND memory 11, and data has been stored therein.

[0106] 13, it is assumed that the host device 2a needs to rewrite data in the designated area RA. The access unit 24a of the host device 2a issues a write command to the memory controller 10, which includes a logical address corresponding to any of the data already written in the designated area RA and data to be rewritten.

[0107] When a logical address corresponding to data already written in the designated area RA is assigned to the received write command, the memory controller 10a writes the data assigned to the write command to a predetermined area other than the designated area RA in the physical address space 100 of the NAND memory 11. The memory controller 10a that has received the write command can determine that the logical address assigned to the write command corresponds to data already written in the designated area RA by referring to the address conversion information 101 on the storage unit 15.

[0108] For example, if the logical address (X0, X1, X2) of the specified data in the designated area RA is attached to the write command from the host device 2a, the memory controller 10a writes the data attached to the write command to the area P1 outside the designated area RA. At this time, the correspondence between the logical address (X0, X1, X2) and the physical address (Y0, Y1, Y2) is added to the logical-physical conversion table in the NAND memory 11, and thereafter, the data specified by these addresses is placed under the management of the logical-physical conversion table.

[0109] In addition, the processing unit 13a of the memory controller 10a invalidates the data specified by the physical address (Y0, Y1, Y2) in the designated area RA corresponding to the logical address (X0, X1, X2). Furthermore, the portion of the address conversion information 101 related to the logical address (X0, X1, X2) and the physical address (Y0, Y1, Y2) is also invalidated.

[0110] Similarly, when a write command is sent from the host device 2a with a logical address identifying other data in the specified area RA, the memory controller 10a writes the data of that write command to other areas P2, P3, etc. in the physical address space 100 of the NAND memory 11, and invalidates the corresponding data in the specified area RA and the corresponding parts of the address conversion information 101.

[0111] As shown in FIG. 14, when the host device 2a subsequently issues write commands specifying data in the designated area RA, the specified data in the designated area RA is rewritten to other areas P4, P5, etc., and the invalid area in the designated area RA increases, and the invalid portion of the address conversion information 101 also increases.

[0112] Such a situation is not preferable in a configuration that aims to simplify logical-physical conversion processing by replacing a part of the functions of the logical-physical conversion table 111 with the address conversion information 101. Therefore, in the second embodiment, processing is performed in which the data rewritten from the designated area RA to the other areas P1 to P5 is placed under the management of newly generated address conversion information.

[0113] As shown in FIG. 15, the host device 2a issues an area designation command to the memory controller 10a, to which is added a logical address designating data already written in the NAND memory 11 and a data size.

[0114] When the received area designation command is assigned a logical address corresponding to data already written in the NAND memory 11, the memory controller 10a sets a group of areas having consecutive physical addresses, which is a predetermined area of ​​the data size assigned to the area designation command, as a designated area RAa in the physical address space 100 of the NAND memory 11, and writes the written data in the NAND memory 11 to the newly set designated area RAa. The memory controller 10a, which has received the area designation command, can confirm that the logical address assigned to the area designation command corresponds to the written data by loading a logical-physical conversion table from the NAND memory 11 and comparing the logical address with the corresponding physical address.

[0115] For example, if the area designation command from the host device 2a includes the logical addresses (X0, X1, X2, . . . ) of data rewritten from the designated area RA to other areas P1 to P5, the memory controller 10a first reads the data in the areas P1 to P5 from the NAND memory 11 and then writes the data to the consecutive physical addresses (Y L0 ,Y L1 ,Y L2The processing unit 13a of the memory controller 10a writes the data in the newly set designated area RAa having the logical addresses (X0, X1, X2, . . . ) and the data size to the physical address (Y L0 ,Y L1 ,Y L2 The starting physical address (Y L0 ) and stores it in the storage unit 15.

[0116] Through the above processing, it becomes possible to manage the data rewritten in the NAND memory 11 by using the newly generated address translation information 101a in place of the address translation information 101 whose function has been impaired due to the rewriting of the data in the designated area RA.

[0117] The host device 2a of the second embodiment can issue an area designation command for designating written data at any time. Alternatively, the area designation command may be issued on the condition that the data in the designated area RA has been rewritten a predetermined number of times.

[0118] In addition, when the function of the address conversion information 101 is impaired, the newly set designated area RAa may be set for multiple areas, with the upper limit being that the corresponding address conversion information 101a is within the capacity that can be held in the memory unit 15 in the memory controller 10.

[0119] Furthermore, in the configuration of embodiment 2, when the address conversion information 101a is generated, some of the data that was under the management of the logical-physical conversion table is transferred to the management of the address conversion information 101a, and the old information of that part of the data remains in the logical-physical conversion table.

[0120] However, when an access command is received from the host device 2a, the memory controller 10a preferentially refers to the address conversion information 101a before the logical-physical conversion table, so that no defects occur in the processing of the memory controller 10a. In addition, in response to an instruction from the host device 2a or when there is no access from the host device 2a for a certain period of time, the processing unit 13a of the memory controller 10a may appropriately perform processing such as invalidating the portion of the logical-physical conversion table that overlaps with the address conversion information 101a.

[0121] (Example of processing by information processing system) Next, a processing example of the information processing system of the second embodiment will be described with reference to FIGS.

[0122] First, an example of processing of the entire information processing system of the second embodiment will be described with reference to Fig. 16. Fig. 16 is a sequence diagram showing an example of a processing procedure in the information processing system according to the second embodiment. Note that, before the sequence shown in Fig. 16, for example, by the sequence in the first half of Fig. 10 of the first embodiment, a designated area RA is set in the physical address space 100 of the NAND memory 11, and data has been written therein.

[0123] As shown in FIG. 16, the host device 2a issues a write command specifying data in the specified area RA multiple times (for example, k times: k is an integer equal to or greater than 1) to the memory controller 10a, and the data in the specified area RA is rewritten (step S11).

[0124] After that, at any timing, the host device 2a issues an area designation command to the memory controller 10a to designate the written data (step S21). The memory controller 10a sets a predetermined area of ​​the data size given in the area designation command as a designated area RAa in the NAND memory 11.

[0125] In addition, the memory controller 10a generates address conversion information 101a that links the first physical address of the newly set specified area RAa with the first address and data size of the logical address assigned to the area designation command from the host device 2a, and stores the information in the memory unit 15 (step S22).

[0126] Moreover, the memory controller 10a requests the NAND memory 11 to read the written data specified by the area specification command (step S23-1). In response to the read request from the memory controller 10a, the NAND memory 11 reads the written data (step S23-2).

[0127] The memory controller 10a requests the NAND memory 11 to write the data read from the NAND memory 11 to the newly created designated area RAa (step S23-3). After writing the data, the NAND memory 11 transmits a write response to the memory controller 10a (step S24). In response to this, the memory controller 10a transmits a completion response to the host device 2a (step S25).

[0128] Thereafter, when a read command specifying data in the specified area RAa is received from the host device 2a, the processing from steps S26 to S30 performed by the memory controller 10a is substantially similar to the processing from steps S6 to S10 performed by the memory controller 10a in Figure 10 of the above-mentioned embodiment 1.

[0129] That is, when a read command specifying data in the specified area RAa is received (step S26), the memory controller 10a performs a logical-physical conversion process by referring to the address conversion information 101a expanded in the memory unit 15 (step S27), reads the data from the NAND memory 11 by specifying the derived physical address (steps S28, S29), and transmits it to the host device 2a (step S30).

[0130] This completes the processing of the information processing system of the second embodiment.

[0131] Next, a process of setting the designated areas RA, RAa by the memory controller 10a according to the second embodiment will be described with reference to Fig. 17. Fig. 17 is a flow diagram showing an example of a procedure of the process of setting the designated areas RA, RAa by the memory controller 10a according to the second embodiment.

[0132] As shown in FIG. 17, when the processing unit 13a of the memory controller 10a receives an area designation command from the host device 2a (step S201), it determines whether or not the data designated by the area designation command has been written in the NAND memory 11 (step S202).

[0133] If the data specified by the area specification command is not already written data (step S202: No), the processes of steps S203 and S204 performed by the memory controller 10a are similar to the processes of steps S103 and S104 in Fig. 11 of the above-mentioned embodiment 1. In this case, the memory controller 10a receives a write command to which data to be written to the specified area RA is added at a predetermined timing.

[0134] That is, the memory controller 10a sets a designated area RA in the NAND memory 11 (step S203), and writes new data thereto (step S204). In addition, the processing unit 13a generates address conversion information 101 for identifying data in the designated area RA, and stores it in the storage unit 15 (step S208).

[0135] On the other hand, if the data specified by the area designation command is already written data (step S202: Yes), the memory controller 10a sets a new designated area RAa in the NAND memory 11 (step S206), reads the already written data specified by the area designation command from a specified area of ​​the NAND memory 11, and writes it to the newly set designated area RAa (step S207).

[0136] Thereafter, the processing unit 13a generates address conversion information 101a for identifying the data in the designated area RAa, and stores it in the storage unit 15 (step S208).

[0137] When any of the above processes is completed, the memory controller 10a transmits a completion response to the host device 2a (step S209).

[0138] This completes the process of setting the designated areas RA and RAa by the memory controller 10a of the second embodiment.

[0139] (Overview) According to the memory system 1a of the second embodiment, when the logical address given to the area designation command from the host device 2a is a logical address that identifies data already written in the NAND memory 11, the memory controller 10a stores the address conversion information 101a in the storage unit 15 and writes the written data into the designated area RAa. This makes it possible to manage these data by the newly generated address conversion information 101a even if the data in the original designated area RA is rewritten and the function of the address conversion information 101 is impaired.

[0140] In addition, the memory system 1a of the second embodiment has the same effects as the memory system 1 of the first embodiment described above.

[0141] In the above-described second embodiment, when the designated area RAa is designated, the host device 2 issues an area designation command with a logical address that designates data that has already been written to the NAND memory 11 and is to be stored in the designated area RA. However, the logical address that is assigned to the area designation command when the designated area RAa is designated may be written data that is stored outside the designated area RA. In this case, the written data that was not originally under the management of the address translation information 101 can be stored in the designated area RAa and then placed under the management of the newly generated address translation information 101a.

[0142] (Variation 1) Next, a memory system according to a first modification of the second embodiment will be described with reference to Fig. 18. The memory system according to the first modification is different from the memory system 1a according to the second embodiment in that, when an area designation command designating written data is received, the memory system according to the first modification may omit the data rewrite process.

[0143] FIG. 18 is a flowchart illustrating an example of a procedure of a setting process of the designated areas RA, RAa of the memory controller according to the first modification of the second embodiment.

[0144] As shown in FIG. 18, except for the process of step S215 of the memory controller in the first modification, the process is performed in the same manner as the process in FIG. 17 of the second embodiment described above.

[0145] That is, when the memory controller of the first modification receives an area designation command from the host device (step S211), it determines whether the data designated by the area designation command has been written (step S212). If the data designated by the area designation command has not been written (step S212: No), the processes of steps S213, S214, and S218 are the same as the processes of steps S203, S204, and S208 of FIG. 17 of the second embodiment described above.

[0146] If the data specified by the area specification command is already written data (step S212: Yes), the memory controller determines whether the physical addresses corresponding to the already written data in the NAND memory are consecutive (step S215).

[0147] If the physical addresses corresponding to the written data are discontinuous (step S215: No), the memory controller of the first modification, like the memory controller 10a of the second embodiment described above, sets a new designated area (corresponding to the designated area RAa of the second embodiment) in the NAND memory (step S216), reads the written data specified by the area specification command from a predetermined area in the NAND memory, and writes it to the newly set designated area (step S217). In addition, it generates address conversion information (corresponding to the address conversion information 101a of the second embodiment) for identifying the data in the newly set designated area, and stores it in the storage unit (step S218).

[0148] On the other hand, if the physical addresses corresponding to the written data are consecutive (step S215: Yes), the memory controller of variant 1 skips the processing of steps S216 and S217, generates address conversion information (corresponding to the address conversion information 101a of embodiment 2) that links the first physical address of these physical addresses to the first logical address of the logical addresses assigned to the area specification command and the data size, and stores the information in a memory unit (step S218).

[0149] That is, the memory controller of the first modification does not perform a rewrite process on data having consecutive physical addresses, but generates only address conversion information for managing this data.

[0150] When any of the above processes is completed, the memory controller transmits a completion response to the host device (step S219).

[0151] This completes the process of setting a designated area by the memory controller according to the first modification.

[0152] According to the memory system of variant example 1, if the logical address assigned to the area specification command is a logical address that identifies already written data and the already written data has consecutive physical addresses, the memory controller does not set a new specified area in the NAND memory or re-write the already written data.

[0153] In this way, when the written data has consecutive physical addresses, the data can be managed by the address conversion information without setting another designated area and rewriting the data. Therefore, unnecessary rewrite processing for the data can be omitted, and the performance of the memory system of the first modification can be further improved.

[0154] According to the memory system of the first modification, when the memory controller does not rewrite data as described above, the memory controller associates the first physical address of consecutive physical addresses of the written data with the first logical address and data size of the area specification command, and stores the address conversion information in the storage unit. By generating address conversion information for the written data having consecutive physical addresses in this manner, the subsequent logical-physical conversion process can be simplified, and the read performance of the memory system can be improved.

[0155] In addition, the memory system of the first modification provides the same effects as the memory system 1a of the second embodiment described above.

[0156] (Variation 2) Next, an information processing system according to Modification 2 of the second embodiment will be described with reference to Fig. 19 and Fig. 20. The information processing system according to Modification 2 differs from the second embodiment in that the host device issues a command to the memory controller to check the state of the NAND memory.

[0157] More specifically, the host device of the second modification issues a designated area check command to the memory controller at a predetermined timing to check the state of a designated area in the NAND memory. The designated area check command enables the host device to check whether the function of the address translation information is impaired by rewriting data from the designated area or the like.

[0158] This allows the host device to determine whether to issue an area designation command after checking whether the function of the address translation information is intact. If it is determined that the function of the address translation information is impaired, the host device can issue an area designation command by specifying written data, as in the above-mentioned second embodiment, for example.

[0159] Alternatively, by issuing a designated area confirmation command, the host device can determine whether or not to issue a read command specifying data in the designated area after confirming whether or not the function of the address translation information is impaired. If it is confirmed that the function of the address translation information is impaired, the host device can issue an area specification command specifying written data, as in the above-mentioned second embodiment, before issuing a read command.

[0160] Fig. 19 is a sequence diagram showing an example of a processing procedure in an information processing system according to Modification 2 of Embodiment 2. Fig. 19 shows an example in which the host device issues a designated area confirmation command to determine whether to issue an area designation command that designates written data.

[0161] As shown in FIG. 19, a write command specifying data in a specified area is issued, for example, k times from the host device to the memory controller, and the data in the specified area is rewritten (step S11).

[0162] Thereafter, in order to determine whether or not to issue an area designation command specifying the written data, the host device issues a designated area confirmation command to the memory controller prior to issuing the area designation command, assigning a logical address corresponding to the written data to be specified by the area designation command (step S31).

[0163] Since the designated area check command is a command for checking the current state of the designated area, the designated area check command is assigned a logical address that has been written to the designated area at least once and has a history in the address conversion information. The memory controller then checks whether the function of the address conversion information of the portion corresponding to the logical address assigned to the designated area check command is impaired, that is, whether the address conversion information of that portion is invalidated, and then responds with the check result to the host device (step S32). This allows the host device to grasp the state of the designated area and to determine whether to issue an area designation command by specifying written data.

[0164] In the example of Fig. 19, it is assumed that the host device decides to issue an area designation command that designates written data based on the response obtained from the memory controller. In this case, the subsequent processes of steps S21 to S25 are the same as the processes of steps S21 to S25 shown in Fig. 16 of the above-mentioned second embodiment.

[0165] That is, the host device specifies the written data and issues an area designation command (step S21), and the memory controller sets a new designated area (step S22), reads the written data from the NAND memory (steps S23-1, S23-2), and writes the data to the newly set designated area (steps S23-3, S24, S25).

[0166] This completes the process in the information processing system of the second modified example.

[0167] Fig. 20 is a sequence diagram showing another example of the procedure of the processing in the information processing system according to the second modification of the second embodiment. Fig. 20 shows an example of the case where the host device issues a designated area check command to check the damage state of the address translation information when specifying data in the designated area and issuing a read command.

[0168] As shown in Fig. 20, before issuing a read command specifying data in a specified area, the host device issues a specified area confirmation command to the memory controller by assigning a logical address corresponding to the data to be specified by the read command (step S31). The memory controller checks whether the function of the address translation information corresponding to the logical address assigned to the specified area confirmation command is impaired, and then responds with the confirmation result to the host device (step S32). This allows the host device to grasp the state of the specified area, and to determine whether it is necessary to issue an area specification command specifying, for example, written data to be read, before issuing a read command.

[0169] In the example of Fig. 20, it is assumed that the host device judges based on the response obtained from the memory controller that it is not necessary to issue an area designation command designating written data. In this case, the subsequent processes of steps S26 to S30 are the same as the processes of steps S26 to S30 shown in Fig. 16 of the above-mentioned second embodiment.

[0170] That is, the host device issues a read command specifying data in a specified area (step S26), and the memory controller derives the physical address of the read destination based on the address conversion information (step S27), reads the data from the identified read destination in the NAND memory (steps S28, S29), and transmits it to the host device (step S30).

[0171] This completes the process of the other example in the information processing system of the second modified example.

[0172] According to the memory system of the second modification, when the memory controller receives a designated area confirmation command with a predetermined logical address from the host device, the memory controller confirms the state of the address conversion information related to the logical address assigned to the designated area confirmation command and transmits the confirmation result to the host device. This allows the host device to confirm the state of the designated area before issuing an area specification command that specifies written data as in the second embodiment or a read command that specifies data in the designated area.

[0173] According to the host device of variant example 2, the host device sends a designated area confirmation command with a logical address corresponding to the written data to the memory controller prior to sending an area designation command with a logical address that identifies the written data.

[0174] This allows the host device to determine whether or not to issue an area designation command such as that in the second embodiment that designates written data, and therefore, it is possible to suppress the issuance of unnecessary area designation commands, thereby reducing the load on the entire information processing system.

[0175] According to the host device of variant example 2, the host device transmits to the memory controller a designated area confirmation command accompanied by the logical address to be assigned to the read command, prior to transmitting a read command accompanied by the logical address contained in the consecutive logical addresses assigned to the area designation command.

[0176] This allows the host device to determine whether the data to be read from the read command to be issued is still under the management of the address translation information. If the function of the address translation information related to the data to be read from is impaired, the host device can issue an area designation command such as that in the above-mentioned second embodiment, which designates the written data, prior to issuing the read command. Therefore, the data that has been replaced under the management of the logical-physical conversion table can be placed under the management of the address translation information again, and the read command can be issued, thereby reducing the delay when reading data and improving the read performance of the memory system.

[0177] [Embodiment 3] In the above-mentioned first and second embodiments, for example, data that is rewritten infrequently is specified and an area specification command is issued, so that the data is placed under the management of the address translation information. In addition, at this time, by specifying a wide area such as OS data, the advantage of transferring part of the function of the logical-physical translation table to the address translation information is enhanced.

[0178] In the third embodiment, the logical-physical conversion process for predetermined data having a very limited capacity is simplified, mainly for data that requires high-speed access. In the configuration of the third embodiment, the frequency of rewriting is not an issue.

[0179] An information processing system according to the third embodiment will be described below with reference to Figures 21 to 24. In the following drawings, the same components as those in the first and second embodiments are denoted by the same reference numerals, and the description thereof may be omitted.

[0180] (Example of operation of information processing system) 21 and 22 are schematic diagrams illustrating an example of the operation of the information processing system according to the third embodiment.

[0181] 21, the information processing system of the third embodiment includes a host device 2b and a memory system 1b. The memory system 1b includes a memory controller 10b having a processing unit 13b, and a NAND memory 11. Data has been stored in some areas P11 to P18 in the physical address space 100 of the NAND memory 11. The data is under the management of a logical-physical conversion table stored in the NAND memory 11.

[0182] The host device 2b of the third embodiment can select data that requires access at a predetermined speed or faster from the data already written in the areas P11 to P18, and the access unit 24b of the host device 2b can issue an area designation command for the data. At this time, the area designation command includes the logical addresses of the data selected by the host device 2b that requires high-speed access and the data size of the data.

[0183] 22, the processing unit 13b of the memory controller 10b sets an area in which data corresponding to these logical addresses are stored as a designated area RAb in the physical address space 100 of the NAND memory 11. In addition, among the physical addresses corresponding to these data, the processing unit 13b generates address conversion information 101b in which the corresponding logical address and data size are linked to the physical address for each predetermined logical unit, and stores the address conversion information 101b in the storage unit 15b.

[0184] Here, as one logical unit, any data capacity can be set in advance, for example, the minimum data management unit, that is, 4 kB, which is the unit of logical address assignment. In this case, the address conversion information 101b takes a format in which a physical address is associated with each logical address assigned to the area designation command, and has a configuration that can be said to be a reduced version of the logical-physical conversion table stored in the NAND memory 11.

[0185] For example, the area designation command from the host device 2b includes a logical address (XP0 ,X Q0 ), the processing unit 13b of the memory controller 10b converts these logical addresses (X P0 ,X Q0 ) corresponding to the physical address (Y P0 ,Y Q0 ), that is, a part of the area P12 is designated as a designated area RAb 12 At this time, the logical address (X P0 ,X Q0 ) may be consecutive logical addresses or may be discontinuous logical addresses.

[0186] Moreover, the processing unit 13b extracts the logical addresses for each logical unit, and generates the address conversion information 101b by linking the physical addresses corresponding to these logical addresses with the data size representing one logical unit. At this time, if one logical unit is the size of one logical address, the address conversion information 101b will contain the logical address (X P0 ,X Q0 ), the corresponding physical address (Y P0 ,Y Q0 ) will be linked and stored.

[0187] Also, for example, the area designation command from the host device 2b includes a logical address (X X0 ,X Y0 ,X Z0 ), the processing unit 13b of the memory controller 10b converts these logical addresses (X X0 ,X Y0 ,X Z0 ) corresponding to the physical address (Y X0 ,Y Y0 ,Y Z0 ), that is, a part of the area P11 is designated as a designated area RAb 11 At this time, the logical address (X X0 ,X Y0 ,X Z0) may be consecutive logical addresses or may be discontinuous logical addresses.

[0188] In addition, the processing unit 13b extracts logical addresses for each logical unit, and generates address conversion information 101b by linking the physical addresses corresponding to these logical addresses with the data size representing one logical unit. At this time, if one logical unit is the size of one logical address, the address conversion information 101b will contain the logical address (X X0 ,X Y0 ,X Z0 ), the corresponding physical address (Y X0 ,Y Y0 ,Y Z0 ) will be linked and stored.

[0189] In addition, the designated area RAb in the third embodiment may also be set for multiple areas and multiple data, with the upper limit being within the capacity that the corresponding address translation information 101b can hold in the memory unit 15b in the memory controller 10.

[0190] Also, in the configuration of embodiment 3, when the address conversion information 101b is generated, some of the data that was under the management of the logical-physical conversion table is transferred to the management of the address conversion information 101b, and the old information of that part of the data remains in the logical-physical conversion table.

[0191] However, even in this case, the memory controller 10b preferentially refers to the address conversion information 101b before the logical-physical conversion table and responds to the access command from the host device 2b, so that no problem occurs in the processing of the memory controller 10b. Furthermore, the processing unit 13b of the memory controller 10b may also appropriately perform processing such as invalidating the portion of the logical-physical conversion table that overlaps with the address conversion information 101b.

[0192] (Example of processing by information processing system) Next, a processing example of the information processing system of the third embodiment will be described with reference to FIGS.

[0193] First, an example of processing of the entire information processing system according to the third embodiment will be described with reference to Fig. 23. Fig. 23 is a sequence diagram showing an example of a processing procedure in the information processing system according to the third embodiment.

[0194] As shown in FIG. 23, a write command with a predetermined logical address is issued, for example, k times from the host device 2b to the memory controller 10b, and data is written to multiple areas of the NAND memory 11 (step S11).

[0195] Thereafter, at any timing, the host device 2b issues an area designation command to the memory controller 10b to designate the written data (step S41). The memory controller 10b sets the area in the NAND memory 11, designated by the logical address given to the area designation command, into which the data has been written, as a designated area RAb (step S42). The memory controller 10b also generates address conversion information 101b by linking each logical unit of the logical address given to the area designation command with the corresponding physical address together with the data size of one logical unit, and stores the information in the storage unit 15b.

[0196] When the above process is completed, the memory controller 10b transmits a completion response to the host device.

[0197] Furthermore, when a read command designating the designated area RAb is received from the host device 2b at any timing (step S44), the memory controller 10b refers to the address conversion information 101b expanded on the memory unit 15b, and derives a physical address corresponding to the logical address (step S45).

[0198] The memory controller 10b also designates the derived physical address and issues a data read request to the NAND memory 11 (step S46). The NAND memory 11 transmits the read data to the memory controller 10b and issues a read response (step S47). The memory controller 10b transmits the data read from the NAND memory 11 to the host device 2b (step S48).

[0199] This completes the processing of the information processing system of the third embodiment.

[0200] Next, a process of setting the designated area RAb by the memory controller 10b according to the third embodiment will be described with reference to Fig. 24. Fig. 24 is a flow chart showing an example of a procedure of the process of setting the designated area RAb by the memory controller 10b according to the third embodiment.

[0201] When the memory controller 10b receives an area designation command from the host device 2b, which is provided with a logical address specifying the written data and a data size (step S301), the memory controller 10b loads a logical-physical conversion table from the NAND memory 11, converts the logical address provided in the area designation command into a physical address, and sets the area in the NAND memory 11 identified by the physical address as the designated area RAb (step S302).

[0202] Furthermore, the memory controller 10b extracts the logical address given to the area specification command for each logical unit (step S303), generates address conversion information 101b that associates the corresponding physical address with the data size of one logical unit, and stores the information in the storage unit 15b (step S304). Upon completion of the above process, the memory controller 10b transmits a completion response to the host device 2b (step S305).

[0203] This completes the process of setting the designated area RAb by the memory controller 10b according to the third embodiment.

[0204] (Overview) According to the memory system 1b of the third embodiment, when the memory controller 10b receives from the host device 2b an area designation command with one or more logical addresses and a data size, which is a logical address identifying data already written in the NAND memory 11, the memory controller 10b sets the area in which the already written data is written as a designated area RAb, extracts a physical address corresponding to the logical address for each predetermined logical unit, and stores in the memory unit 15b address conversion information 101b in which the logical address and the data size of one logical unit are linked to the physical address corresponding to the logical address.

[0205] This allows the host device 2b to individually specify data for which high-speed access is required in logical units, thereby enabling efficient speed-up of access. In this case, the logical address given to the area specification command and the physical address that specifies the specified area may be consecutive or discontinuous.

[0206] Furthermore, since data is managed in logical units, even if data in the designated area RAb is rewritten, the functionality of the address translation information 101b can be maintained by updating only the portion corresponding to that data.

[0207] According to the memory system 1b of embodiment 3, when the memory controller 10b receives from the host device 2b a read command assigned with a logical address corresponding to data in the designated area RAb, the memory controller 10b refers to the address conversion information 101b to identify the physical address corresponding to the logical address assigned to the read command.

[0208] This simplifies the logical-physical conversion process performed by the memory controller 10b, reduces delays in reading data, and improves the read performance of the memory system 1b.

[0209] In addition, the memory system 1b of the third embodiment has the same effects as the memory system 1 of the first embodiment described above.

[0210] The configuration of the third embodiment can also be used in combination with the configuration of the first embodiment. That is, for data that is rewritten infrequently and has a large capacity, the data can be written in the designated area RA of the first embodiment and managed by the address conversion information 101 of the first embodiment. On the other hand, for data that has a very limited capacity and requires high-speed access, the designated area RAb of the third embodiment can be set and managed by the address conversion information 101b of the third embodiment.

[0211] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0212] 1, 1a, 1b... memory system, 2, 2a, 2b... host device, 10, 10a, 10b... memory controller, 11... NAND memory, 13, 13a, 13b... processing unit, 15, 15b... storage unit, 24, 24a, 24b... access unit, 101, 101a, 101b... address conversion information, 111... logical-physical conversion table, 1000... information processing system.

Claims

1. A non-volatile memory; a controller having a host interface and a storage unit and controlling the memory; The controller: When an area designation command to which one or more consecutive logical addresses and a data size are assigned is received from a host device, a designated area having consecutive physical addresses and the data size is set in a storage area of ​​the memory, and first address conversion information in which the first physical address of the consecutive physical addresses is linked to the first logical address and the data size of the consecutive logical addresses is stored in the storage unit; when a read command to which a logical address corresponding to data in the specified area is assigned is received from the host device, a physical address offset from the first physical address of the first address conversion information is specified as a physical address corresponding to the logical address assigned to the read command based on the logical address assigned to the read command; Memory system.

2. The controller: offsetting the difference between the logical address assigned to the read command and the first logical address from the first physical address, thereby identifying the physical address corresponding to the logical address assigned to the read command; 2. The memory system of claim 1.

3. The storage area of ​​the memory includes: a logical-physical conversion table is stored, which provides a one-to-one correspondence between a plurality of logical addresses and a plurality of physical addresses respectively corresponding to the plurality of logical addresses; The controller: when a read command to which a logical address corresponding to data outside the designated area is assigned is received from the host device, the logical-physical conversion table is read from the memory, and a physical address corresponding to the logical address assigned to the read command is identified by referring to the read logical-physical conversion table; 2. The memory system of claim 1.

4. The controller: when the logical address given to the area designation command is a logical address specifying data already written in the memory, storing the first address conversion information in the storage unit and writing the already written data into the designated area; 2. The memory system of claim 1.

5. The controller: when the logical address assigned to the area designation command is the logical address identifying the written data and the written data has consecutive physical addresses, linking the first physical address of the consecutive physical addresses of the written data to the first logical address and the data size without setting the designated area in the memory and without re-writing the written data, and storing the first address conversion information in the storage unit; 5. The memory system of claim 4.

6. The controller: when a designated area confirmation command to which a predetermined logical address is assigned is received from the host device, a state of the first address translation information related to the logical address assigned to the designated area confirmation command is confirmed, and a determination result is transmitted to the host device; 5. The memory system of claim 4.

7. The designated area confirmation command is transmitted to the controller prior to transmission of the area designation command to which the logical address specifying the written data is assigned; 7. The memory system of claim 6.

8. The designated area confirmation command is transmitted to the controller prior to transmission of a read command to which the logical addresses included in the consecutive logical addresses are assigned; 7. The memory system of claim 6.

9. The area designation command includes: A logical address is assigned to identify data whose rewrite frequency is equal to or less than a predetermined value.

2. The memory system of claim 1.

10. The controller: when the logical address given to the area designation command is a logical address specifying data already written in the memory, extracting a physical address corresponding to the logical address for each predetermined logical unit, and storing second address conversion information in which the logical address and the data size of the one logical unit are associated with the corresponding physical address in the storage unit; 2. The memory system of claim 1.

11. The area designation command includes: A logical address is assigned to identify data for which a required access speed is equal to or greater than a predetermined value.

10. The memory system of claim 9.

12. A non-volatile memory; a controller having a host interface and a storage unit and controlling the memory; The controller: When an area designation command is received from a host device, the area in which the written data is written is designated as a designated area, and a physical address corresponding to the logical address is extracted for each predetermined logical unit, and address conversion information in which the logical address and the data size of the one logical unit are linked to the corresponding physical address is stored in the storage unit; when a read command to which a logical address corresponding to data in the specified area is assigned is received from the host device, the address conversion information is referenced to identify a physical address corresponding to the logical address assigned to the read command; Memory system.

13. The one logical unit corresponds to one logical address.

13. The memory system of claim 12.

14. A host device connectable to a controller that controls a non-volatile memory, Transmitting an area designation command to the controller, the area designation command including one or more consecutive logical addresses and a data size; The logical address given to the area designation command is A logical address that identifies data already written in the memory, or a logical address that identifies data to be newly written in the memory. Host device.

15. transmitting, to the controller, a designated area confirmation command to which the logical address corresponding to the written data is assigned, prior to transmitting the area designation command to which the logical address specifying the written data is assigned; 15. The host device of claim 14.

16. transmitting, to the controller, a designated area confirmation command to which the logical address to be assigned is assigned, prior to transmitting a read command to which the logical address included in the consecutive logical addresses is assigned.

15. The host device of claim 14.

17. The logical address to be assigned to the area designation command is Whether or not the frequency of rewriting the data specified by the logical address is equal to or lower than a predetermined value; and whether or not an access speed required for the data specified by the logical address is equal to or higher than a predetermined value; 15. The host device of claim 14.

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