Superconductive device and manufacturing method thereof

Abstract

To enhance reliability of a connection of a superconductive device.SOLUTION: A superconductive device comprises: a superconductive circuit chip 1 to which a function circuit is provided; a multi-layer substrate 3 that has a plurality of wiring layers 2; and a plurality of pins 4 that electrically connects the superconductive circuit chip 1 and the multi-layer substrate 3. Each pin 4 is inserted in a direction crossing each wiring layer 2 of the multi-layer substrate 3. The superconductive device also comprises: the superconductive circuit chip 1; the multi-layer substrate 3 having the plurality of wiring layers 2; an interposer 6 that is arranged between the multi-layer substrate 3 and the superconductive circuit chip 1, and includes wiring layers 5, one of which is electrically connected to the superconductive circuit chip 1, and the other of which is connected to the wiring layer 2 of the multi-layer substrate 3; and a plurality of pins 7 that electrically connects the interposer 6 and the multi-layer substrate 3 with each other. Each pin 7 is inserted into at least any of wiring layers 2 of the multi-layer substrate 3 and the other of the wiring layers 5 of the interposer 6.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a superconducting device and a method for manufacturing the same. [Background technology]

[0002] In a superconducting device configured by mounting a superconducting circuit chip utilizing a quantum state on a circuit board, high reliability is required for the electrical connection between the superconducting circuit chip (or an interposer mounting the superconducting circuit chip) and the circuit board, etc. in a low-temperature environment to realize a superconducting state. Patent Document 1 discloses a technology related to the electrical connection between the wiring layer of the superconducting chip and the circuit board, etc. That is, in Patent Document 1, a mercury ball is interposed between a micro-pin connected to a superconducting chip circuit and a micro-pin connected to a wiring module substrate, and the mercury ball deforms in response to the relative displacement of the micro-pin due to temperature changes, thereby maintaining the connection between the superconducting chip and the wiring module. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 58-030079 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if mercury is used even in part as a constituent material of electronic components, measures must be taken to prevent the diffusion of mercury into the natural environment at each stage of the production, use and disposal of the electronic components. Therefore, there has been a need for the development of technology that can increase the reliability of electrical connections in a superconducting state without using mercury as a constituent material of electronic components.

[0005] The present invention aims to provide mercury-free connections between components of a superconducting device. [Means for solving the problem]

[0006] In order to solve the above problems, the present invention proposes the following means. A superconducting device according to a first aspect of the present invention is a device that utilizes the characteristics of superconductivity, and is characterized in that it comprises a superconducting circuit chip having a functional circuit, a multilayer substrate having a plurality of wiring layers, and a plurality of pins that electrically connect the superconducting circuit chip and the multilayer substrate, the pins being inserted into the wiring layers of the multilayer substrate in a direction that intersects with the wiring layers. A superconducting device according to a second aspect of the present invention is a device that utilizes the characteristics of superconductivity, comprising: a superconducting circuit chip provided with a functional circuit; a multilayer substrate having a plurality of wiring layers; an interposer disposed between the multilayer substrate and the superconducting circuit chip, electrically connected to the superconducting circuit chip, and having a wiring layer connected to the wiring layer of the multilayer substrate; and a plurality of pins electrically connecting the interposer to the multilayer substrate, wherein the pins are inserted into at least one of the wiring layers of the multilayer substrate and the wiring layer of the interposer in a direction that intersects therewith.

[0007] A third aspect of the present invention relates to a method for manufacturing a superconducting device, which comprises electrically connecting a superconducting circuit chip provided with a functional circuit utilizing superconducting properties to a multilayer substrate having a plurality of wiring layers by a plurality of pins, and is characterized in that the pins are inserted into the wiring layer of the multilayer substrate in a direction intersecting the wiring layer, thereby deforming the wiring layer. A fourth aspect of the present invention relates to a method for manufacturing a superconducting device, which electrically connects an interposer, which is electrically connected to a superconducting circuit chip having a functional circuit utilizing superconducting properties, to a multilayer substrate having a plurality of wiring layers, by a plurality of pins, and is characterized in that the pins are inserted into at least one of the wiring layers of the multilayer substrate and the wiring layer of the interposer in a direction intersecting the wiring layer, thereby deforming the wiring layer. Effect of the Invention

[0008] According to the present invention, connections between components of a superconducting device can be maintained in a superconducting environment without the use of mercury. [Brief description of the drawings]

[0009] [Figure 1] 1A and 1B are cross-sectional views showing examples of the minimum configuration of a superconducting device according to the present invention, in which (a) shows an example of connection between a superconducting circuit chip and a multilayer substrate, and (b) shows an example of connection between an interposer and a multilayer substrate. [Diagram 2] 1A and 1B are cross-sectional views of a superconducting device according to a first embodiment of the present invention, and FIG. [Diagram 3] FIG. 3 is a vertical cross-sectional view of the pin shown in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view of a superconducting device according to a second embodiment of the present invention. [Diagram 5] FIG. 4 is a cross-sectional view of a superconducting device according to a third embodiment of the present invention. [Figure 6] FIG. 11 is a cross-sectional view of a superconducting device according to a fourth embodiment of the present invention. [Figure 7] FIG. 2 is a cross-sectional view of a superconducting device as a comparative example to the first to fourth embodiments. [Figure 8] 1A to 1F are longitudinal cross-sectional views showing modified examples of the pins used in the first to fourth embodiments, where (a) is a basic form 1, (b) is a basic form 2, (c) is a modified example 1, (d) is a modified example 2, (e) is a modified example 3, and (f) is a modified example 4. [Figure 9] FIG. 11 is a plan view showing the basic shape of the hole of the pin insertion portion used in the first to fourth embodiments, and modified examples 1 to 11. [Figure 10] FIG. 11 is a plan view showing a basic shape and modified examples 1 to 11 of plated holes in pin insertion portions used in the first to fourth embodiments. [Figure 11] FIG. 1 is a side view of a pin having a basic shape among the pins used in the first to fourth embodiments. [Figure 12]12 is a view taken along line XII-XII in FIG. 11 with respect to the basic shape of the pin and modified examples 1 to 11 shown in FIG. 11. [Figure 13] FIG. 2 is a side view of a pin of a basic shape used in the first to fourth embodiments. [Figure 14] 14 is a diagram showing the basic shape of the pin and the side shapes of Modified Examples 1 to 8, as viewed in the direction of arrow XIV in FIG. 13. [Figure 15] FIG. 11 is a cross-sectional view of a superconducting device according to a fifth embodiment of the present invention. [Figure 16] FIG. 13 is a cross-sectional view of a superconducting device according to a sixth embodiment of the present invention. [Figure 17] 17 is a partial plan view showing the positional relationship between a superconducting circuit chip and a recess in the superconducting device shown in FIG. 16. [Figure 18] FIG. 13 is a cross-sectional view of a superconducting device according to a seventh embodiment of the present invention. [Figure 19] FIG. 13 is a cross-sectional view of a superconducting device according to an eighth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A superconducting device according to an example of a minimum configuration of the present invention will be described with reference to FIG. The superconducting device shown in FIG. 1(a) is a device that utilizes the characteristics of superconductivity, and comprises a superconducting circuit chip 1 provided with a functional circuit, a multilayer substrate 3 having a plurality of wiring layers 2, and a plurality of pins 4 that electrically connect the superconducting circuit chip 1 and the multilayer substrate 3, and the pins 4 are inserted into the wiring layers 2 of the multilayer substrate 3 in a direction that intersects with the wiring layers. The superconducting device shown in FIG. 1(b) is a device that utilizes the characteristics of superconductivity, and comprises a superconducting circuit chip 1 provided with a functional circuit, a multilayer substrate 3 having a plurality of wiring layers 2, an interposer 6 disposed between the multilayer substrate 3 and the superconducting circuit chip 1 and electrically connected to the superconducting circuit chip 1, and having a wiring layer 5 connected to the wiring layer 2 of the multilayer substrate 3, and a plurality of pins 7 that electrically connect the interposer 6 to the multilayer substrate 3, and the pins 7 are inserted into at least one of the wiring layer 2 of the multilayer substrate 3 and the wiring layer 5 of the interposer 6 in a direction that intersects therewith.

[0011] 1(a), by inserting the upper end of the pin 4 in a direction perpendicular to the multilayer substrate 3, the upper end of the pin 4 penetrates the wiring layer 2 while deforming it, and at the penetration point, it comes into close contact with the wiring layer 2 and is electrically connected. The pin 4 penetrates a part of the wiring layer 2 by plastically deforming it, and also penetrates while partially elastically deforming it. Therefore, with the plastic deformation of the metal constituting the wiring layer 2, a large contact area required for electrical connection is secured, and the pin 4 can be tightly connected by the stress generated in the elastically deformed wiring layer 2. Therefore, the pin 4 can increase the reliability of the electrical connection with the wiring layer 2 between the superconducting circuit chip 1 and the multilayer substrate 3.

[0012] In the superconducting device shown in FIG. 1(b), the upper end of the pin 7 is inserted in a direction perpendicular to the wiring layer 2 of the multilayer substrate 3, whereby the upper end of the pin 7 penetrates the wiring layer 2 while deforming it, and is in close contact with the wiring layer 2 at the penetration point, and is electrically connected. The lower end of the pin 7 is inserted while deforming the wiring layer 5 of the interposer 6. The pin 7 penetrates a part of the wiring layers 2 and 5 by plastic deformation, and penetrates another part by elastic deformation, so that a large contact area is secured with the plastic deformation of the metal constituting the wiring layers 2 and 5, and the pin 7 can be in close contact with the wiring layers 2 and 5 by the stress generated in the elastically deformed wiring layers 2 and 5. Therefore, the pin 7 can increase the reliability of the electrical connection with the wiring layers 2 and / or 5 between the multilayer substrate 3 and the interposer 6.

[0013] Furthermore, one method for manufacturing a superconducting device according to a minimum configuration example of the present invention is a method for manufacturing a superconducting device in which a superconducting circuit chip 1 having a functional circuit using superconducting properties and a multilayer substrate 3 having a plurality of wiring layers 2 are electrically connected by a plurality of pins 4, as shown in FIG. 1(a), and is characterized in that the pins 4 are inserted into the wiring layer 2 of the multilayer substrate 3 in a direction intersecting the wiring layer 2, thereby deforming the wiring layer 2. Furthermore, another method for manufacturing a superconducting device according to a minimum configuration example of the present invention is a method for manufacturing a superconducting device in which an interposer 6 electrically connected to a superconducting circuit chip 1 having a functional circuit utilizing superconducting properties is electrically connected to a multilayer substrate 3 having a plurality of wiring layers 2 by a plurality of pins 7, and is characterized in that the pins 7 are inserted into at least one of the wiring layer 2 of the multilayer substrate 3 and the wiring layer 5 of the interposer 6 in a direction intersecting therewith, thereby deforming the wiring layers 2, 5.

[0014] According to the manufacturing method having the above-mentioned configuration, by inserting the upper end of the pin 4 in a direction perpendicular to the multilayer substrate 3, the upper end of the pin 4 penetrates the wiring layer 2 while deforming it, and at the penetration point, it comes into close contact with the wiring layer 2 and is electrically connected. The pin 4 penetrates the wiring layer 2 by plastically deforming a part of it, and also penetrates while elastically deforming a part of it. Therefore, a large contact area is ensured with the plastic deformation of the metal constituting the wiring layer 2, and close contact is achieved by the stress generated in the elastically deformed wiring layer 2, and the reliability of the electrical connection with the wiring layer 2 between the superconducting circuit chip 1 and the multilayer substrate 3 can be improved.

[0015] Furthermore, by inserting the upper end of the pin 7 in a direction perpendicular to the wiring layer 2 of the multilayer substrate 3, the upper end of the pin 7 penetrates the wiring layer 2 while deforming it, and at the penetration point, it comes into close contact with the wiring layer 2 and is electrically connected, and the lower end of the pin 7 penetrates the wiring layer 5 of the interposer 5 while deforming it, so that the pin 7 penetrates a part of the wiring layers 2 and 5 while plastically deforming it, and penetrates another part while elastically deforming it. Therefore, a large contact area is ensured with the plastic deformation of the metal constituting the wiring layers 2 and 5, and close contact is possible due to the stress generated in the elastically deformed wiring layers 2 and 5, and the reliability of the electrical connection between the multilayer substrate 3 and the interposer 6 and the wiring layer 2 and / or 5 can be improved.

[0016] 2 and 3 show a first embodiment of the present invention. The superconducting device of the first embodiment has a basic configuration in which the superconducting circuit chip 1 and the multilayer substrate 30 are connected by pins 40A, 40B, and 40C. In the first to eighth embodiments described below, the superconducting circuit chip refers to an element having a function of processing data using quantum mechanical phenomena caused by quantum bits formed in a superconducting circuit. The multilayer substrate 30 has a base material 31 made of a plate-shaped organic resin or a mixture of this with a reinforcing material such as an organic or inorganic filler, or a reinforcing layer laminated thereon, and wiring layers 21, 22, and 23 composed of conductor circuits of a predetermined pattern laminated on the base material 31 and arranged along the XY plane in the figure.

[0017] The superconducting circuit chip 1 has a function of processing data using quantum mechanical phenomena caused by quantum bits, and has a configuration in which connection parts 12 (which do not necessarily have to be conductor wiring layers forming a circuit pattern, as long as they are conductors that can be connected to circuit elements in the superconducting circuit chip 1) are provided in a predetermined arrangement on the surface of a substrate 11. The connection parts 12 are preferably made of a superconducting material. More specifically, the substrate 11 is made of a material that is less deformed in a superconducting environment, such as silicon (Si), gallium arsenide (GaAs), sapphire, glass, etc. The connection portion 12 constituting the quantum bit circuit formed on the substrate 11 is made of niobium (Nb), niobium nitride such as niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, or an alloy having superconductivity containing at least any of these. In this embodiment, the connecting portion 12 may have a metal layer of gold (Au), platinum (Pt), palladium (Pd), or the like formed on the surface as the metal of the connecting portion, in addition to the superconducting material.

[0018] 2(a), the wiring layers 21, 22, and 23 provided on the base material 31 of the multilayer substrate 30 are made of materials such as copper (Cu) and aluminum (Al), and are formed into a predetermined circuit pattern by means of sputtering, vapor deposition, electroless plating, electrolytic plating, etc. Specific methods for forming a layer of conductive material into a predetermined circuit pattern include a subtractive method using a resist applied to the surface as a mask, an additive method using plating, a SEMI additive method, and a lift-off method in which a pattern is formed by removing the applied resist.

[0019] The structure of the pins 40A, 40B, and 40C will be described in detail with reference to FIG. As shown in Fig. 3, for example, the pin 40A includes an upper pin 41 connected to the wiring layers 21, 22, and 23, and the upper pin 41 is integrally provided with a flange 42 having a larger diameter at its base end. As shown in Fig. 2(a), the upper pins 41 are prepared in a plurality of types with different lengths, such as upper pins 41' shown by chain lines in Fig. 3, depending on the insertion depth (insertion length in the Z-axis direction in Fig. 2) of the pins 40A, 40B, and 40C into the multilayer substrate 30, and an appropriate length is selected depending on whether the pins 40A, 40B, and 40C are to be used. It is assumed that through holes (so-called pilot holes) having an inner diameter slightly larger than that of the upper pin 41 are formed in advance in the base material 31 and the wiring layers 21, 22, and 23 at positions where the pins 40A, 40B, and 40C are to be inserted. The lower surface of the flange 42 is provided with a cylindrical cylinder 43. The cylinder 43 is provided with a cylindrical retaining portion 44 having a smaller diameter than the cylinder 43. The cylinder 43 also supports a lower pin 45 movable in the axial direction and on the same axis as the upper pin 41, and the lower pin 45 is configured to be biased downward by elastically deforming a compression spring 46 when moved upward (Z-axis direction in FIG. 2). The base end of the lower pin 45 has a large diameter portion 47, and the large diameter portion 47 abuts against the retaining portion 44, thereby restricting the length by which the lower pin 45 can move downward (Z-axis direction in FIG. 2) against the bias of the compression spring 46 at a predetermined position.

[0020] The pins 40A, 40B, and 40C have the same configuration as the upper pin 41, but differ only in length. The pin 40A has the longest upper pin 41, and its tip has a length (length from the flange 42 to the tip of the upper pin 41) that allows it to penetrate the uppermost wiring layer 21 of the multilayer substrate 30 through the through hole 21a and protrude upward. The pin 40B has a length (length from the flange 42 to the tip of the upper pin 41) that allows it to penetrate the second wiring layer 22 from the top of the multilayer substrate 30 through the through hole 22a and protrude upward. The pin 40C has a length (length from the flange 42 to the tip of the upper pin 41) that allows it to penetrate the third wiring layer 23 from the top of the multilayer substrate 30 through the through hole 23a and protrude upward.

[0021] As shown in FIG. 2(a), the pin 40A passes through through holes 22b, 23c, which are sufficiently larger in diameter than the upper pin 41 formed in the wiring layers 22, 23, respectively, to reach the wiring layer 21, and penetrates the wiring layer 21 while plastically deforming it, reaching above the through hole 21a. The pin 40B passes through a through hole 23b, which has a diameter sufficiently larger than that of the upper pin 41 formed in the wiring layer 23, reaches the wiring layer 22, and penetrates the wiring layer 22 while plastically deforming it, reaching above the through hole 22a. The pin 40C reaches the lowermost wiring layer 23, and penetrates the wiring layer 23 while plastically deforming it, reaching above the through hole 23a. In the example of FIG. 2(a), the upper pins 41 of the pins 40A, 40B, and 40C all penetrate the wiring layers 21, 22, and 23 from the bottom to the top. In other words, the tips of the upper pins 41 are inserted to a depth that causes them to protrude from the top surfaces of the wiring layers 21, 22, and 23. However, it is not essential that the upper pins 41 completely "penetrate" the wiring layers 21, 22, and 23 and protrude from the top surface. As long as the tips of the upper pins 41 are inserted to a degree that causes at least the bottom surfaces of the wiring layers 21, 22, and 23 to plastically or elastically deform, protrude from the bottom surface to the top surface, have a contact surface with the wiring layers 21, 22, and 23, and generate contact pressure due to elastic deformation between the pins and the through holes 21a, 22a, and 23a of the wiring layers 21, 22, and 23, it is possible to expect the effect of improving the reliability of electrical contact.

[0022] Although the multilayer substrate 30 employs a configuration in which through holes 21a, 22a, and 23a are simply formed in the wiring layers 21, 22, and 23, through holes 24a, 25a, and 26a as in the modified example shown in FIG. 2(b) may also be employed. That is, through holes 24a, 25a, 26a in the modified example are configured by providing a plating layer electrically connected to wiring layers 21, 22, 23, respectively, on base material 31 constituting multilayer substrate 30A. That is, by plating the inner surfaces of through holes 21a, 22a, 23a, at least a part of through holes 21a, 22a, 23a has plating portions 24a, 25a, 26a of conductors electrically connected to wiring layers 21, 22, 23 and reaching the lower surface of multilayer substrate 30A, and the contact area with pins 40A, 40B, 40C can be increased to further improve the reliability of the electrical connection. The inner diameters of the plated portions 24a, 25a, 26a are set to a negative dimensional tolerance with respect to the outer diameters of the pins 40A, 40B, 40C, and are configured to ensure contact pressure by plastic deformation and elastic deformation as the upper pin 41 is inserted. Since the plated portions 24a, 25a, 26a are all formed to a range that reaches the lower surface of the multilayer substrate 30A, the pin 40A does not necessarily need to have a length that reaches the wiring layer 24, and similarly, the pin 40B does not necessarily need a length that reaches the wiring layer 25, so that the pins 40A and 40B need only be the same length as the shortest pin 40C that reaches the wiring layer 26. In other words, pins 40A, 40B, 40C can be of the same length.

[0023] In the superconducting device having the above-mentioned configuration, the pins 40A, 40B, 40C are arranged between the superconducting circuit chip 1 and the multilayer substrate 30 (30A), and the upper pin 41 is inserted in the thickness direction of the multilayer substrate 30 (30A) (the Z-axis direction in the figure), so that the upper pin 41 is inserted while intersecting with the wiring layers 21 (24), 22 (25), 23 (26), and the flange 42 is brought into contact with the underside of the multilayer substrate 30 (30A), thereby regulating the insertion amount to a predetermined depth, and the upper pin 41 can be electrically connected to the wiring layers 21 (24), 22 (25), 23 (26). Here, in the embodiment of Fig. 2(a), the upper pin 41 penetrates the wiring layers 21, 22, 23 while plastically deforming them as it is inserted, and in the embodiment of Fig. 2(b), the upper pin 41 penetrates the plating layers of the through holes 24a, 24b, 24c while plastically deforming them, so that the pins 40A, 40B, 40C can be electrically connected to the wiring layers 21 (24), 22 (25), 23 (26), respectively. Also, in the embodiment of Fig. 2(b), the through holes (plated parts) 24a, 25a, 26a each reach the lower surface of the multilayer board 30A, so that the lengths of the pins 40A, 40B, 40C can be made the same as the shortest pin 40C (having a length that can penetrate the wiring layer 26).

[0024] In addition, the lower pins 45 of the pins 40A, 40B, and 40C are each biased by the compression springs 46, which tend to extend the pins 40A, 40B, and 40C, thereby deforming the surface of the wiring layer (connection portion) 12 of the superconducting circuit chip 1 and making contact therewith, thereby becoming electrically connected.

[0025] According to the above configuration, the upper ends of the upper pins 41 of the pins 40A, 40B, 40C penetrate the wiring layers 21, 23, 23 and deform them to be connected while ensuring a predetermined contact area, and the lower ends of the upper pins 41 of the pins 40A, 40B, 40C are electrically connected while deforming the connection portion 12 of the superconducting circuit chip 1 with a force corresponding to the deformation amount of the compression spring 46.

[0026] A superconducting device according to the second embodiment will be described with reference to Fig. 4. Note that components common to the first embodiment are given the same reference numerals and the description will be simplified. This superconducting device has a basic configuration in which a superconducting circuit chip 1A is connected to a multilayer substrate 30B via an interposer 50, and pins 40D and 40E are used to connect the interposer 50 to the multilayer substrate 30B. The sample stage 60 stores the superconducting circuit chip 1A and the interposer 50 and maintains them at an ultra-low temperature at which a quantum state can be realized. The multilayer board 30B also includes connectors 70A and 70B used for connection to external devices.

[0027] The interposer 50 has a configuration in which wiring layers 52 and 53 are provided on the upper and lower surfaces of an interposer substrate 51 . The interposer substrate 51 is made of a material having superconductivity similar to the superconducting circuit chip 1A, such as silicon (Si), gallium arsenide (GaAs), sapphire, glass, or other material that is less deformed in a superconducting environment. The wiring layers 52 and 53 constituting the superconducting circuit formed on the interposer substrate 51 are made of niobium (Nb), niobium nitride such as niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, and alloys having superconductivity containing at least one of these. A metal layer such as gold (Au), platinum (Pt), or palladium (Pd) may be formed on the surface. Also, a wiring layer 53 on the lower side of the interposer 50 is connected to a wiring layer (connecting portion) 12 of the superconducting circuit chip 1A by a bump 54 made of the same superconducting material as the interposer 50.

[0028] The multilayer substrate 30B includes an upper wiring layer 22 and a lower wiring layer 23, and pins 40D and 40E made of conductors penetrate through the wiring layers 22 and 23. The wiring layer 22 has through holes 22a whose inner diameter is slightly smaller than that of the pins 40D, 40E and which come into contact with the pins 40D, 40E in a plastically and / or elastically deformed state, and through holes 22b whose inner diameter is slightly larger than that of the pins 40D, 40E and which allow the pins 40D, 40E to pass through in a non-contact state. The wiring layer 23 has through holes 23a whose inner diameter is slightly smaller than that of the pins 40D, 40E and which contact the pins 40D, 40E in a plastically and / or elastically deformed state, and through holes 23b whose inner diameter is slightly larger than that of the pins 40D, 40E and which allow the pins 40D, 40E to pass through in a non-contact state.

[0029] The pin 40D contacts the wiring layer 22 at the through hole 22a, passes through the wiring layer 23 at the through hole 23b, and contacts the wiring layer 52 of the interposer 50, thereby electrically connecting the wiring layer 52 of the interposer 50 to the wiring layer 22. Furthermore, the wiring layer 22 is connected to a connector 70B, and forms a circuit extending from the interposer 50 through the wiring layer 52, the pin 40D, the wiring layer 22, and the through via 22c to the connector 70B. The pin 40D contacts the wiring layer 22 at the through hole 22a and passes through the wiring layer 23 at the through hole 23b, thereby electrically connecting the wiring layer 52 of the interposer 50 to the wiring layer 22. Furthermore, the wiring layer 22 is connected to a connector 70B, and forms a circuit extending from the interposer 50 through the wiring layer 52, the pin 40D, the wiring layer 23, and the through via 22c to the connector 70B. Furthermore, the pin 40E contacts the wiring layer 23 at through hole 23a, passes through wiring layer 22 at through hole 22b, and contacts the wiring layer 52 of the interposer 50, thereby electrically connecting the wiring layer 52 of the interposer 50 to the wiring layer 23. Furthermore, the wiring layer 23 is connected to a connector 70A, and forms a circuit extending from the interposer 50 through the wiring layer 52, pin 40E, wiring layer 23, and through via 23d to the connector 70A.

[0030] The sample stage 60 has a cooling function. The sample stage 60 is a so-called cold stage equipped with a cryogenic refrigerator (not shown) of about millikelvin [mK] that can realize a superconducting state in the materials constituting the superconducting circuit chip 1A and the interposer 50. The sample stage 60 is desirably made of metal such as copper (Cu), a copper alloy, aluminum (Al), etc. For example, when the superconducting material of the superconducting circuit chip 1 contains niobium (Nb), the superconducting phenomenon is utilized at ultra-low temperatures of 9.2 Kelvin [K] or less, and when the superconducting material contains aluminum (Al), the superconducting phenomenon is utilized at ultra-low temperatures of 1.2 Kelvin [K] or less, so the sample stage 60 is required to have a cooling capacity capable of realizing the ultra-low temperatures exemplified above. The sample stage 60 has a recess 61 which is open upward and has a shape corresponding to the planar shapes of the superconducting circuit chip 1 and the interposer 50, for example a rectangular planar shape. The superconducting circuit chip 1A is stored in the recess 61. The superconducting circuit chip 1A has a substrate 11 and a connection portion (wiring layer) 12 on its upper surface, and in the illustrated example, is fixed to the recess 61 by an adhesive portion 13 on the upper surface. Note that mechanical fixing means such as a concave-convex fit using a pin may be used instead of the adhesive portion 13, or the fixing means may be omitted.

[0031] In the superconducting device of the second embodiment, the superconducting circuit chip 1A and the interposer 50 are connected to each other by bumps 54 to be integrated, and this is placed in the recess 61 of the sample stage 60. Furthermore, pins 40D, 40E are penetrated in the thickness direction (Z-axis direction) of the multilayer substrate 30B, and the lower ends of these pins 40D, 40E are brought into contact with the wiring layer 52 of the interposer 50, or the lower ends of the pins 40D, 40E are partially penetrated while deforming the surface of the wiring layer 52, whereby the superconducting circuit chip 1 can be connected to an external device via a connector 70A connected to the second wiring layer 23 and a connector 70B connected to the first wiring layer 22.

[0032] A superconducting device according to the third embodiment will be described with reference to Fig. 5. Note that components common to the first and second embodiments are given the same reference numerals and the description will be simplified. The multilayer substrate 30C of the third embodiment has one wiring layer 22. The upper ends of the pins 40D penetrate the wiring layer 22, and the lower ends of the pins 40D contact the wiring layer 52 of the interposer 50. The wiring layer 22 is connected to the connectors 70A and 70B via through vias 22c.

[0033] In this third embodiment, the upper end of the pin 40D penetrates the wiring layer 22, thereby making contact with the wiring layer 22 while causing the wiring layer 22 to be plastically and elastically deformed, thereby enabling the superconducting circuit chip 1A to be connected to an external device via the wiring layer 52 of the interposer 50, the pin 40D, the wiring layer 22, the through via 22c, and the connector 70A (70B).

[0034] A superconducting device according to the fourth embodiment will be described with reference to Fig. 6. Note that components common to the first to fourth embodiments are given the same reference numerals and description thereof will be simplified. The multilayer substrate 30D of the fourth embodiment has an upper wiring layer 24 and a lower wiring layer 26. The upper ends of pins 40D penetrate the wiring layer 24, and the lower ends of the pins 40D contact the wiring layer 52 of the interposer 50. The wiring layer 22 is connected to the connectors 70A and 70B via through vias 22c. The wiring layer 22 has a through hole 24a, and the inner surface of the through hole 24a is plated to form a plated portion. Furthermore, the upper end of a pin 40F penetrates the wiring layer 26, and the lower end of the pin 40F contacts the wiring layer 52 of the interposer 50. The wiring layer 26 has a through hole 26a, and the inner surface of the through hole 26a is plated to form a plating layer. Furthermore, the wiring layer 26 has a through hole 26a for passing the pin 40D to be connected to the upper wiring layer 24, and this through hole 26a has an inner diameter sufficiently larger than the outer diameter of the pin 40D. Note that in Fig. 6, the pin 40F has a length sufficient to penetrate the wiring layer 26 and does not reach the upper wiring layer 24, but in order to avoid contact with the wiring layer 24 when a pin longer than the pin 40F (having a length sufficient to penetrate the wiring layer 24) and having the same length as the pin 40D is used instead of the pin 40F, a through hole 24b having an inner diameter larger than the outer diameter of the pin 24F is provided at a position of the wiring layer 24 corresponding to the pin 24F.

[0035] In the fourth embodiment, the upper end of the pin 40D penetrates the wiring layer 24, thereby contacting the plating layer constituting the through hole 24a of the wiring layer 24 in a state of being plastically and elastically deformed, and thus the superconducting circuit chip 1A can be connected to an external device via the wiring layer 52 of the interposer 50, the pin 40D, the wiring layer 24, the through via 22c, and the connector 70B. Also, the upper end of the pin 40F contacts the plating layer constituting the through hole 26a of the wiring layer 26 in a state of being plastically and elastically deformed. Such contact allows the superconducting circuit chip 1A to be connected to an external device via the wiring layer 52 of the interposer 50, the pin 40F, the wiring layer 26, the through via 22d, and the connector 70A. According to the above configuration, pin 40D and wiring layer 24 can be electrically connected via through hole 24a having a plating layer, and pin 40F and wiring layer 26 can be electrically connected via through hole 26a having a plating layer. This connection can ensure the largest possible contact area and contact pressure while deforming the plating layers of through holes 24a and 26a, thereby improving the reliability of the electrical connection.

[0036] 7 shows a comparative example that does not have the features of the first to fourth embodiments. In the figure, the same components as those in the embodiments are given the same reference numerals, and the explanation will be simplified. The superconducting device of this comparative example has a configuration in which an interposer 50 provided on a superconducting circuit chip 1A and a multilayer substrate 30F are electrically connected by a pin 40G. More specifically, the lower end of the pin 40G contacts a wiring layer 52 of the interposer 50, and the upper end of the pin 40G contacts a wiring layer (not shown) on the lower surface of the multilayer substrate 30F. The multilayer substrate 30F, like each embodiment of the present invention, has a wiring layer (not shown), and when the upper ends of the pins 40G contact the wiring layer on the lower surface, connectors 70A, 70B electrically connected to the wiring layer are connected to the superconducting circuit chip 1A via the wiring layer-pins 40G-interposer 50.

[0037] In this comparative example, the contact state (contact pressure) between the pin 40G and the wiring layer changes due to thermal expansion and contraction caused by temperature changes from low temperature at which the superconducting circuit chip 1A and the interposer 50 can achieve a superconducting state to room temperature, and the pin 40G has a structure in which the pointed tip of the pin 40G makes point contact, so that the contact resistance between the pin 40G and the wiring layer becomes excessive or the pin 40G goes into a non-contact state, which may cause a contact failure. It is difficult to reliably prevent this contact failure, even if the pin 40G has a structure that can expand and contract by incorporating a spring or the like. In contrast to this, in the first to fourth embodiments, the pins 40A, 40B, etc. penetrate the wiring layer 21, etc. (including not only penetrating completely in the thickness direction, but also being inserted halfway in the thickness direction) and come into contact with the cross section of the wiring layer 21, etc. or the plastically deformed or elastically deformed areas, thereby ensuring a large contact area and a predetermined contact pressure, thereby improving the reliability of the electrical connection.

[0038] A modified example of the first embodiment shown in Figures 2 and 3 will be described with reference to Figure 8. In order to facilitate understanding of the modified example, Figure 8(a) shows the same configuration as Figure 2(a) as Basic Form 1, and Figure 8(b) shows the same configuration as Figure 2(b) as Basic Form 2. That is, the superconducting device of basic type 1 shown in FIG. 8(a) has a basic configuration in which the superconducting circuit chip 1 and the multilayer substrate 30 are connected by pins 40A, 40B, and 40C. The multilayer substrate 30 has a base material 31 and wiring layers 21 , 22 , and 23 laminated on the base material 31 .

[0039] The superconducting circuit chip 1 shown in FIG. 8(a) has a function of processing data using quantum mechanical phenomena caused by quantum bits, and has a configuration in which connection parts 12 are provided on the surface of a substrate 11 in a predetermined arrangement. As shown in FIG. 8(a), the wiring layers 21, 22, and 23 provided on the base material 31 of the multilayer substrate 30 are made of a material such as copper (Cu) or aluminum (Al) and have a predetermined circuit pattern formed thereon.

[0040] As shown in the figure, the upper pin 41 of the pin 40A is prepared in a plurality of types with different lengths, such as the upper pin 41' shown by the chain line in FIG. 3, according to the insertion depth of the pins 40A, 40B, and 40C into the multilayer substrate 30. The tip of the pin 40A has a length (length from the flange 42 to the tip of the upper pin 41) that allows it to penetrate the uppermost wiring layer 21 of the multilayer substrate 30 through the through hole 21a and protrude upward. The pin 40B has a length (length from the flange 42 to the tip of the upper pin 41) that allows it to penetrate the second wiring layer 22 from the top of the multilayer substrate 30 through the through hole 22a and protrude upward. The pin 40C has a length (length from the flange 42 to the tip of the upper pin 41) that allows it to penetrate the third wiring layer 23 from the top of the multilayer substrate 30 through the through hole 23a and protrude upward.

[0041] The through holes 24a, 25a, and 26a of the basic form 2 shown in FIG. 8(b) are configured by providing plated portions electrically connected to the wiring layers 21, 22, and 23, respectively, in the base material 31 that constitutes the multilayer substrate 30A. According to the above configuration, the upper ends of the upper pins 43 of the pins 40A, 40B, 40C penetrate the wiring layers 21, 23, 23 (more specifically, the plated portions 24a, 25a, 26a on the inner surface of the through holes integral with these) and are connected while deforming them and ensuring a predetermined contact area, and the lower ends of the upper pins 43 of the pins 40A, 40B, 40C are electrically connected while deforming the connection portion 12 of the superconducting circuit chip 1 with a force corresponding to the deformation amount of the compression spring 46.

[0042] 8(c) shows Modification 1. That is, the multilayer substrate 30A has a configuration in which the pins 40A, 40B, 40C of different lengths are inserted into the positions where they should be inserted, and the through holes 32 are provided to penetrate the pins in the vertical direction, regardless of the lengths of the pins 40A, 40B, 40C. Therefore, the pins 40A, 40B, 40C are inserted near the upper opening, the middle, or near the lower opening of the pins 32 according to their lengths, and penetrate the wiring layers 21, 22, 23 at the through holes 21a, 22a, 23a.

[0043] In this variant example 1, all of the through holes 32 that serve as pilot holes for the through holes 21a, 22a, and 23a in the multilayer substrate 30 are formed from the top surface to the bottom surface of the base material 31. In other words, pilot holes for connecting each pin 40A, 40B, and 40C to the specified wiring layers 21, 22, and 23 can be formed without requiring particularly high processing accuracy for the drilling depth of the through holes 32.

[0044] 8(d) shows Modification 2. That is, the multilayer substrate 30A has through holes 32 penetrating the positions where the pins 40A, 40B, 40C are to be inserted from the upper surface to the lower surface, as in Modification 1. Also, below the positions where these through holes 32 intersect with the wiring layers 21, 22, 23, there are plated parts 24a, 25a, 26a electrically connected to these wiring layers 21, 22, 23. Also, since these plated parts 24a, 24b, 24c are formed up to the lower surface of the multilayer substrate 30A, the length of the pins 40A, 40B, 40C is unified to the same as the shortest pin 40C (having a length that can penetrate the wiring layer 26).

[0045] Even in this variant example 2, all of the through holes 32 which serve as pilot holes when forming the plated portions 24a, 25a, 26a in the multilayer substrate 30A can be made to penetrate vertically. In other words, pins 40A, 40B, 40C which are configured to be the same length can be connected to each wiring layer 21, 22, 23 without requiring particularly high processing accuracy for the drilling depth of the through holes 32.

[0046] 8(e) shows Modification 3. That is, the multilayer substrate 30A has through holes 32, 32A, 32B provided at positions where pins 40A, 40B, 40C of different lengths should be inserted, the through holes penetrating the wiring layers 21, 22, 23 to which the pins 40A, 40B, 40C should be connected, depending on the lengths of the pins 40A, 40B, 40C. Specifically, the through hole 32 penetrates through all of the wiring layers 21, 22, and 23 to reach the multilayer substrate 30 from the bottom to the top, the through hole 32A penetrates through the wiring layers 22 and 23 to a point where it reaches the bottom surface of the wiring layer 21, and the through hole 32B penetrates through the wiring layer 23 to a point where it reaches the bottom surface of the wiring layer 22. The pins 40A, 40B, 40C penetrate the wiring layers 21, 22, 23 at the through holes 21a, 22a, 23a in accordance with their lengths, and are connected thereto.

[0047] In this variant example 3, by forming through holes 32, 32A, and 32B, which serve as pilot holes for the through holes 21a, 22a, and 23a, in the multilayer substrate 30 to a predetermined depth, pins 40A, 40B, and 40C having different shell lengths can be connected to the predetermined wiring layers 21, 22, and 23, respectively.

[0048] 8(f) shows Modification 4. That is, the multilayer substrate 30A has through holes 32C, 32D, and 32E to a predetermined depth at the positions where the pins 40A, 40B, and 40C are to be inserted, similarly to Modification 3. Below the points where these through holes 32C, 32D, 32E intersect with the wiring layers 21, 22, 23, there are plated portions 24a, 25a, 26a electrically connected to these wiring layers 21, 22, 23. Since these plated portions 24a, 24b, 24c are formed up to the lower surface of the multilayer substrate 30A, the lengths of the pins 40A, 40B, 40C are unified to the same as the shortest pin 40C (having a length sufficient to penetrate the wiring layer 26).

[0049] Even in this variant example 4, through holes 32 which serve as pilot holes when forming the plated portions 24a, 25a, 26a can be penetrated to a predetermined depth in the multilayer substrate 30A, and pins 40A, 40B, 40C which are configured to be the same length can be connected to each wiring layer 21, 22, 23.

[0050] FIG. 9 shows a modified example of the cross-sectional shape of the through hole (the pin that is reflexively inserted into the through hole) employed in the first and third embodiments. Generally, the through holes 21a, 22a, 23a and the pins 40A, 40B, 40C, 40D, 40E, 40F made of metal or the like have a perfect circular cross section in consideration of ease of machining into a predetermined shape, but on the other hand, the perfect circular shape minimizes the contact area with the wiring layers 24, 25, 26 at the through holes. Therefore, adopting a shape other than a perfect circle to increase the contact area is also effective for stable electrical connection.

[0051] Reference numeral 80 denotes a perfect circle, which is the same basic shape as the through-hole 21a and the like. Reference numeral 81 denotes an ellipse according to the first modified example. Reference numeral 82 denotes an oval of the second modified example. Reference numerals 83 to 85 denote modified examples 3 to 5 that are polygonal, with reference numeral 83 denoting a triangle, reference numeral 84 denoting a quadrangle (square), and reference numeral 85 denoting an octagon. Reference numerals 86 to 88 denote modified examples 6 to 8 which are star-shaped polygons (projected shapes in which the vertices of polygons are shifted and superimposed), and reference numerals 86, 87, and 88 denote star shape 1, star shape 2, and star shape 3, respectively. Reference numerals 89 to 91 indicate further modified examples 9 to 11, where reference numeral 89 indicates a semicircle, reference numeral 90 indicates a cross shape, and reference numeral 91 indicates an L-shape.

[0052] According to these modifications 1 to 11, the contact areas between the through holes 21a, 22a, and 23a and the pins 40A, 40B, 40C, 40D, 40E, and 40F can be made larger than when the through holes are made perfectly circular.

[0053] FIG. 10 shows a modified example of the cross-sectional shape of the plated portion (the pin that is reflectively inserted into the through hole) employed in the second and fourth embodiments. Reference numeral 92 denotes a perfect circle, which is the same basic shape as the plated portion 24a and the like. Reference numeral 93 denotes an ellipse according to the first modified example. Reference numeral 94 denotes an oval of the second modified example. Reference numerals 95 to 97 denote modified examples 3 to 5 which are polygonal, with reference numeral 95 denoting a triangle, reference numeral 96 denoting a quadrangle (square), and reference numeral 97 denoting an octagon. Reference numerals 98 to 100 denote modified examples 6 to 8 which are star-shaped polygons (projected shapes in which the vertices of polygons are shifted and superimposed), and reference numerals 98, 99, and 100 denote star shape 1, star shape 2, and star shape 3, respectively. Reference numerals 101 to 103 denote star-shaped polygons which are further modified examples 9 to 11, with reference numeral 101 denoting a semicircle, reference numeral 102 denoting a cross shape, and reference numeral 103 denoting an L-shape.

[0054] According to these modifications 1 to 11, the contact area between the plated portions 24a, 25a, and 26a as through holes and the pins 40A, 40B, 40C, 40D, 40E, and 40F can be made larger than when the through holes are made perfectly circular.

[0055] 11 and 12 show upper pins 41 to 41L according to modified examples corresponding to the modified through holes shown in FIGS. 9 and 10. Reference numeral 41 denotes a perfect circle, which is the basic shape similar to that of the first to fourth embodiments. Reference numeral 41A denotes an ellipse according to the first modified example. Reference numeral 41B denotes an oval of the second modified example. Reference numerals 41C to 41E denote modified examples 3 to 5 that are polygonal, with reference numeral 41C denoting a triangle, reference numeral 41D denoting a quadrangle (square), and reference numeral 41E denoting an octagon. Reference numerals 41F to 41H denote modified examples 6 to 8 which are star-shaped polygons (projected shapes in which the vertices of polygons are shifted and superimposed), and reference numerals 41F, 41G, and 41H denote star shape 1, star shape 2, and star shape 3, respectively. Reference numerals 41J to 41L indicate further modified examples 9 to 11, with reference numeral 41J indicating a semicircle, reference numeral 41K indicating a cross shape, and reference numeral 41L indicating an L-shape.

[0056] According to these modifications 1 to 11, the contact areas between the through holes 21a, 22a, 23a and the pins 40A, 40B, 40C, 40D, 40E, 40F can be made larger than when the upper pins 41, 41A to 41L are made perfectly round.

[0057] 13 and 14 show upper pins 41, 41M to 41U according to modified examples corresponding to the modified through holes shown in FIGS. Reference numeral 41 denotes a conical upper pin having the same basic shape as in the first to fourth embodiments. Reference numeral 41M denotes an upper pin according to Modification Example 1, and this upper pin 41M has a configuration in the shape of a truncated cone with a flat tip. Since this upper pin 41M has a flat tip and a conical surface portion continuing from the tip, it is possible to increase the contact area with the wiring layer 21, etc. Reference numeral 41N denotes an upper pin according to Modification 2, and this upper pin 41N has a spherical tip. Since the tip of this upper pin 41N is spherical, it is possible to maintain a stable contact state by closely adhering to the wiring layer 21 etc. while deforming along the spherical surface.

[0058] Reference numeral 41P denotes an upper pin according to Modification 3, and this upper pin 41P has, on its surface, grooves 41a that are inclined in one direction and the other direction with respect to the axis of the upper pin 41P. In this upper pin 41P, the metal constituting the wiring layer 21, etc., is plastically or elastically deformed and bites into the unevenness of the grooves 41a, thereby enabling the upper pin 41P to maintain a stable contact state. Reference numeral 41Q denotes an upper pin according to Modification 4, which has a circumferential groove 41b on its surface that is oriented horizontally relative to the axis of the upper pin 41Q. In this upper pin 41Q, the metal constituting the wiring layer 21, etc., is plastically or elastically deformed and bites into the unevenness of the groove 41b, thereby enabling the upper pin 41Q to maintain a stable contact state. Reference numeral 41R denotes an upper pin according to Modification 5, and this upper pin 41R has, on its surface, a groove portion 41c that is inclined in one direction with respect to the axis of the upper pin 41R. In this upper pin 41R, the metal constituting the wiring layer 21, etc., is plastically or elastically deformed and bites into the unevenness of the groove portion 41c, thereby enabling the upper pin 41R to maintain a stable contact state.

[0059] Reference numeral 41S denotes an upper pin according to the sixth modification, and this upper pin 41S has a configuration including a constricted portion 41e between a conical tip portion 41d and a cylindrical base portion 41f, the constricted portion 41e having a smaller diameter than these portions. In this variant example 6, when tip portion 41d penetrates wiring layer 21 etc., narrowed portion 41e deforms, so that it can accommodate any misalignment between the direction in which force is applied to pin 40A etc. and the direction of through hole 21a etc. Also, tip portion 41d is inserted until it reaches above the top surface of wiring layer 21, and narrowed portion 41e is positioned in the same position as through hole 21a etc., which has the effect of preventing tip portion 41d from coming out. Symbol 41T is an upper pin relating to variant example 7, and this upper pin 41T has two narrowed portions 41e with smaller diameters than the conical tip portion 41d and the cylindrical base portion 41f between them, and has an intermediate portion 41g between these two narrowed portions 41e. In this variant 7, as in variant 6, the two narrowed portions 41e each deform when the tip portion 41d penetrates the wiring layer 21, etc., and this allows the pin 40A, etc. to more flexibly follow any misalignment between the direction in which force is applied to the pin 40A, etc. and the direction of the through hole 21a, etc. In addition, the tip portion 41d or the middle portion 41g is inserted until it reaches above the upper surface of the wiring layer 21, and one of the two narrowed portions 41e is positioned in the same position as the through hole 21a, etc., thereby preventing the tip portion 41d or the middle portion 41g from coming out.

[0060] Reference numeral 41U denotes an upper pin according to the eighth modification, and this upper pin 41U has a long hole 41h in a cylindrical base portion 41f that is integral with a conical tip portion 41d. In this variant example 8, the base 41f has a long hole 41h, so that the base 41f can be deformed more easily than when it is solid, and by coming into contact with the wiring layer 21 in the deformed state, the contact pressure can be increased.

[0061] FIG. 15 shows a superconducting device according to the fifth embodiment. In the superconducting device of the fifth embodiment, the lower surface 14 of the superconducting circuit chip 1A is in contact with a sample stage 60 having a cooling function. For example, in the fifth embodiment, a recess 61 is formed in the sample stage 60. An upper surface 62 of the recess 61 is, for example, a bottom surface facing the Z-axis direction. The recess 61 opens to the Z-axis direction, and when viewed from above, the recess 61 and the upper surface 62 are, for example, rectangular. The superconducting circuit chip 1 A has a planar shape smaller than the recess 61 , and its lower surface 14 is in contact with the upper surface 62 of the recess 61 .

[0062] The portion of the interposer 50 in contact with the sample stage 60 may not require the wiring layer 53 to be formed, or the wiring layer 53 may be formed if an insulating film is formed on the portion in contact with the sample stage 60 to prevent electrical conduction with the sample stage 60.

[0063] In the superconducting device of the fifth embodiment, at least a part of the interposer 50 is in contact with the sample stage 60. In this way, by using the interposer 50 as a heat flow path, the quantum circuit in the superconducting circuit chip 1A can be cooled to an extremely low temperature and the superconducting phenomenon can be utilized. Moreover, the superconducting circuit chip 1A is placed inside a sample stage 60 having a cooling function, and its lower surface 14 is in contact with the bottom surface of a recess 61 of the sample stage 60 without an adhesive therebetween. At least a part of the lower surface 14 may be in contact with a part of the inner surface of the recess 61. With this configuration, the superconducting circuit chip 1A can be cooled by thermal conduction due to direct contact between the superconducting circuit chip 1A and the upper surface 62 of the recess 61 of the sample stage 60, improving the cooling performance. Therefore, the operation of the quantum circuit in the superconducting circuit chip 1A can be stabilized. Furthermore, since the bottom surface 14 of the superconducting circuit chip 1A is only in contact with the top surface 62 of the recess 61, the superconducting circuit chip 1A can move on the XY plane in FIG. 15, and stress and distortion due to the difference in contraction between the superconducting circuit chip 1A and the sample stage 60 caused by a temperature change to an extremely low temperature can be suppressed.

[0064] 16 and 17 show a superconducting device according to the sixth embodiment. As shown in the cross-sectional view of FIG. 16 and the plan view of FIG. 17, the superconducting device of the sixth embodiment has a recess 65 formed by spot facing or the like on the lower surface 62 of the recess 61 of the sample stage 60A. As shown in Fig. 17, the region in which the recess 65 exists is larger than the region 15 surrounding the region in which the quantum circuit is formed in the superconducting circuit chip 1A when viewed from above (as viewed in the Z direction in Figs. 16 and 17). Thus, the region 15 is included inside the region in which the recess 65 exists. The peripheral portion of the lower surface of the superconducting circuit chip 1A may contact the bottom of the recess 61. Therefore, the central portion of the lower surface of the superconducting circuit chip 1A covers the recess 65, and the peripheral portion of the central portion of the lower surface contacts a part of the lower surface 62 of the sample stage 60A.

[0065] In the superconducting device of the sixth embodiment, the area of ​​the recess 65 is larger than the area 15 in which the quantum circuit is formed (specifically, the area on the outer edge of the area in which the quantum circuit is formed) when viewed from above, so that the distance between the area 15 in which the quantum circuit is formed and the sample stage 60A made of a material including metal or the like can be increased. This makes it possible to suppress the generation of a pseudo capacitor caused by the conductor circuits facing each other between conductors, and to reduce the effect of resonance occurring in the substrate 11 such as silicon of the superconducting circuit chip 1A. Therefore, the effect on the operating frequency of the quantum circuit chip 1A can be reduced.

[0066] FIG. 18 shows a superconducting device according to the seventh embodiment. In the eighth embodiment, a sample stage 60B has a through hole 66 at the bottom of a recess 11. Fig. 18 is a cross-sectional view illustrating a through hole 66 formed at the bottom of a recess 61 of a sample stage 60B according to the seventh embodiment. As shown in FIG. 18, in the superconducting device of the seventh embodiment, a through hole 66 is formed at the bottom of the recess 61. As in the case of FIG. 17 according to the sixth embodiment, the area of ​​the through hole 66 is larger than the area 15 in which the quantum circuit is formed when viewed from above. Therefore, the area 15 in which the quantum circuit is formed is included inside the area of ​​the through hole 66. Therefore, the periphery of the lower surface 14 of the superconducting circuit chip 1A may be in contact with the bottom of the recess 61, or may be bonded or joined to the bottom of the recess 61. Therefore, the center of the lower surface 14 of the superconducting circuit chip 1A covers the through hole 66.

[0067] In the superconducting device of the seventh embodiment, the area of ​​the through-hole 66 is larger than the area 15 in which the quantum circuit is formed when viewed from above, so that the distance between the area 15 in which the quantum circuit is formed and the sample stage 60A made of a material including metal or the like can be increased. This can reduce the effect of resonance occurring in the main material such as silicon of the chip substrate 15. Therefore, the effect on the operating frequency of the superconducting circuit chip 1A can be reduced.

[0068] FIG. 19 shows a superconducting device according to the eighth embodiment. In the eighth embodiment, the recess 65 of the recess 61 has pillars 67. Fig. 19 is a cross-sectional view illustrating the recess 65 and pillars 67 formed at the bottom of the recess 61 of the sample stage 60C according to the eighth embodiment. 19, in the superconducting device of the eighth embodiment, a recess 65 is formed at the bottom of a recess 61. One or more pillars 67 are provided in the recess 65. The pillars 67 extend in a direction perpendicular to the lower surface 14 of the superconducting circuit chip 1A and the lower surface 62 of the sample stage 60 (the XY plane in the figure). One end of the pillar 67 is connected to the bottom of the recess 65, and the other end of the pillar 67 is in contact with the lower surface 14 of the superconducting circuit chip 1A. In this way, the superconducting circuit chip 1A is in contact with the pillar 67 extending from the bottom of the recess 65 in a direction perpendicular to the lower surface 14 of the superconducting circuit chip 1A. The pillar 67 may be cylindrical or columnar. The pillar 67 is made of, for example, a normal conducting material similar to or different from the wiring of the interposer 50, a superconducting material, or a ceramic material having high thermal conductivity. One or more pillars 67 and the lower surface 14 of the superconducting circuit chip 1A may be bonded by an adhesive layer or may be joined by a metal layer. In the eighth embodiment, the area of ​​the recess 65 is larger than the area in which the quantum circuit is formed when viewed from above, so that the distance between the area in which the quantum circuit is formed and the sample stage 60 including metal or the like can be increased. It is possible to reduce the effect of resonance occurring in the substrate 11 such as silicon of the superconducting circuit chip 1A. This reduces the effect on the operating frequency of the superconducting circuit chip 1A, and at the same time, the pillars 67 are in contact with the lower surface 14 of the superconducting circuit chip 1A, enabling direct heat conduction between the pillars 67 and the superconducting circuit chip 1A, thereby improving the cooling performance. The pillars 67 may be movable in the vertical (Z-axis) direction from the bottom of the recess 65. The positions, shapes, and numbers of the recesses 65 and through-holes 66 may be changed depending on the area in which the quantum circuit of the superconducting circuit chip 1A is formed. The positions, numbers, and lengths of the pillars 67 may also be changed.

[0069] The specific configuration of the components of the superconducting device, such as the number of wiring layers constituting the multilayer substrate, the distribution range, the number and length of pins and through holes, etc., are not limited to those in the above embodiment.

[0070] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and design modifications and the like are also included within the scope of the present invention that does not deviate from the gist of the present invention. The superconducting device of the present invention may also be used in other devices that utilize superconductivity, such as magnetic field sensors, memories, and amplifiers.

[0071] A part or all of the above-described embodiments can be described as in the following supplementary notes, but are not limited to the aspects specified in the supplementary notes. (Appendix 1) A superconducting device that utilizes the characteristics of superconductivity, comprising: a superconducting circuit chip having a functional circuit; a multilayer substrate having a plurality of wiring layers; and a plurality of pins that electrically connect the superconducting circuit chip and the multilayer substrate, the pins being inserted into the wiring layers of the multilayer substrate in a direction that intersects with the wiring layers. (Appendix 2) A superconducting device that utilizes the characteristics of superconductivity, comprising: a superconducting circuit chip provided with a functional circuit; a multilayer substrate having a plurality of wiring layers; an interposer disposed between the multilayer substrate and the superconducting circuit chip, the interposer having a wiring layer that is electrically connected to the superconducting circuit chip and is connected to the wiring layer of the multilayer substrate; and a plurality of pins that electrically connect the interposer to the multilayer substrate, the pins being inserted into at least one of the wiring layer of the multilayer substrate and the wiring layer of the interposer in a direction that intersects therewith. (Appendix 3) 3. A superconducting device according to claim 1, wherein the pin is electrically connected to one or more of the wiring layers of the multilayer substrate. (Appendix 4) 4. The superconducting device according to any one of claims 1 to 3, wherein the pin is extendable and retractable in the longitudinal direction. (Appendix 5) 5. The superconducting device according to any one of claims 1 to 4, wherein at least a portion of the inserted region of the pin is in contact with the multilayer substrate or the superconducting circuit chip. (Appendix 6) 6. The superconducting device according to any one of claims 1 to 5, wherein the multilayer substrate into which the pin is inserted has a plurality of wiring layers, and some of the plurality of wiring layers have a through hole having a diameter larger than that of the pin through which the pin passes. (Appendix 7) 7. A superconducting device according to any one of claims 1 to 6, wherein the multilayer substrate has a plurality of wiring layers along the insertion direction of the pins, and at least some of the pins have a length along the insertion direction that is different from other pins. (Appendix 8) 8. A superconducting device according to any one of claims 1 to 7, wherein the wiring layer has a plating portion surrounding a through hole into which the pin is inserted and made of a conductive material that is integral with the conductive material that constitutes the wiring layer. (Appendix 9) 9. The superconducting device described in Appendix 8, wherein the wiring layer is provided across multiple layers in a thickness direction of the multilayer substrate, and the plating portion is formed on an entire inner surface of a through hole extending from one wiring layer to one surface of the multilayer substrate. (Appendix 10) 10. The superconducting device according to any one of claims 1 to 9, wherein the through-hole has a cross section that is a perfect circle. (Appendix 11) 11. The superconducting device according to any one of claims 1 to 10, wherein the pin has a cross section that is a perfect circle. (Appendix 12) 10. The superconducting device according to any one of claims 1 to 9, wherein the through-hole has a non-circular cross section. (Appendix 13) 13. The superconducting device according to any one of claims 1 to 9 and 12, wherein the pin has a non-circular cross section. (Appendix 14) 14. The superconducting device according to any one of claims 1 to 13, wherein the pin has a surface having uneven grooves. (Appendix 15) 15. The superconducting device according to any one of claims 1 to 14, having a hole passing through the pin. (Appendix 16) 16. A superconducting device according to any one of appendices 1 to 15, comprising a recess for accommodating at least one of the superconducting circuit chip according to appendices 1, the superconducting circuit chip according to appendices 2, and an interposer, and comprising a sample stage for cooling the accommodated superconducting circuit chip and / or the interposer, the recess of the sample stage being in contact with a lower surface of the superconducting circuit chip. (Appendix 17) 17. The superconducting device according to claim 1, wherein a surface of said superconducting circuit and an inner surface of said recess of said sample stage are in direct contact with each other. (Appendix 18) 17. The superconducting device according to claim 1, wherein a surface of said superconducting circuit and an inner surface of said recess of said sample stage are in contact with each other via an adhesive layer. (Appendix 19) 17. The superconducting device according to claim 16, wherein the recess in the sample stage has a countersunk recess at its bottom, the recess opening toward a quantum circuit of the superconducting circuit chip. (Appendix 20) 20. The superconducting device of claim 19, wherein the countersunk recess has a pillar for thermally conducting between the countersunk recess and a bottom surface of the superconducting circuit chip. (Appendix 21) 17. The superconducting device according to claim 16, wherein the recess in the sample stage has a through hole penetrating its bottom, the through hole opening toward a quantum circuit of the superconducting circuit chip. (Appendix 22) A method for manufacturing a superconducting device in which a superconducting circuit chip having a functional circuit utilizing superconducting properties is electrically connected to a multilayer substrate having a plurality of wiring layers by a plurality of pins, the method being characterized in that the pins are inserted into the wiring layer of the multilayer substrate in a direction intersecting the wiring layer, thereby deforming the wiring layer. (Appendix 23) A method for manufacturing a superconducting device in which an interposer, which is electrically connected to a superconducting circuit chip having a functional circuit that utilizes superconducting properties, is electrically connected to a multilayer substrate having multiple wiring layers by multiple pins, the method being characterized in that the wiring layer is deformed by inserting the pins into at least one of the wiring layer of the multilayer substrate and the wiring layer of the interposer in a direction that intersects with the wiring layer. [Industrial Applicability]

[0072] The present invention can be used in superconducting devices and methods for manufacturing the same. [Explanation of symbols]

[0073] 1. 1A superconducting circuit chip 2 wiring layers 3 Multilayer board 4 pin 5 wiring layer 6 Interposer 7-pin 11 Base material 12 Connection section (wiring layer) 13 Adhesive part 14 Bottom side 21, 22, 23, 24, 25, 26 wiring layer 21a, 22a, 22b, 23a, 23b, 23c through hole 22c, 23d Through via 24a, 25a, 26a Through holes (plated parts) 25b, 26b, 26c through hole 30, 30A, 30B, 30C, 30D, 30F multilayer board 31 Base material 32 Through hole 40A, 40B, 40C, 40D, 40E, 40F pins 41, 41A, 41B, 41C, 41D, 41E, 41F, 41G, 41H, 41J, 41K, 41L, 41M, 41N, 41P, 41Q, 41R, 41S, 41T, 41U Top Pin 41a, 41b, 41c Groove 41d Tip 41e Neck 41f columnar part 41g middle part 41h long hole 42 Flange (restriction part) 43 Cylinder 44 Stopper 45 Bottom Pin 46 Compression Spring 47 Large diameter section 50 Interposer 51 Interposer board 52, 53 wiring layer 54 Bump 60, 60A sample stage 61 Recess 62 Top surface 65 Recess 66 Through hole 67 Pillar 70A, 70B Connectors

Claims

1. A superconducting device using the characteristics of superconductivity, a superconducting circuit chip provided with a functional circuit; A multilayer substrate having a plurality of wiring layers; a plurality of pins electrically connecting the superconducting circuit chip and the multilayer substrate; Equipped with A superconducting device, characterized in that the pins are inserted into the wiring layers of the multi-layer board in a direction intersecting the wiring layers.

2. A superconducting device using the characteristics of superconductivity, a superconducting circuit chip provided with a functional circuit; A multilayer substrate having a plurality of wiring layers; an interposer disposed between the multilayer substrate and the superconducting circuit chip, electrically connected to the superconducting circuit chip, and having a wiring layer connected to a wiring layer of the multilayer substrate; a plurality of pins electrically connecting the interposer and the multilayer substrate; Equipped with A superconducting device, characterized in that the pin is inserted into at least one of the wiring layers of the multilayer substrate and the wiring layer of the interposer in a direction intersecting the wiring layer.

3. 3. The superconducting device according to claim 1, wherein the pin is electrically connected to one or more of the wiring layers of the multilayer substrate.

4. 3. The superconducting device according to claim 1, wherein the pin is extendable and contractible in the longitudinal direction.

5. 3. The superconducting device according to claim 1, wherein at least a portion of the inserted region of the pin is in contact with the multilayer substrate or the superconducting circuit chip.

6. 3. The superconducting device according to claim 1, wherein the multilayer substrate into which the pin is inserted comprises a plurality of wiring layers, and some of the plurality of wiring layers have a through hole having a diameter larger than that of the pin through which the pin passes.

7. 3. The superconducting device according to claim 1, wherein the multilayer substrate has a plurality of wiring layers along the insertion direction of the pins, and at least some of the pins have a length along the insertion direction that is different from other pins.

8. A method for manufacturing a superconducting device in which a superconducting circuit chip provided with a functional circuit using superconducting characteristics and a multilayer substrate having a plurality of wiring layers are electrically connected by a plurality of pins, the method comprising the steps of: A method of manufacturing a superconducting device, comprising the steps of: inserting said pin into a wiring layer of said multilayer substrate in a direction intersecting said wiring layer, thereby deforming said wiring layer.

9. A method for manufacturing a superconducting device, comprising: electrically connecting an interposer, which is electrically connected to a superconducting circuit chip provided with a functional circuit using superconducting characteristics, and a multilayer substrate having a plurality of wiring layers by a plurality of pins, the method comprising the steps of: A method for manufacturing a superconducting device, comprising inserting the pin into at least one of the wiring layers of the multilayer substrate and the wiring layer of the interposer in a direction intersecting the wiring layer, thereby deforming the wiring layer.

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