Display apparatus

Abstract

To improve reliability of a display apparatus.SOLUTION: A display apparatus includes a light-emitting device, a first transistor and a second transistor. The first transistor includes: a first gate electrode provided on a substrate; a first insulator film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulator film and including a region superposed with the first gate electrode; a second insulator film provided on the first oxide semiconductor layer; and a first conductive layer provided on the second insulator film. The second transistor includes: a first insulator film provided on a substrate; a second oxide semiconductor layer provided on the first insulator film; a second insulator film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a smaller film thickness than a film thickness of the first insulator film; and a second gate electrode provided on the second insulator film and including a region superposed with the second oxide semiconductor layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel. [Background technology]

[0002] In recent years, development of semiconductor devices using oxide semiconductor films as channels instead of silicon semiconductors using amorphous silicon, low-temperature polysilicon, single crystal silicon, etc. has been progressing (see, for example, Patent Documents 1 to 6). A semiconductor device including such an oxide semiconductor film can be formed with a simple structure and a low-temperature process, similar to a semiconductor device including an amorphous silicon film. In addition, a semiconductor device including an oxide semiconductor film is known to have a higher field-effect mobility than a semiconductor device including an amorphous silicon film.

[0003] In addition, the use of oxide semiconductors as semiconductor layers constituting organic EL display devices has been attracting attention. Transistors using oxide semiconductor layers have low off-leakage currents and can be driven at low frequencies, so they are expected to be applied to display devices with low power consumption. In particular, the application of transistors using oxide semiconductor layers to self-emitting organic EL display devices has a significant effect on reducing power consumption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0005] A transistor including an oxide semiconductor layer has a problem in that it has low reliability, for example, a change in threshold voltage over time. When a transistor including an oxide semiconductor layer has a bottom-gate structure or a dual-gate structure, it is difficult to ensure sufficient reliability.

[0006] In view of the above problems, one object of one embodiment of the present invention is to improve the reliability of a display device. [Means for solving the problem]

[0007] A display device according to an embodiment of the present invention includes a light-emitting element, a first transistor that controls a current value flowing from a drive power line to the light-emitting element, and a second transistor that writes a voltage corresponding to the light emission luminance of the light-emitting element to a first gate electrode of the first transistor, the first transistor including a first gate electrode, a first insulating film provided on the first gate electrode, a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode, a second insulating film provided on the first oxide semiconductor layer, and a first conductive layer provided on the second insulating film, the second transistor including a first insulating film, a second oxide semiconductor layer provided on the first insulating film, and a first conductive layer formed on the first oxide semiconductor layer and the second oxide semiconductor layer. The semiconductor device includes a second insulating film provided on the conductor layer and having a thickness smaller than that of the first insulating film, and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer, wherein the first oxide semiconductor layer has a first channel region and a first high-concentration impurity region provided on either side of the first channel region, the second oxide semiconductor layer has a second channel region and a second high-concentration impurity region provided on either side of the second channel region, the first conductive layer is electrically connected to the light-emitting element, and an etching rate when the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

[0008] A display device according to an embodiment of the present invention includes a light-emitting element, a first transistor for controlling a current value flowing from a drive power line to the light-emitting element, and a second transistor for writing a voltage corresponding to the light emission luminance of the light-emitting element to a first gate electrode of the first transistor, the first transistor including a first gate electrode, a first insulating film provided on the first gate electrode, and a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode, the second transistor including a first insulating film, a second oxide semiconductor layer provided on the first insulating film, and a second oxide semiconductor layer provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a thickness smaller than the thickness of the first insulating film. and a second insulating film having a thickness, and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer, the first oxide semiconductor layer has a first channel region, a low concentration impurity region provided on either side of the first channel region, and a first high concentration impurity region provided adjacent to the low concentration impurity region, and the second oxide semiconductor layer has a second channel region and a second high concentration impurity region provided on either side of the second channel region, and an etching rate when the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view illustrating a configuration of a display device according to an embodiment of the present invention. [Diagram 2] 1 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention. [Diagram 3] 1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention. [Figure 4] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Diagram 5] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 6] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 7] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 8] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 9] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 10] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 13] 1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention. [Figure 14] 1 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention. [Figure 15] 1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 17] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 18] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 19] 1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention. [Figure 20] 1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention. [Figure 21] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 22] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 23]1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention. [Figure 24] 1 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention. [Diagram 25] 25 is a timing chart of the pixel circuit shown in FIG. 24. [Figure 26] 1 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention. [Figure 27] 27 is a timing chart of the pixel circuit shown in FIG. 26. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. However, the present invention can be implemented in various forms without departing from the gist of the present invention, and should not be interpreted as being limited to the description of the embodiments exemplified below. In addition, in the drawings, the width, thickness, shape, etc. of each part may be shown in a schematic manner compared to the actual form in order to make the explanation clearer, but these schematic drawings are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements that are the same or similar to those described in the previous drawings may be given the same reference numerals, and duplicate explanations may be omitted.

[0011] In this specification, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.

[0012] In this specification, expressions such as "above" and "below" when describing the drawings express the relative positional relationship between a structure of interest and other structures. In this specification, the direction from a first substrate to a pixel electrode, which will be described later, is defined as "above" in a side view, and the opposite direction is defined as "below". In this specification and claims, when expressing a mode in which another structure is disposed on a certain structure, the term "above" is used to include both a case in which another structure is disposed directly above a certain structure so as to be in contact with the certain structure, and a case in which another structure is disposed above the certain structure via another structure, unless otherwise specified.

[0013] (First embodiment) A display device 100 according to one embodiment of the present invention will be described with reference to FIGS.

[0014] 1 is a plan view illustrating a configuration of a display device 100 according to an embodiment of the present invention, as shown in FIG.

[0015] The display region 102 includes a plurality of pixels 103 arranged in a matrix. Each of the pixels 103 includes a plurality of transistors and a light-emitting element.

[0016] The peripheral region 109 is provided so as to surround the display region 102. The peripheral region 109 refers to a region on the substrate 101 from the display region 102 to an end of the substrate 101. In other words, the peripheral region 109 refers to a region on the substrate 101 other than where the display region 102 is provided (i.e., a region outside the display region 102). The peripheral region 109 has gate driving circuits 104_1 and 104_2, a terminal section 107 including a plurality of terminals 106, and a driver IC 105. The gate driving circuits 104_1 and 104_2 are provided so as to sandwich the display region 102. The driver IC 105 is connected to the plurality of terminals 106, and the plurality of terminals 106 are connected to a flexible printed circuit 108. 1 shows an example in which a source driving circuit is incorporated in the driver IC 105, but is not limited to this form, and a source driving circuit may be provided on the substrate 101 separately from the driver IC 105. Also, an example in which the driver IC 105 is disposed on the substrate 101 in the form of an IC chip, but is not limited to this form, and may be disposed on a flexible printed circuit 108.

[0017] The driver IC 105 is connected to the gate drive circuits 104_1 and 104_2 and a plurality of video signal lines VL. The gate drive circuit 104_1 or the gate drive circuit 104_2 is connected to the pixels 103 via the write control scanning lines Sg. For example, the odd-numbered write control scanning lines Sg of the plurality of write control scanning lines Sg are connected to the gate drive circuit 104_1, and the even-numbered write control scanning lines Sg are connected to the gate drive circuit 104_2. The video signal lines VL are connected to the pixels 103. A control signal SG for selecting each pixel 103 is provided from the driver IC 105 to the display area 102 via the gate drive circuits 104_1 and 104_2 and the write control scanning lines Sg. A video signal Vsig is provided from the driver IC 105 to the display area 102 via the video signal lines VL. These signals drive the transistors of the pixels 103, and an image corresponding to the video signal Vsig can be displayed in the display area 102. The high potential power supply SLa and the low potential power supply electrode SLb connected to the pixels 103 are connected to different terminals 106, respectively.

[0018] A glass substrate or a flexible plastic substrate is used as the substrate 101. When a flexible plastic substrate is used as the substrate 101, the region between the display region 102 and the terminal portion 107 can be folded. This allows the frame of the display device 100 to be narrowed.

[0019] <Equivalent circuit diagram> 2 is an equivalent circuit diagram of a pixel 103 included in a display device 100 according to an embodiment of the present invention. The display device 100 has a high potential power supply SLa, a low potential power supply electrode SLb, a write control scanning line Sg, and a video signal line VL. The high potential power supply SLa is supplied with a high potential power supply Pvdd, and the low potential power supply electrode SLb is supplied with a low potential power supply Pvss. The write control scanning line Sg is connected to gate drive circuits 104_1 and 104_2, and the video signal line VL is connected to a driver IC 105.

[0020] Each pixel 103 has at least a driving transistor DRT, a writing transistor SST, and a light-emitting element OLED. A high potential power supply Pvdd is applied to the anode (also called a pixel electrode) of the light-emitting element OLED via the driving transistor DRT, and a low potential power supply Pvss is applied to the cathode (also called a common electrode). The driving transistor DRT is connected in series with the light-emitting element OLED between the high potential power supply SLa and the low potential power supply electrode SLb. The driving transistor DRT functions as a current control element that controls the current value flowing through the light-emitting element OLED according to the gate-source voltage. The writing transistor SST functions as a switching element that selects conduction or non-conduction between two nodes, and writes a voltage corresponding to the light emission luminance of the light-emitting element OLED. A storage capacitance Cs may be provided between the gate and source of the driving transistor DRT. The storage capacitance Cs stores the gate-source voltage of the driving transistor DRT for a certain period of time.

[0021] The write transistor SST has a first terminal, a second terminal, and a control terminal. The drive transistor DRT has a first terminal, a second terminal, a first control terminal, and a second control terminal. In this embodiment, the first terminal is described as a source electrode, the second terminal is described as a drain electrode, the first control terminal is described as a first gate electrode, and the second control terminal is described as a second gate electrode.

[0022] The write transistor SST has a first gate electrode and a second gate electrode connected to the write control scanning line Sg, a source electrode connected to the video signal line VL, and a drain electrode connected to the first gate electrode of the drive transistor DRT. In the drive transistor DRT, the drain electrode is connected to the high potential power supply SLa, and the source electrode is connected to the second gate electrode and one electrode (here, the anode) of the light-emitting element OLED. The other electrode (here, the cathode) of the light-emitting element OLED is connected to the low potential power supply electrode SLb. The drive transistor DRT outputs a drive current of an amount corresponding to the video signal Vsig to the light-emitting element OLED.

[0023] For example, amorphous silicon, low-temperature polysilicon, or oxide semiconductor is used as the semiconductor layer of the transistor constituting the display device 100. Here, the transistor using the oxide semiconductor layer has a low off-leak current and can be driven at a low frequency, so that the display device 100 with low power consumption can be realized. Furthermore, the transistor using the oxide semiconductor layer has good saturation characteristics because the kink effect is not observed compared to the transistor having the low-temperature polysilicon layer. In this embodiment, the case where an oxide semiconductor layer is used as the semiconductor layer of the transistor constituting the display device 100 will be described.

[0024] A problem with transistors using an oxide semiconductor layer is that they have low reliability, such as a change in threshold voltage over time. For example, when a writing transistor and a driving transistor are formed in a dual gate structure in order to increase the on-current of a transistor using an oxide semiconductor layer, the driving transistor is likely to be subjected to a voltage applied to the oxide semiconductor layer, and a large amount of current flows through the driving transistor. This causes thermal degradation of the oxide semiconductor layer, and the reliability of the driving transistor decreases.

[0025] When a transistor using an oxide semiconductor layer is formed to have a top gate structure, the on-current can be increased and the subthreshold swing value (hereinafter, referred to as S value) can be reduced by forming the gate insulating film to a thin thickness of 100 nm or more and 200 nm or less. Therefore, when a transistor with a top gate structure is used as a writing transistor, the effect of improving switching characteristics can be obtained due to the small S value. On the other hand, when a transistor with a top gate structure is used as a driving transistor, a problem occurs in that the current change becomes large due to the small S value because the transistor is current-driven. In particular, in a low gradation region that needs to be controlled with a small current, the current change of the driving transistor becomes large, making it impossible to finely control the gradation. This causes a problem in that display unevenness is likely to occur in the display region 102.

[0026] In addition, when a transistor using an oxide semiconductor layer is formed to have a bottom-gate structure, the amount of current flowing through the transistor can be reduced by increasing the thickness of the gate insulating film, since a voltage is less likely to be applied to the oxide semiconductor layer. Therefore, when a bottom-gate transistor having a thick gate insulating film is used as a drive transistor, thermal degradation of the oxide semiconductor layer is suppressed, and the reliability of the transistor is improved. On the other hand, when a bottom-gate transistor having a thick gate insulating film is used as a write transistor, the on-current Ion of the write transistor tends to decrease due to the thick gate insulating film.

[0027] Therefore, when a transistor using an oxide semiconductor layer is applied to a display device, it is preferable to provide transistors having different characteristics and structures depending on a required function. For example, it is preferable to provide a transistor having good switching characteristics and high on-state current as the writing transistor, and a transistor having switching characteristics lower than those of the writing transistor, in which thermal degradation is suppressed and which is highly reliable as the driving transistor.

[0028] Therefore, in the display device 100 according to an embodiment of the present invention, the transistors constituting the writing transistor SST having a switching function and the gate drive circuits 104_1 and 104_2 are top-gate driven or dual-gate driven, and the drive transistors having a current control function are bottom-gate driven. In this specification and the like, the top-gate drive is a transistor in which on / off is controlled by a gate electrode arranged above the oxide semiconductor layer. The top-gate drive transistor may have a top-gate structure constituted by a gate electrode arranged above the oxide semiconductor layer, or a dual-gate structure constituted by gate electrodes arranged above and below the oxide semiconductor layer. In this specification and the like, the bottom-gate drive is a transistor in which on / off is controlled by a gate electrode arranged below the oxide semiconductor layer. The bottom-gate drive transistor may have a bottom-gate structure constituted by a gate electrode arranged below the oxide semiconductor layer, or a dual-gate structure constituted by gate electrodes arranged above and below the oxide semiconductor layer. In this specification and the like, the dual-gate drive is a transistor in which on / off is controlled by inputting the same control signal to gate electrodes arranged above and below the oxide semiconductor layer.

[0029] <Cross-sectional structure of pixel> Fig. 3 is a diagram illustrating a cross-sectional structure of a pixel 103 of a display device 100 according to an embodiment of the present invention. As shown in Fig. 3, a transistor 210 and a transistor 220 are provided on a substrate 101 via an undercoat film 202. The transistor 210 is connected to a light-emitting element 230. Here, the transistor 210 corresponds to the drive transistor DRT, the transistor 220 corresponds to the write transistor SST, and the light-emitting element 230 corresponds to the light-emitting element OLED.

[0030] The transistor 210 functioning as the driving transistor DRT has a dual-gate structure. The transistor 210 includes at least a conductive layer 204_1, an insulating film 206 provided on the conductive layer 204_1, an oxide semiconductor layer 208_1 provided on the insulating film 206, an insulating film 212 provided on the oxide semiconductor layer 208_1, and a conductive layer 214_1 provided on the insulating film 212. Here, a first control terminal that controls switching of the transistor 210 is the conductive layer 204_1. Therefore, the transistor 210 is a bottom-gate driven transistor. The conductive layer 204_1 also functions as a light-shielding layer for suppressing light irradiation on the back surface of the oxide semiconductor layer 208. A second control terminal is the conductive layer 214_1. Here, the oxide semiconductor layer 208_1 includes a channel region 208a and high-concentration impurity regions 208b and 208c. The high-concentration impurity regions 208b and 208c are provided with a channel region 208a therebetween. The channel region 208a overlaps with the conductive layer 204_1. The insulating film 206 functions as a gate insulating film of the transistor 210.

[0031] The channel region 208a has semiconductor properties. Therefore, when a voltage is applied to the conductive layer 204_1, a channel that serves as a current path is formed in the channel region 208a. The high-concentration impurity region 208b and the high-concentration impurity region 208c each have conductive properties due to the addition of an impurity element. Therefore, the carrier concentrations of the high-concentration impurity region 208b and the high-concentration impurity region 208c are higher than the carrier concentration of the channel region 208a. In other words, the channel region 208a has a higher electrical resistivity (or a lower electrical conductivity) than the high-concentration impurity region 208b and the high-concentration impurity region 208c. When the oxide semiconductor layers 208_1 and 208_2 are measured by SIMS analysis, the oxide semiconductor layers 208_1 and 208_2 have a conductivity of 1×10 18 cm -3 More than 1×10 21 cm -3 When the impurity element is added at a concentration below 1000 Ω / sq., the sheet resistance can be reduced. For example, the sheet resistance of the high concentration impurity region 208b and the high concentration impurity region 208c is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. Hereinafter, for convenience of explanation, a region having a higher electrical resistivity than the high concentration impurity region 208b and the high concentration impurity region 208c, such as the channel region 208a, will be referred to as a "high resistance region."

[0032] An insulating film 216 is provided on the oxide semiconductor layer 208_1. The insulating film 216 functions as an interlayer insulating film. Source or drain electrodes 218_1 and 218_2 are provided on the insulating film 216. The source or drain electrode 218_1 is connected to the high-concentration impurity region 208b through a contact hole provided in the insulating films 212 and 216. The source or drain electrode 218_2 is connected to the high-concentration impurity region 208c and the conductive layer 214_1. The conductive layer 214_1 is connected to the pixel electrode 226 of the light-emitting element OLED through the source or drain electrode 218_2. Although not shown, the conductive layer 204_1 is electrically connected to one of the source or drain electrodes 218_3 and 218_4. The conductive layer 214_1 may be connected to a fixed potential, for example, in addition to the mode shown in FIG. 3. An example of the fixed potential is a high potential power supply Pvdd, which is a driving power supply for the light emitting element OLED, or a low potential power supply Pvss.

[0033] The transistor 220 functioning as the write transistor SST has a dual gate structure. The transistor 220 includes at least a conductive layer 204_2, an insulating film 206 provided on the conductive layer 204_2, an oxide semiconductor layer 208_2 provided on the insulating film 206, an insulating film 212 provided on the oxide semiconductor layer 208_2, and a conductive layer 214_2 provided on the insulating film 212. Here, a first control terminal for controlling switching of the transistor 220 is the conductive layer 204_2 and the conductive layer 214_2. Therefore, the transistor 220 is dual gate driven. The conductive layer 204_1 also functions as a light shielding layer for suppressing light irradiation on the back surface of the oxide semiconductor layer 208. The insulating film 206 and the insulating film 212 function as gate insulating films. The oxide semiconductor layer 208_2 includes a channel region 208f and high-concentration impurity regions 208g and 208h. The high-concentration impurity regions 208g and 208h are provided with a channel region 208f therebetween. Here, the channel region 208f overlaps with the conductive layer 214_2.

[0034] The channel region 208f has a semiconductor property. Therefore, when a voltage is applied to the conductive layer 204_2 and the conductive layer 214_2, a channel that becomes a current path is formed in the channel region 208f. Each of the high concentration impurity region 208g and the high concentration impurity region 208h has a conductor property. Therefore, the carrier concentration of the high concentration impurity region 208g and the high concentration impurity region 208h is higher than the carrier concentration of the channel region 208f. In other words, the channel region 208a has a higher electrical resistivity (or a lower electrical conductivity) than each of the high concentration impurity region 208g and the high concentration impurity region 208h. For example, the sheet resistance of the high concentration impurity region 208g and the high concentration impurity region 208h is 1000Ω / sq. or less, preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less. The channel region 208f is called a high resistance region.

[0035] An insulating film 216 is provided on the conductive layer 214_2. Source or drain electrodes 218_3 and 218_4 are provided on the insulating film 216. The source or drain electrodes 218_3 and 218_4 are connected to the high-concentration impurity regions 208g and 208h via contact holes provided in the insulating films 212 and 216.

[0036] In the present embodiment, in the display device 100, a dual-gate drive transistor having a dual gate structure is provided as the write transistor SST, and a bottom-gate drive transistor having a dual gate structure is provided as the drive transistor DRT on the same substrate. At this time, among the insulating films 206 and 212 sandwiching the oxide semiconductor layers 208_1 and 208_2 from above and below, in the write transistor SST, both the insulating film 212 and the insulating film 206 function as gate insulating films, and in the drive transistor DRT, the insulating film 206 functions as a gate insulating film. The film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. Therefore, the thickness of the gate insulating film can be made different between the write transistor SST and the drive transistor DRT. Although the write transistor SST is configured as a dual-gate drive, the threshold voltage is dominated by the applied voltage by the conductive layer 214_2 provided via the thin insulating film 212.

[0037] Since the gate insulating film of the write transistor SST can be made thinner than that of the drive transistor DRT, an electric field is easily applied to the oxide semiconductor layer 208_2, and the on-current of the drive transistor DRT can be increased. Furthermore, in the write transistor SST and the drive transistor DRT, an impurity element is added to the oxide semiconductor layer 208_2 using the conductive layers 214_1 and 214_2 as a mask, and therefore the channel length L can be shortened. In one embodiment of the present invention, the channel length L of the write transistor SST and the drive transistor DRT can be set to, for example, 2.0 μm or more and 4.0 μm or less. This allows the S value of the write transistor SST to be reduced, and therefore the switching characteristics of the write transistor SST are improved. On the other hand, since the gate insulating film of the drive transistor DRT can be made thicker than that of the write transistor SST, an electric field is less likely to be applied to the oxide semiconductor layer 208_1, and the on-current of the drive transistor DRT can be reduced. Furthermore, since the S value of the drive transistor DRT can be increased, a current change can be reduced in a low gradation region controlled by a minute current, and the gradation can be finely controlled. This makes it possible to prevent display unevenness from occurring in the display region 102. Furthermore, it is possible to prevent a large amount of current from continuously flowing through the drive transistor DRT, thereby preventing a decrease in reliability due to thermal degradation.

[0038] In the driving transistor DRT, the conductive layer 214_1 and the high concentration impurity region 208c are connected via a source electrode or a drain electrode 218_2. The conductive layer 214_1 is connected to the pixel electrode 226 of the light emitting element OLED via the source electrode or the drain electrode 218_2. This makes it possible to stabilize the signal on the source side of the driving transistor DRT. Therefore, it is possible to suppress the occurrence of display unevenness in the display region 102.

[0039] By applying the transistor 220 having the same configuration as the write transistor SST to the transistors constituting the gate drive circuits 104_1 and 104_2, it is possible to drive the gate drive circuits 104_1 and 104_2 at high speed.

[0040] A planarization film 222 is provided on the source or drain electrodes 218_1 to 218_4. The planarization film 222 can be made of an organic resin material such as polyimide, polyamide, acrylic, or epoxy. These materials can be formed into a film by a solution coating method, and have a high planarization effect. The planarization film 222 is not provided in the peripheral region 109.

[0041] The transistor 210 is connected to a light-emitting element 230. The light-emitting element 230 has a pixel electrode 226, an organic layer 232, and a common electrode 234. In one embodiment of the present invention, the display device 100 may be a top-emission type or a bottom-emission type. In this embodiment, the display device 100 is described as having a top-emission structure. In the case of the top-emission structure, the pixel electrode 226 serves as an anode, and the common electrode 234 serves as a cathode.

[0042] A pixel electrode 226 is provided on the planarization film 222. The pixel electrode 226 is provided for each pixel 103. The pixel electrode 226 is connected to a source electrode or a drain electrode 218_2 of the transistor 210 via a contact hole provided in the planarization film 222. A metal film having high reflectance is used as the pixel electrode 226. Alternatively, a laminated structure of a transparent conductive layer having a high work function, such as an indium oxide-based transparent conductive layer (e.g., ITO) or a zinc oxide-based transparent conductive layer (e.g., IZO, ZnO), and a metal film can be used as the pixel electrode 226.

[0043] An insulating film 228 is provided so as to cover the end of the pixel electrode 226. The insulating film 228 is also called a partition wall or a bank. As with the planarizing film 222, photosensitive acrylic is used for the insulating film 228. The insulating film 228 is opened so that the pixel electrode 226 is exposed, and it is preferable that the end of the opening has a gentle tapered shape. If the end of the opening has a steep shape, poor coverage of the organic layer 232 to be formed later occurs.

[0044] A plurality of organic materials constituting the organic layer 232 are laminated on the pixel electrode 226 and the insulating film 228. The organic layer 232 is provided by laminating a hole transport layer, a light emitting layer, an electron transport layer, and the like in this order from the pixel electrode 226 side. These layers may be formed by deposition or by coating on a solvent dispersion. The hole transport layer, the electron transport layer, and the like may be selectively formed for each subpixel, or may be formed over the entire surface of the display region 102.

[0045] A common electrode 234 is provided on the organic layer 232. Since this embodiment has a top emission structure, the common electrode 234 needs to be light-transmitting. When MgAg is used as the common electrode 234, it is formed as a thin film that transmits light emitted from the organic layer 232. The common electrode 234 is connected to the wiring layer at a cathode contact portion provided in the peripheral region 109, and is electrically connected to the terminal 106.

[0046] A sealing film 240 is provided on the common electrode 234. The sealing film 240 is provided to prevent moisture from entering from the outside from entering the organic layer 232. In this embodiment, an example is shown in which the sealing film 240 is formed in a three-layer structure of an inorganic insulating film 236, an organic insulating film 238, and an inorganic insulating film 242. It is preferable to use silicon nitride, which has high gas barrier properties, as the inorganic insulating films 236 and 233, and an organic resin material, which has high flexibility, as the organic insulating film 238. Note that a silicon oxide film or an amorphous silicon film may be provided between the silicon nitride and the organic resin material. This can improve the adhesion between the silicon nitride and the organic resin material. For example, an overcoat layer may be provided on the inorganic insulating film 242, which also serves as a planarization layer.

[0047] The touch sensor 110 is provided on the sealing film 240. The touch sensor 110 may be formed directly on the sealing film 240. Alternatively, a cover glass on which the touch sensor 110 is formed may be provided on the sealing film 240.

[0048] <Characteristics of Oxide Semiconductor Layers 208_1 and 208_2> In one embodiment of the present invention, the oxide semiconductor layers 208_1 and 208_2 have properties different from those of a conventional oxide semiconductor having a polycrystalline structure. Therefore, in order to distinguish the oxide semiconductors included in the oxide semiconductor layers 208_1 and 208_2 from the conventional oxide semiconductor having a polycrystalline structure, the oxide semiconductors included in the oxide semiconductor layers 208_1 and 208_2 will be referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) in the following description.

[0049] In the Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of the Poly-OS can be identified by an electron beam diffraction method, an XRD method, or the like. That is, the crystal structures of the oxide semiconductor layers 208_1 and 208_2 can be identified by an electron beam diffraction method, an XRD method, or the like.

[0050] The oxide semiconductor layers 208_1 and 208_2 containing Poly-OS have excellent etching resistance. Specifically, the oxide semiconductor layers 208_1 and 208_2 have a very small etching rate when etched with an etchant for wet etching. This means that the oxide semiconductor layers 208_1 and 208_2 are hardly etched by the etchant.

[0051] Specifically, when the oxide semiconductor layers 208_1 and 208_2 of this embodiment are etched using an etching solution containing phosphoric acid as a main component (e.g., a mixed acid etching solution) in a temperature range of 35° C. to 45° C. (e.g., a range including an error of ±5° C. at a set temperature of 40° C.), the etching rate is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the etching solution is 50% or more, 60% or more, or 70% or more. The etching solution may contain nitric acid and acetic acid in addition to phosphoric acid. In contrast, the oxide semiconductor layer having an amorphous structure (the oxide semiconductor layer before OS annealing) has an etching rate of 100 nm / min or more when etched using the above-mentioned etching solution in a temperature range of 35° C. to 45° C.

[0052] Furthermore, when the oxide semiconductor layers 208_1 and 208_2 of this embodiment are etched using an etching solution containing hydrogen fluoride (e.g., a hydrofluoric acid solution) at room temperature (which means "25°C±5°C" here), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. The proportion of hydrogen fluoride in the etching solution is 0.5%. In contrast, the oxide semiconductor layer having an amorphous structure has an etching rate of 15 nm / min or more when etched using the above-mentioned etching solution at room temperature.

[0053] Here, the etching rates of various oxide semiconductor layers are shown in Table 1. Table 1 shows the etching rates of the prepared samples with respect to the mixed acid etching solution and 0.5% hydrofluoric acid solution. As the mixed acid etching solution, "Mixed Acid AT-2F (product name)" manufactured by Rasa Kogyo Co., Ltd. was used. The ratio of phosphoric acid in the mixed acid etching solution was about 65%. In addition, the temperature of the mixed acid etching solution when etching each sample was set to 40°C, and the temperature of the 0.5% hydrofluoric acid solution was set to 22°C. In Table 1, Sample 1 is an oxide semiconductor layer having a polycrystalline structure of this embodiment, Sample 2 is an oxide semiconductor layer having an amorphous structure of this embodiment, and Sample 3 is an oxide semiconductor layer containing indium gallium zinc oxide (IGZO) with an indium ratio of less than 50%.

[0054] [Table 1]

[0055] As shown in Table 1, Sample 1 was hardly etched even when using a mixed acid etching solution, and was etched at most about 2 nm / min even when using a 0.5% hydrofluoric acid solution. The etching rate of Sample 1 was 1 / 100 or less with the mixed acid etching solution and about 1 / 10 or less with the 0.5% hydrofluoric acid solution compared to the etching rate of Sample 2. Furthermore, the etching rate of Sample 1 was 1 / 100 or less with the mixed acid etching solution compared to the etching rate of Sample 3. Thus, it was found that Sample 1 has significantly better etching resistance than Samples 2 and 3.

[0056] The excellent etching resistance of the oxide semiconductor layers 208_1 and 208_2 of this embodiment is a property that cannot be obtained in a conventional oxide semiconductor layer having a polycrystalline structure fabricated by a process at 500° C. or less. Although the detailed mechanism is unclear, such excellent etching resistance is evidence that the oxide semiconductor layers 208_1 and 208_2 of this embodiment have a polycrystalline structure different from the conventional one. In addition, the oxide semiconductor layers having a polycrystalline structure described in the modified examples and embodiments described below have the same property.

[0057] As described above, the oxide semiconductor layers 208_1 and 208_2 containing Poly-OS have a very small etching rate with respect to the etching solution. Therefore, it is very difficult to pattern the oxide semiconductor layers 208_1 and 208_2. In order to form the island-shaped oxide semiconductor layers 208_1 and 208_2, an oxide semiconductor film having an amorphous structure before heat treatment is patterned into an island shape, and then the oxide semiconductor film is crystallized by heat treatment. In this way, the island-shaped oxide semiconductor layers 208_1 and 208_2 containing Poly-OS can be formed.

[0058] In the display device 100 according to the present embodiment, the transistors are formed using the oxide semiconductor layers 208_1 and 208_2 having a good polycrystalline structure. In the transistors including the oxide semiconductor layers 208_1 and 208_2, the mobility is 30 cm when the channel length L of the channel regions 208a and 208f is in the range of 2 μm to 4 μm and the channel width of the channel regions 208a and 208f is in the range of 2 μm to 25 μm. 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the mobility means the field effect mobility in the saturation region of the transistor, and means the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is larger than the voltage (Vg) supplied to the gate electrode minus the threshold voltage (Vth) of the transistor (Vg-Vth).

[0059] <Display Device Manufacturing Method> Next, a method for manufacturing the display device 100 according to one embodiment of the present invention will be described with reference to FIGS.

[0060] 4 is a diagram illustrating the process of forming an undercoat film 202 through an insulating film 206 on a substrate 101. As the substrate 101, a glass substrate, a quartz substrate, or a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose, cyclic olefin copolymer, cycloolefin polymer, or other flexible resin substrate) can be used.

[0061] An undercoat film 202 is formed on the substrate 101. As the undercoat film 202, silicon oxide or silicon nitride may be used as a single layer, or silicon oxide and silicon nitride may be combined and used as a laminate. Conductive layers 204_1 and 204_2 are formed on the undercoat film 202. The conductive layers 204_1 and 204_2 are formed by forming a conductive film on the undercoat film 202 and processing it by a photolithography method. As the conductive layers 204_1 and 204_2, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), copper (Cu), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi), or the like may be used. In addition, an alloy of these metals may be used.

[0062] Next, an insulating film 206 is formed over the conductive layers 204_1 and 204_2. As the insulating film 206, a single layer of silicon oxide or silicon nitride may be used, or a combination of silicon oxide and silicon nitride may be used in a laminated state. The thickness of the insulating film 206 is preferably larger than the thickness of the insulating film 212 described later. The insulating film 206 is formed to a thickness of, for example, 100 nm or more and 500 nm or less, preferably 150 nm or more and 300 nm or less.

[0063] FIG. 5 illustrates a step of forming the oxide semiconductor film 207 over the insulating film 206. In FIG.

[0064] The oxide semiconductor film 207 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 207 is, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0065] A metal oxide having semiconductor properties can be used as the oxide semiconductor film 207. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor film 207. The ratio of indium to the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid is used as the oxide semiconductor film 207. An element other than the above may be used as the oxide semiconductor film 207. In this embodiment, a metal oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor film 207.

[0066] When the oxide semiconductor film 207 is crystallized by an OS annealing treatment described later, the oxide semiconductor film 207 after deposition and before the OS annealing treatment is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the oxide semiconductor film 207 is preferably formed under conditions that prevent the oxide semiconductor film 207 from crystallizing immediately after deposition as much as possible. For example, when the oxide semiconductor film 207 is formed by a sputtering method, the oxide semiconductor film 207 is formed while controlling the temperature of an object to be formed (the substrate SUB1 and a structure formed thereon).

[0067] When a film is formed on a target object by sputtering, ions generated in plasma and atoms recoiled from the sputtering target collide with the target object, and thus the temperature of the target object increases during the film formation process. If the temperature of the target object increases during the film formation process, the oxide semiconductor film 207 contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing process is inhibited. In order to control the temperature of the target object as described above, for example, the target object may be cooled while the film is formed. For example, the target object may be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. By forming the oxide semiconductor film 207 while cooling the target object as described above, the oxide semiconductor film 207 having a small amount of crystalline components immediately after the film formation can be formed.

[0068] 6A to 6C are diagrams illustrating a process of forming a pattern of the oxide semiconductor layers 207_1 and 207_2 from the oxide semiconductor film 207. A resist mask is formed over the oxide semiconductor film 207, and the oxide semiconductor film 207 is etched using the resist mask. For the etching of the oxide semiconductor film 207, wet etching or dry etching may be used. For the wet etching, etching may be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid may be used as the etchant.

[0069] The oxide semiconductor film 207 is preferably patterned into the oxide semiconductor layers 207_1 and 207_2 before the OS annealing treatment. As described above, when the oxide semiconductor film 207 is crystallized by the OS annealing treatment, the etching resistance is improved, and therefore the oxide semiconductor film 207 tends to be difficult to etch. In addition, even if the oxide semiconductor film 207 is damaged by etching, the damage can be repaired by the OS annealing treatment, which is preferable.

[0070] FIG. 7 is a diagram illustrating a step of performing heat treatment (also referred to as OS annealing treatment) on the oxide semiconductor layers 207_1 and 207_2. In the OS annealing treatment, the oxide semiconductor layers 207_1 and 207_2 are held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or higher and 500° C. or lower, and preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or longer and 120 minutes or shorter, and preferably 30 minutes or longer and 60 minutes or shorter. By performing the OS annealing treatment, the oxide semiconductor layers 207_1 and 207_2 are crystallized, and oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure are formed. As a result, the oxide semiconductor layers 208_1 and 208_2 having high etching resistance can be formed.

[0071] Next, the insulating film 212 is formed over the oxide semiconductor layers 208_1 and 208_2.

[0072] The description of the insulating film 206 may be referred to for the method of forming the insulating film 212 and the insulating material thereof. The insulating film 212 has a thickness of, for example, 30 nm or more and 150 nm or less.

[0073] It is preferable to use an insulating material containing oxygen for the insulating film 212. It is also preferable to use an insulating film with few defects for the insulating film 212. For example, when the oxygen composition ratio in the insulating film 212 is compared with the oxygen composition ratio in an insulating film having the same composition as the base film 202 (hereinafter referred to as "another insulating film"), the oxygen composition ratio in the insulating film 212 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating film. For example, when silicon oxide (SiO x ), the composition ratio of oxygen in the silicon oxide used as the insulating film 212 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the undercoat film 202. For example, the insulating film 212 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0074] In order to form an insulating film with few defects as the insulating film 212, the insulating film 212 may be formed at a film formation temperature of 350° C. or higher. In addition, after forming the insulating film 212, a process of implanting oxygen into a part of the insulating film 212 may be performed. In this embodiment, in order to form an insulating film with few defects as the insulating film 212, silicon oxide is formed at a film formation temperature of 350° C. or higher.

[0075] FIG. 8 is a diagram illustrating a process of forming metal oxide film 213 containing aluminum as a main component on insulating film 212. As shown in FIG.

[0076] The metal oxide film 213 is a metal oxide containing aluminum as a main component. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) and other inorganic insulating materials are used. x N y is an aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). AlN x O y is an aluminum compound that contains a smaller proportion of oxygen than nitrogen (x>y).

[0077] "A metal oxide film containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide film 213 is 1% or more of the entire metal oxide film 213. The ratio of aluminum contained in the metal oxide film 213 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide film 213. The above ratio may be a mass ratio or a weight ratio.

[0078] The metal oxide film 213 is formed by, for example, a sputtering method. The thickness of the metal oxide film 213 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm.

[0079] For example, when the metal oxide film 213 is formed by a sputtering method, oxygen is implanted into the insulating film 212 by the formation of the metal oxide film 213. Therefore, the process gas used in the sputtering remains in the insulating film 212. For example, when Ar is used as the process gas for sputtering, Ar may remain in the insulating film 212. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the insulating film 212.

[0080] In this embodiment, aluminum oxide is used as the metal oxide film 213. Aluminum oxide has high barrier properties against gas. In this embodiment, by using aluminum oxide as the metal oxide film 213, outward diffusion of oxygen implanted into the insulating film 212 during the formation of the metal oxide film 213 is suppressed.

[0081] An insulating film 212 is formed on the oxide semiconductor layers 208_1 and 208_2, and a metal oxide film 213 is formed on the insulating film 212. In this state, a heat treatment (oxidation annealing treatment) is performed to supply oxygen to the oxide semiconductor layers 208_1 and 208_2.

[0082] During the process from when the oxide semiconductor layers 208_1 and 208_2 are formed until when the insulating film 212 is formed on the oxide semiconductor layers 208_1 and 208_2, many oxygen defects are generated on the upper and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Therefore, the number of oxygen defects formed near the upper surfaces of the oxide semiconductor layers 208_1 and 208_2 is greater than the number of oxygen defects formed near the lower surfaces of the oxide semiconductor layers 208_1 and 208_2. In other words, the oxygen defects in the oxide semiconductor layers 208_1 and 208_2 are not uniformly present in the thickness direction of the oxide semiconductor layers 208_1 and 208_2, but are non-uniformly distributed in the thickness direction of the oxide semiconductor layers 208_1 and 208_2. Specifically, the number of oxygen defects in the oxide semiconductor layers 208_1 and 208_2 is smaller toward the lower surface of the oxide semiconductor layers 208_1 and 208_2 and is larger toward the upper surface of the oxide semiconductor layers 208_1 and 208_2.

[0083] In this embodiment, oxidation annealing is performed in a state where the metal oxide film 213 is provided on the oxide semiconductor layers 208_1 and 208_2. In this manner, oxygen implanted into the insulating film 212 in the above-described oxidation annealing process is blocked by the metal oxide film 213, and is therefore prevented from being released into the atmosphere. In addition, oxygen released from the insulating film 206 is supplied to the upper and side surfaces of the oxide semiconductor layers 208_1 and 208_2. This allows the oxygen to be efficiently supplied to the oxide semiconductor layers 208_1 and 208_2, and oxygen defects can be repaired.

[0084] Next, after the oxidation annealing treatment, the metal oxide film 213 is etched (removed). For etching the metal oxide film 213, wet etching or dry etching may be used. For example, diluted hydrofluoric acid (DHF) is used for wet etching. By this etching, the metal oxide film 213 formed on the entire surface is removed. In other words, the metal oxide film 213 is removed without using a mask. In further other words, by this etching, all the metal oxide film 213 in the regions overlapping with the oxide semiconductor layers 208_1 and 208_2 formed in one pattern is removed at least in a plan view.

[0085] 9 illustrates a step of forming the conductive layers 214_1 and 214_2 over the insulating film 212. The conductive layers 214_1 and 214_2 are formed by forming a conductive film over the insulating film 212 and processing it by photolithography. The conductive layers 214_1 and 214_2 can be formed using, for example, a material similar to that of the conductive layers 204_1 and 204_2. The conductive layer 214_1 is formed in a region overlapping with the conductive layer 204_1 and the oxide semiconductor layer 208_1, and the conductive layer 214_2 is formed in a region overlapping with the conductive layer 204_2 and the oxide semiconductor layer 208_2.

[0086] 10A and 10B are diagrams illustrating a step of adding an impurity element to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. In this embodiment, the case where the impurity element is added by ion implantation is described, but the impurity may be added by ion doping.

[0087] Specifically, impurity elements are added to the oxide semiconductor layers 208_1 and 208_2 by ion implantation through the insulating film 212, forming high-concentration impurity regions 208b, 208c, 208g, and 208h. Regions of the oxide semiconductor layers 208_1 and 208_2 overlapping with the gate wiring GL1 become channel regions 208a and 208f. Examples of the impurity element that may be used include argon (Ar), phosphorus (P), and boron (B). When boron (B) is added by ion implantation, the acceleration energy is set to 20 keV to 40 keV, and the amount of boron (B) injected is set to 1×10 14 cm -2 More than 1×10 16 cm -2 The following would suffice.

[0088] The concentration of impurity elements contained in the high-concentration impurity regions 208b, 208c, 208g, and 208h is 1×10 18 cm -3 More than 1×10 21 cm -3In addition, the high concentration impurity region OS2 is preferably 1×10 18 cm -3 More than 1×10 21 cm -3 If the following is present, it is presumed that impurity elements have been intentionally added by ion implantation or doping.

[0089] FIG. 11 is a diagram for explaining a process of forming the insulating film 216 to the source or drain electrodes 218_1 to 218_4 on the oxide semiconductor layers 208_1 and 208_2. First, the insulating film 216 is formed on the oxide semiconductor layers 208_1 and 208_2. As the insulating film 216, a single layer of silicon oxide or silicon nitride may be used, or a combination of silicon oxide and silicon nitride may be used. The thickness of the insulating film 216 is preferably larger than the thickness of the insulating film 212. The thickness of the insulating film 216 is preferably, for example, 250 nm to 600 nm. By using silicon nitride as the insulating film 216, hydrogen contained in the silicon nitride is introduced into oxygen defects formed by ion implantation in the oxide semiconductor layers 208_1 and 208_2. This can further reduce the resistance of the high-concentration impurity regions 208b, 208c, 208g, and 208h.

[0090] Next, contact holes reaching the oxide semiconductor layers 208_1 and 208_2 and the conductive layer 214_1 are formed in the insulating film 212 and the insulating film 216. Next, the source or drain electrodes 218_1 to 218_4 are formed on the insulating film 216. The source or drain electrodes 218_1 to 218_4 are formed by forming a conductive film on the insulating film 216 and processing the conductive film by a photolithography method. As a result, the source or drain electrode 218_1 is connected to the high concentration impurity region 208b, and the source or drain electrode 218_2 is connected to the high concentration impurity region 208c and the conductive layer 214_1. The source or drain electrode 218_3 is connected to the high concentration impurity region 208g, and the source or drain electrode 218_4 is connected to the high concentration impurity region 208h. The source or drain electrodes 218_1 to 218_4 can be formed using a material similar to that of the conductive layers 204_1 and 204_2. Although not shown, in this step, a contact hole reaching the conductive layer 204_1 may be formed in the insulating films 206, 212, and 216. This allows the conductive layer 204_1 to be connected to the source or drain electrode 218_3. Through the steps up to this point, the transistors 210 and 220 can be formed.

[0091] 12 is a diagram for explaining a process of forming a planarizing film 222 and a pixel electrode 226. The planarizing film 222 is formed on the source or drain electrodes 218_1 to 218_4. The planarizing film 222 can be made of an organic resin material such as polyimide, acrylic, or epoxy. These materials can be formed into a film by a solution coating method, and are characterized by a high planarizing effect.

[0092] The light emitting element 230 is formed by forming the pixel electrode 226, the organic layer 232, and the common electrode 234. First, a contact hole reaching the source or drain electrode 218_2 is formed in the planarization film 222. Next, the pixel electrode 226 is formed on the planarization film 222. The pixel electrode 226 is formed by forming a conductive film on the planarization film 222 and processing the conductive film by a photolithography method. An insulating film 228 is formed with an opening so that the pixel electrode 226 is exposed. Next, a plurality of organic materials constituting the organic layer 232 are formed on the pixel electrode 226 and the insulating film 228. Next, the common electrode 234 is formed on the organic layer 232.

[0093] Thereafter, the inorganic insulating film 236, the organic insulating film 238, and the inorganic insulating film 242 are formed on the common electrode 234 to form the sealing film 240. First, the inorganic insulating film 236 is formed on the common electrode 234. Next, the organic insulating film 238 is formed on the inorganic insulating film 236. Next, the inorganic insulating film 242 is formed on the organic insulating film 238. At this time, it is preferable that the end of the inorganic insulating film 236 and the end of the inorganic insulating film 242 are in contact with each other to seal the organic insulating film 238. This makes it possible to suppress deterioration of the light emitting element 230 due to the intrusion of moisture from the outside of the sealing film 240.

[0094] Through the above steps, a display device 100 having the pixel 103 configuration shown in FIG. 3 can be manufactured.

[0095] According to the manufacturing method of the display device 100 of one embodiment of the present invention, even in a small area such as within one pixel, two types of transistors with different characteristics and structures can be formed more simply and without increasing the number of processes.

[0096] (Variation 1) Next, a pixel 103A having a configuration partially different from that of the pixel 103 shown in FIG. 3 will be described with reference to FIG.

[0097] Fig. 13 is a diagram illustrating a cross-sectional structure of a pixel 103A of a display device 100 according to an embodiment of the present invention. As shown in Fig. 13, a transistor 210 and a transistor 250 are provided on a substrate 101 via an undercoat film 202. Here, the transistor 210 corresponds to the drive transistor DRT shown in Fig. 3, and the transistor 250 corresponds to the write transistor SST shown in Fig. 3. Note that the structure of the transistor 210 is similar to that of the transistor 210 shown in Fig. 3, and therefore description thereof will be omitted.

[0098] The transistor 250 functioning as the write transistor SST has a top-gate structure. The transistor 250 includes at least an oxide semiconductor layer 208_3 provided on the insulating film 206, an insulating film 212 provided on the oxide semiconductor layer 208_3, and a conductive layer 214_3 provided on the insulating film 212. Here, a control terminal for controlling switching of the transistor 250 is the conductive layer 214_3. The insulating film 212 functions as a gate insulating film. The oxide semiconductor layer 208 includes a channel region 208i and high-concentration impurity regions 208j and 208k. The insulating film 212 is provided on the conductive layer 214_3. Source or drain electrodes 218_5 and 218_6 are provided on the insulating film 212. The source or drain electrodes 218_5 and 218_6 are connected to the high-concentration impurity regions 208j and 208k through contact holes provided in the insulating films 212 and 216.

[0099] Since the gate insulating film of the write transistor SST can be made thinner than the gate insulating film of the drive transistor DRT, an electric field is easily applied to the oxide semiconductor layer 208_3, and the on-current can be increased. In addition, since the channel length L can be shortened, the switching characteristics are improved. On the other hand, since the gate insulating film of the drive transistor DRT can be made thicker than the gate insulating film of the write transistor SST, an electric field is not easily applied to the oxide semiconductor layer 208_1, and the on-current can be reduced. In particular, in a low gradation region controlled by a minute current, the current change of the drive transistor DRT can be made small, and the gradation can be finely controlled. This makes it possible to suppress the occurrence of display unevenness in the display region 102. Furthermore, since it is possible to suppress a large amount of current from continuously flowing through the drive transistor DRT, it is possible to suppress a decrease in reliability due to thermal deterioration.

[0100] Second embodiment In this embodiment, the configuration of a pixel 103B, which has a configuration partially different from the configuration of the pixel 103 described in the first embodiment, will be described with reference to Figures 14 and 15. Note that in the configuration of pixel 103B, the same parts as those of pixel 103 or parts having similar functions are denoted by the same reference numerals, and repeated description will be omitted.

[0101] <Equivalent circuit diagram> Fig. 14 is an equivalent circuit diagram of a pixel 103B included in a display device 100 according to one embodiment of the present invention. The equivalent circuit diagram shown in Fig. 14 differs from the equivalent circuit diagram shown in Fig. 2 in the configuration of the drive transistor DRT. In Fig. 14, the drive transistor DRT is bottom-gate driven, and the write transistor SST is top-gate driven.

[0102] <Cross-sectional structure of pixel> Fig. 15 is a diagram illustrating a cross-sectional structure of a pixel 103B of a display device 100 according to an embodiment of the present invention. As shown in Fig. 15, a transistor 210A and a transistor 250 are provided on a substrate 101 via an undercoat film 202. Here, the transistor 250 corresponds to the write transistor SST shown in Fig. 14, and the transistor 210A corresponds to the drive transistor DRT shown in Fig. 14. Note that the structure of the transistor 250 is similar to the structure of the transistor 250 shown in Fig. 13, and therefore a detailed description thereof will be omitted.

[0103] The transistor 210A functioning as the driving transistor DRT has a bottom-gate structure. The transistor 210A includes at least a conductive layer 204_1, an insulating film 206 provided over the conductive layer 204_1, and an oxide semiconductor layer 208_1 provided over the insulating film 206. The oxide semiconductor layer 208_1 includes a channel region 208a, high-concentration impurity regions 208b and 208c, and low-concentration impurity regions 208d and 208e. The low-concentration impurity regions 208d and 208e are provided with the channel region 208a sandwiched therebetween. The high-concentration impurity regions 208b and 208c are provided adjacent to the low-concentration impurity regions 208d and 208e. The channel region 208a and the low-concentration impurity regions 208d and 208e overlap with the conductive layer 204_1. The insulating film 206 functions as a gate insulating film of the transistor 210. An insulating film 212 is provided over the oxide semiconductor layer 208_1, and an insulating film 216 is further provided over the insulating film 212. The thickness of the insulating film 206 is preferably larger than that of the insulating film 212. The thickness of the insulating film 206 is 100 nm to 400 nm, preferably more than 150 nm to 300 nm. The thickness of the insulating film 212 is 30 nm to 150 nm. Source or drain electrodes 218_1 and 218_2 are provided over the insulating film 216. The source or drain electrodes 218_1 and 218_2 are connected to the high-concentration impurity regions 208b and 208c through contact holes provided in the insulating films 212 and 216. Although not shown, the conductive layer 204_1 is electrically connected to one of the source or drain electrodes 218_3 and 218_4.

[0104] 15, the transistor 210A includes low-concentration impurity regions 208d and 208e between the channel region 208a and the high-concentration impurity regions 208b and 208c in the oxide semiconductor layer 208_1. This reduces the electric field applied near the end of the channel region 208a, thereby improving the source-drain breakdown voltage. The low-concentration impurity regions 208d and 208e overlap with the conductive layer 204_1, thereby further improving the source-drain breakdown voltage.

[0105] As shown in FIG. 15, in the display device 100, a transistor having a top gate structure is provided as the write transistor SST, and a transistor having a bottom gate structure is provided as the drive transistor DRT on the same substrate. At this time, of the insulating films 206 and 212 sandwiching the oxide semiconductor layers 208_1 and 208_2 from above and below, the insulating film 212 functions as a gate insulating film in the write transistor SST, and the insulating film 206 functions as a gate insulating film in the drive transistor DRT. At this time, the film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. Therefore, the thickness of the gate insulating film can be made different between the write transistor SST and the drive transistor DRT. That is, a thin gate insulating film can be applied to the top-gate driven SST, and a thick gate insulating film can be applied to the bottom-gate driven drive transistor DRT.

[0106] Since the gate insulating film of the write transistor SST can be made thinner than the gate insulating film of the drive transistor DRT, an electric field is easily applied to the oxide semiconductor layer 208_2, and the on-current can be increased. In addition, in the write transistor SST, an impurity element is added to the oxide semiconductor layer 208_2 through the conductive layer 214_2, and the channel length L can be shortened. This allows the S value of the write transistor SST to be reduced. On the other hand, since the gate insulating film of the drive transistor DRT can be made thicker than the gate insulating film of the write transistor SST, an electric field is not easily applied to the oxide semiconductor layer 208_1, and the on-current can be reduced. In particular, in a low gradation region controlled by a minute current, the current change of the drive transistor DRT can be made small, and the gradation can be finely controlled. This allows the display unevenness to be suppressed from occurring in the display region 102. Furthermore, since a large amount of current can be prevented from continuously flowing through the drive transistor DRT, the deterioration of reliability due to thermal deterioration can be suppressed. As described in the first embodiment, when the write transistor SST is driven by dual gates, the BT stress of the gate is larger than that of the single gate drive. Therefore, although there is an advantage that the on / off characteristics of the transistor become sharper, reliability may be somewhat sacrificed. Therefore, when the driving capability is sufficient with the top gate drive and there is no need to shield the back surface from light, the reliability can be improved by omitting the gate electrode on the bottom side.

[0107] <Display Device Manufacturing Method> Next, a method for manufacturing the display device 100 according to one embodiment of the present invention will be described with reference to Fig. 16 to Fig. 18. Note that for the process from forming the base film 202 on the substrate 101 to the process of performing oxidation annealing, the explanations for Fig. 4 to Fig. 8 can be referred to.

[0108] FIG. 16 illustrates a step of forming a conductive layer 214_2 and a resist mask 215 over the insulating film 212. First, the conductive layer 214_2 is formed over the insulating film 212. The conductive layer 214_4 is formed by forming a conductive film over the insulating film 212 and processing the conductive film by photolithography. The conductive layer 214_2 is formed in a region overlapping with the oxide semiconductor layer 208_2. Next, a resist mask 215 is formed in a part of a region overlapping with the oxide semiconductor layer 208_1 provided over the insulating film 212. Here, the resist mask 215 is formed so that an end portion thereof has a tapered shape. The resist mask 215 is not limited to a tapered shape as long as the thickness of the resist mask 215 decreases toward the end portion.

[0109] 17 is a diagram illustrating a step of adding an impurity element to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. Using the conductive layer 214_2 and the resist mask 215 as masks, the impurity element is added to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. As a result, high-concentration impurity regions 208g and 208h are formed in a region of the oxide semiconductor layer 208_2 that does not overlap with the conductive layer 214_2, and a channel region 208f is formed in a region that overlaps with the conductive layer 214_2. The concentration of the impurity element in the high-concentration impurity regions 208g and 208h is 1×10 18 cm -3 More than 1×10 21 cm -3 or less. At the same time, high-concentration impurity regions 208b and 208c are formed in regions of the oxide semiconductor layer 208_1 that are not overlapped by the resist mask 215. In addition, an impurity element is added through the resist mask 215 to a region that overlaps with the tapered shape among the regions that are overlapped by the resist mask 215, so that low-concentration impurity regions 208d and 208e are formed. In addition, a channel region 208a is formed in a region of the resist mask 215 that overlaps with a portion other than the tapered shape. The concentration of the impurity element in the high-concentration impurity regions 208b and 208c is 1×10 18 cm -3 More than 1×1021 cm -3 It is preferable that the concentration of the impurity added to the low concentration impurity regions 208d and 208e is 1×10 or less. Furthermore, impurity elements are added to the low concentration impurity regions 208d and 208e through the resist mask 215. Therefore, the concentration of the impurity added to the low concentration impurity regions 208d and 208e is relatively lower than the concentration of the impurity added to the high concentration impurity regions 208b and 208c. For example, by appropriately controlling the inclination of the side surface of the resist mask 215, the concentration of the impurity added to the low concentration impurity regions 208d and 208e can be made one order of magnitude lower than the concentration of the impurity added to the high concentration impurity regions 208b and 208c. Therefore, the concentration of the impurity element in the low concentration impurity regions 208d and 208e is 1×10 or less when measured by SIMS analysis. 18 cm -3 The concentration of the impurity added to the low-concentration impurity regions 208d and 208e can be lower than the concentration of the impurity added to the high-concentration impurity regions 208b and 208c by one order of magnitude or more. As a result, the electrical conductivity of the low-concentration impurity regions 208d and 208e is lower than the electrical conductivity of the high-concentration impurity regions 208b and 208c. In other words, the electrical resistivity of the low-concentration impurity regions 208d and 208e is higher than the electrical resistivity of the high-concentration impurity regions 208b and 208c. In other words, the sheet resistance of the low-concentration impurity regions 208d and 208e is higher than the sheet resistance of the high-concentration impurity regions 208b and 208c. Note that the region where the thickest region of the resist mask 215 overlaps with the oxide semiconductor layer 208_1 determines the channel region of the transistor 210A. When the thickest region of the resist mask 215 is 2 μm to 4 μm, the channel length L can also be 2 μm to 4 μm. However, the channel length L of the transistor 210A and the channel length L of the transistor 250 may be the same or different as long as they are in the range of 2 μm to 4 μm.

[0110] Adding an impurity element to the oxide semiconductor layers 208_1 and 208_2 generates defects in the crystals of the oxide semiconductor layers 208_1 and 208_2, and thus the resistance of the oxide semiconductor layers 208_1 and 208_2 is reduced. The resistance of the oxide semiconductor layers 208_1 and 208_2 can be reduced depending on the concentration of the added impurity element. Thus, the resistance of the high-concentration impurity regions 208b, 208c, 208g, and 208h can be made lower than the resistance of the low-concentration impurity regions 208d and 208e. By using the tapered resist mask 215 and the conductive layer 214_2 as masks, a structure including the low-concentration impurity regions 208d and 208e can be formed in the oxide semiconductor layer 208_1 and a structure not including the low-concentration impurity regions can be formed in the oxide semiconductor layer 208_2 in a single step of adding the impurity element. On the other hand, the channel regions 208a and 208f have few crystal defects and low hydrogen concentrations, and therefore the resistance remains high. In this manner, the different oxide semiconductor layers 208_1 and 208_2 can be formed in the same process. After the impurity element is added, the resist mask 215 is removed.

[0111] Fig. 18 is a diagram for explaining the process from the step of forming the insulating film 216 to the step of forming the pixel electrode 226. For the process from the step of forming the insulating film 216 to the step of forming the pixel electrode 226, refer to the explanation in Fig. 12. Moreover, for the process from the step of forming the insulating film 228 to the step of forming the inorganic insulating film 242, the manufacturing method explained in the first embodiment may be applied.

[0112] Through the above steps, a display device 100 having the pixel 103B configuration shown in FIG. 15 can be manufactured.

[0113] According to the manufacturing method of the display device 100 according to the embodiment of the present invention, even in a small area such as within one pixel, two types of transistors having different characteristics and structures can be easily formed without increasing the number of processes. In particular, the oxide semiconductor layer 208_1 including the high-concentration impurity regions 208b, 208c and the low-concentration impurity regions 208d, 208e and the oxide semiconductor layer 208_2 including the high-concentration impurity regions 208g, 208h can be simultaneously formed.

[0114] (Variation 2) Fig. 19 is a diagram illustrating a cross-sectional structure of a pixel 103C of a display device 100 according to one embodiment of the present invention. As shown in Fig. 19, a transistor 210B and a transistor 250 are provided on a substrate 101 via an undercoat film 202. Here, the transistor 250 corresponds to the write transistor SST shown in Fig. 13, and the transistor 210B corresponds to the drive transistor DRT shown in Fig. 13.

[0115] In the transistor 210B, the conductive layer 214_1 and the high-concentration impurity region 208b are connected to each other through a source electrode or drain electrode 218_2 in the configuration of the transistor 210A. In forming the transistor 210B, after forming the conductive layers 214_1 and 214_2, an impurity element is added at a concentration of 5×10 12 atoms / cm 2 ~1×10 14 atoms / cm 2 After that, a resist mask is formed so as to cover the conductive layer 214_1 and the low-concentration impurity regions 208d and 208e, and then the impurity element is added at a concentration of about 1×10 14 atoms / cm 2 ~5×10 13 atoms / cm 2 As a result, a channel region 208a, high-concentration impurity regions 208b and 208c, and low-concentration impurity regions 208d and 208e may be formed in the oxide semiconductor layer 208_1 included in the driving transistor DRT.

[0116] Third embodiment In this embodiment, the configuration of a pixel 103D, which has a configuration partially different from that of the pixel 103 described in the first and second embodiments, will be described with reference to Fig. 20 to Fig. 22. Note that the same parts as those of the pixel 103D or parts having similar functions are given the same reference numerals, and repeated description will be omitted.

[0117] Fig. 20 is a diagram illustrating a cross-sectional structure of a pixel 103D of a display device according to an embodiment of the present invention. As shown in Fig. 20, a case will be described in which metal oxide layers 205_1 and 205_2 are provided between an insulating film 206 and oxide semiconductor layers 208_1 and 208_2.

[0118] The metal oxide layers 205_1 and 205_2 are metal oxides mainly composed of aluminum. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used as an inorganic insulating material. The ratio of aluminum contained in the metal oxide layers 205_1 and 205_2 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layers 205_1 and 205_2. The above ratio may be a mass ratio or a weight ratio.

[0119] The thickness of the metal oxide layers 205_1 and 205_2 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, aluminum oxide is used as the metal oxide layers 205_1 and 205_2. Aluminum oxide has high barrier properties against gas.

[0120] <Display Device Manufacturing Method> Next, a method for manufacturing the display device 100 according to one embodiment of the present invention will be described with reference to Fig. 21 and Fig. 22. Note that, for processes from the step of forming the base film 202 on the substrate 101 to the step of forming the insulating film 206, the description of Fig. 4 may be referred to.

[0121] 21 is a diagram illustrating a process of forming a metal oxide film 205 containing aluminum as a main component and an oxide semiconductor film 207 over an insulating film 206. The metal oxide layers 205_1 and 205_2 are formed by a sputtering method. The thicknesses of the metal oxide layers 205_1 and 205_2 are, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm.

[0122] Next, the oxide semiconductor film 207 is formed over the metal oxide layers 205_1 and 205_2. For the method of forming the oxide semiconductor film 207, the description of the formation of the oxide semiconductor film 207 in FIG.

[0123] Next, the oxide semiconductor layers 207_1 and 207_2 are patterned from the oxide semiconductor film 207. For the patterning of the oxide semiconductor film 207, the description of the patterning of the oxide semiconductor film 207 in FIG.

[0124] Next, the oxide semiconductor layers are subjected to OS annealing treatment. For the OS annealing treatment, see the description of the OS annealing treatment in FIG 7. By the OS annealing treatment, the oxide semiconductor layers 207_1 and 207_2 are crystallized, and the oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure are formed.

[0125] When oxygen supplying treatment is performed uniformly on the oxide semiconductor layers 208_1 and 208_2 having the above-described oxygen defect distribution, if an amount of oxygen necessary to repair oxygen defects formed on the upper surface sides of the oxide semiconductor layers 208_1 and 208_2 is supplied, oxygen is excessively supplied to the lower surface sides of the oxide semiconductor layers 208_1 and 208_2. As a result, a defect level different from the oxygen defects is formed on the lower surface sides due to the excess oxygen. As a result, phenomena such as characteristic fluctuation in a reliability test or a decrease in field effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface sides of the oxide semiconductor layers 208_1 and 208_2 while suppressing the supply of oxygen to the lower surface sides of the oxide semiconductor layers 208_1 and 208_2.

[0126] Oxidation annealing is performed in a state where the metal oxide layers 205_1 and 205_2 are provided under the oxide semiconductor layers 208_1 and 208_2 and the metal oxide film 213 is provided on the oxide semiconductor layers 208_1 and 208_2. In this manner, oxygen implanted into the insulating film 212 in the above-described oxidation annealing process is blocked by the metal oxide film 213, and thus is prevented from being released into the atmosphere. Furthermore, oxygen released from the insulating film 206 is supplied to the upper and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Furthermore, the metal oxide layers 205_1 and 205_2 can prevent oxygen from being excessively supplied below the oxide semiconductor layers 208_1 and 208_2. As a result, the oxygen is efficiently supplied to the oxide semiconductor layers 208_1 and 208_2, and oxygen defects can be repaired.

[0127] FIG. 22 is a diagram for explaining a process of forming a pattern of metal oxide layers 205_1 and 205_2 from a metal oxide film 205 using oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure. The metal oxide layers 205_1 and 205_2 are etched using the oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure as a mask. As the etching of the metal oxide layers 205_1 and 205_2, wet etching may be used or dry etching may be used. As the wet etching, for example, a mixed acid etching solution or a 0.5% hydrofluoric acid solution is used. As described in the first embodiment, the oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure have etching resistance to a mixed acid etching solution or a 0.5% hydrofluoric acid solution compared to the amorphous oxide semiconductor layers 207_1 and 207_2. The oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure are hardly reduced in thickness by etching and have excellent etching resistance. Therefore, the metal oxide layers 205_1 and 205_2 can be etched using the oxide semiconductor layers 208_1 and 208_2 as masks. This makes it possible to omit a photolithography process.

[0128] 8, an insulating film 212 is formed on the oxide semiconductor layers 208_1 and 208_2, and a metal oxide film 213 is formed on the insulating film 212. For materials and film formation methods of the insulating film 212 and the metal oxide film 213, refer to the description of the previous embodiment.

[0129] During the process from when the oxide semiconductor layers 208_1 and 208_2 are formed until when the insulating film 212 is formed on the oxide semiconductor layers 208_1 and 208_2, many oxygen defects are generated on the upper and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Therefore, the number of oxygen defects formed near the upper surfaces of the oxide semiconductor layers 208_1 and 208_2 is greater than the number of oxygen defects formed near the lower surfaces of the oxide semiconductor layers 208_1 and 208_2. In other words, the oxygen defects in the oxide semiconductor layers 208_1 and 208_2 are not uniformly present in the thickness direction of the oxide semiconductor layers 208_1 and 208_2, but are non-uniformly distributed in the thickness direction of the oxide semiconductor layers 208_1 and 208_2. Specifically, the number of oxygen defects in the oxide semiconductor layers 208_1 and 208_2 is smaller toward the lower surface of the oxide semiconductor layers 208_1 and 208_2 and is larger toward the upper surface of the oxide semiconductor layers 208_1 and 208_2.

[0130] When oxygen supplying treatment is performed uniformly on the oxide semiconductor layers 208_1 and 208_2 having the above-described oxygen defect distribution, if an amount of oxygen necessary to repair oxygen defects formed on the upper surface sides of the oxide semiconductor layers 208_1 and 208_2 is supplied, oxygen is excessively supplied to the lower surface sides of the oxide semiconductor layers 208_1 and 208_2. As a result, a defect level different from the oxygen defects is formed on the lower surface sides due to the excess oxygen. As a result, phenomena such as characteristic fluctuation in a reliability test or a decrease in field effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface sides of the oxide semiconductor layers 208_1 and 208_2 while suppressing the supply of oxygen to the lower surface sides of the oxide semiconductor layers 208_1 and 208_2.

[0131] Oxidation annealing is performed in a state where the metal oxide layers 205_1 and 205_2 are provided under the oxide semiconductor layers 208_1 and 208_2 and the metal oxide film 213 is provided on the oxide semiconductor layers 208_1 and 208_2. In this manner, oxygen implanted into the insulating film 212 in the above-described oxidation annealing process is blocked by the metal oxide film 213, and thus is prevented from being released into the atmosphere. Furthermore, oxygen released from the insulating film 206 is supplied to the upper and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Furthermore, the metal oxide layers 205_1 and 205_2 can prevent oxygen from being excessively supplied below the oxide semiconductor layers 208_1 and 208_2. As a result, the oxygen is efficiently supplied to the oxide semiconductor layers 208_1 and 208_2, and oxygen defects can be repaired.

[0132] After the oxidation annealing is performed, the metal oxide film 213 is removed. For the subsequent steps, refer to the explanations of FIGS.

[0133] In the transistor including the oxide semiconductor layers 208_1 and 208_2 manufactured by the above manufacturing method, when the channel length L of the channel regions 208a and 208f is in the range of 2 μm to 4 μm and the channel width of the channel regions 208a and 208f is in the range of 2 μm to 25 μm, the mobility is 50 [cm 2 / Vs] or more, 55[cm 2 / Vs] or more, or 60 [cm 2 / Vs] or higher electrical characteristics can be obtained.

[0134] (Variation 3) Fig. 23 is a diagram illustrating a cross-sectional structure of a pixel 103E of a display device 100 according to an embodiment of the present invention. As shown in Fig. 23, metal oxide layers 205_1 and 205_2 may be provided between an insulating film 206 and oxide semiconductor layers 208_1 and 208_2. For a method of forming the metal oxide layers 205_1 and 205_2 shown in Fig. 23, refer to the descriptions of Figs. 21 and 22.

[0135] In the transistor including the oxide semiconductor layers 208_1 and 208_2 manufactured by the above manufacturing method, when the channel length L of the channel regions 208a and 208i is in the range of 2 μm to 4 μm and the channel width of the channel regions 208a and 208i is in the range of 2 μm to 25 μm, the mobility is 50 [cm 2 / Vs] or more, 55[cm 2 / Vs] or more, or 60 [cm 2 / Vs] or higher electrical characteristics can be obtained.

[0136] (Variation 4) In this embodiment, the case where oxidation annealing is performed in a state where the metal oxide layers 205_1, 205_2 and the metal oxide film 213 are formed has been described, but an embodiment of the present invention is not limited thereto. After forming the oxide semiconductor layers 208_1, 208_2 having the polycrystalline structure described in Fig. 22, the insulating film 212 may be formed and oxidation annealing may be performed without forming the metal oxide film 213. In this case, the structure of the pixel is similar to that of the pixel 103D shown in Fig. 20 and the pixel 103E shown in Fig. 23, and therefore illustration of this modification is omitted.

[0137] In the display device 100 according to the present embodiment, a transistor is formed using oxide semiconductor layers 208_1 and 208_2 having a good polycrystalline structure. In the transistor Tr including the oxide semiconductor layers 208_1 and 208_2, the mobility is 30 cm when the channel length L of the channel regions 208a and 208i is in the range of 2 μm to 4 μm and the channel width of the channel regions 208a and 208i is in the range of 2 μm to 25 μm. 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 Electrical characteristics of at least / Vs can be obtained.

[0138] (Fourth embodiment) In this embodiment, the circuit configuration and operation method of a pixel included in a display device 100 will be described with reference to FIGS.

[0139] <Equivalent circuit diagram> 24 is an equivalent circuit diagram of a pixel 103E included in a display device 100 according to an embodiment of the present invention. The display device 100 has a high potential power supply SLa, a low potential power supply electrode SLb, a light emission control scanning line Sga, a write control scanning line Sgb, a reset control scanning line Sgc, and a video signal line VL. The high potential power supply SLa is supplied with a high potential power supply Pvdd, and the low potential power supply electrode SLb is supplied with a low potential power supply Pvss. The light emission control scanning line Sga, the write control scanning line Sgb, and the reset control scanning line Sgc are connected to gate drive circuits 104_1 and 104_2. The video signal line VL is connected to a driver IC 105.

[0140] The pixel 103E has a writing transistor SST, a driving transistor DRT, a storage capacitance Cs, and an additional capacitance Cad. The storage capacitance Cs and the additional capacitance Cad are capacitors. The additional capacitance Cad is an element provided to adjust the amount of light emission current, and may not be necessary in some cases. The parasitic capacitance Cel is the capacitance of the light emitting element itself (parasitic capacitance of the light emitting element OLED). The light emitting element OLED also functions as a capacitor.

[0141] Each pixel 103E has an output transistor BCT. In this embodiment, four pixels 103E adjacent to each other in the row direction X and column direction Y share one output transistor BCT. In addition, the gate drive circuits 104_1 and 104_2 are provided with a plurality of reset transistors RST. The reset transistors RST and the reset control scanning lines Sgr are connected in a one-to-one relationship.

[0142] The drive transistor DRT has the structure of the transistor 210 shown in the first embodiment, and the write transistor SST, the output transistor BCT, and the reset transistor RST have the structure of the transistor 220 shown in the first embodiment. Alternatively, the drive transistor DRT may have the structure of the transistor 210A or the transistor 210B shown in the second embodiment, and the write transistor SST, the output transistor BCT, and the reset transistor RST may have the structure of the transistor 220 or the transistor 250 shown in the second embodiment. In the display device 100 according to this embodiment, the transistors constituting each of the drive transistors and each of the switches are all formed in the same process.

[0143] Each of the write transistor SST, the drive transistor DRT, the output transistor BCT, and the reset transistor RST has a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is a source electrode, the second terminal is a drain electrode, and the control terminal is a gate electrode.

[0144] In the pixel circuit of the pixel, the drive transistor DRT is connected in series with the light emitting element OLED between the high potential power supply SLa and the low potential power supply electrode SLb.

[0145] In the output transistor BCT, the drain electrode is connected to the high potential power supply SLa, the source electrode is connected to the drain electrode of the drive transistor DRT, and the gate electrode is connected to the light emission control scanning line Sga. As a result, the output transistor BCT is controlled to be turned on (conductive state) or off (non-conductive state) by a control signal BG (1 to m / 2) from the light emission control scanning line Sga. The output transistor BCT controls the light emission time of the light emitting element OLED in response to the control signal BG.

[0146] In the driving transistor DRT, the drain electrode is connected to the source electrode of the output transistor BCT and the reset control scanning line Sgr, and the source electrode is connected to one electrode (here, the anode) of the light-emitting element OLED. The other electrode (here, the cathode) of the light-emitting element OLED is connected to the low potential power electrode SLb. The driving transistor DRT outputs a driving current of a current amount according to the video signal Vsig to the light-emitting element OLED.

[0147] In the write transistor SST, the source electrode is connected to the video signal line VL(1-n), the drain electrode is connected to the gate electrode of the drive transistor DRT, and the gate electrode is connected to the write control scanning line Sgb(1-m) that functions as a gate wiring for signal write control. The write transistor SST is controlled to be turned on and off by a control signal SG(1-m) supplied from the write control scanning line Sgb. In response to the control signal SG(1-m), the write transistor SST controls the connection and disconnection between the pixel circuit and the video signal line VL(1-n) and takes in the video signal Vsig from the corresponding video signal line VL(1-n) into the pixel circuit.

[0148] The reset transistors RST are provided in the gate drive circuits 104_1 and 104_2 for every two rows. The reset transistors RST are connected between the drain electrodes of the drive transistors DRT and a reset power supply. In the reset transistors RST, the source electrodes are connected to a reset power supply line SLc connected to the reset power supply, the drain electrodes are connected to a reset control scanning line Sgr, and the gate electrodes are connected to a reset control scanning line Sgc that functions as a reset control gate wiring. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed to a reset potential Vrst, which is a constant potential.

[0149] The reset transistor RST switches between a conductive state (on) and a non-conductive state (off) between the reset power line SLc and the reset control scan line Sgr in response to the control signals RG(1~m / 2) supplied through the reset control scan line Sgc. When the reset transistor RST is switched to the on state, the potential of the source electrode of the drive transistor DRT is initialized.

[0150] The gate drive circuits 104_1 and 104_2 include a shift register, an output buffer, etc. (not shown), transfer the horizontal scan start pulse supplied from the outside to the next stage in sequence, and supply three types of control signals, namely, the control signals BG(1~m / 2), the control signals SG(1~m), and the control signals RG(1~m / 2) to the pixels 103E of each row through the output buffer. Note that although the control signal RG is not directly supplied to the pixel 103E, a predetermined voltage is supplied from the reset power line SLc fixed at the reset potential Vrst at a predetermined timing according to the control signal RG. Thereby, the emission control scan line Sga, the write control scan line Sgb, and the reset control scan line Sgc are driven by the control signals BG, SG, and RG, respectively.

[0151] <Timing Chart> FIG. 25 is a timing chart of the gate drive circuits 104_1 and 104_2 for driving the pixels shown in FIG. 24. In FIG. 25, the control signal RGk, the control signal BGk, and the control signal SGk of the k-th row, and the control signal RGk+1, the control signal BGk+1, and the control signal SGk+1 of the (k + 1)-th row are shown. Each section indicated by G1~G4 is one horizontal period, and although it is omitted hereinafter, it continues to the last row. Regarding the period indicated by T0~ in FIG. 24, it will be described in detail below.

[0152] <T0. Pre-frame Emission> Until the processing in a certain frame period starts, the pixel continues the emission state of the previous frame.

[0153] <T1. DRT Source Initialization Operation> During this period, first, the control signal BG is at the L level, the control signal RG is at the H level, and the control signal SG is at the L level. As a result, the output transistor BCT turns off, the reset transistor RST turns on, and the write transistor SST turns off. Here, the holding capacitor Cs holds the "voltage corresponding to the video signal written in the previous frame". If the video signal Vsig is greater than the reset potential Vrst, the source side also approaches the reset potential Vrst through the driving transistor DRT. Also, since the reset potential Vrst is almost the same as the low potential power supply Pvss, the current supply to the light emitting element OLED stops. As a result, the potential of the source side of the driving transistor DRT becomes the lowest state in the pixel system.

[0154] <T2. Initialization of DRT Gate> During this period, the control signal BG is at the L level, the control signal RG is at the H level, the control signal SG is at the H level, the video signal line VL becomes the initialization potential Vini, the output transistor BCT turns off, the reset transistor RST turns on, and the write transistor SST turns on. In each pixel 103E of each row, the gate of the driving transistor DRT is fixed to the initialization potential Vini via the write transistor SST. The initialization potential Vini is set to a potential higher than the threshold value of the driving transistor DRT with respect to the reset potential Vrst. That is, by this operation, the driving transistor DRT is turned on. However, since the output transistor BCT is in the off state, no current flows through the driving transistor DRT yet. Even if the video signal Vsig was not greater than the reset potential Vrst in the T1.DRT source initialization operation, the source of the driving transistor DRT can also be initialized during this period.

[0155] <T3. Offset Cancellation Operation> During this period, the control signal BG is at the H level, the control signal RG is at the L level, the control signal SG is at the H level, the video signal line VL becomes the initialization potential Vini, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned on. Since the driving transistor DRT is in the on state due to the previous operation, current is supplied from the high potential power supply Pvdd to the driving transistor DRT through the output transistor BCT. At this stage, since the voltage between the anode and cathode of the light-emitting element OLED does not exceed the light emission start voltage, no current flows. Therefore, the source of the driving transistor DRT is charged by the current supplied from the high potential power supply Pvdd, and its potential rises. At this time, since the gate potential of the driving transistor DRT is Vini, when the source of the driving transistor DRT becomes (Vini - Vth), the driving transistor DRT turns off and the potential rise stops. Vth is the threshold voltage of the driving transistor DRT, and since there are variations depending on the pixel 103E, the potential of the source of the driving transistor DRT when the potential rise stops varies depending on the pixel. That is, by this operation, a voltage corresponding to the threshold voltage of the driving transistor DRT is obtained for each pixel 103E. At this time, a voltage of {(Vini - Vth) - Pvss} is applied between the anode and cathode of the light-emitting element OLED, but since this voltage still does not exceed the light emission start voltage, no current flows through the light-emitting element OLED.

[0156] According to the timing chart of FIG. 25, the operations 1 to 3 are performed in parallel for two lines, but this is not the limit. They may be sequentially performed for each line, or three or more lines may be performed in parallel.

[0157] <T4. Mobility Cancellation and Video Signal Writing Operation> When the control signal BG is at the H level, the control signal RG is at the L level, the control signal SG is at the H level, the video signal line VL becomes the video signal Vsig, the output transistor BCT turns on, the reset transistor RST turns off, and the write transistor SST turns on. In each pixel 103E of the row, the video signal Vsig is input to the gate of the drive transistor DRT, and the gate potential of the drive transistor DRT changes from the initialization potential Vini to the video signal Vsig. On the other hand, the source potential of the drive transistor DRT remains (Vini - Vth). As a result, the voltage between the gate and source of the drive transistor DRT becomes {Vsig - (Vini - Vth)}, which reflects the variation in the threshold value between the pixels 103E.

[0158] Since the video signal line VL that shares the video signal Vsig is common to the pixels 103E in a plurality of rows belonging to the same column, the video signal writing operation is sequentially performed for each row.

[0159] <T5. Emission operation> The control signal BG is at H level, the control signal RG is at L level, and the control signal SG is at L level, so the output transistor BCT turns on, the reset transistor RST turns off, and the write transistor SST turns off. A current is supplied from the high potential power supply Pvdd to the drive transistor DRT through the output transistor BCT. The drive transistor DRT passes a current according to the gate-source voltage set in the previous stage to the light-emitting element OLED, and the light-emitting element OLED emits light with a brightness according to the current. At this time, the anode-cathode voltage of the light-emitting element OLED becomes a voltage according to the current, so the potential on the anode side rises, but since the gate-source voltage of the drive transistor DRT is held by the storage capacitance Cs, the gate potential of the drive transistor DRT also rises due to coupling of the storage capacitance Cs as the potential on the anode side rises. In reality, the gate of the drive transistor DRT has not only the storage capacitance Cs but also the additional capacitance Cad and other parasitic capacitances, so the increase in the gate potential of the drive transistor DRT is slightly smaller than the increase in the potential on the anode side. However, since this value is known, it is sufficient to determine the potential of the video signal Vsig so that the final gate-source voltage of the drive transistor DRT becomes the desired current value.

[0160] This completes a series of pixel operations. When this operation is completed from the first row to the last row, one screen is displayed within one frame period. After this, the operation is repeated to display an image.

[0161] Any one of the bottom gate drive transistors 210, 210A, and 210B described in the first and second embodiments is applied to the drive transistor DRT. Also, any one of the top gate drive transistors 220 and 250 described in the first and second embodiments is applied to the write transistor SST, reset transistor RST, initialization transistor IST, and the like. As a result, since the S value of the drive transistor DRT is large, in the low gradation region where control with a minute current is required, the current change of the drive transistor DRT can be made small, and the gradation can be controlled finely. As a result, display unevenness can be suppressed in the display region 102.

[0162] Fifth embodiment In this embodiment, the circuit configuration and operation method of the pixel 103F of the display device 100 will be described with reference to FIGS.

[0163] <Circuit diagram> FIG. 26 is an equivalent circuit diagram of the pixel circuit of pixel 103F. The emission control scanning line Sga, the write control scanning line Sgb, the reset control scanning line Sgc, and the initialization control scanning line Sgd are each connected to the gate drive circuits 104_1 and 104_2 provided outside the display area 102. Each pixel 103F is provided with an output transistor BCT, an initialization transistor IST, a write transistor SST, and a drive transistor DRT. Some of the transistors may be shared among a plurality of adjacent pixels 103F. The reset transistor RST is provided, for example, one for each row outside the display area. A holding capacitor Cs may be provided between the gate and source of the drive transistor DRT. The parasitic capacitance Cel is the parasitic capacitance between the anode and cathode of the light-emitting element OLED. The high-potential power supply Pvdd is supplied to the anode of the light-emitting element OLED via the output transistor BCT and the drive transistor DRT, and the low-potential power supply Pvss is supplied to the cathode. The output transistor BCT, the initialization transistor IST, and the write transistor SST function as switching elements for selecting conduction and non-conduction between two nodes, and the drive transistor DRT functions as a current control element for controlling the current value flowing through the OLED according to the voltage between its gate and source. In this embodiment, transistor 210 is applied as the drive transistor DRT, and the structure of transistor 220 is applied as the output transistor BCT, the initialization transistor IST, and the write transistor SST.

[0164] <Timing Chart> FIG. 27 is a timing chart of the gate drive circuits 104_1 and 104_2 for driving the pixels shown in FIG. 26. Each section indicated by G1 to G3 is one horizontal period and continues to the last row. The periods indicated by T0 to T6 in FIG. 27 will be described below.

[0165] <T0. Emission in the previous frame> Until the start of the process in a certain frame period, the pixel continues the emission state of the previous frame.

[0166] <T1. Source initialization operation of the drive transistor DRT> During this period, first, the control signal BG is at the L level, the control signal RG is at the H level, the control signal IG is at the L level, and the control signal SG is at the L level. As a result, the output transistor BCT turns off, the reset transistor RST turns on, the initialization transistor IST turns off, and the write transistor SST turns off. Here, the holding capacitor Cs holds the "voltage corresponding to the video signal written in the previous frame". If the video signal Vsig is greater than the reset potential Vrst, the source side also approaches the reset potential Vrst through the driving transistor DRT. Also, since the reset potential Vrst is almost the same as the low potential power supply Pvss, the current supply to the light emitting element OLED stops. As a result, the potential on the source side of the driving transistor DRT becomes the lowest state in the pixel system.

[0167] <T2. Gate Initialization of the Driving Transistor DRT> The control signal IG becomes the H level, and the initialization transistor IST turns on. In each pixel of the row, the gate of the driving transistor DRT is fixed to the initialization potential Vini through the initialization transistor IST. The initialization potential Vini is set to a potential higher than the threshold value of the driving transistor DRT with respect to the reset potential Vrst. That is, by this operation, the driving transistor DRT becomes in the on state. However, since the output transistor BCT is off, no current flows through the driving transistor DRT yet.

[0168] <T3. Offset Cancellation Operation> The control signal BG is at the H level, the control signal RG is at the L level, the control signal IG is at the H level, the output transistor BCT is turned on, the reset transistor RST is turned off, and the initialization transistor IST is turned on. Since the driving transistor DRT is in the on state by the previous operation, current is supplied from Pvdd to the driving transistor DRT through the output transistor BCT. At this stage, since the voltage between the anode and cathode of the light-emitting element OLED does not exceed the light-emitting start voltage, no current flows. Therefore, the source of the driving transistor DRT is charged by the current supplied from the high-potential power supply Pvdd, and its potential rises. At this time, since the gate potential of the driving transistor DRT is the initialization potential Vini, when the source of the driving transistor DRT reaches (Vini - Vth), the driving transistor DRT turns off and the potential rise stops. Vth is the threshold voltage of the driving transistor DRT, and since there are variations depending on the pixel 103F, the potential of the source of the DRT when the potential rise stops varies from pixel to pixel. That is, by this operation, a voltage corresponding to the threshold voltage of the driving transistor DRT is obtained for each pixel. At this time, a voltage of {(Vini - Vth) - Pvss} is applied between the anode and cathode of the light-emitting element OLED, but since this voltage still does not exceed the light-emitting start voltage, no current flows through the light-emitting element OLED.

[0169] According to the timing chart of FIG. 27, the operations of T1 to T3 are performed in parallel for two rows, but this is not the limit. They may be sequentially performed for each row, or three or more rows may be performed in parallel.

[0170] <T4.T5. Video signal writing operation> The control signal BG is at the H level, the control signal RG is at the L level, the control signal IG is at the L level, the control signal SG is at the H level, the output transistor BCT is turned on, the reset transistor RST is turned off, the initialization transistor IST is turned off, and the write transistor SST is turned on. In each pixel of the row, the video signal Vsig is input to the gate of the driving transistor DRT, and the gate potential of the driving transistor DRT changes from Vini to Vsig. On the other hand, the source potential of the driving transistor DRT remains (Vini - Vth). As a result, the voltage between the gate and the source of the driving transistor DRT becomes {Vsig - (Vini - Vth)}, and the variation in the threshold value between pixels is reflected.

[0171] Since the video signal line VL that shares Vsig is common to the pixels of a plurality of rows belonging to the same column, the writing operation of the video signal VSig is sequentially performed for each row.

[0172] <T6. Light Emission Operation> The control signal BG is at H level, the control signal RG is at L level, the control signal IG is at L level, and the control signal SG is at L level, so that the output transistor BCT turns on, the reset transistor RST turns off, the initialization transistor IST turns off, and the write transistor SST turns off. A current is supplied from the high potential power supply Pvdd to the drive transistor DRT through the output transistor BCT. The drive transistor DRT passes a current according to the gate-source voltage set in the previous stage to the light-emitting element OLED, and the light-emitting element OLED emits light with a brightness according to the current. At this time, the anode-cathode voltage of the light-emitting element OLED becomes a voltage according to the current, so the potential on the anode side rises, but since the gate-source voltage of the drive transistor DRT is held by the holding capacitance Cs, the gate potential of the drive transistor DRT also rises due to the coupling of the holding capacitance Cs as the potential on the anode side rises. In reality, the gate of the drive transistor DRT is connected to not only the storage capacitance Cs but also the additional capacitance Cad and other parasitic capacitances Cel, so the increase in the gate potential of the drive transistor DRT is slightly smaller than the increase in the potential on the anode side. However, since this value is known, it is sufficient to determine the potential of the video signal Vsig so that the final gate-source voltage of the drive transistor DRT becomes the desired current value.

[0173] This completes a series of operations for pixel 103F. When this operation is completed from the first row to the last row, one screen is displayed within one frame period. After that, this operation is repeated to display an image.

[0174] Any one of the bottom gate drive transistors 210, 210A, and 210B described in the first and second embodiments is applied to the drive transistor DRT. Also, any one of the top gate drive transistors 220 and 250 described in the first and second embodiments is applied to the write transistor SST, reset transistor RST, initialization transistor IST, and the like. As a result, since the S value of the drive transistor DRT is large, in the low gradation region where control is required with a minute current, the current change of the drive transistor DRT can be made small, and the gradation can be controlled finely. As a result, display unevenness can be suppressed in the display region 102.

[0175] Based on the display device described as the embodiment and example of the present invention, a display device in which a person skilled in the art appropriately adds, removes, or modifies components, or adds, omits, or modifies conditions of a process, is also included in the scope of the present invention as long as the gist of the present invention is maintained. In addition, the above-mentioned embodiments can be combined with each other to the extent that no technical contradiction occurs.

[0176] Furthermore, even if there are other effects and advantages different from those brought about by the aspects of the above-mentioned embodiment, those which are clear from the description in this specification or which can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0177] Within the scope of the present invention, those skilled in the art will understand that various modifications and alterations may occur, and that these modifications and alterations also fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds, deletes, or modifies the design of the above-mentioned embodiments, or adds, omits, or modifies the conditions of a process, are also included in the scope of the present invention as long as they include the gist of the present invention. [Explanation of symbols]

[0178] 100: display device, 101: substrate, 102: display region, 103: pixel, 103A to 103E: pixels, 104_1, 104_2: gate drive circuit, 105: driver IC, 106: terminal, 107: terminal section, 108: flexible printed circuit, 109: peripheral region, 110: touch sensor, 202: undercoat film, 204_1, 204_2: conductive layer, 205: metal oxide film, 206: insulating film, 207_1, 207_2: oxide semiconductor layer, 208_1, 208_2: oxide semiconductor layer, 208a: channel region, 208b: high-concentration impurity region, 208c : high concentration impurity region, 208d: low concentration impurity region, 208e: low concentration impurity region, 208f: channel region, 208g: high concentration impurity region, 208h: high concentration impurity region, 208i: channel region, 208j: high concentration impurity region, 208k: high concentration impurity region, 210, 210A: transistor, 212: insulating film, 213: metal oxide film, 214: conductive layer, 215: resist mask, 216: insulating film, 218: drain electrode, 220, 220A: transistor, 222: planarization film, 226: pixel electrode, 228: insulating film, 230: light emitting element child, 232: organic layer, 233: inorganic insulating film, 234: common electrode, 236: inorganic insulating film, 238: organic insulating film, 240: sealing film, 242: inorganic insulating film, 250: transistor, 301: substrate, 302: undercoat film, 304: conductive layer, 306: insulating film, 308: oxide semiconductor layer, 310: transistor, 312: insulating film, 314: conductive layer, 316: insulating film, 318: drain electrode, 320: transistor, 350: transistor, BCT: output transistor, BG: control signal, Cad: additional capacitance, Cel: parasitic capacitance, DRT: drive transistor, IST: initialization transistor, OLED: light emitting element, Pvdd: high potential power supply, Pvss: low potential power supply, RG: control signal, RST: reset transistor, Sg: write control scanning line, SG: control signal, Sga: light emitting control scanning line, Sgb: write control scanning line, Sgc: reset control scanning line, Sgd: initialization control scanning line, Sgr: reset control scanning line, SLa: high potential power supply, SLb: low potential power supply electrode, SLc: reset power supply line, SST: write transistor, Vini: initialization potential, VL: video signal line, Vrst: reset potential, Vsig: video signal

Claims

1. A light-emitting element; a first transistor for controlling a value of a current flowing from a driving power line to the light emitting element; a second transistor for writing a voltage corresponding to the light emission luminance of the light emitting element to a first gate electrode of the first transistor; The first transistor is The first gate electrode; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode; a second insulating film provided on the first oxide semiconductor layer; a first conductive layer provided on the second insulating film; The second transistor is The first insulating film; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a thickness smaller than a thickness of the first insulating film; a second gate electrode provided on the second insulating film and having a region overlapping the second oxide semiconductor layer; the first oxide semiconductor layer has a first channel region and a first high concentration impurity region provided on either side of the first channel region; the second oxide semiconductor layer has a second channel region and a second high concentration impurity region provided on either side of the second channel region, the first conductive layer is electrically connected to the light emitting element; The display device, wherein an etching rate when the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

2. The thickness of the first insulating film is 100 nm or more and 500 nm or less, The display device according to claim 1 , wherein the second insulating film has a thickness of 30 nm or more and 150 nm or less.

3. an impurity element contained in the first high concentration impurity region and an impurity element contained in the second high concentration impurity region are the same element, The concentration of the impurity element contained in the first high concentration impurity region and the second high concentration impurity region is 1×10 １８ cm －３ Above 1 x 10 ２１ cm －３ 2. The display device according to claim 1, wherein:

4. 4. The display device according to claim 3, wherein the sheet resistance of the first high concentration impurity region and the second high concentration impurity region is 1000 Ω / sq. or less.

5. a first metal oxide layer provided between the first insulating film and the first oxide semiconductor layer; a second metal oxide layer provided between the first insulating film and the second oxide semiconductor layer, The display device according to claim 1 , wherein the first metal oxide layer and the second metal oxide layer have a thickness of 1 nm or more and 10 nm or less.

6. The display device according to claim 1 , wherein the etching solution contains nitric acid and acetic acid.

7. The display device according to claim 1 , wherein an etching rate of the first oxide semiconductor layer and the second oxide semiconductor layer when etched with a 0.5% hydrofluoric acid solution at room temperature is less than 5 nm / min.

8. the first oxide semiconductor layer and the second oxide semiconductor layer are formed by performing a heat treatment on an oxide semiconductor film having an amorphous structure; The display device according to claim 1 , wherein the oxide semiconductor film is etched at a rate of 100 nm / min or more when the oxide semiconductor film is etched with the etching solution at 40° C.

9. the first oxide semiconductor layer and the second oxide semiconductor layer contain a plurality of metal elements; one of the metal elements is indium; The display device according to claim 1 , wherein an atomic ratio of the indium to the plurality of metal elements is 50% or more.

10. A light-emitting element; a first transistor for controlling a value of a current flowing from a driving power line to the light emitting element; a second transistor for writing a voltage corresponding to the light emission luminance of the light emitting element to a first gate electrode of the first transistor; The first transistor is A first gate electrode; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode; The second transistor is The first insulating film; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a thickness smaller than a thickness of the first insulating film; a second gate electrode provided on the second insulating film and having a region overlapping the second oxide semiconductor layer; the first oxide semiconductor layer has a first channel region, low-concentration impurity regions provided on either side of the first channel region, and a first high-concentration impurity region provided adjacent to the low-concentration impurity region; the second oxide semiconductor layer has a second channel region and a second high concentration impurity region provided on either side of the second channel region, The display device, wherein an etching rate when the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

11. The display device according to claim 10 , wherein the low concentration impurity region overlaps with the first gate electrode.

12. The thickness of the first insulating film is 100 nm or more and 500 nm or less, The display device according to claim 10 , wherein the second insulating film has a thickness of 30 nm or more and 150 nm or less.

13. The display device according to claim 10 , wherein the impurity element contained in the first high concentration impurity region and the impurity element contained in the second high concentration impurity region are the same element.

14. The concentration of the impurity element contained in the first high concentration impurity region and the second high concentration impurity region is 1×10 １８ cm －３ Above 1 x 10 ２１ cm －３ is as follows: The concentration of the impurity element contained in the low concentration impurity region is 1×10 １８ cm －３ The display device of claim 10, wherein the .lambda.

15. 15. The display device according to claim 14, wherein the sheet resistance of the first high concentration impurity region and the second high concentration impurity region is 1000 Ω / sq. or less.

16. a first metal oxide layer provided between the first insulating film and the first oxide semiconductor layer; a second metal oxide layer provided between the first insulating film and the second oxide semiconductor layer, The display device according to claim 10 , wherein the first metal oxide layer and the second metal oxide layer have a thickness of 1 nm or more and 10 nm or less.

17. The display device according to claim 10 , wherein the etching solution contains nitric acid and acetic acid.

18. The display device according to claim 10 , wherein an etching rate when the first oxide semiconductor layer and the second oxide semiconductor layer are etched with a 0.5% hydrofluoric acid solution at room temperature is less than 5 nm / min.

19. the first oxide semiconductor layer and the second oxide semiconductor layer are formed by performing a heat treatment on an oxide semiconductor film having an amorphous structure; The display device according to claim 10 , wherein an etching rate of the oxide semiconductor film when etched with the etching solution at 40° C. is 100 nm / min or more.

20. the first oxide semiconductor layer and the second oxide semiconductor layer contain a plurality of metal elements; one of the metal elements is indium; The display device according to claim 10 , wherein an atomic ratio of the indium to the plurality of metal elements is 50% or more.

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