Semiconductor device

Abstract

To provide a semiconductor device with high reliability.SOLUTION: A semiconductor device includes a gate electrode, an oxide semiconductor layer with a polycrystalline structure, a gate insulating layer between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode on the oxide semiconductor layer. The oxide semiconductor layer includes a source region containing an impurity element and electrically connected to the source electrode, a drain region containing an impurity element and electrically connected to the drain electrode, a channel region between the source region and the drain region, and a first region including a first edge part extending along a first direction from the source region to the drain region, the first region being adjacent to the channel region. The first region has a higher electric resistivity than each of the source region and the drain region. The etching rate when the oxide semiconductor layer is etched using an etchant mainly containing phosphate at 40°C is less than 3 nm / min.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. [Background technology]

[0002] In recent years, development of semiconductor devices including oxide semiconductor films has been progressing in place of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single crystal silicon, etc. (see, for example, Patent Documents 1 to 6). A semiconductor device including such an oxide semiconductor film can be formed with a simple structure and a low-temperature process, similar to a semiconductor device including an amorphous silicon film. In addition, a semiconductor device including an oxide semiconductor film is known to have a higher field-effect mobility than a semiconductor device including an amorphous silicon film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device is required to have not only high field effect mobility but also high reliability. One object of an embodiment of the present invention is to provide a semiconductor device having high reliability. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present invention includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, a gate insulating layer between the gate electrode and the oxide semiconductor layer, a source electrode on the oxide semiconductor layer, and a drain electrode on the oxide semiconductor layer. The oxide semiconductor layer includes a source region containing an impurity element and electrically connected to the source electrode, a drain region containing an impurity element and electrically connected to the drain electrode, a channel region between the source region and the drain region, and a first region adjacent to the channel region and including a first edge portion extending along a first direction from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region, and an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

[0006] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer including a gate electrode extending in a first direction and a first edge portion and a second edge portion extending in a second direction intersecting the first direction, a gate insulating layer between the gate electrode and the oxide semiconductor layer, a source electrode on the oxide semiconductor layer, and a drain electrode on the oxide semiconductor layer, the oxide semiconductor layer including a first region overlapping with the gate electrode in a plan view, a source region adjacent to the first region and electrically connected to the source electrode via a first contact hole containing an impurity element, and a second contact hole adjacent to the first region and containing an impurity element. a drain region electrically connected to the source region, a second region surrounded by the source region and including part of the first edge, a third region surrounded by the source region and including part of the second edge, a fourth region surrounded by the drain region and including part of the first edge, and a fifth region surrounded by the drain region and including part of the second edge, wherein each of the first region, the second region, the third region, the fourth region, and the fifth region has a higher electrical resistivity than each of the source region and the drain region, and an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

[0007] A semiconductor device according to one embodiment of the present invention includes a gate electrode extending in a first direction, an oxide semiconductor layer having a polycrystalline structure including a first edge portion and a second edge portion extending in a second direction intersecting the first direction, a gate insulating layer between the gate electrode and the oxide semiconductor layer, a source electrode on the oxide semiconductor layer, and a drain electrode on the oxide semiconductor layer, the oxide semiconductor layer including a first region overlapping with the gate electrode in a plan view, a source region adjacent to the first region, containing an impurity element, and electrically connected to the source electrode via a first contact hole, and a drain electrode between the first region and the first region. and a drain region adjacent to the source region and containing an impurity element and electrically connected to the drain electrode via a second contact hole, wherein the first region has a higher electrical resistivity than each of the source region and the drain region, a first distance along a first direction from the first edge to the first contact hole in a plan view is greater than a second distance along a second direction from the first region to the first contact hole, and an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 3A] 1A to 1C are schematic cross-sectional views showing a method for forming a source region and a drain region in an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 3B] 1A to 1C are schematic cross-sectional views showing a method for forming a source region and a drain region in an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 11 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to a modified example of an embodiment of the present invention. [Diagram 5]10A to 10C are schematic cross-sectional views showing a method for forming a source region and a drain region in an oxide semiconductor layer of a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 6] FIG. 11 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 7] FIG. 11 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 8] FIG. 11 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 9] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a modified example of the embodiment of the present invention. [Figure 10] 1 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 12] FIG. 11 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 13] 1 is a schematic plan view showing a configuration of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 14A] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 14B] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 15A] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 15B] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 15C] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention. [Figure 16] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, film thickness, shape, etc. of the components compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "upper" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "lower" or "lower". Thus, for convenience of explanation, the terms "upper" and "lower" are used in the explanation, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the figure. In addition, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. "Upper" and "lower" refer to the order of stacking in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a semiconductor device, the semiconductor device and the pixel electrode may overlap in a planar view. Note that the planar view refers to a view from a direction perpendicular to the surface of the substrate.

[0011] In this specification and the like, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other components.

[0012] In this specification and the like, the term "semiconductor device" refers to a device in general that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are included in one form of semiconductor device. The semiconductor device of the embodiment described below may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a transistor used in a memory circuit.

[0013] In this specification, the term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent.

[0014] In this specification and the like, the terms "film" and "layer" may be interchangeable in some cases.

[0015] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0016] First Embodiment A semiconductor device 10 according to one embodiment of the present invention will be described with reference to FIGS. 1 to 3A.

[0017] [1. Configuration of Semiconductor Device 10] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention.

[0018] As shown in FIG. 1, the semiconductor device 10 includes a substrate 100, a first insulating layer 110, a light-shielding layer 120, a second insulating layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a source electrode 180, and a drain electrode 190. The first insulating layer 110 is provided on the substrate 100. The light-shielding layer 120 is provided on the first insulating layer 110. The second insulating layer 130 covers the upper surface and end surfaces of the light-shielding layer 120 and is provided on the first insulating layer 110. The oxide semiconductor layer 140 is provided on the second insulating layer 130. The gate insulating layer 150 covers the upper surface and end surfaces of the oxide semiconductor layer 140 and is provided on the second insulating layer 130. The gate electrode 160 overlaps the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surfaces of the gate electrode 160 and is provided on the gate insulating layer 150. The source electrode 180 and the drain electrode 190 are provided on the third insulating layer 170. The source electrode 180 is in contact with the oxide semiconductor layer 140 through a contact hole CH1 that penetrates the gate insulating layer 150 and the third insulating layer 170. The drain electrode 190 is in contact with the oxide semiconductor layer 140 through a contact hole CH2 that penetrates the gate insulating layer 150 and the third insulating layer 170. The source electrode 180 and the drain electrode 190 are electrically connected to the oxide semiconductor layer 140.

[0019] The substrate 100 can support each layer constituting the semiconductor device 10. For example, the substrate 100 can be a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate. The substrate 100 can also be a rigid substrate having no light-transmitting properties, such as a silicon substrate. The substrate 100 can also be a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the flexible substrate.

[0020] The first insulating layer 110 can suppress the diffusion of impurities from the substrate 100 or from the outside. For example, the first insulating layer 110 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ), or silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x ), or aluminum oxide nitride (AlN x O y The first insulating layer 110 may have a single-layer structure or a multi-layer structure.

[0021] Here, silicon oxynitride (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are oxides that contain a smaller ratio (x>y) of nitrogen (N) than oxygen (O). Silicon oxynitride (SiN x O y ) and aluminum oxide nitride (AlN x O y ) is a nitride containing a smaller ratio of oxygen than nitrogen (x>y). For convenience of explanation, silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) is simply called "silicon oxide" and silicon nitride (SiN x ) and silicon oxynitride (SiN x O y ) is sometimes simply called "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxide nitride (AlO x N y) is simply called "aluminum oxide" and aluminum nitride (AlN x ) and aluminum oxide nitride (AlN x O y ) is sometimes simply called "aluminum nitride."

[0022] The light-shielding layer 120 can reflect or absorb light incident from the substrate 100 side. In other words, the light-shielding layer 120 can block light incident on the oxide semiconductor layer 140. For example, the light-shielding layer 120 can be made of a metal such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy or compound of these metals. In addition, when the light-shielding layer 120 does not need to be conductive, the light-shielding layer 120 may not contain a metal. When the light-shielding layer 120 does not contain a metal, a black matrix made of a black resin can be used as the light-shielding layer 120. The light-shielding layer 120 may have a single-layer structure or a laminated structure. For example, the light-shielding layer 120 may have a laminated structure including a red color filter, a green color filter, and a blue color filter.

[0023] The second insulating layer 130 can suppress the diffusion of impurities from the light-shielding layer 120. In addition, when the light-shielding layer 120 has conductivity, the second insulating layer 130 can electrically insulate the light-shielding layer 120 from the oxide semiconductor layer 140. For example, the second insulating layer 130 can be made of the same oxide or nitride as the first insulating layer 110. The second insulating layer 130 may have a single-layer structure or a laminated structure. For example, the second insulating layer 130 may have a laminated structure including a silicon oxide film and a silicon nitride film.

[0024] Although the detailed configuration of the oxide semiconductor layer 140 will be described later, when the oxide semiconductor layer 140 comes into contact with a nitride, oxygen defects may be generated in the oxide semiconductor layer 140, or hydrogen may be supplied to the oxide semiconductor layer 140. In this case, the conductivity of the oxide semiconductor layer 140 increases, and the semiconductor properties are lost. For this reason, it is preferable to use an oxide for the second insulating layer 130 in contact with the oxide semiconductor layer 140. Specifically, when the second insulating layer 130 has a stacked structure including a silicon oxide film and a silicon nitride film, the silicon oxide film is provided on the silicon nitride film so that the silicon oxide film comes into contact with the oxide semiconductor layer 140.

[0025] The gate insulating layer 150 is located between the oxide semiconductor layer 140 and the gate electrode 160, and can electrically insulate the oxide semiconductor layer 140 from the gate electrode 160. The gate insulating layer 150 can be made of an oxide or nitride similar to that of the first insulating layer 110. The gate insulating layer 150 may have a single layer structure or a multilayer structure.

[0026] As described above, when the oxide semiconductor layer 140 is in contact with a nitride, hydrogen may be supplied to the oxide semiconductor layer 140. Therefore, it is preferable to use an oxide for the gate insulating layer 150 in contact with the oxide semiconductor layer 140. Specifically, the gate insulating layer 150 is made of silicon oxide.

[0027] The gate electrode 160 functions as an electrode that forms a channel in the oxide semiconductor layer 140. For example, the gate electrode 160 may be made of a metal such as copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof. The gate electrode 160 may have a single-layer structure or a multilayer structure.

[0028] The third insulating layer 170 can suppress the diffusion of impurities from the outside. For example, the third insulating layer 170 can be made of an oxide or a nitride similar to that of the first insulating layer 110. The third insulating layer 170 may have a single-layer structure or a multilayer structure.

[0029] Each of the source electrode 180 and the drain electrode functions as an input electrode or an output electrode of a current flowing through the oxide semiconductor layer 140. For example, the source electrode 180 and the drain electrode 190 can be made of a metal, an alloy, or a compound similar to that of the gate electrode. The source electrode 180 and the drain electrode may have a single-layer structure or a stacked-layer structure.

[0030] The semiconductor device 10 described above is a so-called top-gate transistor. The semiconductor device 10 can be modified in various ways. For example, when the light-shielding layer 120 is conductive, the semiconductor device 10 may have a configuration in which the light-shielding layer 120 functions as a gate electrode and the second insulating layer 130 functions as a gate insulating layer. In this case, the semiconductor device 10 is a so-called dual-gate transistor. When the light-shielding layer 120 is conductive, the light-shielding layer 120 may be a floating electrode and may be connected to the source electrode 180. Furthermore, the semiconductor device 10 may be a so-called bottom-gate transistor in which the light-shielding layer 120 functions as a main gate electrode.

[0031] 2. Configuration of Oxide Semiconductor Layer 140 [2-1. Composition of the oxide semiconductor layer 140] An oxide semiconductor containing two or more metal elements including indium (In) is used as the oxide semiconductor layer 140. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanoids are used.

[0032] The oxide semiconductor layer 140 has a light-transmitting property and a polycrystalline structure including a plurality of crystal grains. In order for the oxide semiconductor layer 140 to have a polycrystalline structure, it is preferable to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio. When the ratio of indium is large, the oxide semiconductor layer 140 is more likely to crystallize. In addition, it is preferable to contain gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is hardly impaired by gallium.

[0033] Although the details will be described later, the oxide semiconductor layer 140 has properties different from those of conventional oxide semiconductors having a polycrystalline structure. Therefore, in order to distinguish the oxide semiconductor contained in the oxide semiconductor layer 140 from conventional oxide semiconductors having a polycrystalline structure, the oxide semiconductor contained in the oxide semiconductor layer 140 will be referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) in the following description.

[0034] The Poly-OS included in the oxide semiconductor layer 140 can be formed by sputtering and heat treatment. Here, a method for forming the oxide semiconductor layer 140 will be described.

[0035] First, an oxide semiconductor film is formed by sputtering. The formed oxide semiconductor film has an amorphous structure. Here, the amorphous structure refers to a structure in which a long-range ordered structure does not exist and a periodic crystal lattice arrangement is not observed. For example, when an oxide semiconductor film having an amorphous structure is observed by X-ray diffraction (XRD), a specific peak based on a crystal structure is not obtained in the diffraction pattern. Note that an oxide semiconductor film having an amorphous structure may have a short-range ordered structure in a micro domain. However, such an oxide semiconductor film does not exhibit the characteristics of Poly-OS, and therefore can be classified as an oxide semiconductor film having an amorphous structure.

[0036] An oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor film is formed is 150° C. or lower, preferably 100° C. or lower, and more preferably 50° C. or lower. When the substrate temperature is high, microcrystals are likely to be generated in the oxide semiconductor film to be formed. In addition, the oxygen partial pressure in the chamber during film formation is 1% to 10%, preferably 1% to 5%, and more preferably 2% to 4%. When the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to excess oxygen contained in the oxide semiconductor. On the other hand, under conditions where the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes nonuniform, and an oxide semiconductor film containing many microcrystals or an oxide semiconductor film that does not crystallize even when heat treatment is performed is formed.

[0037] Next, the oxide semiconductor film formed by sputtering is subjected to heat treatment. The heat treatment is performed in air, but the atmosphere is not limited thereto. The heat treatment temperature is 300° C. to 500° C., and preferably 350° C. to 450° C. The heat treatment time is 15 minutes to 120 minutes, and preferably 30 minutes to 60 minutes. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized, and an oxide semiconductor layer 140 containing Poly-OS is formed.

[0038] The composition of the oxide semiconductor layer 140 is approximately equal to the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the composition of the metal elements of the sputtering target. The composition of the oxide semiconductor layer 140 may be specified by using an XRD method. Specifically, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained by the XRD method. Furthermore, the composition of the metal elements of the oxide semiconductor layer 140 can also be specified by using an X-ray fluorescence analysis or an Electron Probe Micro Analyzer (EPMA) analysis. Note that the oxygen contained in the oxide semiconductor layer 140 is not limited to this because it changes depending on the process conditions of the sputtering.

[0039] [2-2. Characteristics of the oxide semiconductor layer 140] Next, characteristics of the oxide semiconductor layer 140 containing Poly-OS will be described.

[0040] The oxide semiconductor layer 140 has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer 140 is very small when the oxide semiconductor layer 140 is etched using an etching solution for wet etching. This means that the oxide semiconductor layer 140 is hardly etched by the etching solution. The etching rate of the oxide semiconductor layer 140 when the oxide semiconductor layer 140 is etched using an etching solution containing phosphoric acid as a main component at 40° C. (hereinafter, referred to as a “mixed acid etching solution”) is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the mixed acid etching solution is 50% or more, 60% or more, or 70% or more. The mixed acid etching solution may contain acetic acid and nitric acid in addition to phosphoric acid. Note that, in an oxide semiconductor film not containing Poly-OS, for example, an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate of the oxide semiconductor film when the oxide semiconductor film is etched using a mixed acid etching solution at 40° C. is 100 nm / min or more. Furthermore, the etching rate when the oxide semiconductor layer 140 is etched using a 0.5% hydrofluoric acid solution at room temperature is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Note that, in the case of an oxide semiconductor film not including Poly-OS, the etching rate when the oxide semiconductor film is etched using a 0.5% hydrofluoric acid solution at room temperature is 15 nm / min or more. Here, "40°C" includes a range of 40±5°C, and may be the temperature of the etching solution or the set temperature of the etching solution. Furthermore, "room temperature" refers to 25±5°C.

[0041] An example of the oxide semiconductor layer 140 is shown in Table 1. Table 1 shows the etching rates of each of the prepared samples with respect to a mixed acid etching solution ("Mixed Acid AT-2F" manufactured by Nasa Industries Co., Ltd., in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and a 0.5% hydrofluoric acid solution. When each sample was etched, the temperature of the mixed acid etching solution was 40°C, and the temperature of the 0.5% hydrofluoric acid solution was room temperature (22°C). In Table 1, Sample 1 is an oxide semiconductor layer 140 containing Poly-OS, Sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor film containing indium gallium zinc oxide (IGZO) in which the ratio of indium is less than 50%.

[0042] [Table 1]

[0043] As shown in Table 1, Sample 1 (oxide semiconductor layer 140 containing Poly-OS) is hardly etched using a mixed acid etching solution, and is etched at only 2 nm / min at most using a 0.5% hydrofluoric acid solution. Sample 1 has an etching rate of 1 / 100 or less with a mixed acid etching solution and approximately 1 / 10 or less with a 0.5% hydrofluoric acid solution than Sample 2 (oxide semiconductor film having an amorphous structure before heat treatment). Sample 1 also has an etching rate of 1 / 100 or less with a mixed acid etching solution than Sample 3 (oxide semiconductor film containing IGZO with an indium ratio of less than 50%). That is, Sample 1 is significantly more etch-resistant than Samples 2 and 3.

[0044] Such excellent etching resistance of the oxide semiconductor layer 140 containing Poly-OS is a property that cannot be obtained from a conventional oxide semiconductor having a polycrystalline structure that is fabricated by a process at or below 500° C. Although the detailed mechanism of the excellent etching resistance of the oxide semiconductor layer 140 containing Poly-OS is unclear, it is believed that Poly-OS has a polycrystalline structure different from the conventional one.

[0045] As described above, the oxide semiconductor layer 140 containing Poly-OS has a very low etching rate with respect to an etching solution. Therefore, it is very difficult to pattern the oxide semiconductor layer 140. Therefore, when forming the island-shaped oxide semiconductor layer 140, an oxide semiconductor film having an amorphous structure before heat treatment is patterned into islands, and then the oxide semiconductor film is crystallized by heat treatment. In this way, the island-shaped oxide semiconductor layer 140 containing Poly-OS can be formed.

[0046] [2-3. Structure of the oxide semiconductor layer 140] Fig. 2 is a schematic plan view showing a configuration of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention. For convenience of explanation, the gate electrode 160, the source electrode 180, and the drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 2.

[0047] The oxide semiconductor layer 140 is formed in an island shape. For example, the planar shape of the oxide semiconductor layer 140 is a rectangle, but is not limited thereto. Since the oxide semiconductor layer 140 is formed in an island shape, it has one or more edges. As shown in FIG. 2, when the planar shape of the oxide semiconductor layer 140 is a rectangle, the oxide semiconductor layer 140 has four edges.

[0048] As shown in FIG. 2, the oxide semiconductor layer 140 includes a channel region 141, a source region 142, and a drain region 143. The channel region 141 is located between the source region 142 and the drain region 143. The channel region 141 overlaps with the gate electrode 160. The source region 142 overlaps with the source electrode 180. The drain region 143 overlaps with the drain electrode 190. The source electrode 180 is electrically connected to the source region 142 through a contact hole CH1, and the drain electrode 190 is electrically connected to the drain region 143 through a contact hole CH2. The channel region 141 has a semiconductor property. Therefore, when a voltage is applied to the gate electrode 160, a channel that becomes a current path is formed in the channel region 141. Each of the source region 142 and the drain region 143 has a conductor property. Therefore, the carrier concentration of the source region 142 and the drain region 143 is higher than the carrier concentration of the channel region 141. In other words, the channel region 141 has a higher electrical resistivity (or a lower electrical conductivity) than each of the source region 142 and the drain region 143. For example, the sheet resistance of the source region 142 and the drain region 143 is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. Hereinafter, for convenience of explanation, a region such as the channel region 141 having a higher electrical resistivity than the source region 142 and the drain region 143 will be referred to as a "high resistance region."

[0049] The oxide semiconductor layer 140 includes a first region A1, a second region A2, and a third region A3 as high resistance regions. The first region A1 is located between the source region 142 and the drain region 143. That is, the first region A1 is a channel region 141. The second region A2 includes a first edge portion E1 extending along the x-axis direction of the oxide semiconductor layer 140 and is adjacent to the first region A1. The third region A3 includes a second edge portion E2 extending along the x-axis direction of the oxide semiconductor layer 140 and is adjacent to the first region A1. The second edge portion E2 is located on the opposite side of the first edge portion E1. That is, the third region A3 is located on the opposite side of the second region A2 with the first region A1 interposed therebetween. In a plan view, each of the source region 142 and the drain region 143 is surrounded by the first region A1 to the third region A3.

[0050] In a plan view, the gate electrode 160 extends so as to overlap the first region A1, the second region A2, and the third region A3, and covers the entire first region A1. The gate electrode 160 also overlaps a part of the source region 142 and a part of the drain region 143. Therefore, a first width W1 (corresponding to the channel length of the channel region 141) of the first region A1 in the x-axis direction is smaller than a second width W2 of the gate electrode 160 in the x-axis direction.

[0051] [2-4. Formation of source region 142 and drain region 143] 3A and 3B are schematic cross-sectional views showing a method for forming a source region 142 and a drain region 143 in an oxide semiconductor layer 140 of a semiconductor device 10 according to an embodiment of the present invention. Specifically, each of Fig. 3A and Fig. 3B is a cross-sectional view taken along line Y1-Y2 in Fig. 2.

[0052] FIG. 3A shows an oxide semiconductor layer 140 formed on the second insulating layer 130 using the Poly-OS technique described above. Therefore, the oxide semiconductor layer 140 in FIG. 3A has a predetermined shape and includes Poly-OS. In the method of forming the source region 142 and the drain region 143 shown in FIG. 3A, a resist R1 having a desired shape is formed on the oxide semiconductor layer 140. The resist R1 overlaps with the regions (the first region A1, the second region A2, and the third region A3) where the high resistance regions are to be formed. On the other hand, the resist R1 does not overlap with the regions where the source region 142 and the drain region 143 are to be formed.

[0053] Next, ions are implanted into the oxide semiconductor layer 140 using the resist R1 as a mask. In one example, the oxide semiconductor layer 140 is doped with boron (B) as an impurity element by ion implantation. Note that, instead of boron, other impurity elements such as phosphorus (P) may be doped into the oxide semiconductor layer 140. As a result, a source region 142 and a drain region 143 doped with the impurity element are formed in the oxide semiconductor layer 140. Since oxygen defects are formed in the source region 142 and the drain region 143 by the doping of the impurity element, the source region 142 and the drain region 143 have low resistance. On the other hand, a high resistance region not containing the impurity element is also formed by being masked with the resist R1. Note that, in the oxide semiconductor layer 140 including the Poly-OS, the source region 142 and the drain region doped with the impurity element may have crystallinity, which is also one of the characteristics of the Poly-OS. In this case, the crystal structure of each of the source region 142 and the drain region 143 is the same as the crystal structure of the channel region 141.

[0054] Next, after removing the resist R1, a silicon oxide film is formed to form the gate insulating layer 150. Then, the gate electrode 160 is formed on the gate insulating layer 150. At this time, the gate electrode 160 is patterned so as to overlap with the first region A1.

[0055] 3B shows a method for forming the source region 142 and the drain region 143, which is different from that shown in FIG. 3A. FIG. 3B shows a gate insulating layer 150 formed on an oxide semiconductor layer 140 including Poly-OS. In the method for forming the source region 142 and the drain region 143 shown in FIG. 3B, a resist R1 having a desired shape is formed on the gate insulating layer 150. The resist R1 overlaps with a region where a high resistance region is to be formed. On the other hand, the resist R1 does not overlap with a region where the source region 142 and the drain region 143 are to be formed.

[0056] Next, using the resist R1 as a mask, ions are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150. As a result, a source region 142 and a drain region 143 doped with impurities are formed in the oxide semiconductor layer 140.

[0057] Subsequently, after removing the resist R1, the gate electrode 160 is formed on the gate insulating layer 150. At this time, the gate electrode 160 is patterned so as to overlap with the first region A1.

[0058] In the method of forming the source region 142 and the drain region 143 shown in FIG. 3A and FIG. 3B, the ion implantation into the oxide semiconductor layer 140 is performed using the resist R1 as a mask, not the gate electrode 160 as a mask. Therefore, as shown in FIG. 2, the second width W2 of the gate electrode 160 does not necessarily match the first width W1 of the first region A1. In addition, the second width W2 is set to be larger than the first width W1 because the gate electrode 160 overlaps the entire first region A1. Therefore, the gate electrode 160 overlaps the entire first region A1, and also overlaps with a part of the source region 142 and a part of the drain region 143. In addition, the gate electrode 160 overlaps with a part of the second region A2 and a part of the third region A3.

[0059] In the semiconductor device 10 fabricated using the method for forming the source region 142 and the drain region 143 shown in FIG. 3A or FIG. 3B, the second region A2 including the first edge E1 and the third region A3 including the second edge E2 have high resistance similar to that of the first region A1 corresponding to the channel region 141. Therefore, the second region A2 and the third region A3 cannot become a current path like the source region 142 and the drain region 143. That is, when a gate voltage equal to or higher than the threshold is applied to the gate electrode 160, a current flows between the source electrode 180 and the drain electrode 190 through the channel region 141, the source region 142, and the drain region 143 of the oxide semiconductor layer 140. On the other hand, in the oxide semiconductor layer 140, almost no current flows through the second region A2 and the third region A3.

[0060] The second region A2 including the first edge E1 and the third region A3 including the second edge E2 are regions that are easily damaged by etching when forming the island-shaped oxide semiconductor layer 140 and are easily deteriorated due to heat generated by current flow. In this embodiment, heat generation in the second region A2 and the third region A3 is reduced, and deterioration due to heat generation in the second region A2 and the third region A3 can be suppressed. Therefore, increasing the resistance of the second region A2 and the third region A3 to make it difficult for current to flow is effective in suppressing deterioration of the second region A2 and the third region A3.

[0061] Even if the second region A2 and the third region A3 are deteriorated, the influence on the electrical characteristics of the semiconductor device 10 is small because the second region A2 and the third region A3 are not regions where a current path is originally formed. For example, in the semiconductor device 10, a shift in the threshold voltage is suppressed. Therefore, the semiconductor device 10 can have high reliability.

[0062] <Variation 1> A modified example of this embodiment will be described with reference to Figures 4 and 5. Note that in the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0063] Fig. 4 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modified embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 4.

[0064] The shapes of the first region A1 to the third region A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as described with reference to FIG. 2. In the oxide semiconductor layer 140 shown in FIG. 4, the first width W1 of the first region A1 in the x-axis direction is substantially the same as the second width of the gate electrode 160 in the x-axis direction. The gate electrode 160 overlaps not only the entire first region A1, but also the entire second region A2 and the entire third region A3. In a plan view, the boundaries between the first region A1 to the third region A3 and the source region 142 substantially coincide with the edges of the gate electrode 160. Similarly, the boundaries between the first region A1 to the third region A3 and the drain region 143 substantially coincide with the edges of the gate electrode 160.

[0065] In a plan view, the source electrode 180 overlaps with the source region 142 but does not overlap with the first region A1 to the third region A3. Similarly, the drain electrode 190 overlaps with the drain region 143 but does not overlap with the first region A1 to the third region A3. The source electrode 180 contacts the source region 142 through a contact hole CH1, and the drain electrode 190 contacts the drain region 143 through a contact hole CH2.

[0066] 5A and 5B are schematic cross-sectional views showing a method for forming a source region 142 and a drain region 143 in an oxide semiconductor layer 140 of a semiconductor device 10 according to a modified example of an embodiment of the present invention. Specifically, each of Figs. 5A and 5B is a cross-sectional view taken along line Y1-Y2 in Fig. 4.

[0067] 5 shows a gate insulating layer 150 formed on an oxide semiconductor layer 140 including Poly-OS. In the formation method shown in FIG. 5, a gate electrode 160 having a desired shape is formed on the gate insulating layer 150. The gate electrode 160 overlaps with regions (first region A1, second region A2, and third region A3) where high resistance regions are to be formed. On the other hand, the gate electrode 160 does not overlap with regions where the source region 142 and the drain region 143 are to be formed.

[0068] Next, using the gate electrode 160 as a mask, ions are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150. As a result, a source region 142 and a drain region 143 doped with an impurity element are formed in the oxide semiconductor layer 140.

[0069] 5, the gate electrode 160 is used as a mask for ion implantation into the oxide semiconductor layer 140. Therefore, as shown in FIG. 4, the second width W2 of the gate electrode 160 is substantially equal to the first width W1 of the first region A1. The gate electrode 160 does not overlap the source region 142 and the drain region 143, but overlaps the entire second region A2 and the entire third region A3.

[0070] The semiconductor device 10 described with reference to FIGS. 4 and 5 also provides the same effects as those described above.

[0071] <Variation 2> Another modified example of this embodiment will be described with reference to Fig. 6. Note that in the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0072] Fig. 6 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modified embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 6.

[0073] The shapes of the first region A1 to the third region A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as described with reference to FIG. 2. In the oxide semiconductor layer 140 shown in FIG. 6, the first width W1 of the first region A1 in the x-axis direction is substantially the same as the second width W2 of the gate electrode 160 in the x-axis direction. The gate electrode 160 overlaps the entire first region A1, but overlaps a part of the second region A2 and a part of the third region A3. That is, the gate electrode 160 extends along the y-axis direction with the second width W2 and overlaps the second region A2 and the third region A3.

[0074] In a plan view, the source electrode 180 overlaps with the second region A2, the third region A3, and the source region 142. The drain electrode 190 overlaps with the second region A2, the third region A3, and the drain region 143. However, the source electrode 180 and the drain electrode 190 are not in contact with the second region A2 and the third region A3. The source electrode 180 contacts the source region 142 through a contact hole CH1, and the drain electrode 190 contacts the drain region 143 through a contact hole CH2.

[0075] The shape of the gate electrode 160 can be formed, for example, as follows. That is, as described with reference to FIG. 5, the gate electrode 160 is patterned so as to overlap with regions (first region A1 to third region) of the oxide semiconductor layer 140 in which high-resistance regions are to be formed. Then, ions are implanted into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Then, parts of the gate electrode 160 that overlap with parts of the second region A2 and the third region A3 adjacent to the source region 142 and the drain region 143 are removed by etching. As a result, the gate electrode 160 having the shape shown in FIG. 6 is formed.

[0076] The semiconductor device 10 described with reference to FIG. 6 also provides the same effects as those described above.

[0077] <Variation 3> Another modified example of this embodiment will be described with reference to Fig. 7. In the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0078] Fig. 7 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modified embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 7.

[0079] The shapes of the first region A1 to the third region A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as described with reference to FIG. 2. In the oxide semiconductor layer 140 shown in FIG. 7, the gate electrode 160 has a second width W2 and a third width W3 in the x-axis direction and extends in the y-axis direction. The portion of the gate electrode 160 overlapping with the first region A1 has the second width W2. The portion of the gate electrode 160 overlapping with the second region A2 and the third region A3 has the third width W3. The second width W2 is approximately the same as the first width W1. Meanwhile, the third width W3 is larger than the first width W1.

[0080] The shape of the gate electrode 160 can be formed, for example, as follows. That is, as described with reference to FIG. 5, the gate electrode 160 is patterned so as to overlap with regions (first region A1 to third region) of the oxide semiconductor layer 140 where high-resistance regions are to be formed. Then, ions are implanted into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Then, a part of the gate electrode 160 is removed by etching. At this time, the gate electrode 160 is etched so that the width of the portions overlapping the second region A2 and the third region A3 is larger than the width of the portion overlapping the first region A1. As a result, the gate electrode 160 having the shape shown in FIG. 7 is formed.

[0081] The semiconductor device 10 described with reference to FIG. 7 also provides the same effects as those described above.

[0082] <Modification 4> Another modified example of this embodiment will be described with reference to Fig. 8. Note that in the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0083] Fig. 8 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modified embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 8.

[0084] The shapes of the first region A1 to the third region A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as described with reference to FIG. 2. In the oxide semiconductor layer 140 shown in FIG. 8, the gate electrode 160 has a second width W2 and a third width W3 in the x-axis direction and extends in the y-axis direction. The portion of the gate electrode 160 overlapping with the first region A1 has the second width W2. The portion of the gate electrode 160 overlapping with the second region A2 and the third region A3 has the third width W3. The second width W2 is approximately the same as the first width W1. Meanwhile, the third width W3 is smaller than the first width W1.

[0085] The shape of the gate electrode 160 can be formed, for example, as follows. That is, as described with reference to FIG. 5, the gate electrode 160 is patterned so as to overlap with regions (first region A1 to third region) of the oxide semiconductor layer 140 in which high-resistance regions are to be formed. Then, ions are implanted into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Then, a part of the gate electrode 160 is removed by etching. At this time, the gate electrode 160 is etched so that the width of the portions overlapping the second region A2 and the third region A3 is smaller than the width of the portion overlapping the first region A1. As a result, the gate electrode 160 having the shape shown in FIG. 8 is formed.

[0086] The semiconductor device 10 described with reference to FIG. 8 also provides the same effects as those described above.

[0087] <Variation 5> Another modified example of this embodiment will be described with reference to Fig. 9. In the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0088] FIG. 9 is a schematic plan view showing the configuration of a semiconductor device 10A according to a modified example of one embodiment of the present invention.

[0089] As shown in FIG. 9, the semiconductor device 10A includes a substrate 100, a first insulating layer 110, a light-shielding layer 120, a second insulating layer 130, a metal oxide layer 135, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a source electrode 180, and a drain electrode 190. In the semiconductor device 10A, a metal oxide layer 135 is provided under the oxide semiconductor layer 140 and in contact with the oxide semiconductor layer 140. An end face of the metal oxide layer 135 is approximately aligned with an end face of the oxide semiconductor layer 135. The gate insulating layer 150 covers the end face of the metal oxide layer 135 and the upper surface and end face of the oxide semiconductor layer 140, and is provided on the second insulating layer 130.

[0090] The metal oxide layer 135 can function as a buffer layer that improves the crystallinity of the oxide semiconductor layer 140. In the semiconductor device 10A including the oxide semiconductor layer 135 with improved crystallinity, the field effect mobility is further improved.

[0091] A metal oxide containing aluminum as a main component is used as the metal oxide layer 135. The ratio of aluminum contained in the metal oxide layer 135 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer 135. The above ratio may be a mass ratio or a weight ratio.

[0092] The thickness of the metal oxide layer 135 is 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. Aluminum oxide is preferably used as the metal oxide layer 135. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. Here, the barrier properties refer to the function of suppressing the permeation of gases such as oxygen and hydrogen.

[0093] Note that a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide layer 135. For example, the metal oxide layer 135 may be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like.

[0094] The metal oxide layer 135 can be formed by sputtering or atomic layer deposition (ALD). The metal oxide layer 135 can be patterned using the oxide semiconductor layer 140 as a mask. As described above, the oxide semiconductor layer 140 including Poly-OS has excellent etching resistance. Therefore, even when the metal oxide layer 135 is etched in the patterning of the metal oxide layer 135, the oxide semiconductor layer 140 used as a mask is not etched. In the semiconductor device 10A, the oxide semiconductor layer 140 can be used as a mask in the formation of the metal oxide layer 135, so that a photolithography process can be omitted.

[0095] The semiconductor device 10A described with reference to Fig. 9 also provides the same effects as those described above. In addition, in the semiconductor device 10A, the Poly-OS is formed using the metal oxide layer 135 as a buffer layer, so that the crystallinity of the oxide semiconductor layer 140 including the Poly-OS is improved. As a result, the semiconductor device 10A has a higher field-effect mobility.

[0096] <Second embodiment> A semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 10. Note that in the following, descriptions of configurations similar to those described in the first embodiment may be omitted.

[0097] Fig. 10 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to an embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 10.

[0098] The oxide semiconductor layer 140 shown in FIG. 10 includes high resistance regions (the first region A1, the 2-1 region A2-1, the 2-2 region A2-2, the 3-1 region A3-1, and the 3-2 region A3-2), a source region 142, and a drain region 143. The first region A1 is located between the source region 142 and the drain region 143. The 2-1 region A2-1 includes a part of the first edge E1 and is located in the source region 142. The 2-2 region A2-2 includes a part of the first edge E1 and is located in the drain region 143. The 3-1 region A3-1 includes a part of the second edge E2 and is located in the source region 142. The 3-2 region A3-2 includes a part of the second edge E2 and is located in the drain region. In other words, the 2-1 region A2-1 and the 3-1 region A3-1 are surrounded by a source region, and the 2-2 region A2-2 and the 3-2 region A3-2 are surrounded by a drain region.

[0099] The gate electrode 160 overlaps the entire first region A1 and extends in the y-axis direction. A first width W1 of the first region A1 in the x-axis direction is substantially the same as a second width W2 of the gate electrode 160 in the x-axis direction. In this embodiment, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 are provided as the same layer as the gate electrode 160. That is, the gate electrode 160 and the first to fourth metal layers M1 to M4 can be formed collectively in the same process. The first to fourth metal layers M1 to M4 have an island shape. The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 respectively overlap the entirety of region A2-1 of 2-1, the entirety of region A2-2 of 2-2, the entirety of region A3-1 of 3-1, and the entirety of region A3-2 of 3-2.

[0100] In a plan view, the 2-1 region A2-1 and the 3-1 region A3-1 are located between the gate electrode 160 and the source electrode 180. The 2-2 region A2-2 and the 3-2 region A3-2 are located between the gate electrode 160 and the drain electrode 190. The source electrode 180 contacts the source region 142 through a contact hole CH1, and the drain electrode 190 contacts the drain region 143 through a contact hole CH2.

[0101] The first metal layer M1 to the fourth metal layer M4 do not overlap with the gate electrode 160, the source electrode 180, and the drain electrode 190. Therefore, the first metal layer M1 to the fourth metal layer M4 are electrically floating, but are hardly affected by the potential of any of the gate electrode 160, the source electrode 180, and the drain electrode 190.

[0102] 10 can be formed by performing ion implantation using the gate electrode 160 and the first to fourth metal layers M1 to M4 as masks. Note that the first to fourth metal layers M1 to M4 may be removed after the ion implantation.

[0103] In the semiconductor device 10 described with reference to Fig. 10, the high-resistance 2-1 region A2-1 and 2-2 region A2-2 are provided to include the first edge E1, and the high-resistance 3-1 region A3-1 and 3-2 region A3-2 are provided to include the second edge E2. Therefore, a channel region 141 is formed in the center of the first region A1 away from the first edge E1 and the second edge E2, and no current path is formed near the first edge E1 and near the second edge E2. Therefore, the semiconductor device 10 described with reference to Fig. 10 also has the same effect as the first embodiment.

[0104] <Third embodiment> A semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 11. Note that in the following, description of configurations similar to those described in the first or second embodiment may be omitted.

[0105] Fig. 11 is a schematic plan view showing a configuration of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention. For convenience of explanation, the gate electrode 160, the source electrode 180, and the drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 10.

[0106] 11 includes a high-resistance region (first region A1), a source region 142, and a drain region 143. The first region A1 is located between the source region 142 and the drain region 143. In this embodiment, the oxide semiconductor layer 140 does not include the high-resistance second region A2 and third region A3 described in the first embodiment.

[0107] The source electrode 180 overlaps the oxide semiconductor layer 140 at a position approximately midway between the first edge E1 and the second edge E2 in a plan view, and is in contact with the source region 142 through the contact hole CH1. A distance D11 from the first edge E1 to the contact hole CH1 along the y-axis direction is approximately equal to a distance D12 from the second edge E2 to the contact hole CH1 along the y-axis direction. A distance D13 from the first region A1 to the contact hole CH1 along the x-axis direction is smaller than the distance D11 and the distance D12. In one example, the distance D11 and the distance D12 are equal to or greater than twice the distance D13.

[0108] The drain electrode 190 overlaps the oxide semiconductor layer 140 at a position approximately midway between the first edge E1 and the second edge E2 in a plan view, and is in contact with the drain region 143 via the contact hole CH2. A distance D21 from the first edge E1 to the contact hole CH1 along the y-axis direction is approximately equal to a distance D22 from the second edge E2 to the contact hole CH2 along the y-axis direction. A distance D23 from the first region A1 to the contact hole CH2 along the x-axis direction is smaller than the distance D21 and the distance D22. In one example, the distances D21 and D22 are equal to or greater than twice the distance D23.

[0109] In the semiconductor device 10 described with reference to FIG. 11, when a gate voltage equal to or higher than a threshold value is applied to the gate electrode 160, the electric field lines between the source electrode 180 and the drain electrode 190 are concentrated in the central portion of the oxide semiconductor layer 140, while the electric field lines are unlikely to spread to the vicinity of the first edge E1 and the vicinity of the second edge E2. Therefore, the channel region 141 is formed in the central portion of the first region A1 away from the first edge E1 and the second edge E2, and no current path is formed in the vicinity of the first edge E1 and the vicinity of the second edge E2. Therefore, the semiconductor device 10 described with reference to FIG. 11 also has the same effect as the first embodiment.

[0110] <Modification> A modified example of this embodiment will be described with reference to Fig. 12. Note that in the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0111] Fig. 12 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modified embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in Fig. 12.

[0112] In the oxide semiconductor layer 140 shown in FIG. 12, the source electrode 180 and the drain electrode 190 extend in the y-axis direction, and overlap the first edge E1 and the second edge E2. However, the source electrode 180 contacts the source region 142 through a contact hole CH1 formed at a position sufficiently distant from the first edge E1 and the second edge E2, as in the configuration shown in FIG. 12. The drain electrode 190 also contacts the drain region 143 through a contact hole CH2 formed at a position sufficiently distant from the first edge E1 and the second edge E2. Therefore, the channel region 141 is formed in the center of the first region A1 away from the first edge E1 and the second edge E2, and no current path is formed in the vicinity of the first edge E1 and the vicinity of the second edge E2.

[0113] The semiconductor device 10 described with reference to FIG. 12 also provides the same effects as those described above.

[0114] <Fourth embodiment> 13 to 15C, a semiconductor device 10 according to an embodiment of the present invention will be described. Note that, in the following, descriptions of configurations similar to those described in the first and second embodiments may be omitted.

[0115] FIG. 13 is a schematic plan view showing a configuration of an oxide semiconductor layer 140 of a semiconductor device 10 according to an embodiment of the present invention. For convenience of explanation, a gate electrode 160, a source electrode 180, and a drain electrode 190 located above the oxide semiconductor layer 140 are shown by dotted lines in FIG. 13. Also, each of FIG. 14A and FIG. 14B is a schematic cross-sectional view showing a configuration of a semiconductor device 10 according to an embodiment of the present invention. Specifically, FIG. 14A is a cross-sectional view of the semiconductor device 10 taken along line Y3-Y4 in FIG. 13, and FIG. 14B is a cross-sectional view taken along line Y5-Y6 in FIG. 13.

[0116] 13, the oxide semiconductor layer 140 has a change in thickness in the second region A2 including the first edge E1 and the third region A3 including the second edge E2. Specifically, as shown in FIGS. 14A and 14B, the thickness of the second region A2 decreases from the first region A1 toward the first edge E1, and the thickness of the third region A3 decreases from the first region A1 toward the second edge E2. For example, the width of the second region A2 and the width of the third region A3 in the y-axis direction are about 2 μm.

[0117] The source electrode 180 extends along the y-axis direction in a plan view and overlaps with the second region A2, the third region A3, and the source region 142. The source electrode 180 does not contact the second region A2 and the third region A3, and contacts the source region 142 through a contact hole CH1. The drain electrode 190 extends along the y-axis direction in a plan view and overlaps with the second region A2, the third region A3, and the drain region 143. The drain electrode 190 does not contact the second region A2 and the third region A3, and contacts the drain region 143 through a contact hole CH2.

[0118] Here, an example of a method for manufacturing the oxide semiconductor layer 140 shown in FIG. 13 will be described with reference to FIGS. 15A to 15C.

[0119] 15A to 15C are schematic cross-sectional views showing a method for producing the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention.

[0120] First, the oxide semiconductor film 145 is formed on the second insulating layer 130. After that, a resist R2 patterned into a desired shape is formed on the oxide semiconductor film 145. Next, the oxide semiconductor film 145 is etched using the resist R2 as a mask. As a result, an island-shaped oxide semiconductor film 145 is formed.

[0121] By continuing etching (or performing an ashing process), the volume of the resist R2 is reduced, and the region of the oxide semiconductor film 145 near the first edge E1 and the region near the second edge E2 are exposed from the resist R2, and the surface layer of the oxide semiconductor film 145 is removed.

[0122] The etching time of the region near the first edge E1 of the oxide semiconductor film 145 is longer than the etching time of the region overlapping with the edge of the resist R2. Therefore, the film thickness of the region near the first edge E1 is smaller than the film thickness of the region overlapping with the edge of the resist R2. Similarly, the etching time of the region near the second edge E2 of the oxide semiconductor film 145 is longer than the etching time of the region overlapping with the edge of the resist R2. Therefore, the film thickness of the region near the second edge E2 is smaller than the film thickness of the region overlapping with the edge of the resist R2. On the other hand, the film thickness of the center part of the oxide semiconductor film 145 is almost unchanged even after etching because the resist R2 remains overlapping. As a result, the oxide semiconductor film 145 is formed whose film thickness decreases toward the first edge E1 and the second edge E2.

[0123] Then, the oxide semiconductor film 145 having the desired shape is subjected to a heat treatment, whereby the oxide semiconductor film 145 is crystallized, and the oxide semiconductor layer 140 including Poly-OS is formed. When ion implantation is performed using the gate electrode 160 as a mask in the oxide semiconductor layer 140 having such a shape, the impurity element is doped in a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160. Therefore, the impurity element is also doped in the first edge E1 included in the second region A2 and the second edge E2 included in the third region A3. However, the film thickness near the first edge E1 and the film thickness near the second edge E2 are extremely small, and the resistance is not reduced like the source region 142 and the drain region 143. Therefore, no current path is formed near the first edge E1 and the second edge E2. Therefore, the semiconductor device 10 described with reference to FIG. 13 also has the same effect as the first embodiment.

[0124] <Fifth embodiment> A semiconductor device 1 according to one embodiment of the present invention will be described with reference to Fig. 16. Note that in the following, descriptions of configurations similar to those described in the first to fourth embodiments may be omitted.

[0125] FIG. 16 is a schematic cross-sectional view of a semiconductor device 1 according to one embodiment of the present invention.

[0126] The semiconductor device 1 includes a first transistor TR1 and a second transistor TR2 provided on a substrate 100. The first transistor TR1 has a configuration similar to that of the semiconductor device 10 described above, and includes an oxide semiconductor layer 140. The gate electrode 160 of the first transistor TR1 is electrically connected to a gate line. The source electrode 180 of the first transistor TR1 is electrically connected to a source line, a power line, or the like. The drain electrode 190 of the first transistor TR1 is electrically connected to an element electrode 360.

[0127] The second transistor TR2 includes a substrate 100, a base insulating layer 210, a light-shielding layer 220, a first insulating layer 110, a silicon semiconductor layer 240, a gate insulating layer 250, a gate electrode 260, a second insulating layer 130, a source electrode 280, and a drain electrode 290. The base insulating layer 210 is provided on the substrate 100. The light-shielding layer 220 is provided on the base insulating layer 210. The first insulating layer 110 covers the upper surface and end surface of the light-shielding layer 220 and is provided on the base insulating layer 210. The silicon semiconductor layer 240 is provided on the first insulating layer 110. The gate insulating layer 250 covers the upper surface and end surface of the silicon semiconductor layer 240 and is provided on the first insulating layer 110. The gate electrode 260 overlaps the silicon semiconductor layer 240 and is provided on the gate insulating layer 250. The second insulating layer 130 covers the upper surface and end surfaces of the gate electrode 260 and is provided on the gate insulating layer 250. An insulating layer (hereinafter, for convenience of explanation, will be described as "insulating layer 255") formed of the same layer as the gate insulating layer 150 of the first transistor TR1 is provided on the second insulating layer 130. The source electrode 280 and the drain electrode 290 are provided on the insulating layer 255. The source electrode 280 is in contact with the silicon semiconductor layer 240 through a contact hole CH3 that penetrates the gate insulating layer 250, the second insulating layer 130, and the insulating layer 255. The drain electrode 290 is in contact with the silicon semiconductor layer 240 through a contact hole CH4 that penetrates the gate insulating layer 250, the second insulating layer 130, and the insulating layer 255. The source electrode 280 and the drain electrode 190 are electrically connected to the silicon semiconductor layer 240. The gate electrode 260 is electrically connected to the gate line. The source electrode 280 is electrically connected to a source line 310 .

[0128] The base insulating layer 210 of the second transistor TR2 has a similar configuration to the first insulating layer 110 of the first transistor TR1. The light-shielding layer 220 of the second transistor TR2 has a similar configuration to the light-shielding layer 120 of the first transistor TR1. The first insulating layer 110 of the second transistor TR2 has a similar configuration to the second insulating layer 130 of the first transistor TR1.

[0129] The silicon semiconductor layer 240 of the second transistor TR2 may be, but is not limited to, a polycrystalline silicon semiconductor, but may be any other silicon-based semiconductor.

[0130] The gate insulating layer 250 of the second transistor TR2 has a similar configuration to the gate insulating layer 150 of the first transistor TR1. In the first transistor TR1, an insulating layer formed of the same layer as the gate insulating layer 250 is located below the light-shielding layer 120 and has a similar function to the first insulating layer 110.

[0131] The gate electrode 260 of the second transistor TR2 has a structure similar to that of the gate electrode 160 of the first transistor TR1. The gate electrode 260 may be electrically connected to the light-shielding layer 220.

[0132] The source electrode 280 and the drain electrode 290 of the second transistor TR2 have the same configurations as the source electrode 180 and the drain electrode 190 of the first transistor TR1, respectively.

[0133] In the following, components included in the semiconductor device 1 other than the above-mentioned components will be described.

[0134] The connection electrode 340 is disposed on the first planarization layer 330 and is covered by the second planarization layer 350. The connection electrode 340 is in contact with the drain electrode 190 of the first transistor TR1 through a contact hole CH5 that penetrates the protective insulating layer 320 and the first planarization layer 330. The connection electrode 340 is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but may also be a metal layer.

[0135] The element electrode 360 ​​is disposed on the second planarization layer 350 and is in contact with the connection electrode 340 through a contact hole CH6 that penetrates the second planarization layer 350. The element electrode 360 ​​is a pixel electrode, a lower electrode, an anode, or a cathode of various electronic devices. The element electrode 360 ​​is, for example, a transparent electrode formed of a transparent conductive material such as ITO or IZO. The element electrode 360 ​​may be a metal electrode formed of a metal material such as silver or aluminum. The element electrode 360 ​​may have a laminated structure of a transparent electrode and a metal electrode. For example, the element electrode 360 ​​may have a laminated structure in which a transparent electrode, a metal electrode, and a transparent electrode are laminated in this order, or may have a laminated structure of three or more layers.

[0136] The protective insulating layer 320 can cover and protect the first transistor TR1 and the second transistor TR2. The protective insulating layer 320 can be made of an oxide or a nitride similar to that of the first insulating layer 110. The protective insulating layer 320 may have a single layer structure or a stacked layer structure.

[0137] The first planarization layer 330 and the second planarization layer may be made of a transparent resin such as polyimide.

[0138] The first transistor TR1 included in the semiconductor device 1 according to this embodiment has a configuration similar to that of the semiconductor device 10 described in the first to fourth embodiments. Therefore, deterioration of the first edge portion E1 and the second edge portion E2 of the oxide semiconductor layer 140 of the first transistor TR1 is suppressed, and the semiconductor device 1 can have high reliability.

[0139] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0140] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0141] 1, 10, 10A: semiconductor device, 100: substrate, 110: first insulating layer, 120: light shielding layer, 130: second insulating layer, 135: metal oxide layer, 140: oxide semiconductor layer, 141: channel region, 142: source region, 143: drain region, 145: oxide semiconductor film, 150: gate insulating layer, 160: gate electrode, 170: third insulating layer, 180: source electrode, 190: drain electrode, 210: base insulating layer, 220: light shielding layer, 240: silicon semiconductor layer, 250: gate insulating layer, 255: insulating layer, 260: gate electrode, 280: source electrode, 290: drain electrode, 310: source line, 320: protective insulating layer, 330: first planarization layer, 340: connection electrode, 350: second planarization layer, 360: element electrode, A1: first region, A2: second region, A2-1: 2-1 region, A2-2: 2-2 region, A3: third region, A3-1: 3-1 region, A3-2: 3-2 region, CH1, CH2, CH3, CH4, CH5, CH6: contact holes, E1: first edge, E2: second edge, M1: first metal layer, M2: second metal layer, M3: third metal layer, M4: fourth metal layer, R1, R2: resist, TR1: first transistor, TR2: second transistor

Claims

1. A gate electrode; an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on the oxide semiconductor layer; a drain electrode on the oxide semiconductor layer; The oxide semiconductor layer is a source region containing an impurity element and electrically connected to the source electrode; a drain region containing the impurity element and electrically connected to the drain electrode; a channel region between the source region and the drain region; a first region adjacent to the channel region, the first region including a first edge extending along a first direction from the source region toward the drain region; the first region has a higher electrical resistivity than each of the source region and the drain region; The semiconductor device, wherein an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

2. the gate electrode extends in a second direction intersecting the first direction; 2. The semiconductor device according to claim 1, wherein a width of the gate electrode in the first direction is larger than a width of the channel region in the first direction.

3. The semiconductor device according to claim 1 , wherein said gate electrode overlaps with said first region entirely.

4. the gate electrode includes a first portion overlapping the channel region in a plan view; The semiconductor device according to claim 1 , wherein a first width of said first portion in said first direction is substantially the same as a width of said channel region in said first direction.

5. the gate electrode includes a second portion overlapping the first region in a plan view; The semiconductor device according to claim 4 , wherein a second width of said second portion in said first direction is greater than said first width.

6. the gate electrode includes a second portion overlapping the first region in a plan view; The semiconductor device according to claim 4 , wherein a second width of said second portion in said first direction is smaller than said first width.

7. 2. The semiconductor device according to claim 1, wherein a thickness of said first region decreases from said channel region toward said first edge portion.

8. the source electrode is electrically connected to the source region through a first contact hole provided in the gate insulating layer; 2. The semiconductor device according to claim 1, wherein said drain electrode is electrically connected to said drain region through a second contact hole provided in said gate insulating layer.

9. the oxide semiconductor layer further includes a second region adjacent to the channel region, the second region including a second edge portion opposite the first edge portion; 2. The semiconductor device according to claim 1, wherein said second region has a higher electrical conductivity than each of said source region and said drain region.

10. The semiconductor device according to claim 1 , wherein said first region does not contain said impurity element.

11. a gate electrode extending in a first direction; an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer including a first edge portion and a second edge portion extending in a second direction intersecting the first direction; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on the oxide semiconductor layer; a drain electrode on the oxide semiconductor layer; The oxide semiconductor layer is a first region overlapping the gate electrode in a plan view; a source region adjacent to the first region, containing an impurity element, and electrically connected to the source electrode via a first contact hole; a drain region adjacent to the first region, containing the impurity element, and electrically connected to the drain electrode via a second contact hole; a second region including a portion of the first edge surrounded by the source region; a third region including a portion of the second edge surrounded by the source region; a fourth region including a portion of the first edge and surrounded by the drain region; a fifth region including a portion of the second edge surrounded by the drain region; each of the first region, the second region, the third region, the fourth region, and the fifth region has a higher electrical resistivity than each of the source region and the drain region; The semiconductor device, wherein an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

12. 12. The semiconductor device according to claim 11, wherein, in the plan view, each of the second region, the third region, the fourth region, and the fifth region overlaps with a metal layer formed in the same layer as the gate electrode.

13. 12. The semiconductor device according to claim 11, wherein each of said first region, said second region, said third region, said fourth region, and said fifth region does not contain said impurity element.

14. a gate electrode extending in a first direction; an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer including a first edge portion and a second edge portion extending in a second direction intersecting the first direction; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on the oxide semiconductor layer; a drain electrode on the oxide semiconductor layer; The oxide semiconductor layer is a first region overlapping the gate electrode in a plan view; a source region adjacent to the first region, containing an impurity element, and electrically connected to the source electrode via a first contact hole; a drain region adjacent to the first region, containing the impurity element, and electrically connected to the drain electrode via a second contact hole; the first region has a higher electrical resistivity than each of the source region and the drain region; In the plan view, a first distance from the first edge portion to the first contact hole along the first direction is greater than a second distance from the first region to the first contact hole along the second direction; The semiconductor device, wherein an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

15. The semiconductor device according to claim 14 , wherein the first region does not contain the impurity element.

16. The semiconductor device according to claim 1 , wherein the etching solution contains nitric acid and acetic acid.

17. 16 . The semiconductor device according to claim 1 , wherein an etching rate of the oxide semiconductor layer when the oxide semiconductor layer is etched with a 0.5% hydrofluoric acid solution at room temperature is less than 5 nm / min.

18. the oxide semiconductor layer is formed by performing a heat treatment on an oxide semiconductor film having an amorphous structure; 16 . The semiconductor device according to claim 1 , wherein an etching rate when the oxide semiconductor film is etched using the etching solution at 40° C. is 100 nm / min or more.

19. the oxide semiconductor layer contains a plurality of metal elements, one of the metal elements is indium; 16. The semiconductor device according to claim 1, wherein an atomic ratio of said indium to said plurality of metal elements is 50% or more.

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