PFM control circuit and step-up switching regulator

Abstract

To provide a PFM control circuit that can reduce possibility that overcurrent occurs.SOLUTION: A PFM control circuit 15 includes a drive output 37b that outputs drive signals SDRV for driving switching elements 23, a first comparison circuit 31 that compares first monitor signals related to output voltage on the secondary side of a switching regulator 17 with a first reference value to generate first comparison signals, a second comparison circuit 43 that compares second monitor signals related to current flowing through the switching elements 23 with a second reference value to generate second comparison signals, a determination circuit 47 that is configured to determine whether or not to expand one of the HIGH width and the LOW width of clock signals CLK based on the first comparison signals and the second comparison signals and generate expansion signals SXTN that indicate the result of the determination, a pulse generation circuit 45 that includes an expansion circuit 49 that generates a pulse signal SPLS from the clock signals CLK in response to the expansion signals SXTN, and a drive circuit 53 that provides the drive signals SDRV to the drive output 37b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a PFM control circuit and a step-up switching regulator. [Background technology]

[0002] Patent Document 1 discloses a step-up switching regulator that can suppress ripples in the output voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-180087 A Summary of the Invention [Problem to be solved by the invention]

[0004] The PFM (Pulse Frequency Modulation) method is used to control external devices. The PFM method controls the frequency of clock transitions in a clock signal.

[0005] The PFM (Pulse Frequency Modulation) method can be adopted to control, for example, a switching regulator. The switching regulator is controlled by a control circuit. The switching regulator is adopted, for example, in a display panel driver, and the control circuit is built into the integrated circuit of the display panel driver.

[0006] The duty of the drive signal can be set according to the worst conditions assumed in, for example, the fluctuation of the usage environment and the manufacturing variation. Therefore, under normal and favorable usage conditions, the switching regulator may be in a state in which its circuit capacity is excessive. For example, an overcurrent may occur, which may cause a large increase in the secondary voltage, which may cause the voltage ripple of the secondary output to deteriorate.

[0007] An object of the present invention is to provide a PFM control circuit capable of reducing the possibility of an overcurrent occurring, and a step-up switching regulator including this PFM control circuit. [Means for solving the problem]

[0008] A PFM control circuit according to a first aspect of the present invention includes a drive output configured to output a drive signal for driving a switch of a switching regulator, a first input configured to receive a first monitor signal related to an output voltage on a secondary side of the switching regulator, a second input configured to receive a second monitor signal related to an element current flowing through the switch, a first comparator configured to compare the first monitor signal with a first reference value related to the output voltage on the secondary side to generate a first comparison signal, a second comparator configured to compare the second monitor signal with a second reference value related to the element current to generate a second comparison signal, and a clock signal. a pulse generation circuit for a clock signal processing device, the pulse generation circuit including: a determination circuit configured to determine whether to expand a width of the clock signal and to generate an expansion signal indicative of a result of the determination; and an expansion circuit configured to generate a pulse signal from the clock signal, the pulse signal being either expanded in width or maintained at the width, in response to the expansion signal; and a drive circuit having an input connected to the pulse generation circuit and an output connected to the drive output, the drive circuit providing the drive signal to the output, wherein the width of the clock signal is either a high width or a low width of the clock signal, and the determination is made based on an order of transitions of the second comparison signal and the first comparison signal.

[0009] A step-up switching regulator according to a second aspect of the present invention includes the PFM control circuit described in the first aspect, a chopper circuit including an inductor and a diode, a switch connected to the inductor and the diode of the chopper circuit and configured to be driven by the drive signal from the drive output, a voltage detection circuit that detects an output voltage of the output of the chopper circuit and is connected to the first input, and a current sensor that detects a current flowing through the switch and is connected to the second input. Effect of the Invention

[0010] According to the above aspects, it is possible to provide a PFM control circuit capable of reducing the possibility of occurrence of an overcurrent, and a step-up switching regulator including this PFM control circuit. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram that illustrates a schematic diagram of an apparatus including a PFM control circuit according to an embodiment of the present invention and an external circuit controlled by the PFM control circuit. [Diagram 2] FIG. 2 is a diagram illustrating a schematic configuration of a PFM control circuit according to the present embodiment. [Diagram 3] FIG. 3 is a diagram illustrating a schematic configuration of a main part of the step-up switching regulator according to the present embodiment. [Figure 4] FIG. 4 is a diagram showing waveforms of main nodes of the boost switching regulator shown in FIG. [Diagram 5] FIG. 5 is a diagram showing waveforms of main nodes of the PFM control circuit shown in FIG. [Figure 6] FIG. 6 is a diagram illustrating a schematic configuration of a main part of an exemplary determination circuit of the PFM control circuit according to the present embodiment. [Figure 7] FIG. 7 is a diagram illustrating a schematic configuration of the decompression circuit according to the present embodiment. [Figure 8]FIG. 8 is a diagram showing a waveform at the output node of the delay circuit when the expansion signal indicates "with delay." [Figure 9] FIG. 9 is a diagram showing a waveform at the output node of the delay circuit when the expansion signal indicates "no delay." [Figure 10] FIG. 10 is a diagram illustrating a schematic configuration of a determination circuit according to the present embodiment. [Figure 11] FIG. 11 is a diagram illustrating a schematic configuration of a determination circuit according to the present embodiment. [Figure 12] FIG. 12 is a diagram illustrating a delay circuit according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. In the following description, the same parts are designated by the same reference numerals and duplicated description will be omitted.

[0013] Fig. 1 is a diagram showing an apparatus including an external circuit controlled by a PFM (Pulse Frequency Modulation) method according to the present embodiment and a PFM control circuit for the PFM method. Fig. 2 is a diagram showing a PFM control circuit according to the present embodiment. The PFM method controls the frequency of clock transitions in a fixed-cycle clock.

[0014] 1, device 11 includes external circuitry 13 and PFM control circuitry 15. Exemplary external circuitry 13 includes external components of a boost switching regulator 17.

[0015] An exemplary external circuit 13 includes a boost circuit of a switching regulator 17 , and the output voltage of the external circuit 13 may be the output voltage of the secondary side of the switching regulator 17 .

[0016] The PFM control circuit 15 and the switching regulator 17 will be described with reference to FIG.

[0017] The switching regulator 17 includes a PFM control circuit 15, a chopper circuit 21, a switch such as a switching element 23, a voltage detection circuit 25, and a current sensor 27. In Fig. 1, an exemplary switching element 23 is depicted as a circuit symbol of a field effect transistor, and the field effect transistor MN0 has a source (S), a drain (D), and a gate (G).

[0018] The chopper circuit 21 includes an inductor 31 and a diode 33 connected in series, and a switching element 23. A shared node NDS2 of the inductor 31 and the diode 33 is connected to the switching element 23. The inductor 31 is connected to a primary-side power supply input 35b, and generates electromagnetic induction in response to a switching operation of a switch (e.g., the switching element 23). In response to a boost in the shared node NDS2 due to electromagnetic induction, a forward voltage is applied to the diode 33. The application of a forward voltage to the diode 33 supplies a current to a secondary-side power supply output 35c. A capacitor 29 is connected to the output of the chopper circuit 21.

[0019] The voltage detection circuit 25 detects the output voltage of the chopper circuit 21 and generates a first monitor signal SMON1. The voltage detection circuit 25 may include, for example, a voltage divider circuit. The current sensor 27 detects the element current flowing through the switching element 23 and generates a second monitor signal SMON2. The current sensor 27 is connected between the switching element 23 and the power supply line 10 and converts the current flowing through the switching element 23 into a voltage signal.

[0020] The PFM control circuit 15 can be configured, for example, as a semiconductor device 20, which can include a number of electrodes (10b, 10c, 10d), such as pad electrodes, to enable electrical connection between the semiconductor device 20 and an external circuit 13.

[0021] The PFM control circuit 15 is configured to provide a drive signal for PFM control to the external circuit 13 and to receive two types of monitor signals from the external circuit 13. The drive signal from the PFM control circuit 15 is provided to a control input (e.g., gate) of the switching element 23 via an electrode (10b). On the other hand, a voltage divider circuit of the voltage detection circuit 25 is connected to an electrode (10c), and more specifically, the electrode (10c) is connected to a shared node NDS3 of two resistors of the voltage divider circuit. Also, a shared node NDS1 between a first current terminal (e.g., source) of the switching element 23 and the current sensor 27 is connected to an electrode (10d). A second current terminal (e.g., drain) of the switching element 23 is connected to a shared node NDS2.

[0022] In the following description, the exemplary PFM control circuit 15 controls the switching regulator 17 by a PFM control method. However, the PFM control circuit 15 is not limited to the application of the PFM control of the switching regulator 17.

[0023] 2, the PFM control circuit 15 has a drive output 37b, a first input 37c, and a second input 37d. The drive output 37b is configured to output a drive signal SDRV that drives the switching element 23 of the switching regulator 17. The first input 37c is configured to receive a first monitor signal SMON1 associated with an output voltage on the secondary side of the switching regulator 17. The second input 37d is configured to receive a second monitor signal SMON2 associated with an element current flowing through the switching element 23.

[0024] The PFM control circuit 15 also includes a first comparison circuit 41 and a second comparison circuit 43. The first comparison circuit 41 is connected to the first input 37c and receives a first monitor signal SMON1 from the first input 37c. The exemplary first comparison circuit 41 includes a first comparator 41b and a first comparison voltage generation circuit 41c that generates a first reference value Vref1, and the first comparator 41b is configured to compare the first monitor signal SMON1 with the first reference value Vref1 to generate a first comparison signal SCMP1. The first reference value Vref1 is associated with the output voltage on the secondary side of the switching regulator 17. Specifically, the first comparison circuit 41 detects that the output voltage on the secondary side of the switching regulator is a voltage that exceeds the allowable fluctuation range.

[0025] The second comparison circuit 43 is connected to the second input 37d and receives the second monitor signal SMON2 from the second input 37d. The exemplary second comparison circuit 43 includes a second comparator 43b and a second comparison voltage generation circuit 43c that generates a second reference value Vref2, and the second comparator 43b is configured to compare the second monitor signal SMON2 with the second reference value Vref2 to generate the second comparison signal SCMP2. The second reference value Vref2 is associated with the element current flowing through the switching element 23. Specifically, the second comparison circuit 43 monitors, for example, the current flowing through the switching element 23 and detects that this current has a current value that exceeds the allowable fluctuation range.

[0026] The PFM control circuit 15 includes a pulse generating circuit 45. The pulse generating circuit 45 receives a clock signal CLK and several signals SATH (others include, for example, a duty setting signal).

[0027] The pulse generating circuit 45 includes a determination circuit 47 and an extension circuit 49 .

[0028] The decision circuit 47 is configured to determine whether or not to expand the width of the clock signal CLK based on the first comparison signal SCMP1 and the second comparison signal SCMP2. The width of the clock signal CLK is either the high width (i.e., the width of the high period of the clock signal CLK) or the low width (i.e., the width of the low period of the clock signal CLK) of the clock signal CLK. The exemplary decision circuit 47 determines whether or not to expand the width based on the order of transitions of the first comparison signal SCMP1 and the second comparison signal SCMP2. The decision circuit 47 is also configured to generate an expansion signal SXTN indicating the result of the decision. The expansion circuit 49 is configured to generate a pulse signal SPLS from the clock signal CLK in response to the expansion signal SXTN.

[0029] Specifically, when the expansion signal SXTN indicates "expansion", the expansion circuit 49 generates a pulse signal SPLS in which either the high width or the low width is longer and the other width is shorter based on the transition of the clock signal CLK. When the expansion signal SXTN indicates "no expansion", the expansion circuit 49 generates a signal in which both the high width and the low width of the clock signal CLK are maintained, that is, a pulse signal SPLS that is substantially the same as the clock signal CLK. Therefore, the pulse signal SPLS is a signal in which either the high width or the low width of the clock signal CLK is expanded, or a signal in which both the high width and the low width of the clock signal CLK are maintained.

[0030] In general, the pulse generating circuit 45 detects that a transition of the first comparison signal SCMP1 occurs after a transition of the second comparison signal SCMP2. Specifically, this detection is performed by the determination circuit 47, and in response to the detection by the determination circuit 47, the expansion circuit 49 generates the expansion signal SXTN. However, the function of the pulse generating circuit 45 is not limited to the above operation, and for example, the pulse generating circuit 45 can detect that a transition of the second comparison signal SCMP2 occurs after a transition of the first comparison signal SCMP1.

[0031] The PFM control circuit 15 includes a drive circuit 53, which generates a drive signal SDRV from the pulse signal SPLS based on the first comparison signal SCMP1 and the second comparison signal SCMP2. The drive circuit 53 has an output 53b, a first input 53c, a second input 53d, and a pulse input 53f, and provides the drive signal SDRV to the output 53b. In the drive circuit 53, the output 53b is connected to the drive output 37b. The first input 53c receives the first comparison signal SCMP1. The second input 53d receives the second comparison signal SCMP2. The pulse input 53f receives the pulse signal SPLS.

[0032] As already described, the determination circuit 47 and the drive circuit 53 operate in response to the first comparison signal SCMP1 and the second comparison signal SCMP2. Specifically, the first comparison signal SCMP1 and the second comparison signal SCMP2 indicate that the switching regulator 17 is in the first state and the second state, respectively. The first state indicates that the output voltage (secondary side) of the switching regulator 17 exceeds an allowable fluctuation range (for example, an upper limit or lower limit of a target value). The second state indicates that the current flowing through the switching element 23 is greater than the allowable fluctuation range (the current flowing through the diode 33 is small) and the non-conducting period of the switching element 23 is insufficient.

[0033] The exemplary decision circuit 47 sets the expansion signal SXTN to width expansion in response to detecting a transition of the first comparison signal SCMP1 to the first state within a first period from a transition of the second comparison signal SCMP2 indicating the second state of the switching regulator 17.

[0034] The exemplary drive circuit 53 generates a drive signal SDRV with an expanded LOW width from a pulse signal SPLS with either the expanded HIGH width or the expanded LOW width. This drive signal SDRV lengthens the non-conducting period of the switching element 23 compared to the previous non-conducting period. During the non-conducting period, a high voltage is maintained at the shared node NDS2 of the inductor 31 and the diode 33, and the charge of the shared node NDS2 is provided to the power output 35c on the secondary side of the switching regulator 17 through the diode 33. This operation acts to increase the boost voltage of the switching regulator 17.

[0035] The drive circuit 53 includes a drive control circuit 51 and an output circuit 55, and the drive control circuit 51 has a first input 51b for receiving a first comparison signal SCMP1, a pulse input 51c for receiving a pulse signal SPLS, a second input 51d for receiving a second comparison signal SCMP2, and a control output 51f.

[0036] The output circuit 55 has a control input 55 b for receiving the control signal SENB from the control output 51 f, a pulse input 55 c for receiving the pulse signal SPLS, and an output 55 d connected to the output 53 b of the drive circuit 53 .

[0037] The drive control circuit 51 operates to prevent the output circuit 55 from providing the drive signal SDRV to the drive output 37b when the second comparison signal SCMP2 indicates that the switching regulator 17 is in the second state.

[0038] Specifically, when the second comparison signal SCMP2 indicates that the current flowing through the switching element 23 is a large value exceeding the allowable fluctuation range, the drive control circuit 51 generates a signal that does not permit the output of the drive signal SDRV. In other words, the drive circuit 53 does not operate the switching element 23 in a non-conducting state.

[0039] When the second comparison signal SCMP2 does not indicate that the switching regulator 17 is in the second state, and when the first comparison signal SCMP1 indicates that the switching regulator 17 is in the first state, the operation of the drive control circuit 51 is as follows. The drive control circuit 51 operates to prevent the output circuit 55 from providing the drive signal SDRV to the drive output 37b. That is, the drive circuit 53 does not operate the switching element 23 in a non-conducting state.

[0040] Specifically, when the current of the switching element 23 does not exceed the allowable fluctuation range, and the first comparison signal SCMP1 indicates that the secondary output voltage of the switching regulator 17 exceeds the allowable fluctuation range, the operation of the drive control circuit 51 is as follows: The drive control circuit 51 operates to generate a signal that does not permit the output of the drive signal SDRV.

[0041] When the second comparison signal SCMP2 does not indicate that the switching regulator 17 is in the second state, and when the first comparison signal SCMP1 does not indicate that the switching regulator 17 is in the first state, the operation of the drive control circuit 51 is as follows. The drive control circuit 51 operates so that the output circuit 55 provides the drive signal SDRV to the drive output 37b. That is, the drive circuit 53 operates the switching element 23.

[0042] Specifically, when the current of the switching element 23 does not exceed the allowable fluctuation range, and the first comparison signal SCMP1 indicates that the output voltage on the secondary side of the switching regulator 17 does not exceed the allowable fluctuation range, the operation of the drive control circuit 51 is as follows: The drive control circuit 51 operates to generate a signal that permits the output of the drive signal SDRV.

[0043] The decision circuit 47 may include a flip-flop circuit 57 configured to specify whether or not to perform width expansion in the expansion circuit 49. The decision circuit 47 is configured to set the flip-flop circuit 57 to perform "width expansion" (e.g., a flag) in response to the first comparison signal SCMP1 indicating that the switching regulator 17 is in a first state within a first period. The first period is defined based on a transition of the second comparison signal SCMP2 indicating the second state. In response to "width expansion" being set in the flip-flop circuit 57, the expansion circuit 49 performs the expansion operation.

[0044] When the determination circuit 47 detects the following state, it determines that the accumulation of charge in the chopper circuit 21 is large, and generates the expansion signal SXTN. That is, it detects, based on the second comparison signal SCMP2, that the current flowing through the switching element 23 is large and exceeds the allowable fluctuation range (second state). Then, during the following first period, it detects, based on the first comparison signal SCMP1, that the output voltage on the secondary side of the switching regulator 17 is large and exceeds the allowable fluctuation range (first state).

[0045] Specifically, the flip-flop circuit 57 may include an RS flip-flop circuit. The decision circuit 47 generates the extension signal SXTN in response to receiving a set signal to a set input of the RS flip-flop circuit. The decision circuit 47 stops generating the extension signal SXTN in response to receiving a reset signal to a reset input of the RS flip-flop circuit (57).

[0046] The exemplary decision circuit 47 may include a first flip-flop circuit 59 , one or more second flip-flop circuits 61 , and a third flip-flop circuit 63 .

[0047] The first flip-flop circuit 59, the second flip-flop circuit 61, and the third flip-flop circuit 63 are connected in series. The first flip-flop circuit 59 operates in response to a transition of the second comparison signal SCMP2. The second flip-flop circuit 61 and the third flip-flop circuit 63 operate in response to the pulse signal SPLS (or the clock signal CLK). The total number of stages of the second flip-flop circuit 61 and the third flip-flop circuit 63 is associated with the length of the first period.

[0048] When the second comparison signal SCMP2 transitions to indicate that the switching regulator 17 is in the second state, the first flip-flop circuit 59 captures a first logic value (e.g., “H”) from the signal source 65. The second flip-flop circuit 61 and the third flip-flop circuit 63 operate in response to the pulse signal SPLS (or the clock signal CLK) to transfer the first logic value from the first flip-flop circuit 59.

[0049] Due to the transition of the second comparison signal SCMP2, a first logic value (e.g., “H”) appears at the Q output of the first flip-flop circuit 59. Due to the first transfer, the first logic value (e.g., “H”) appears at the Q output of the second flip-flop circuit 61. Due to the second transfer, the first logic value (e.g., “H”) appears at the Q output of the third flip-flop circuit 63.

[0050] The output of the third flip-flop circuit 63 (specifically, the Q-bar output) is connected to the resets of the first flip-flop circuit 59, the second flip-flop circuit 61, and the third flip-flop circuit 63. The result of the transfer is that in response to the third flip-flop circuit 63 receiving the first logic value, the third flip-flop circuit 63 resets the first flip-flop circuit 59, the second flip-flop circuit 61, and the third flip-flop circuit 63.

[0051] The series connection of a first flip-flop circuit 59, a second flip-flop circuit 61 and a third flip-flop circuit 63 has an output at a shared node NOUT of the Q output of the first flip-flop circuit 59 and the D input of the second flip-flop circuit 61.

[0052] The decision circuit 47 may include a logic gate 67, which may include, for example, an OR gate, an AND gate, or a combination thereof. The logic gate 67 has a first input 67b for receiving the period setting signal ST1 from the shared node NOUT, a second input 67c for receiving the first comparison signal SCMP1, and an output 67d connected to a set input of the RS flip-flop circuit (57). When the period setting signal ST1 is, for example, a first logic value (for example, "H"), the logic gate 67 generates, at the output 67d, the logic value of the signal received at the second input 67c. Specifically, the logic gate 67 generates, at the output 67d, the value of the first comparison signal SCMP1 during a period (for example, a first period) during which the first flip-flop circuit 59 provides the first logic value to the output. Thus, the RS flip-flop circuit (57) is set in response to the first comparison signal SCMP1 indicating that the switching regulator 17 is in the first state. The RS flip-flop circuit 57 is reset by a signal at its reset input. For example, the RS flip-flop circuit 57 can be reset by the system reset signal SRSY.

[0053] The pulse generating circuit 45 may further include a monitoring circuit 69 in addition to the determination circuit 47 and the stretching circuit 49. The monitoring circuit 69 monitors whether the first comparison signal SCMP1 has changed. This monitoring is performed continuously within a second period (longer than the first period) after the RS flip-flop circuit (57) is set. When the first comparison signal SCMP1 does not change within the second period, the monitoring circuit 69 generates a reset signal RST1 that resets the RS flip-flop circuit (57). If the first comparison signal SCMP1 does not indicate that the output voltage Vout of the secondary power output 35c of the switching regulator 17 has exceeded the allowable fluctuation range during the long period indicated by the second period, the monitoring circuit 69 initializes the "width stretch" setting (e.g., a flag) of the PFM control circuit 15.

[0054] The monitoring can be done, for example, by using a counter circuit.

[0055] The exemplary monitoring circuit 69 (69b) may include a counter circuit 71 (71b), a detection circuit 73, and a reset circuit 75. The counter circuit 71b may be configured to receive a pulse signal SPLS (or a clock signal CLK) at a clock input 69f and count a count number associated with a second period. The detection circuit 73 may be configured to detect an overflow or underflow of the counter circuit 71b and generate a detection signal SDET1. The reset circuit 75 generates a reset signal SRST1 at a reset output 69g in response to the detection signal SDET1 from the detection circuit 73.

[0056] Alternatively, the monitoring circuit 69 (69c) may include a counter circuit 71 (71c), a comparison circuit 79, and a reset circuit 75. The counter circuit 71c may be configured to receive the pulse signal SPLS (or the clock signal CLK) at a clock input 69f and count it. The comparison circuit 79 may be configured to receive a decision value VL2 associated with the second period and compare the decision value VL2 with the count value of the counter circuit to generate a comparison signal SDET2. The reset circuit 75 generates a reset signal SRST1 at a reset output 69g in response to the comparison signal SDET2 from the comparison circuit 79.

[0057] The monitoring circuit 69 (69b, 69c) further includes an initialization circuit 77 configured to initialize the counter circuit 71b and resume the operation of the counter circuit 71b in response to detecting a change in the first comparison signal SCMP1 received at the first input 69h. The initialization circuit 77 is also configured to generate a reset signal SRST1, initialize the counter circuit 71b, and resume the operation of the counter circuit 71b.

[0058] The monitoring circuit 69 (69b, 69c) can receive a system reset signal SRSY.

[0059] The PFM control circuit 15 may include a logic gate 81 (eg, a logical OR gate) that receives the system reset signal SRSY and the reset signal SRST 1 from the reset circuit 75 .

[0060] In the PFM control circuit 15, the expansion circuit 49 includes a delay circuit 83 having a delay time associated with the “width expansion.” The delay circuit 83 is configured to generate a delay signal SDLY from the clock signal CLK.

[0061] The stretching circuit 49 may include a pulse generator 85 that receives the clock signal CLK and several other signals SATH (among others, for example, a duty setting signal). The pulse generator 85 provides the clock signal CLK to a clock input 83b of the delay circuit 83 and to a clock input 87b of the first logic gate 87.

[0062] A switching logic gate 89 is connected between a delay output 83c of the delay circuit 83 and a delay input 87c of the first logic gate 87. A delay output 89b of the switching logic gate 89 is connected to the delay input 87c of the first logic gate 87. A delay input 89c of the switching logic gate 89 is connected to the delay output 83c of the delay circuit 83. A control input 89d of the switching logic gate 89 receives the extension signal SXTN. The switching logic gate 89 can switch between enabling and disabling the delay of the delay circuit 83 in the pulse signal SPLS in response to the extension signal SXTN.

[0063] When the stretch signal SXTN indicates that the delay of the delay circuit 83 is valid, the first logic gate 87 receives the delay of the delay circuit 83 at a delay input 87c of the first logic gate 87 and generates at an output 87d a pulse signal SPLS of stretched width.

[0064] When the stretch signal SXTN indicates that the delay of the delay circuit 83 is invalid, the first logic gate 87 receives the delay of the delay circuit 83 at its delay input 87c and generates at its output 87d a pulse signal SPLS of the original width that has not been stretched.

[0065] In the exemplary PFM control circuit 15, the pulse generating circuit 45 can be configured to change the delay time of the delay circuit 83 in response to the number of transitions of at least one of the first comparison signal SCMP1 and the second comparison signal SCMP2. The number of transitions can be counted, for example, by the counter circuit 86. Here, the transition indicates either a transition from a logical value "H" to "L" or a transition from a logical value "L" to "H".

[0066] The exemplary delay circuit 83 may include a reference delay 82 b corresponding to a base portion of the delay time of the delay circuit 83 , and one or more delays 82 c corresponding to changes in the delay time of the delay circuit 83 .

[0067] The exemplary expander circuit 49 may include a delay change circuit 84 that may change the number of stages that connect the delays 82c to the reference delays 82b. The delay change circuit 84 may include a switch SW configured to enable or disable the delay in each of the delays 82c. Each of the exemplary delays 82c may have a switch SW connected between its input and output, and the delay change circuit 84 may generate a SW control signal SCSW that individually controls the opening and closing of each switch SW.

[0068] The delay change circuit 84 receives an initial value indicating an initial delay value, and can set the number of stages to which delay devices 82c are connected in the delay circuit 83 in response to this initial value.

[0069] In the pulse generating circuit 45, the exemplary counter circuit 86 may include at least one of a first counter circuit 86b, a second counter circuit 86c, and a third counter circuit 86d. The first counter circuit 86b counts the number of transitions of the first comparison signal SCMP1. The second counter circuit 86c counts the number of transitions of the second comparison signal SCMP2. The third counter circuit 86d counts the number of transitions of the first comparison signal SCMP1 as one of increments and decrements (e.g., increments) and counts the number of transitions of the second comparison signal SCMP2 as the other of increments and decrements (e.g., decrements). The delay change circuit 84 changes the number of connection stages of the delay devices 82c of the delay circuit 83 according to the output value of any one of these counter circuits.

[0070] The first counter circuit 86b may be configured to either increase or decrease the count value in response to a transition of the first comparison signal SCMP1, and to generate a change signal indicative of the change in the count value.

[0071] The second counter circuit 86c may be configured to either increment or decrement the count value in response to a transition of the second comparison signal SCMP2, and to generate a change signal indicative of the change in the count value.

[0072] The third counter circuit 86d may operate as follows: The third counter circuit 86d may be configured to one of increment and decrement a count value in response to a transition of the first comparison signal SCMP1. The third counter circuit 86d may be configured to the other of increment and decrement a count value in response to a transition of the second comparison signal SCMP2. The exemplary third counter circuit 86d may include an increment counter and a decrement counter and may be configured to generate a change signal indicative of a difference between the counters.

[0073] The use of these increments and / or decrements can be performed by a counter control circuit 88 of the pulse generating circuit 45. The counter control circuit 88 can also receive a counter setting signal VLC that sets the initial values ​​of the individual counter circuits.

[0074] Exemplary width expansion is performed in the PFM control circuit 15 to shorten the conduction period of the switching element 23 during the initial stage of PFM control, while after the initial stage of PFM control, the conduction period is both shortened and extended to stabilize the voltage of the secondary power output 35c.

[0075] FIG. 3 is a diagram showing a schematic diagram of a main part of a boost switching regulator according to the present embodiment. FIG. 4 is a diagram showing waveforms of main nodes of the boost switching regulator shown in FIG. 2 and FIG. 3. FIG. 5 is a diagram showing waveforms of main nodes of the boost switching regulator shown in FIG. 3. FIG. 6 is a diagram showing a schematic diagram of main parts of an exemplary determination circuit of a PFM control circuit according to the present embodiment. In FIG. 3 and FIG. 6, reference symbols in FIG. 1 and FIG. 2 are used where possible, and redundant description is omitted.

[0076] The operation of the PFM control circuit 15 will be described with reference to FIGS.

[0077] The PFM control circuit 15 operates in response to a clock signal CLK. As shown in Fig. 4 and Fig. 5, the output voltage Vout of the secondary power supply output 35c and the current IL1 of the inductor 31 (the current flowing from the primary side 25b to the shared node NDS2) vary in response to the power consumption of the load and the operation of the PFM control circuit 15.

[0078] In a period between times t1 and t2, the current IL1 of the inductor 31 exceeds the overcurrent level LOVI (see FIGS. 4 and 5). This excessive current is detected as a voltage of the shared node NDS1 (or NDS2) by the second comparison circuit 43 via the resistor R3, and the second comparison circuit 43 generates a second comparison signal SCMP2 (for example, a logical value [L]).

[0079] In the drive circuit 53, as shown in Fig. 4, the flip-flop circuit of the drive control circuit 51 outputs a logical value [L] to the data output (Q) at time t1 in response to the second comparison signal SCMP2([L]) received at the reset input. As shown in Fig. 4, when the logical AND gate of the output circuit 55 receives the logical value [L], it does not output the drive signal SDRV.

[0080] The drive control circuit 51 operates according to the value of the first comparison signal SCMP1 received at the data input (D) at the rising edge (time t3) of the pulse signal SPLS. The flip-flop circuit of the drive control circuit 51 receives the value of the first comparison signal SCMP1 at its data input (D) at the rising edge of the pulse signal SPLS after time t1 (around time t3). Specifically, this flip-flop circuit is released from reset at time t2, and its data output (Q) is determined by the value of the first comparison signal SCMP1 captured at the rising edge of the pulse signal SPLS.

[0081] At time t3, the output voltage Vout of the secondary power output 35c has already reached the target voltage VTGT. This voltage arrival is detected by the first comparison circuit 41, which generates a first comparison signal SCMP1([L]). When the first comparison circuit 41 detects the voltage arrival, it stops providing the drive signal SDRV to the output circuit 55, while the pulse generation circuit 45 continues to generate the pulse signal SPLS. As shown in FIG. 4, during the stop period TDST of the drive signal SDRV, the switching element 23 is continuously non-conductive, and the current of the inductor 31 is zero or decreases toward zero.

[0082] 5, the dashed line DOT1 indicates a change in the output voltage Vout (secondary voltage) when the provision of the drive signal SDRV is not stopped, and the dashed line DOT2 indicates a change in the current of the inductor 31 when the provision of the drive signal SDRV is not stopped.

[0083] At time t4, when the first comparison circuit 41 detects that the voltage has not yet reached the target voltage, the drive control circuit 51 enables the output circuit 55 to provide the drive signal SDRV. This causes the drive signal SDRV to be output to the switching element 23, and the switching element 23 performs a switching operation in response to the drive signal SDRV. In response to this switching operation, a current flows through the inductor 31, and a diode current ID1 also flows through the diode 33 during the period when the switching element 23 is not conducting.

[0084] The operation of the determination circuit 47 will be described with reference to FIGS.

[0085] In the decision circuit 47 of Fig. 6, when the second comparison circuit 43 detects an overcurrent at time t1 (see Fig. 4), it generates a second comparison signal SCMP2 (logical value [L]). The decision circuit 47 provides the second comparison signal SCMP2 (logical value [L]) to the clock input of a flip-flop circuit 59 via an inverter INV1. As shown in Fig. 4, in response to a change (rising edge) of the second comparison signal SCMP2, the flip-flop circuit 59 takes in a logical value [H] at the data input (D) and outputs a logical value [H] to the data output (Q) of the flip-flop circuit 59. In the serially connected flip-flop circuits 59, 61, and 63, the flip-flop circuits 61 and 63 transfer the logical value [H] in response to the transition (rising edge) of the pulse signal SPLS, and at time t5, the logical value [H] reaches the data output (Q, Q_, where "Q_" represents the inverted output of Q) of the flip-flop circuit 63.

[0086] The data output (Q_) of the flip-flop circuit 63 is connected to the reset input (R_, where "R_" represents the inverted input of R) of the flip-flop circuits 59, 61, and 63, and after the passage of time according to the number of stages of the flip-flop circuits connected in series, all of the flip-flop circuits connected in series are reset.

[0087] In response to a reset, flip-flop circuit 59 outputs a logic value [L] to its data output (Q).

[0088] During the period when the data output (Q) of the flip-flop circuit 59 outputs a logical value [H] (the period from time t1 to time t5), the first comparison circuit 41 detects the arrival of the voltage and generates a first comparison signal SCMP1 ([L]). When the determination circuit 47 provides the first comparison signal SCMP1 (logical value [L]) to a logic gate 67 (e.g., an AND gate) through an inverter INV2, the RS flip-flop circuit (57) is set. The set state of the RS flip-flop circuit (57) causes the expansion circuit 49 to expand the width. As shown in FIG. 4 and FIG. 5, a delay (DLY) due to the expansion of the width works, and the low period of the pulse signal SPLS is expanded and the high period of the pulse signal SPLS is shortened. The set state of the RS flip-flop circuit (57) can be reset by receiving a system reset signal SRSY through an inverter INV3 at the reset input. The pulse signal SPLS is provided to the drive circuit 53 , while in the drive circuit 53 , the output circuit 55 controls the supply of the drive signal SDRV in response to a control signal from the drive control circuit 51 .

[0089] Specifically, the judgment circuit 47 detects that the first comparison signal SCMP1 (logical value [L]) is generated (the voltage of the secondary side power supply output 35c has reached the target voltage) during a first period following the generation of the second comparison signal SCMP2 (logical value [L]) (detection of an overcurrent).

[0090] If the arrival of this voltage is caused by charges from the current flowing through the inductor 31 accumulating in the shared node NDS2, this can be improved by increasing the non-conducting period of the switching element 23. The increase in the non-conducting period of the switching element 23 is provided by the expansion circuit 49 expanding the width of the clock signal CLK. When the width of the pulse signal SPLS is expanded, it is possible to increase the current flowing from the inductor 31 through the diode 33 in the chopper circuit 21 to the secondary power supply output 35c.

[0091] 7 is a diagram showing a schematic diagram of the decompression circuit according to the present embodiment. In the exemplary decompression circuit 49, a periodic signal is provided from a pulse generator 85 to a clock input 83b of the delay circuit 83 and a clock input 87b of a first logic gate 87. A switching logic gate 89 is connected between a delay output 83c of the delay circuit 83 and a delay input 87c of the first logic gate 87, and receives the decompression signal SXTN at a control input 89d. The first logic gate 87 is, for example, a logical AND gate. The switching logic gate 89 is, for example, a logical OR gate.

[0092] 8 shows a waveform at the output node of the delay circuit 83 when the extension signal SXTN indicates "with delay." The delay period TDRY of the delay circuit 83 works to extend the low period of the pulse signal SPLS.

[0093] 9 shows a waveform at the output node of the delay circuit 83 when the extension signal SXTN indicates "no delay." The delay period TDRY of the delay circuit 83 does not work to extend the low period of the pulse signal SPLS.

[0094] FIG. 10 is a diagram illustrating a schematic configuration of a determination circuit according to the present embodiment.

[0095] The exemplary determination circuit 47 includes a counter circuit 86. The exemplary counter circuit 86 detects that the first comparison circuit 41 has not detected the arrival of the voltage during a period in which pulses are counted based on a set value or a fixed value set by a setting signal. At this time, the voltage of the power supply output 35c on the secondary side of the step-up switching regulator may not have reached the target voltage. When the arrival of the voltage has not been detected, the RS flip-flop circuit (57) that sets the width expansion is reset.

[0096] The counter circuit 86 receives the system reset signal SRSY, and resets the RS flip-flop circuit (57) when the system reset signal SRSY is generated.

[0097] 11 is a diagram illustrating a schematic diagram of a determination circuit according to the present embodiment. In the exemplary determination circuit 47, when the second comparison signal SCMP2 generates a logical value [L], the delay amount of the delay circuit 83 is increased by a unit delay amount. When the first comparison signal SCMP1 generates a logical value [L], the delay amount of the delay circuit 83 is decreased by a unit delay amount.

[0098] 12 is a schematic diagram of a delay circuit according to the present embodiment. An exemplary delay circuit 83 may include a reference delay unit 82b corresponding to the base portion of the delay time of the delay circuit 83, and one or more delay units 82c corresponding to the change portion of the delay time of the delay circuit 83.

[0099] The exemplary delay circuit 83 may include multiple delays 82c without including a reference delay 82b.

[0100] In the exemplary expander circuit 49, the number of stages of the delay device 82c that contributes to the delay period TDRY (see FIGS. 8 and 9) can be controlled by the delay change circuit 84.

[0101] As described above, according to the present embodiment, it is possible to provide a PFM control circuit capable of avoiding the occurrence of an overcurrent, and a step-up switching regulator including this PFM control circuit.

[0102] The present embodiment has various aspects as described below.

[0103] A PFM control circuit according to a first aspect of the present embodiment includes a drive output configured to output a drive signal for driving a switch of a switching regulator, a first input configured to receive a first monitor signal associated with an output voltage on a secondary side of the switching regulator, a second input configured to receive a second monitor signal associated with an element current flowing through the switch, a first comparator configured to compare the first monitor signal with a first reference value associated with the output voltage on the secondary side to generate a first comparison signal, a second comparator configured to compare the second monitor signal with a second reference value associated with the element current to generate a second comparison signal, and a clock signal. the pulse generation circuit includes a determination circuit configured to determine whether or not to expand the width of the clock signal and to generate an expansion signal indicative of the result of the determination, and an expansion circuit configured to generate a pulse signal from the clock signal, which either expands the width or maintains the width, in response to the expansion signal; and a drive circuit having an input connected to the pulse generation circuit and an output connected to the drive output, for providing the drive signal to the output, wherein the width of the clock signal is either a high width or a low width of the clock signal, and the determination is made based on the order of transitions of the second comparison signal and the first comparison signal.

[0104] In a PFM control circuit of a second aspect according to the first aspect of this embodiment, the first comparison signal and the second comparison signal are associated with the switching regulator being in a first state and a second state, respectively, the first state indicating that the output voltage of the switching regulator exceeds an allowable fluctuation range, and the second state indicating that the current flowing through the switch exceeds an allowable fluctuation range, and the judgment circuit is configured to set the extension signal to the width extension in response to a transition of the first comparison signal within a first period from a transition of the second comparison signal indicating that the switching regulator is in the second state, and the transition of the first comparison signal can indicate that the switching regulator has entered the first state.

[0105] In a PFM control circuit of a third aspect according to the second aspect of this embodiment, the drive circuit includes a drive control circuit and an output circuit, the drive control circuit having a first input, a second input and a first pulse input for respectively receiving the first comparison signal, the second comparison signal and the pulse signal, and a control output, the output circuit having a first control input receiving a control signal from the control output, a second pulse input for receiving the pulse signal, and an output connected to the output of the drive circuit, and the drive control circuit is operable such that the output circuit provides the drive signal to the drive output when the second comparison signal does not indicate that the switching regulator is in the second state and when the first comparison signal does not indicate that the switching regulator is in the first state.

[0106] In a PFM control circuit of a fourth aspect according to the second or third aspect of this embodiment, the drive control circuit operates to prevent the output circuit from providing the drive signal to the drive output when the second comparison signal indicates that the switching regulator is in the second state, and the drive control circuit can operate to prevent the output circuit from providing the drive signal to the drive output when the second comparison signal does not indicate that the switching regulator is in the second state and when the first comparison signal indicates that the switching regulator is in the first state.

[0107] In the PFM control circuit of the second aspect, the third aspect or the fifth aspect according to claim 4 of this embodiment, the determination circuit includes a flip-flop circuit configured to determine that the expansion circuit enables the width expansion, and the determination circuit can be configured to set the flip-flop circuit to expand the width in response to the first comparison signal indicating that the switching regulator is in the first state within the first period.

[0108] In a PFM control circuit of a sixth aspect according to a fifth aspect of this embodiment, the flip-flop circuit includes an RS flip-flop circuit, and the judgment circuit further includes a first flip-flop circuit, one or more second flip-flop circuits, and a third flip-flop circuit, the first flip-flop circuit, the second flip-flop circuit, and the third flip-flop circuit are connected in series, and the first flip-flop circuit captures a first logical value and provides it to an output of the first flip-flop circuit in response to a transition of the second comparison signal indicating that the switching regulator is in the second state, the second flip-flop circuit and the third flip-flop circuit operate in response to the pulse signal to transfer the first logical value, and the third flip-flop circuit can reset the first flip-flop circuit, the second flip-flop circuit, and the third flip-flop circuit in response to the third flip-flop circuit capturing the first logical value.

[0109] In a PFM control circuit of a seventh aspect in accordance with the sixth aspect of this embodiment, the judgment circuit includes a logic circuit that receives a signal indicated by a circuit that gives the first logical value to the first comparison signal when the switching regulator is in the first state, and a signal from the output of the first flip-flop circuit, and the flip-flop circuit can have an input connected to the output of the logic circuit.

[0110] In a PFM control circuit of an eighth aspect according to the sixth or seventh aspect of this embodiment, the pulse generating circuit may further include a monitoring circuit that monitors whether the first comparison signal has changed within a second period.

[0111] In the PFM control circuit of the ninth aspect according to the eighth aspect of this embodiment, the pulse generating circuit can generate a reset signal that resets the RS flip-flop circuit when the first comparison signal does not change within the second period.

[0112] In a PFM control circuit according to a tenth aspect of any one of the first to ninth aspects of this embodiment, the expansion circuit may include a delay circuit having a delay time associated with the expansion of the width.

[0113] In a PFM control circuit of an eleventh aspect according to a tenth aspect of this embodiment, the pulse generating circuit is configured to change the delay time in response to a transition of at least one of the first comparison signal and the second comparison signal, and the transition can indicate either a transition from a logical value "H" to "L" or a transition from a logical value "L" to "H".

[0114] In a PFM control circuit of a twelfth aspect according to an eleventh aspect of this embodiment, the expansion circuit includes one or more delay devices corresponding to a change in the delay time, and the pulse generation circuit may further include a counter circuit that counts the number of transitions, and a delay change circuit that changes the number of stages connecting the delay devices to the delay circuit depending on an output value of the counter circuit.

[0115] A step-up switching regulator according to a thirteenth aspect of this embodiment includes a PFM control circuit as described in any one of the first to twelfth aspects, a chopper circuit including an inductor and a diode, a switch connected to the inductor and the diode of the chopper circuit and configured to be driven by the drive signal from the drive output, a voltage detection circuit that detects an output voltage of the output of the chopper circuit and is connected to the first input, and a current sensor that detects a current flowing through the switch and is connected to the second input.

[0116] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0117] 10...power line, 11...equipment, 13...external circuit, 15...PFM control circuit, 17 Switching regulator, 20... Semiconductor device, 21 Chopper circuit, 23... Switching element, 25 Voltage detection circuit, 25b...Primary side, 27 Current sensor, 29 Capacitor, 31... Inductor, 33... Diode, 35b Power input, 35c...power output, 37b Drive output, 37c... First input, 37d...Second input, 41...first comparison circuit, 41b...first comparator, 41c: a first comparison voltage generating circuit; 43...second comparison circuit, 43b...Second comparator, 43c... A second comparison voltage generating circuit; 45 Pulse generating circuit, 47...judgment circuit, 49...Extension circuit, 51... Drive control circuit, 53 Drive circuit, 55 Output circuit, 57 RS flip-flop circuit, 59, 61, 63...flip-flop circuit, 65...signal source, 69...Monitoring circuit, 71, 71b, 71c Counter circuit 73... Detection circuit, 75 Reset circuit, 77...Initialization circuit, 79...comparison circuit, 82b Reference delay unit, 82c... Delay device, 83... Delay circuit, 85 Pulse generator, 86 Counter circuit, 86b...first counter circuit; 86c... second counter circuit; 86d...Third counter circuit, 88 Counter control circuit, 89... Switching logic gates, CLK: Clock signal, ID1: Diode current, IL1...current, INV1, INV2, INV3... inverters, LOVI: Overcurrent level, MN0: Field-effect transistor, NDS1, NDS2, NDS3, NOUT... shared nodes, SCMP1...1st comparison signal, SCMP2...Second comparison signal, SCSW... Control signal, SDET1: Detection signal, SDET2...Comparison signal, SDLY: Delay signal, SDRV: Drive signal, SENB control signal, SMON1: First monitor signal, SMON2: Second monitor signal, SPLS: Pulse signal, SRST, SRSY Reset signal ST1: Period setting signal, SW... Switch, SXTN...Extended signal, TDRY: Delay period, TDST...stop period, VL2: Judgment value, VLC: Counter setting signal, VTGT: target voltage, Vout: Output voltage (secondary voltage), Vref1: First reference value, Vref2: Second reference value,

Claims

1. a drive output configured to output a drive signal to drive a switch of the switching regulator; a first input configured to receive a first monitor signal related to an output voltage on a secondary side of the switching regulator; a second input configured to receive a second monitor signal related to a device current through the switch; a first comparator configured to compare the first monitor signal with a first reference value related to an output voltage of the secondary side to generate a first comparison signal; a second comparator configured to compare the second monitor signal with a second reference value related to the element current to generate a second comparison signal; a pulse generation circuit including: a determination circuit configured to receive a clock signal, the determination circuit determining whether or not to extend the width of the clock signal and generating an extension signal indicative of the result of the determination; and an extension circuit configured to generate a pulse signal from the clock signal, the pulse signal being either the extension of the width or the maintenance of the width, in response to the extension signal; a drive circuit having an input connected to the pulse generating circuit and an output connected to the drive output, the drive circuit providing the drive signal to the output; Equipped with the width of the clock signal is either a high width or a low width of the clock signal, the determination is made based on an order of a transition of the second comparison signal and a transition of the first comparison signal. PFM control circuit.

2. the first comparison signal and the second comparison signal are associated with the switching regulator being in a first state and a second state, respectively; the first state represents that the output voltage of the switching regulator exceeds an allowable fluctuation range, The second state indicates that a current flowing through the switch exceeds an allowable fluctuation range, the determination circuit is configured to set the expansion signal to the width expansion in response to a transition of the first comparison signal within a first period from a transition of the second comparison signal indicating that the switching regulator is in the second state; the transition of the first comparison signal indicates that the switching regulator has entered the first state.

2. The PFM control circuit according to claim 1.

3. the drive circuit includes a drive control circuit and an output circuit; the drive control circuit has a first input, a second input and a first pulse input for respectively receiving the first comparison signal, the second comparison signal and the pulse signal, and a control output; the output circuit has a first control input for receiving a control signal from the control output, a second pulse input for receiving the pulse signal, and an output connected to the output of the drive circuit; the drive control circuitry operates the output circuitry to provide the drive signal to the drive output when the second comparison signal does not indicate that the switching regulator is in the second state and when the first comparison signal does not indicate that the switching regulator is in the first state.

3. A PFM control circuit according to claim 2.

4. the drive control circuit is operative to prevent the output circuit from providing the drive signal to the drive output when the second comparison signal indicates that the switching regulator is in the second state; the drive control circuit operates to prevent the output circuit from providing the drive signal to the drive output when the second comparison signal does not indicate that the switching regulator is in the second state and when the first comparison signal indicates that the switching regulator is in the first state.

4. A PFM control circuit according to claim 3.

5. the determination circuit includes a flip-flop circuit configured to determine that the expansion circuit enables the width expansion; the determination circuit is configured to set the width expansion in the flip-flop circuit in response to the first comparison signal indicating that the switching regulator is in the first state within the first time period.

3. A PFM control circuit according to claim 2.

6. the flip-flop circuit includes an RS flip-flop circuit, the determination circuit further includes a first flip-flop circuit, one or more second flip-flop circuits, and a third flip-flop circuit; the first flip-flop circuit, the second flip-flop circuit, and the third flip-flop circuit are connected in series; the first flip-flop circuit responds to a transition of the second comparison signal indicating that the switching regulator is in the second state by capturing and providing a first logic value at an output of the first flip-flop circuit; the second flip-flop circuit and the third flip-flop circuit operate in response to the pulse signal to transfer the first logic value; the third flip-flop circuit resets the first flip-flop circuit, the second flip-flop circuit, and the third flip-flop circuit in response to the third flip-flop circuit capturing the first logical value; 6. A PFM control circuit according to claim 5.

7. the determination circuit includes a logic circuit that receives a signal indicating a state of the first comparison signal from a circuit that provides the first logic value to the first comparison signal when the switching regulator is in the first state, and a signal from the output of the first flip-flop circuit; the flip-flop circuit has an input connected to an output of the logic circuit; 7. A PFM control circuit according to claim 6.

8. the pulse generating circuit further includes a monitoring circuit that monitors whether the first comparison signal has changed within a second period.

7. A PFM control circuit according to claim 6.

9. the pulse generating circuit generates a reset signal for resetting the RS flip-flop circuit when the first comparison signal does not change within the second period.

9. A PFM control circuit according to claim 8.

10. the expansion circuit includes a delay circuit having a delay time associated with the width expansion; 2. The PFM control circuit according to claim 1.

11. the pulse generating circuit is configured to change the delay time in response to a transition of at least one of the first comparison signal and the second comparison signal; The transition indicates either a transition from a logical value "H" to a logical value "L" or a transition from a logical value "L" to a logical value "H"; 11. The PFM control circuit according to claim 10.

12. the expansion circuit includes one or more delay elements corresponding to the change in the delay time, The pulse generating circuit further includes a counter circuit that counts the number of transitions, and a delay changing circuit that changes the number of stages that connect the delay device to the delay circuit according to an output value of the counter circuit.

12. A PFM control circuit according to claim 11.

13. A PFM control circuit according to any one of claims 1 to 12; a chopper circuit including an inductor and a diode; a switch connected to the inductor and the diode of the chopper circuit and configured to be driven by the drive signal from the drive output; a voltage detection circuit for detecting an output voltage of the output of the chopper circuit and connected to the first input; a current sensor connected to the second input and sensing a current through the switch; Equipped with Step-up switching regulator.

Images