Defect analysis device and defect analysis method

Abstract

To provide a defect analysis device capable of enhancing the efficiency of defect analysis.SOLUTION: A defect analysis device analyzes a defect of a semiconductor device on which a logic circuit and a memory circuit are mounted, and includes a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and fault diagnosis result data obtained by fault diagnosis with respect to the test result of the logic circuit. The processor extracts a fail I / O value from the fail bit data, extracts data of a memory connection terminal which is a connection terminal to the memory circuit from an estimated defective part included in the failure diagnosis result data, and determines coincidence / discrepancy between the fail I / O value and a terminal ID value included in the data of the memory connection terminal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a failure analysis device and a failure analysis method. [Background technology]

[0002] Patent Document 1 (US Pat. No. 11,288,435) shows a failure analysis device that can improve the efficiency of failure analysis. The failure analysis device uses a layout tool to display the physical coordinate positions of fail bits in a memory and logic failure locations, and associates memory failures with logic failures. When associating, the failure analysis device extracts, from among multiple logic failure locations, a logic failure location that has the shortest total distance from multiple fail bits, and determines that the extracted logic failure location is associated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 11,288,435 Summary of the Invention [Problem to be solved by the invention]

[0004] In general, logic failure analysis and memory failure analysis are performed independently because their analysis methods are different from each other. Meanwhile, in recent years, semiconductor devices in which logic circuits and memory circuits are mixed, such as in-vehicle SoCs (System on Chip), are widely used. When testing a logic circuit in such a semiconductor device, the memory circuit may be pointed out as a suspected defective part. Specifically, for example, a terminal that accesses the memory circuit in the logic circuit may be pointed out as a suspected defective part.

[0005] In this case, however, the defect location that is the root cause of the defect is not necessarily located in the logic circuit, but may be located in the memory circuit. Similarly, when a fail bit occurs by testing a memory circuit in a semiconductor device, the defect location that is the root cause of the fail bit is not necessarily located in the memory circuit, but may be located in the logic circuit.

[0006] For this reason, in either case, in order to specify or narrow down the location of the defect, it is necessary to perform, for example, an optical emission analysis on a relatively wide area. However, the optical emission analysis leads to an increase in the number of analysis steps. On the other hand, in order to increase the yield of semiconductor devices, it is necessary to specify and narrow down the location of the defect. For these reasons, an efficient analysis method that can specify or narrow down the location of the defect without performing an optical emission analysis is desired.

[0007] As such a method, for example, as shown in Patent Document 1, a method of identifying a logic failure point with the shortest total distance from a plurality of fail bits as a failure occurrence point related to a fail bit is exemplified. However, depending on the layout, among a plurality of logic failure points, the failure point with the longest distance from the fail bit may be related to the fail bit, not the failure point with the shortest distance. For this reason, in practice, it is necessary to separately compare the layout with the circuit diagram, which may increase the number of analysis steps.

[0008] Furthermore, when a defect occurrence location is identified by distance calculation based on physical coordinates, for example, when a semiconductor device is shrunk, there is a risk of an error occurring. Specifically, for example, the physical coordinates on the layout tool calculated from the fail bits may deviate from the physical coordinates of the fail bits in the actual semiconductor device. This is because, for example, in GDS-II, which is a standard format for layout data, rounding errors occur in the coordinates when shrinking is performed. In this way, when an error occurs in the physical coordinates on the layout tool, the distance calculation may not be performed correctly.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] In view of this, a failure analysis device according to an embodiment analyzes failures in a semiconductor device equipped with a logic circuit and a memory circuit, and includes a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis result data obtained by performing failure diagnosis on the test result of the logic circuit. The processor extracts fail I / O values ​​from the fail bit data, extracts data on memory connection terminals, which are connection terminals to the memory circuit, from estimated failure locations included in the failure diagnosis result data, and determines whether the fail I / O values ​​match or do not match terminal ID values ​​included in the data on the memory connection terminals. Effect of the Invention

[0011] By using the failure analysis device of the embodiment, it is possible to improve the efficiency of failure analysis. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of a failure analysis system according to the first embodiment. [Diagram 2] FIG. 2 is a functional block diagram showing an example of the configuration of a main part of a failure analysis device realized using the configuration of FIG. [Diagram 3] FIG. 3 is a diagram for explaining an example of main processing contents of the estimated defect portion limitation unit in FIG. [Figure 4A] FIG. 4A is a diagram showing an example of processing contents when the estimated defect portion limiting unit in FIG. 2 limits an estimated defect portion. [Figure 4B] FIG. 4B is a specific example of the processing contents shown in FIG. 4A, and is a diagram showing an example of a schematic layout around an estimated defective portion. [Diagram 5]FIG. 5 is a flowchart showing an example of processing contents using the failure analysis system shown in FIGS. 1 and 2 in the failure analysis method according to the first embodiment. [Figure 6] FIG. 6 is a flowchart showing an example of the processing contents following FIG. [Figure 7] FIG. 7 is a schematic diagram showing an example of the configuration of a failure analysis system according to the second embodiment. [Figure 8] FIG. 8 is a functional block diagram showing a configuration example of a main part of a failure analysis device realized using the configuration of FIG. [Figure 9] FIG. 9 is a diagram showing an example of the EDA data in FIG. 7 and FIG. [Figure 10A] FIG. 10A is a diagram showing an example of processing contents when the estimated defect portion limiting unit in FIG. 8 limits an estimated defect portion. [Figure 10B] FIG. 10B is a specific example of the processing contents shown in FIG. 10A, and is a diagram showing an example of a schematic layout around an estimated defective portion. [Figure 11] FIG. 11 is a flowchart showing an example of the process contents subsequent to FIG. 5 in the failure analysis method according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number.

[0014] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be obviously not essential in principle. The same applies to the above numerical values ​​and ranges.

[0015] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0016] (First embodiment) <Configuration of failure analysis system> Fig. 1 is a schematic diagram showing a configuration example of a failure analysis system according to a first embodiment. The failure analysis system shown in Fig. 1 includes an LSI (Large Scale Integration) tester 100, a communication network 200, a computer 300, and a display device 350. The communication network 200 is, for example, a wired LAN (Local Area Network) or a wireless LAN, and connects the LSI tester 100 and the computer 300. The display device 350 is, for example, a liquid crystal display or an organic EL (Electro Luminescence) display, and displays various information based on commands from the computer 300.

[0017] The LSI tester 100 is composed of, for example, a logic tester. The device under test is a semiconductor device equipped with a logic circuit and a memory circuit. The memory circuit is, for example, an SRAM. The LSI tester 100 tests the logic circuit and the memory circuit mounted on the semiconductor device. At this time, the memory circuit is tested using, for example, a memory BIST (Built In Self Test) circuit that is a part of the logic circuit. The LSI tester 100 transmits logic failure data 325, which is a test result of the logic circuit, and fail bit data 322, which is a test result of the memory circuit, to the computer 300 via the communication network 200.

[0018] The computer 300 includes a processor 310 and a storage device 320. The storage device 320 is configured, for example, by combining a non-volatile storage device such as a hard disk drive, a solid state drive (SSD), or a flash memory with a volatile storage device such as a random access memory (RAM). The storage device 320 stores a failure analysis tool 329 and a layout tool 330, which are programs. The processor 310 executes the failure analysis tool 329 and the layout tool 330, causing the computer 300 to function as a failure analysis device.

[0019] The storage device 320 also stores, as data, fail bit data 322 and logic failure data 325 from the LSI tester 100. In addition, the storage device 320 stores memory circuit data 321, physical address data 323, memory failure data 324, fault diagnosis result data 326, memory connection terminal data 327, and layout data 328. The layout data 328 is used by a layout tool 330, for example, when displaying the layout of the semiconductor device on a display device 350.

[0020] Fig. 2 is a functional block diagram showing an example of the configuration of the main part of a failure analysis device realized by using the configuration of Fig. 1. The failure analysis device 400 shown in Fig. 2 is a device that analyzes failures of a semiconductor device including a memory circuit and a logic circuit. The failure analysis device 400 includes a physical address conversion unit 331, a fail I / O extraction unit 332, a failure mode classification unit 333, a memory failure data creation unit 334, a logic fault diagnosis unit 335, a memory connection terminal extraction unit 336, an estimated failure location limitation unit 337, and a display control unit 338.

[0021] The physical address conversion unit 331, the fail I / O extraction unit 332, the failure mode classification unit 333, the memory failure data creation unit 334, the logic fault diagnosis unit 335, the memory connection terminal extraction unit 336 and the estimated failure point limitation unit 337 are realized by the processor 310 executing the failure analysis tool 329 stored in the storage device 320. The display control unit 338 is realized by the processor 310 executing the layout tool 330 stored in the storage device 320.

[0022] 1. The fail bit data 322 is obtained by testing the memory circuit using the LSI tester 100, and includes a fail logical address LADR and a fail I / O value FIO that identify a failed memory cell.

[0023] The memory circuit data 321 includes, for example, information necessary for converting the fail logical address LADR and the fail I / O value FIO into the fail physical address PADR. The physical address conversion unit 331 converts the fail logical address LADR and the fail I / O value FIO into the fail physical address PADR using the memory circuit data 321. The logical address is an address input to the memory circuit, and is an address that represents the logical arrangement order of memory cells in a memory array in the memory circuit. On the other hand, the physical address is an address that represents the physical arrangement order of memory cells in the memory array.

[0024] That is, in a memory array, logical addresses are not necessarily assigned in order to the physical arrangement order of memory cells. When performing a failure analysis, the physical arrangement or arrangement order of failed memory cells is required. Therefore, the physical address conversion unit 331 converts the failed logical address LADR and the failed I / O value FIO into a predetermined arithmetic expression based on the memory circuit data 321, for example, to a failed physical address PADR. Then, the physical address conversion unit 331 creates physical address data 323 including the failed physical address PADR.

[0025] In parallel with the processing of the physical address conversion unit 331, the fail I / O extraction unit 332 extracts a fail I / O value FIO from the fail bit data 322. The failure mode classification unit 333 classifies each fail bit into one of a plurality of failure modes FMD based on the fail physical address PADR included in the physical address data 323 and the fail I / O value FIO extracted by the fail I / O extraction unit 332.

[0026] The multiple failure modes FMD include a bit failure mode, a line failure mode, and an I / O block failure mode. The bit failure mode is a mode in which a fail bit exists in isolation. The line failure mode is a mode in which a plurality of fail bits exists on the same bit line or the same word line in a memory array. The I / O block failure mode is a mode in which a predetermined number or more of bit line failures, which is at least two, occur in the same I / O terminal, for example.

[0027] The memory failure data creation unit 334 creates the memory failure data 324 by integrating the fail physical address PADR from the physical address conversion unit 331, the fail I / O value FIO from the fail I / O extraction unit 332, and the fail mode FMD from the fail mode classification unit 333.

[0028] The logic fault diagnosis unit 335 performs fault diagnosis on the test results of the logic circuit by the LSI tester 100, i.e., logic fault data 325. Then, the logic fault diagnosis unit 335 creates fault diagnosis result data 326 obtained by the fault diagnosis. Specifically, in a logic circuit test, the LSI tester 100 usually observes output patterns for various input patterns and judges whether the output pattern matches or does not match an expected value pattern. The logic fault diagnosis unit 335 comprehensively diagnoses the match / mismatch judgment results to determine terminals in the logic circuit, more specifically, logic cells, logic wiring, etc., as suspected fault locations.

[0029] At this time, the logic fault diagnosis unit 335 may determine a memory connection terminal, which is a connection terminal to a memory circuit in the logic circuit, as the presumed fault location. The fault diagnosis result data 326 is data including a list of presumed fault locations obtained in this manner. The logic fault diagnosis unit 335 is realized by a part of the fault analysis tool 329, and is realized by a commonly known EDA (Electronic Design Automation) tool. Such an EDA tool can also create an input pattern that takes fault detection rate into consideration.

[0030] The memory connection terminal extraction unit 336 extracts data 327 of the memory connection terminal MCP from the estimated defective parts included in the fault diagnosis result data 326. In detail, the memory connection terminal extraction unit 336 judges whether or not the memory connection terminal MCP is included as an estimated defective part in the fault diagnosis result data 326, and performs extraction processing if included. The estimated defective part limitation unit 337, the details of which will be described later, limits the estimated defective part based on the memory defective data 324 and the data 327 of the memory connection terminal.

[0031] The display control unit 338 displays information on the estimated defective parts limited by the estimated defective part limiting unit 337 on the display device 350. At this time, the display control unit 338 may input information on the estimated defective parts to the layout tool 330, for example, to display on the display device 350 a layout screen or the like of the semiconductor device in which the estimated defective parts are highlighted.

[0032] <Details of the estimated defective area> Fig. 3 is a diagram for explaining an example of main processing contents of the estimated defective part limitation unit 337 in Fig. 2. Fig. 3 shows an example of the data 327 of the memory connection terminal in Fig. 1 and Fig. 2, and an example of the memory defect data 324. The data 327 of the memory connection terminal is also a part of the fault diagnosis result data 326. The data 327 of the memory connection terminal shown in Fig. 3 includes score information 361, an instance name 362, and a memory module name 364.

[0033] The score information 361 indicates the reliability of the diagnosis result by the logic fault diagnosis unit 335, i.e., the estimated defective location. The memory module name 364 is a name determined for each configuration of the memory circuit, and is determined to be different if the configuration, such as the capacity value or the number of I / Os, is different. The instance name 362 is a name determined for each individual memory circuit, for example, when a semiconductor device is equipped with a plurality of memory circuits having a certain memory module name 364.

[0034] Information representing the memory connection terminal MCP is included in the instance name 362. The information representing the memory connection terminal MCP is composed of identification information 363 for distinguishing between an input terminal from a memory circuit or an output terminal to a memory circuit, in this example, identification information "Q" representing an output terminal, and a terminal ID value PID of the terminal, in this example, "46".

[0035] On the other hand, the memory failure data 324 includes a fail physical address PADR, a fail mode FMD, a memory module name 366, a fail I / O value FIO, and an instance name 365. The memory module name 366 and the instance name 365 are the same as those in the data 327 of the memory connection terminal described above. However, unlike the instance name 362 in the data 327 of the memory connection terminal, the instance name 365 does not include information representing the memory connection terminal MCP. Also, the memory module name 366 and the instance name 365 are written in the fail bit data 322 as information on the test target.

[0036] Here, the estimated defective part fining section 337 checks whether the instance name 362 and the memory module name 364 in the data 327 of the memory connection terminal are identical to the instance name 365 and the memory module name 366 in the memory failure data 324. If the instance names and memory module names are identical, the estimated defective part fining section 337 judges whether the fail I / O value FIO included in the memory failure data 324 matches or does not match the terminal ID value PID included in the data 327 of the memory connection terminal.

[0037] When designing a semiconductor device, the terminal ID value PID is usually set to a value based on the I / O value of the memory circuit in order to define the connection relationship between the logic circuit and the memory circuit. Therefore, if the fail I / O value FIO and the terminal ID value PID match, there is a possibility that the estimated defective location occurring in the logic circuit, in this example, the memory connection terminal MCP "Q

[46] ", and the fail bit occurring in the I / O terminal "46" of the memory circuit are related to each other.

[0038] 3, the failure mode FMD is an I / O block failure mode. In particular, in such a case, it is highly likely that an I / O block failure occurs in the memory circuit due to a failure of the memory connection terminal MCP in the logic circuit or a failure on the signal transmission path of the terminal. On the other hand, from the viewpoint of memory failure analysis, if only the memory failure data 324 is referred to, it is not easy to specify or narrow down the failure occurrence location that is the cause of the I / O block failure. Furthermore, from the viewpoint of logic failure analysis, even if the memory connection terminal MCP is included in the estimated failure location, the memory connection terminal MCP is not necessarily the failure occurrence location.

[0039] Therefore, it is particularly useful to compare the fail I / O value FIO with the terminal ID value PID when an I / O block failure occurs. This makes it possible to easily identify or narrow down the suspected defective location, and thus the location where the failure occurs, when the comparison results in a match. That is, from the viewpoint of memory failure analysis, the suspected defective location that is the cause of the I / O block failure can be narrowed down to the area around the memory connection terminal MCP. Furthermore, from the viewpoint of logic failure analysis, it is possible to increase the certainty that the memory connection terminal MCP is the defective location.

[0040] Fig. 4A is a diagram showing an example of processing contents when the estimated defective part limiting unit 337 in Fig. 2 limits the estimated defective part. Fig. 4B is a diagram showing an example of a schematic layout around the estimated defective part, which is a specific example of the processing contents shown in Fig. 4A. In Fig. 4A, the estimated defective part limiting unit 337 judges whether the fail I / O value FIO and the terminal ID value PID match / mismatch when the fail mode FMD of the fail bit is an I / O block failure mode. Then, when the fail I / O value FIO and the terminal ID value PID match, the estimated defective part limiting unit 337 limits the estimated defective part to a related part of the memory connection terminal MCP in the logic circuit area AR1 or the peripheral circuit area AR2.

[0041] Specifically, as shown in Fig. 4B, the semiconductor device is provided with a logic circuit region AR1 and a memory circuit region AR4. The memory circuit region AR4 has a peripheral circuit region AR2 connected to the logic circuit region AR1, and a memory array region AR3 connected to the logic circuit region AR1 via the peripheral circuit region AR2. The memory array region AR3 has a plurality of memory cells arranged in a matrix, and word lines and bit lines connected to the plurality of memory cells. The peripheral circuit region AR2 has drivers for driving the word lines and bit lines, sense amplifiers for amplifying signals on the bit lines, and the like.

[0042] The logic circuit area AR1 includes a memory connection terminal MCP that is a presumed defective location. In this example, the memory connection terminal MCP is an output terminal to a memory circuit and has a terminal ID value PID of "46." The memory array area AR3 includes a large number of fail bits classified as I / O block failures in an I / O terminal with a fail I / O value FIO of "46."

[0043] When the fail I / O value FIO and the terminal ID value PID match in this way, the estimated defective part limiting unit 337 limits the estimated defective part to the signal transmission path SP1 of the memory connection terminal MCP in the logic circuit or the signal transmission path SP2 of the memory connection terminal MCP in the peripheral circuit in the memory circuit. Then, the estimated defective part limiting unit 337 causes the display device 350 to display, via the display control unit 338, a layout screen in which the signal transmission path SP1 is emphasized as in FIG. 4B.

[0044] 4A, when the failure mode FMD is an I / O block failure mode and the fail I / O value FIO does not match the terminal ID value PID, the estimated failure location limiting unit 337 determines the estimated failure location to be the entire peripheral circuit area AR2. In this case, it is necessary to specify or narrow down the failure location by using, for example, a separate light emission analysis or the like.

[0045] On the other hand, when the failure mode FMD is not the I / O block failure mode, that is, when it is a bit failure mode or a line failure mode, the estimated failure location limiting unit 337 determines the estimated failure location to be a target portion in the memory array area AR3 or its periphery. In detail, when it is a bit failure mode, the estimated failure location is determined to be a corresponding memory cell, and when it is a line failure mode, the estimated failure location is determined to be a corresponding bit line or word line, or a corresponding driver or sense amplifier.

[0046] <Failure analysis method> Fig. 5 is a flowchart showing an example of the processing contents using the failure analysis system shown in Fig. 1 and Fig. 2 in the failure analysis method according to the first embodiment. Fig. 6 is a flowchart showing an example of the processing contents following Fig. 5. In Fig. 5, first, the LSI tester 100 executes a logic circuit test on the logic circuit in the semiconductor device (step S101). Then, a plurality of processes included in step S102, that is, the processes of steps S201-S214, are performed using the failure analysis device 400 shown in Fig. 2, more specifically, the processor 310 shown in Fig. 1.

[0047] In step S102, first, the logic fault diagnosis unit 335 performs fault diagnosis on the logic fault data 325, which is the result of the logic circuit test (step S201). Next, the fault analysis device 400 judges the presence or absence of a logic fault based on the result of the fault diagnosis (step S202). If there is no logic fault (step S202: NO), the process proceeds to the next test step (step S203). On the other hand, if there is a logic fault (step S202: YES), the memory connection terminal extraction unit 336 judges whether or not the memory connection terminal MCP is included in the estimated fault location in the logic circuit, that is, the fault diagnosis result data 326 (step S204).

[0048] If the memory connection terminal MCP is not included in the fault diagnosis result data 326 (step S204: NO), the memory connection terminal extraction unit 336 notifies the estimated fault location limitation unit 337 of that fact. In response to this, the estimated fault location limitation unit 337 determines the estimated fault location to be in the logic circuit area AR1, more specifically, to a logic wiring or logic cell described in the fault diagnosis result data 326 (step S205). In this case, a physical analysis or the like is then performed on the estimated fault location (step S103).

[0049] On the other hand, if the memory connection terminal MCP is included in the failure diagnosis result data 326 (step S204: YES), the memory connection terminal extraction unit 336 extracts the data 327 of the memory connection terminal (step S206). Next, the failure analysis device 400 causes the LSI tester 100 to execute a memory circuit test on the memory circuit in the semiconductor device (step S207). In response, the LSI tester 100 executes a memory circuit test using, for example, a memory BIST circuit in a logic circuit included in the semiconductor device, and notifies the failure analysis device 400 of the test result.

[0050] The failure analysis device 400 receives the test result from the LSI tester 100 and determines whether or not there is a fail bit (step S208). If there is no fail bit (step S208: NO), the failure analysis device 400 proceeds to step S205. On the other hand, if there is a fail bit (step S208: YES), the failure analysis device 400 analyzes the fail bit (step S209).

[0051] In step S209, specifically, the physical address conversion unit 331 converts the address into a fail physical address PADR, the fail I / O extraction unit 332 extracts a fail I / O value FIO, and the fail mode classification unit 333 classifies the fail mode FMD. Furthermore, in response to these processing results, the memory fail data creation unit 334 creates the memory fail data 324.

[0052] 6, the estimated failure location limiting unit 337 determines whether the failure mode FMD is an I / O block failure mode based on the classification result of the failure mode FMD (step S210). If the failure mode FMD is not an I / O block failure mode (step S210: NO), the estimated failure location limiting unit 337 determines the estimated failure location to be a target portion in the memory array area AR3 or its periphery (step S211), as described in FIG. 4A and FIG. 4B. In this case, physical analysis or the like can then be performed on the estimated failure location (step S104).

[0053] On the other hand, if the failure mode FMD is an I / O block failure mode (step S210: YES), the estimated failure portion limiting unit 337 judges whether the terminal ID value PID and the fail I / O value FIO match or not (step S212) as described in Fig. 3. If the terminal ID value PID and the fail I / O value FIO do not match (step S212: NO), the estimated failure portion limiting unit 337 determines the estimated failure portion to be the entire peripheral circuit area AR2 (step S213) as described in Fig. 4A and Fig. 4B. In this case, it is necessary to subsequently perform light emission analysis or the like to identify or narrow down the failure occurrence portion (step S105).

[0054] On the other hand, if the terminal ID value PID and the fail I / O value FIO match (step S212: YES), the estimated defective part limiting unit 337 limits the estimated defective part to a related portion of the memory connection terminal MCP in the logic circuit area AR1 or the peripheral circuit area AR2, as shown in Fig. 4A. That is, the estimated defective part limiting unit 337 limits the estimated defective part to the signal transmission path SP1 of the memory connection terminal MCP in the logic circuit, or the signal transmission path SP2 of the memory connection terminal MCP in the peripheral circuit, as shown in Fig. 4B, for example. In this case, a physical analysis or the like can be performed on the estimated defective part without going through a light emission analysis or the like (step S106).

[0055] <Main Effects of the First Embodiment> As described above, in the method of the first embodiment, when a memory connection terminal is included in the estimated defective portion in the logic circuit and a fail bit occurs in the memory circuit, the terminal ID value of the memory connection terminal is compared with the fail I / O value of the fail bit. This makes it possible to determine whether or not there is a relationship between the logic failure and the memory failure. In particular, when the comparison result shows a match and the fail bit is classified as an I / O block failure, it is determined that there is a relationship, and the estimated defective portion can be identified or narrowed down.

[0056] This makes it possible to improve the efficiency of failure analysis. Specifically, since the suspected failure location can be specified or narrowed down without performing light emission analysis or detailed investigation of the layout and circuit diagram, the time required for analysis can be shortened. As a result, it becomes possible to increase the yield of semiconductor devices at an early stage.

[0057] (Second embodiment) <Configuration of failure analysis system> Fig. 7 is a schematic diagram showing a configuration example of a failure analysis system according to the second embodiment. The failure analysis system shown in Fig. 7 is different from the configuration example shown in Fig. 1 in that data stored in a storage device 320 in a computer 300 is different. That is, the storage device 320 shown in Fig. 7 stores EDA data 340 and faulty scan flip-flop data 341 in addition to the various data shown in Fig. 1.

[0058] Fig. 8 is a functional block diagram showing a configuration example of the main part of a failure analysis device realized by using the configuration of Fig. 7. A failure analysis device 400a shown in Fig. 8 further includes a failure scan flip-flop data acquisition unit 342 in addition to the configuration example shown in Fig. 2. Accordingly, the failure analysis device 400a stores the EDA data 340 and the failure scan flip-flop data 341 shown in Fig. 7. Furthermore, unlike the case of Fig. 2, the estimated failure part limiting unit 337 limits the estimated failure part by using the failure scan flip-flop data 341 in addition to the memory failure data 324 and the data 327 of the memory connection terminal.

[0059] 7 executes the failure analysis tool 329 in the storage device 320. The fault scan flip-flop data acquisition unit 342 acquires data corresponding to the memory connection terminal MCP from the EDA data 340 as fault scan flip-flop data 341, based on the information of the memory connection terminal MCP extracted by the memory connection terminal extraction unit 336.

[0060] <Details of the faulty scan flip-flop data acquisition section> Fig. 9 is a diagram showing an example of the EDA data 340 in Fig. 7 and Fig. 8. The EDA data 340 shown in Fig. 9 includes scan chain data 345. The scan chain data 345 is provided in the same number as the scan chains mounted in the semiconductor device, specifically, in the logic circuit. Each scan chain is distinguished by a scan chain name 370.

[0061] Each scan chain data 345 includes a scan chain name 370, a scan-in terminal name 371, a scan-out terminal name 372, and detailed information of multiple scan flip-flops that configure the scan chain. The detailed information includes identification information 373 for each of the multiple scan flip-flops, such as a number, an instance name 374, a logic cell name 375, and layout arrangement information 376, such as layout coordinates.

[0062] The faulty scan flip-flop data acquiring unit 342 acquires data corresponding to the memory connection terminal MCP from such scan chain data 345 as faulty scan flip-flop data 341. Specifically, the faulty scan flip-flop data acquiring unit 342 receives information on the memory connection terminal MCP including the instance name from the memory connection terminal extracting unit 336, and searches the scan chain data 345 for an instance name 374 that matches the instance name.

[0063] Then, the faulty scan flip-flop data acquiring unit 342 acquires data of the scan flip-flop hit by the search as the faulty scan flip-flop data 341. In this example, the faulty scan flip-flop data acquiring unit 342 receives an instance name including “Q

[46] ” which is information of the memory connection terminal MCP, and acquires data of the scan flip-flop corresponding to the instance name as the faulty scan flip-flop data 341.

[0064] <Details of the estimated defective area> Fig. 10A is a diagram showing an example of processing contents when the estimated defective part limiting unit 337 in Fig. 8 limits an estimated defective part. Fig. 10B is a diagram showing an example of a schematic layout around the estimated defective part, which is a specific example of the processing contents shown in Fig. 10A. Fig. 10A differs from Fig. 4A described above in that the estimated defective part when an I / O block defect occurs.

[0065] When an I / O block failure occurs and the fail I / O value FIO matches the terminal ID value PID, the estimated failure location limiting unit 337 limits the estimated failure location to a portion related to the memory connection terminal MCP in the logic circuit area AR1 or the connection circuit area AR2a. On the other hand, when an I / O block failure occurs and the fail I / O value FIO does not match the terminal ID value PID, the estimated failure location limiting unit 337 determines the estimated failure location to be the entire array control circuit area AR2b.

[0066] Specifically, the peripheral circuit region AR2 in the memory circuit shown in Fig. 4B can be separated into a connection circuit region AR2a and an array control circuit region AR2b as shown in Fig. 10B. The array control circuit region AR2b is connected to the memory array region AR3 and is a circuit region that is mainly composed of analog circuits such as drivers and sense amplifiers. The connection circuit region AR2a is a circuit region that serves as an interface between the logic circuit region AR1 and the array control circuit region AR2b and is a circuit region that is composed of digital circuits.

[0067] As shown in Fig. 10B, the connection circuit area AR2a and the array control circuit area AR2b are separated by the scan chain SC as a boundary. Each scan flip-flop SFF included in the scan chain SC has a function of holding, for example, input data or output data of a memory circuit. Here, in the example shown in Fig. 10B, the memory connection terminal MCP, which is the presumed defective portion, is the scan flip-flop SFF

[46] having the terminal ID value PID of "46". The placement location of the scan flip-flop SFF

[46] is identified by the layout placement information 376 included in the faulty scan flip-flop data 341 shown in Fig. 9.

[0068] Therefore, the estimated defective part limiting section 337 determines the boundary of the estimated defective part based on the layout arrangement information 376. Then, when the fail I / O value FIO and the terminal ID value PID match, the estimated defective part limiting section 337 limits the estimated defective part to the signal transmission path SP3 of the memory connection terminal MCP, which is located on the logic circuit side of the determined boundary, as shown in Fig. 10B. This makes it possible to further narrow down the estimated defective part compared to the case of Fig. 4B.

[0069] On the other hand, when the fail I / O value FIO and the terminal ID value PID do not match, the estimated defective part limiting section 337 determines the estimated defective part to be the array control circuit area AR2b located on the memory circuit side with the scan chain SC as the boundary. This makes it possible to narrow down the estimated defective parts a little more than in the cases of Figures 4A and 4B.

[0070] <Failure analysis method> Fig. 11 is a flowchart showing an example of the process contents following Fig. 5 in the failure analysis method according to the second embodiment. In the flow shown in Fig. 11, compared to the flow shown in Fig. 6, step S301 is added between step S210 and step S212, and steps S213 and S214 are replaced with steps S302 and S303, respectively.

[0071] In step S301, when the failure mode FMD is an I / O block failure mode (step S210: YES), the estimated failure part limitation unit 337 acquires data corresponding to the memory connection terminal MCP from the scan chain data 345 as the failure scan flip-flop data 341, as shown in Fig. 9. Then, the estimated failure part limitation unit 337 determines the boundary of the estimated failure part based on the layout arrangement information 376 included in the failure scan flip-flop data 341, and proceeds to step S212.

[0072] Also, in step S302, if the fail I / O value FIO and the terminal ID value PID do not match (step S212: NO), the estimated defective part limiting unit 337 determines the estimated defective part to be the array control circuit area AR2b as described in Figures 10A and 10B. In this case, since the area is still large, it is necessary to perform light emission analysis or the like afterwards (step S105).

[0073] On the other hand, in step S303, if the fail I / O value FIO and the terminal ID value PID match (step S212: YES), the estimated fault location limiting unit 337 determines the estimated fault location to be a related portion of the memory connection terminal MCP in the logic circuit area AR1 or the connection circuit area AR2a, as shown in Fig. 10A. That is, the estimated fault location limiting unit 337 limits the estimated fault location to the signal transmission path SP3 of the memory connection terminal MCP, which is located on the logic circuit side of the determined boundary, as shown in Fig. 10B. In this case, physical analysis or the like targeting the estimated fault location can be performed thereafter more efficiently than in the case of Fig. 6 (step S106).

[0074] <Main Effects of the Second Embodiment> As described above, by using the method of the second embodiment, it is possible to obtain the same effects as those described in the first embodiment. Furthermore, by using data from the scan flip-flops SFF, it is possible to further narrow down the estimated defective parts, so that it is possible to further improve the efficiency of the defect analysis compared to the first embodiment.

[0075] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0076] For example, in the failure analysis device 400, 400a shown in Fig. 2 or Fig. 8, some or all of the components may be implemented in other forms without being limited to program processing by a processor. Specifically, for example, some or all of the units (331-338, 342) shown in Fig. 8 may be implemented in hardware such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or may be implemented in a combination of software and hardware.

[0077] The above-mentioned program may be stored in a non-transitory tangible computer-readable recording medium and then supplied to the computer. Examples of such a recording medium include magnetic recording media such as hard disk drives, optical recording media such as DVDs (Digital Versatile Discs) and Blu-ray discs, and semiconductor memories such as flash memories and SSDs. [Explanation of symbols]

[0078] 310: processor; 320: storage device; 322: fail bit data; 326: fault diagnosis result data; 327: memory connection terminal data; 332: fail I / O extraction unit; 336: memory connection terminal extraction unit; 337: estimated defective portion limitation unit

Claims

1. A failure analysis device for analyzing failures in a semiconductor device equipped with a logic circuit and a memory circuit, comprising: a storage device for storing fail bit data obtained by testing the memory circuit and fault diagnosis result data obtained by fault diagnosis of the test result of the logic circuit; A processor; having The processor, Extracting a fail I / O value from the fail bit data; extracting data on a memory connection terminal that is a connection terminal to the memory circuit from among the estimated defective points included in the failure diagnosis result data; determining whether the fail I / O value matches a terminal ID value included in the data of the memory connection terminal; Failure analysis device.

2. 2. The failure analysis apparatus according to claim 1, The processor, converting the fail logical address and the fail I / O value included in the fail bit data into a fail physical address; classifying a fail bit into one of a plurality of fail modes including a bit fail mode, a line fail mode, and an I / O block fail mode based on the fail physical address and the fail I / O value; When the classification result of the failure mode is the I / O block failure mode, it is determined whether the fail I / O value and the terminal ID value match or not. Failure analysis device.

3. 3. The failure analysis device according to claim 2, When the fail I / O value and the terminal ID value match, the processor limits the estimated defective location to a signal transmission path of the memory connection terminal in the logic circuit or a signal transmission path of the memory connection terminal in a peripheral circuit within the memory circuit. Failure analysis device.

4. 3. The failure analysis device according to claim 2, the storage device further stores scan chain data including identification information for each of a plurality of scan flip-flops constituting a scan chain and layout arrangement information for each of the plurality of scan flip-flops; The processor, acquiring data corresponding to the memory connection terminal from the scan chain data as faulty scan flip-flop data; determining a boundary of the estimated defective portion based on the layout arrangement information included in the faulty scan flip-flop data; Failure analysis device.

5. 5. The failure analysis apparatus according to claim 4, when the fail I / O value and the terminal ID value match, the processor limits the estimated defective location to a signal transmission path of the memory connection terminal located on the logic circuit side of the boundary; Failure analysis device.

6. A failure analysis method for a semiconductor device equipped with a logic circuit and a memory circuit, comprising the steps of: storing fail bit data obtained by testing the memory circuit and fault diagnosis result data obtained by fault diagnosis of the test result of the logic circuit in a storage device; Extracting a fail I / O value from the fail bit data; extracting data on a memory connection terminal that is a connection terminal to the memory circuit from among the estimated defective points included in the failure diagnosis result data; determining whether the fail I / O value matches a terminal ID value included in the data of the memory connection terminal; Failure analysis method.

7. 7. The failure analysis method according to claim 6, converting the fail logical address and the fail I / O value included in the fail bit data into a fail physical address; classifying a fail bit into one of a plurality of fail modes including a bit fail mode, a line fail mode, and an I / O block fail mode based on the fail physical address and the fail I / O value; When the classification result of the failure mode is the I / O block failure mode, it is determined whether the fail I / O value and the terminal ID value match or not. Failure analysis method.

8. 8. The failure analysis method according to claim 7, When the fail I / O value and the terminal ID value match, the estimated defective location is limited to a signal transmission path of the memory connection terminal in the logic circuit, or a signal transmission path of the memory connection terminal in a peripheral circuit within the memory circuit. Failure analysis method.

9. 8. The failure analysis method according to claim 7, storing scan chain data including identification information for each of a plurality of scan flip-flops constituting a scan chain and layout arrangement information for each of the plurality of scan flip-flops in the storage device; acquiring data corresponding to the memory connection terminal from the scan chain data as faulty scan flip-flop data; determining a boundary of the estimated defective portion based on the layout arrangement information included in the faulty scan flip-flop data; Failure analysis method.

10. 10. The failure analysis method according to claim 9, When the fail I / O value and the terminal ID value match, the estimated defective portion is limited to a signal transmission path of the memory connection terminal located on the logic circuit side of the boundary. Failure analysis method.

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