Semiconductor device

Abstract

To provide a semiconductor device consuming less power and capable of executing convolutional processing.SOLUTION: The semiconductor device comprises: a first circuit including a first holding part and a first transistor; and a second circuit including a second holding part and a second transistor. The first and second circuits are electrically connected to first and second input wires and first and second wires. The first holding part has a function of holding first current flowing through the first transistor while the second holding part has a function of holding second current flowing through the second transistor. The first and second currents are determined according to a filter value used for convolutional processing. Potential according to image data to be subjected to convolutional processing is inputted into the first and second input wires, so that the first circuit outputs current to one of the first wire and the second wire while the second circuit outputs current to the other of the first wire and the second wire. An amount of current outputted by the first and second circuits to the first wire or the second wire is determined according to the filter value and the image data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is actively progressing. Such integrated circuits incorporate the mechanisms of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to perform parallel processing with extremely low power consumption, compared to the von Neumann architecture, which consumes more power as the processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using SRAM (Static Random Access Memory). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In an artificial neural network, a calculation is performed in which the connection strength (sometimes called a weighting factor) of a synapse connecting two neurons is multiplied by a signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and add the connection strength of each synapse between a plurality of first neurons in the first layer and one of the second neurons in the second layer by each signal input from a plurality of first neurons in the first layer to one of the second neurons in the second layer, that is, a product-sum operation is required, and the number of connection strengths and the number of parameters indicating the signals are determined according to the scale of the artificial neural network. In addition, the second neuron performs a calculation using an activation function using the result of the product-sum operation between the connection strength of the synapse and the signal output by the first neuron, and outputs the result of the calculation as a signal to the third neuron in the third layer. In other words, in an artificial neural network, the greater the number of layers and the number of neurons, the greater the number of circuits corresponding to "neurons" and "synapses", and the amount of calculation may become enormous. This can result in increased power consumption and increased heat generation by the circuit.

[0007] There are also various models of artificial neural networks. For example, one model used in image analysis is called a convolutional neural network (CNN). A convolutional neural network is a type of neural network that exhibits excellent performance in the field of image recognition, but the amount of calculations is determined by the image resolution, the size of the filter, and other factors. Specifically, for example, the higher the image resolution, the larger the filter size, and the smaller the stride, the greater the amount of calculations in the convolutional neural network, which may increase the power consumption of the circuit.

[0008] Furthermore, as the number of circuits constituting a chip increases, power consumption increases and the amount of heat generated during operation of the device also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements contained in the chip are affected, so it is preferable that the circuits constituting the chip have circuit elements that are less susceptible to temperature effects. Furthermore, if the characteristics of the transistors, current sources, etc. contained in the chip vary, the results of the calculations will also vary.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device or the like that performs product-sum calculation and / or function calculation. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that performs convolution processing. Another object of one embodiment of the present invention is to provide a semiconductor device or the like for AI. Another object of one embodiment of the present invention is to provide a semiconductor device or the like for DNN. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that has low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is not easily affected by environmental temperature. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is not easily affected by characteristic variations of transistors. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is not easily affected by characteristic variations of a current source. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0010] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0011] (1) One aspect of the present invention is a semiconductor device having a first circuit and a second circuit. The first circuit has a first holding section and a first drive transistor, and the second circuit has a second holding section and a second drive transistor. The first circuit is electrically connected to a first input wiring, a second input wiring, a first wiring, and a second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and a second wiring. The first holding section has a function of holding a first potential according to a first current flowing from the first wiring between the source and drain of the first drive transistor, and the second holding section has a function of holding a second potential according to a second current flowing from the second wiring between the source and drain of the second drive transistor. The first circuit also has a function of outputting a first current to the first wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring, a function of outputting the first current to the second wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring, and a function of not outputting the first current to the first wiring and the second wiring when a second level potential is input to the first input wiring and a second level potential is input to the second input wiring. The second circuit has a function of outputting a second current to the second wiring when the first input wiring is input with a first level potential and the second input wiring is input with a second level potential, a function of outputting a second current to the first wiring when the first input wiring is input with a second level potential and the second input wiring is input with a first level potential, and a function of not outputting the second current to the first wiring and the second wiring when the first input wiring is input with a second level potential and the second input wiring is input with a second level potential. The current amounts of the first current and the second current are amounts according to a filter value included in a filter used for the convolution process. The first level potential and the second level potential input to the first input wiring and the second input wiring are determined according to image data to be subjected to the convolution process.

[0012] (2) Alternatively, one aspect of the present invention is a semiconductor device having a first circuit and a second circuit, and different components from those of the above (1). The first circuit has a first holding section and a first drive transistor, and the second circuit has a second holding section and a second drive transistor. The first circuit is electrically connected to a first input wiring, a second input wiring, a first wiring, and a second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and a second wiring. The first holding section has a function of holding a first potential corresponding to a first current flowing from the first wiring between the source and drain of the first drive transistor, and the second holding section has a function of holding a second potential corresponding to a second current flowing from the second wiring between the source and drain of the second drive transistor. The first drive transistor has a function of passing a first current corresponding to a first potential held between the source and drain of the first drive transistor, and the second drive transistor has a function of passing a second current corresponding to a second potential held between the source and drain of the second drive transistor. The first circuit has a function of outputting the first current to the first wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring during a first period, a function of outputting the first current to the second wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring during the first period, and a function of not outputting the first current to the first wiring and the second wiring when a second level potential is input to the first input wiring and a second level potential is input to the second input wiring during the first period. The second circuit has a function of outputting a second current to the second wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring during a first period, a function of outputting a second current to the first wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring during a first period, and a function of not outputting the second current to the first wiring and the second wiring when a second level potential is input to the first input wiring and a second level potential is input to the second input wiring during a first period.The respective current amounts of the first current and the second current correspond to filter values ​​included in a filter used in the convolution process, and the first level potential and the second level potential input to the first input wiring and the second input wiring, respectively, and the length of the first period are determined according to image data to be subjected to the convolution process.

[0013] (3) Alternatively, in one aspect of the present invention, in the configuration of (2) above, the first period may include a second period and a third period. Specifically, the first input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period. The second input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period. The first input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the third period. The second input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the third period. Note that the length of the third period is preferably 1.8 times or more and 2.2 times or less than the length of the second period.

[0014] (4) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the first circuit may have a first transistor, a second transistor, a third transistor, and a first capacitance, and the second circuit may have a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitance. Specifically, the first holding unit has a first transistor and a first capacitance, and the second holding unit has a fourth transistor and a second capacitance. A first terminal of the first transistor is electrically connected to a first terminal of the first capacitance and a gate of the first driving transistor, and a second terminal of the first transistor is electrically connected to the first wiring. Also, the first terminal of the first driving transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor, the second terminal of the second transistor is electrically connected to the first wiring, the gate of the second transistor is electrically connected to the first input wiring, the second terminal of the third transistor is electrically connected to the second wiring, and the gate of the third transistor is electrically connected to the second input wiring. Also, the first terminal of the fourth transistor is electrically connected to the first terminal of the second capacitance and the gate of the second driving transistor, and the second terminal of the fourth transistor is electrically connected to the second wiring. Also, the first terminal of the second driving transistor is electrically connected to the first terminal of the fifth transistor and the first terminal of the sixth transistor, the second terminal of the fifth transistor is electrically connected to the second wiring, the gate of the fifth transistor is electrically connected to the first input wiring, the second terminal of the sixth transistor is electrically connected to the first wiring, and the gate of the sixth transistor is electrically connected to the second input wiring.

[0015] (5) Alternatively, in one aspect of the present invention, in the above (4), the first circuit may have a seventh transistor, and the second circuit may have an eighth transistor. Specifically, the first terminal of the seventh transistor is electrically connected to the first terminal of the first driving transistor, the first terminal of the second transistor, and the first terminal of the third transistor, and the second terminal of the seventh transistor is electrically connected to either the first terminal or the second terminal of the first transistor. In addition, the first terminal of the eighth transistor is electrically connected to the first terminal of the second driving transistor, the first terminal of the fifth transistor, and the first terminal of the sixth transistor, and the second terminal of the eighth transistor is electrically connected to either the first terminal or the second terminal of the fourth transistor. In addition, the gate of the first transistor is electrically connected to the gate of the fourth transistor, the gate of the seventh transistor, and the gate of the eighth transistor.

[0016] (6) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the first circuit may have a first transistor, a second transistor, a third transistor, and a first capacitance, and the second circuit may have a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitance. Specifically, the first holding unit has a first transistor and a first capacitance, and the second holding unit has a fourth transistor and a second capacitance. A first terminal of the first transistor is electrically connected to a first terminal of the first capacitance and a gate of the first driving transistor, and a first terminal of the first driving transistor is electrically connected to a second terminal of the first transistor, a first terminal of the second transistor, and a first terminal of the third transistor. Also, the second terminal of the second transistor is electrically connected to the first wiring, the gate of the second transistor is electrically connected to the first input wiring, the second terminal of the third transistor is electrically connected to the second wiring, and the gate of the third transistor is electrically connected to the second input wiring. Also, the first terminal of the fourth transistor is electrically connected to the first terminal of the second capacitance and the gate of the second drive transistor, and the first terminal of the second drive transistor is electrically connected to the second terminal of the fourth transistor, the first terminal of the fifth transistor, and the first terminal of the sixth transistor. Also, the second terminal of the fifth transistor is electrically connected to the second wiring, the gate of the fifth transistor is electrically connected to the first input wiring, the second terminal of the sixth transistor is electrically connected to the first wiring, and the gate of the sixth transistor is electrically connected to the second input wiring.

[0017] (7) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the first circuit may have a third holding section and a third drive transistor, and the second circuit may have a fourth holding section and a fourth drive transistor. Specifically, the first circuit is electrically connected to the third wiring, and the second circuit is electrically connected to the third wiring. The third holding section has a function of holding a third potential corresponding to a third current flowing from the first wiring between the source and drain of the third drive transistor, and the fourth holding section has a function of holding a fourth potential corresponding to a fourth current flowing from the second wiring between the source and drain of the fourth drive transistor. The third drive transistor has a function of passing a third current corresponding to the held third potential between the source and drain of the third drive transistor, and the fourth drive transistor has a function of passing a fourth current corresponding to the held fourth potential between the source and drain of the fourth drive transistor. In addition, the semiconductor device has a function of switching a first current flowing through one of the first wiring or the second wiring to a third current, and switching a second current flowing through the other of the first wiring or the second wiring to a fourth current, depending on a signal input to the third wiring.

[0018] (8) Alternatively, one aspect of the present invention may be configured in any one of the above (1) to (7) to include a third circuit, a fourth circuit, and a fifth circuit. The third circuit has a function of supplying a first current corresponding to the filter value to the first circuit via a first wiring, and a function of supplying a second current corresponding to the filter value to the second circuit via a second wiring. The fourth circuit has a function of inputting a first level potential or a second level potential to the first input wiring according to image data, and a function of inputting the first level potential or the second level potential to the second input wiring according to the image data. The fifth circuit has a function of comparing the currents flowing from the first wiring and the second wiring, and outputting a potential corresponding to the product of the filter value and the image data from an output terminal of the fifth circuit.

[0019] (9) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (8) above and a housing. The electronic device may extract features of an image by convolution processing.

[0020] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, etc. may themselves be a semiconductor device or may have a semiconductor device.

[0021] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0022] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0023] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0024] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0025] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0026] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0027] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" may be rephrased as "resistance", "load", "region having a resistance value", and the like. Conversely, the terms "resistance", "load", and "region having a resistance value" may be rephrased as "resistance element", and the like. The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0028] In addition, in this specification, the term "capacitive element" may be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, etc. Therefore, in this specification, the terms "capacitive element", "parasitic capacitance", "gate capacitance", etc. may be replaced with terms such as "capacitance". Conversely, the term "capacitance" may be replaced with terms such as "capacitive element", "parasitic capacitance", "gate capacitance". In addition, the term "pair of electrodes" in "capacitance" may be replaced with "pair of conductors", "pair of conductive regions", "pair of regions", etc. The value of the electrostatic capacitance may be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0029] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain can be replaced. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0030] In addition, even when a single circuit element is illustrated on a circuit diagram, the circuit element may have multiple circuit elements. For example, when one resistor is illustrated on a circuit diagram, this includes the case where two or more resistors are electrically connected in series. For example, when one capacitance is illustrated on a circuit diagram, this includes the case where two or more capacitances are electrically connected in parallel. For example, when one transistor is illustrated on a circuit diagram, this includes the case where two or more transistors are electrically connected in series and the gates of the respective transistors are electrically connected to each other. Similarly, when one switch is illustrated on a circuit diagram, this includes the case where the switch has two or more transistors, the two or more transistors are electrically connected in series, and the gates of the respective transistors are electrically connected to each other.

[0031] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0032] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0033] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is described as a positive current amount. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0037] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0039] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes", "wirings", and the like are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring", "electrode", and the like, and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wirings", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0040] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0041] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, a transition metal other than the main component, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 15 element, and the like (however, oxygen and hydrogen are not included).

[0042] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Effect of the Invention

[0046] According to one embodiment of the present invention, a semiconductor device or the like that performs product-sum calculations and / or function calculations can be provided. According to one embodiment of the present invention, a semiconductor device or the like that performs convolution processing can be provided. According to one embodiment of the present invention, a semiconductor device or the like that consumes low power can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to the effects of environmental temperature can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to the effects of variations in characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to the effects of variations in characteristics of current sources can be provided. According to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

[0047] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0048] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of the semiconductor device. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 5] Each of FIGS. 5A to 5F is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 6] Each of FIGS. 6A to 6F is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 8] Each of FIGS. 8A to 8D is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 9] Each of FIGS. 9A to 9F is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 10] 10A and 10B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 15] Each of FIGS. 15A to 15C is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 17] Each of FIGS. 17A to 17C is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 18] Each of FIGS. 18A to 18C is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 19] Each of FIGS. 19A to 19C is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 20] Each of FIGS. 20A to 20C is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 23] 23A and 23B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 24] FIG. 24 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 25] FIG. 25 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 27] FIG. 27 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 29] FIG. 29 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 30] 30A and 30B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Diagram 31] FIG. 31 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 32] FIG. 32 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 33] FIG. 33 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 34]FIG. 34 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 35] FIG. 35 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 36] FIG. 36 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 37] FIG. 37 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 38] FIG. 38 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 39] FIG. 39 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 40] FIG. 40 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 41] Each of FIGS. 41A to 41C is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 42] FIG. 42 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 43] FIG. 43 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 44] FIG. 44 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 45] FIG. 45 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 46] FIG. 46 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 47] 47A and 47B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 48] FIG. 48 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 49] Each of FIGS. 49A to 49C is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 50] Each of FIGS. 50A to 50C is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 51]FIG. 51 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 52] FIG. 52 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Diagram 53] FIG. 53 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 54] FIG. 54 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 55] 55A and 55B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 56] Each of FIGS. 56A to 56C is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 57] 57A and 57B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 58] FIG. 58 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 59] 59A and 59B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 60] 60A and 60B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 61] 61A and 61B are diagrams showing voltage-current characteristics of a transistor included in a semiconductor device. [Figure 62] FIG. 62 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 63] FIG. 63 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 64] FIG. 64 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 65] FIG. 65 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 66] FIG. 66 is a block diagram showing an example of the configuration of a CNN. [Figure 67] FIG. 67A is a diagram showing an example of the configuration of a pixel, and FIG. 67B is a diagram showing an example of the configuration of a filter. [Figure 68] 68A and 68B are diagrams illustrating an example of the convolution process. [Figure 69] FIG. 69 is a diagram illustrating an example of the convolution process. [Figure 70] FIG. 70 is a diagram showing an example of the configuration of a feature map. [Figure 71] FIG. 71 is a block diagram illustrating an example of a semiconductor device that performs the calculation of the convolution process. [Figure 72] FIG. 72 is a block diagram illustrating an example of a semiconductor device that performs the calculation of the convolution process. [Figure 73] FIG. 73 is a block diagram illustrating an example of a semiconductor device that performs the calculation of the convolution process. [Figure 74] FIG. 74 is a block diagram illustrating an example of a semiconductor device that performs the calculation of the convolution process. [Figure 75] 75A and 75B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 76] 76A to 76D are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 77] FIG. 77 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 78] 78A to 78C are schematic cross-sectional views showing configuration examples of transistors. [Figure 79] FIG. 79 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 80] 80A and 80B are schematic cross-sectional views showing configuration examples of a transistor. [Figure 81] FIG. 81 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 82] FIG. 82A is a diagram for explaining the classification of IGZO crystal structures, FIG. 82B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 82C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. [Figure 83]FIG. 83A is a perspective view showing an example of a semiconductor wafer, FIG. 83B is a perspective view showing an example of a chip, and FIGS. 83C and 83D are perspective views showing an example of an electronic component. [Figure 84] FIG. 84 is a perspective view showing an example of an electronic device. [Figure 85] 85A to 85C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] In an artificial neural network (hereafter referred to as a neural network), the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining the strength of connections is sometimes called "learning."

[0050] In addition, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), it is possible for the network to output new information based on the connection strengths. In this way, the process of outputting new information based on given information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0051] Examples of neural network models include the Hopfield type and hierarchical type. In particular, a neural network with a multi-layer structure is sometimes called a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes called "deep learning."

[0052] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is included in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0053] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0054] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0055] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0056] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0057] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0058] The embodiments described in this specification are described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views, etc., the description of some components may be omitted in order to ensure the clarity of the drawings.

[0059] In this specification, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification reference numeral such as "_1", "[n]", "[m,n]" may be added to the reference numeral. In addition, when an identification reference numeral such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., when it is not necessary to distinguish between them in this specification, the identification reference numeral may not be added.

[0060] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0061] (Embodiment 1) In this embodiment, an arithmetic circuit that performs a product-sum operation and / or a function operation, which is a semiconductor device of one embodiment of the present invention, will be described.

[0062] <Hierarchical neural network> First, a hierarchical neural network will be described. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. FIG. 1A shows an example of a hierarchical neural network 100, which has a first layer to an Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. FIG. 1A shows the (k-1)th layer and the kth layer (where k is an integer of 3 or more and R-1 or less) as intermediate layers, and does not show the other intermediate layers.

[0063] Each layer of the neural network 100 has one or more neurons. In FIG. 1A, the first layer has neurons N 1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N 1 (k-1) Neuron N m (k-1) (where m is an integer equal to or greater than 1), and the kth layer has neurons N 1 (k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer has neurons N 1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0064] In addition, in Fig. 1A, neuron N 1 (1) , neuron N p(1) , neuron N 1 (k-1) , neuron N m (k-1) , neuron N 1 (k) , neuron N n (k) , neuron N 1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0065] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output to and from each neuron. j (k) Focus on.

[0066] Figure 1B shows the kth layer of neurons N j (k) and neuron N j (k) The input signal to neuron N j (k) 4 shows a signal output from the

[0067] Specifically, the (k-1)th layer neuron N 1 (k-1) Neuron N m (k-1) The output signals of each 1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z 1 (k-1) ~zm (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0068] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse that connects those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the kth layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the kth layer neuron N j (k) The signal input to can be expressed by equation (1.1).

[0069]

number

[0070] In other words, the (k-1)th layer of neurons N 1 (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to z 1 (k-1) ~z m (k-1) The weighting coefficients w 1 (k-1) j (k) Or even w m (k-1) j (k)Then, the kth layer neuron N j (k) For w 1 (k-1) j (k) z 1 (k-1) Or even w m (k-1) j (k) z m (k-1) At this time, the kth layer neuron N j (k) The sum of the signals input to j (k) becomes equation (1.2).

[0071]

number

[0072] In addition, the weighting factor w 1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron's signal z 1 (k-1) ~z m (k-1) The result of the multiplication and accumulation of and can be biased. When the bias is b, equation (1.2) can be rewritten as the following equation.

[0073]

number

[0074] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k)is defined as follows:

[0075]

number

[0076] The function f(u j (k) ) is an activation function in a hierarchical neural network, and may be a step function, a ramp function (ReLU function), a sigmoid function, a tanh function, a softmax function, or the like. The activation function may be the same for all neurons, or may be different. In addition, the activation function of a neuron may be the same for each layer, or may be different.

[0077] Incidentally, the signal, weighting coefficient w, or bias b output by the neuron of each layer may be an analog value or a digital value. The digital value may be, for example, a binary value or a ternary value. It may also be a value with a larger number of bits. For example, in the case of an analog value, a linear ramp function, a sigmoid function, or the like may be used as an activation function. In the case of a binary digital value, for example, a step function with an output of -1 or 1, or 0 or 1 may be used. In addition, the signal output by the neuron of each layer may be three or more values. For example, as an activation function that outputs three values, for example, a step function with an output of -1, 0, or 1, or a step function with an output of 0, 1, or 2 may be used. In addition, as an activation function that outputs five values, for example, a step function with an output of -2, -1, 0, 1, or 2 may be used. By using digital values ​​for at least one of the signals, weighting coefficients w, or biases b output by the neurons in each layer, it is possible to reduce the circuit size, reduce power consumption, increase the calculation speed, etc. Also, by using analog values ​​for at least one of the signals, weighting coefficients w, or biases b output by the neurons in each layer, it is possible to improve the accuracy of calculations.

[0078] In neural network 100, when an input signal is input to the first layer (input layer), each layer from the first layer (input layer) to the last layer (output layer) generates an output signal based on the signal input from the previous layer using formula (1.1), formula (1.2) (or formula (1.3)), and formula (1.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0079] <Example of arithmetic circuit configuration> Here, an example of a calculation circuit capable of performing the calculations of formula (1.2) (or formula (1.3)) and formula (1.4) in the above-mentioned neural network 100 will be described. In addition, in the calculation circuit, as an example, the weight coefficients of the synapse circuits of the neural network 100 are set to a binary value (a combination of "-1" and "+1", or a combination of "0" and "+1", etc.), a ternary value (a combination of "-1", "0", "1", etc.), or a multi-value of four or more values ​​(in the case of five values, a combination of "-2", "-1", "0", "1", "2", etc.), and the activation function of the neuron is set to a function that outputs a binary value (a combination of "-1" and "+1", or a combination of "0", "+1", etc.), a ternary value (a combination of "-1", "0", "1", etc.), or a multi-value of four or more values ​​(in the case of four values, a combination of "0", "1", "2", "3", etc.). In addition, in this specification, one of the weight coefficients and the value of the signal input from the neuron in the previous layer to the neuron in the next layer (sometimes referred to as the calculation value) may be referred to as the first data, and the other may be referred to as the second data. Note that the weight coefficients and the calculation value of the synapse circuit of the neural network 100 are not limited to digital values, and at least one of them may be an analog value.

[0080] 2 is a semiconductor device having an array part ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP, for example. The arithmetic circuit 110 corresponds to the k-th layer neuron N 1 (k)Neuron N n (k) The signal z input to 1 (k-1) ~z m (k-1) Then, neuron N 1 (k) Neuron N n (k) The signal z output from each 1 (k) ~z n (k) This is a circuit that generates the following:

[0081] The entire arithmetic circuit 110 or a part thereof may be used for purposes other than neural networks, AI, etc. For example, when performing product-sum calculations, matrix calculations, etc. in graphics-oriented calculations (such as convolution processing for extracting image features), scientific calculations, etc., the entire arithmetic circuit 110 or a part thereof may be used for processing. In other words, the entire arithmetic circuit 110 or a part thereof may be used not only for AI-oriented calculations, but also for general calculations.

[0082] For example, the circuit ILD is electrically connected to wirings IL[1] to IL[n] and wirings ILB[1] to ILB[n]. For example, the circuit WLD is electrically connected to wirings WLS[1] to WLS[m]. For example, the circuit XLD is electrically connected to wirings XLS[1] to XLS[m]. For example, the circuit AFP is electrically connected to wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n].

[0083] <<Array section ALP>> The array section ALP has, for example, m×n circuits MP. For example, the circuits MP are arranged in a matrix of m rows and n columns in the array section ALP. In addition, in FIG. 2, the circuit MP located in the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) is represented as the circuit MP[i,j]. However, in FIG. 2, only the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n], and the circuit MP[m,n] are illustrated, and the other circuits MP are omitted from the illustration.

[0084] As an example, the circuit MP[i,j] is electrically connected to a wiring IL[j], a wiring ILB[j], a wiring WLS[i], a wiring XLS[i], a wiring OL[j], and a wiring OLB[j].

[0085] A circuit MP[i,j] is, for example, a network of neurons N i (k-1) and neuron N j (k) Specifically, the circuit MP[i,j] holds information (such as a potential, a resistance value, or a current value) corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. The circuit MP[i,j] also holds information corresponding to the first data (weighting coefficient) input from the neuron N i (k-1) The signal z output from i (k-1) (sometimes called the other of the first data and the second data. Here, called the second data) and the first data. As a specific example, the circuit MP[i,j] receives the second data z i (k-1)By inputting the first data and the second data, information corresponding to the product of the first data and the second data (e.g., a current, a voltage, etc.) or information related to the product of the first data and the second data (e.g., a current, a voltage, etc.) is output to the wiring OL[j] and the wiring OLB[j]. Note that, although an example in which the wiring IL[j] and the wiring ILB[j] are arranged has been shown, one embodiment of the present invention is not limited to this. Only one of the wiring IL[j] and the wiring ILB[j] may be arranged.

[0086] <<Circuit ILD>> For example, the circuit ILD transmits first data w , which is a weighting coefficient, to each of the circuits MP[1,1] to MP[m,n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. 1 (k-1) 1 (k) Or even w m (k-1) n (k) As a specific example, the circuit ILD has a function of inputting information (e.g., potential, resistance value, current value, etc.) corresponding to the circuit MP[i,j]. i (k-1) j (k) Information corresponding to the above (for example, a potential, a resistance value, or a current value) is supplied via the wiring IL[j] and the wiring ILB[j].

[0087] <<Circuit XLD>> For example, the circuit XLD is connected to the neurons N 1 (k-1) Neuron N m (k-1) The second data z corresponding to the calculated value output from 1 (k-1) ~z m (k-1) Specifically, the circuit XLD provides the neurons N i(k-1) The second data z output from i (k-1) Information (for example, a potential, a current value, and the like) corresponding to the signal is supplied through the wiring XLS[i]. Note that although an example in which the wiring XLS[i] is provided is shown, one embodiment of the present invention is not limited thereto. For example, in the arithmetic circuit 110 in FIG. 2, the wiring XLS[i] may be a plurality of wirings. As a specific example, FIG. 3 shows an arithmetic circuit 120 in which the wiring XLS[i] electrically connected to the circuit MP[i,j] of the arithmetic circuit 110 is replaced with two wirings, that is, a wiring X1L and a wiring X2L. Note that although an example in which the wiring XLS[i] is provided is shown, one embodiment of the present invention is not limited thereto. In addition to the wiring XLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring XLS[i] may be separately provided.

[0088] <<Circuit WLD>> For example, the circuit WLD has a function of selecting a circuit MP to which information (e.g., potential, resistance, current, etc.) corresponding to the first data input from the circuit ILD is to be written. For example, when writing information (e.g., potential, resistance, current, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit WLD may supply a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WLS[i], and may supply a potential for turning off the write switching elements included in the circuits MP other than the i-th row to the wiring WLS. Note that although an example in which the wiring WLS[i] is provided has been shown, one embodiment of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring WLS[i] may be provided separately.

[0089] Note that although a configuration example in which the wiring WLS[i] is provided in the arithmetic circuit 110 in FIG. 2 is shown, one embodiment of the present invention is not limited thereto. For example, the wiring WLS[i] may be replaced with a plurality of wirings. For example, the wiring X1L[i] of the arithmetic circuit 120 in FIG. 3 may also be used as a selection signal line for writing information to the circuits MP[i,1] to MP[i,n]. Specifically, as in the arithmetic circuit 130 shown in FIG. 4, the wiring X1L[i] of the arithmetic circuit 120 may be a wiring WX1L[i], and the wiring WX1L may be electrically connected to the circuit WLD and the circuit XLD. Note that when a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] is supplied to the wiring WX1L[i] from the circuit WLD, the circuit XLD preferably has a function of bringing the circuit XLD and the wiring WX1L into a non-conductive state. Also, through the wire WX1L[i], the neuron N 1 (k-1) Neuron N m (k-1) The second data z corresponding to the calculated value output from 1 (k-1) ~z m (k-1) When the signal is supplied from the circuit XLD to the circuits MP[i,1] to MP[i,n], the circuit WLD preferably has a function of bringing the circuit WLD and the wiring WX1L into a non-conductive state.

[0090] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] is electrically connected to each of the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] generates a signal according to the respective pieces of information (e.g., potential, current value, etc.) input from the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] compares the respective pieces of information (e.g., potential, current value, etc.) input from the wirings OL[j] and OLB[j], and generates a signal according to the comparison result. The signal is input to the neuron N j (k) The signal z output from j(k) That is, the circuits ACTF[1] to ACTF[n] function as, for example, circuits that perform the calculation of the activation function of the neural network described above. However, one embodiment of the present invention is not limited thereto. For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting an output impedance. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of converting a current or a charge into a voltage. Alternatively, for example, the circuit ACTF[j] may have a function of initializing the potentials of the wiring OL[j] and the wiring OLB[j].

[0091] 2 to 4 show examples in which the circuit ACTF is provided in the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130, respectively, but one embodiment of the present invention is not limited to this. For example, the circuit ACTF does not necessarily have to be provided in the circuit AFP.

[0092] Next, the circuits ACTF[1] to ACTF[n] will be described. The circuits ACTF[1] to ACTF[n] can have the circuit configuration shown in FIG. 5A, for example. FIG. 5A shows an example in which a signal z j (k) Specifically, FIG. 5A shows a circuit that generates an output signal z j (k) 4 shows an example of an activation function calculation circuit that outputs

[0093] In FIG. 5A, the circuit ACTF[j] has, as an example, a resistor RE, a resistor REB, and a comparator CMP. The resistors RE and REB have a function of converting a current into a voltage. Therefore, as long as the element or circuit has a function of converting a current into a voltage, it is not limited to a resistor. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the second input terminal of the comparator CMP. In addition, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor RE and the second terminal of the resistor REB may be connected to the same wiring. Or, they may be connected to different wirings having the same potential.

[0094] The resistance values ​​of the resistors RE and REB are preferably equal to each other. For example, it is desirable that the difference between the resistance values ​​of the resistors RE and REB is within 10% of the resistance value of the resistor RE, more preferably within 5%. However, one aspect of the present invention is not limited to this. In some cases or depending on the situation, the resistance values ​​of the resistors RE and REB may be different from each other.

[0095] For example, the wiring VAL functions as a wiring that provides a constant voltage. The constant voltage can be, for example, a high-level potential VDD, a low-level potential VSS, a ground potential (GND), or the like. It is preferable that the constant voltage is appropriately set according to the configuration of the circuit MP. For example, a pulse signal may be supplied to the wiring VAL instead of a constant voltage.

[0096] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMP. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the second input terminal of the comparator CMP.

[0097] As an example, the comparator CMP has a function of comparing the voltages input to the first input terminal and the second input terminal, and outputting a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP can output a high-level potential from the output terminal of the comparator CMP when the voltage input to the second input terminal is higher than the voltage input to the first input terminal, and can output a low-level potential from the output terminal of the comparator CMP when the voltage input to the first input terminal is higher than the voltage input to the second input terminal. In other words, the potentials output from the output terminal of the comparator CMP are two, a high-level potential and a low-level potential, so that the output signal z output by the circuit ACTF[j] j (k) For example, the high level potential and the low level potential output from the output terminal of the comparator CMP are expressed as the output signal z j (k) In some cases, the high level potential and the low level potential output from the output terminal of the comparator CMP correspond to the output signal z j (k) may correspond to "+1" and "0".

[0098] In addition, in the circuit ACTF[j] of FIG. 5A, the resistors RE and REB are used, but they are not limited to resistors as long as they are elements or circuits having a function of converting a current into a voltage. Therefore, the resistors RE and REB of the circuit ACTF[j] of FIG. 5A can be replaced with other circuit elements. For example, the circuit ACTF[j] shown in FIG. 5B is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 5A are replaced with capacitors CE and CEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 5A. Note that the capacitance values ​​of the capacitors CE and CEB are preferably equal to each other. For example, it is desirable that the difference between the capacitance values ​​of the capacitors CE and CEB is within 10% of the capacitance value of the capacitor CE, more preferably within 5%. However, one embodiment of the present invention is not limited to this. Note that a circuit for initializing the charge stored in the capacitors CE and CEB may be provided. For example, a switch may be provided in parallel with the capacitor CE. That is, the second terminal of the switch may be connected to the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitance CE, the wiring OL[j], and the first input terminal of the comparator CMP. Alternatively, the second terminal of the switch may be connected to a wiring different from the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitance CE, the wiring OL[j], and the first input terminal of the comparator CMP. In addition, the circuit ACTF[j] shown in FIG. 5C is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 5A are replaced with diode elements DE and DEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 5A. It is desirable to appropriately change the orientation (the connection point between the anode and the cathode) of the diode elements DE and DEB depending on the magnitude of the potential of the wiring VAL.

[0099] Also, the comparator CMP included in the circuit ACTF[j] in Figures 5A to 5C can be replaced with an operational amplifier OP, for example. The circuit ACTF[j] shown in Figure 5D is a circuit diagram in which the comparator CMP of the circuit ACTF[j] in Figure 5A is replaced with an operational amplifier OP.

[0100] Also, the circuit ACTF[j] of FIG. 5B may be provided with switches S01a and S01b. This allows the circuit ACTF[j] to hold potentials corresponding to the currents input from the wiring OL[j] and wiring OLB[j] to the capacitance CE and capacitance CEB, respectively. As an example of a specific circuit, as shown in FIG. 5E, the wiring OL[j] is electrically connected to the first terminal of the switch S01a, the first terminal of the capacitance CE and the first input terminal of the comparator CMP are electrically connected to the second terminal of the switch S01a, the wiring OLB[j] is electrically connected to the first terminal of the switch S01b, and the first terminal of the capacitance CEB and the second input terminal of the comparator CMP are electrically connected to the second terminal of the switch S01b. In the circuit ACTF[j] of FIG. 5E, when the potentials of the wiring OL[j] and wiring OLB[j] are input to the first input terminal and the second input terminal of the comparator CMP, respectively, this can be done by turning on the switches S01a and S01b. Then, by turning off the switches S01a and S01b, the potentials input to the first and second input terminals of the comparator CMP can be held in the capacitors CE and CEB. The switches S01a and S01b can be, for example, electrical switches such as analog switches and transistors. The switches S01a and S01b can be, for example, mechanical switches. When transistors are used as the switches S01a and S01b, the transistors can be OS transistors or transistors having silicon in their channel formation regions (hereinafter, referred to as Si transistors). Alternatively, the voltage values ​​of the capacitors CE and CEB can be controlled by controlling the period during which the switches S01a and S01b are kept on. For example, when the current values ​​flowing through the capacitors CE and CEB are large, the voltage values ​​of the capacitors CE and CEB can be prevented from becoming too large by shortening the period during which the switches S01a and S01b are kept on.

[0101] 5A to 5C and 5E, the comparator CMP included in the circuit ACTF[j] may be, for example, a chopper type comparator. The comparator CMP shown in FIG. 5F is a chopper type comparator, and the comparator CMP has switches S02a, S02b, and S03, a capacitance CC, and an inverter circuit INV3. The switches S02a, S02b, and S03 may be mechanical switches, OS transistors, Si transistors, or other transistors, similar to the above-mentioned switches S01a and S01b.

[0102] A first terminal of the switch S02a is electrically connected to the terminal VinT, a first terminal of the switch S02b is electrically connected to the terminal VrefT, and a second terminal of the switch S02a is electrically connected to the second terminal of the switch S02b and the first terminal of the capacitor CC. The second terminal of the capacitor CC is electrically connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3 and the second terminal of the switch S03.

[0103] The terminal VinT functions as a terminal for inputting an input potential to the comparator CMP, the terminal VrefT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal VoutT functions as a terminal for outputting an output potential from the comparator CMP. The terminal VinT can correspond to one of the first terminal or the second terminal of the comparator CMP in Figures 5A to 5C and 5E, and the terminal VrefT can correspond to the other of the first terminal or the second terminal of the comparator CMP in Figures 5A to 5C and 5E.

[0104] The circuit ACTF[j] of FIG. 5A to FIG. 5E outputs an output signal z j (k) The activation function ACTF[j] outputs the output signal z j (k) Alternatively, the signal may be output as three or more values ​​or as an analog value.

[0105] 6A to 6F show a signal z in response to a current input from the wiring OL[j] and the wiring OLB[j]. j (k) is a circuit that generates an output signal z represented by a ternary value. j (k) 4 shows an example of an activation function calculation circuit that outputs

[0106] The circuit ACTF[j] shown in FIG. 6A includes a resistor RE, a resistor REB, a comparator CMPa, and a comparator CMPb. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMPa, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the first input terminal of the comparator CMPb. In addition, the second input terminal of the comparator CMPa and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0107] The wire VrefL is a constant voltage V ref It acts as a voltage line that gives V ref It is preferable that V is, for example, equal to or higher than GND and equal to or lower than VDD. ref V may be at a potential lower than GND or higher than VDD. ref is treated as a reference potential (potential for comparison) in comparators CMPa and CMPb.

[0108] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMPa. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the first input terminal of the comparator CMPb.

[0109] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPa according to the comparison result. For example, the comparator CMPa detects that the voltage input to the second input terminal (V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and the voltage (V ref ) the voltage input to the first input terminal is higher than the low level potential, a low level potential can be output from the output terminal of the comparator CMPa.

[0110] Similar to the comparator CMPa, the comparator CMPb compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb detects that the voltage input to the second input terminal (V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPb, and the voltage (V ref ) is higher than the voltage input to the first input terminal, a low-level potential can be output from the output terminal of the comparator CMPb.

[0111] At this time, the potentials output from the output terminals of the comparators CMPa and CMPb are, for example, a ternary output signal z j (k) For example, when a high-level potential is output from the output terminal of the comparator CMPa and a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to "+1", and when a low level potential is output from the output terminal of the comparator CMPa and a high level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to "-1", and when a low level potential is output from the output terminal of the comparator CMPa and a low level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) can be set to "0".

[0112] Moreover, the circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 6A, and can be modified according to circumstances. For example, if it is desired to combine the two output results of the comparators CMPa and CMPb in the circuit ACTF[j] of FIG. 6A into one signal, a conversion circuit TRF can be provided in the circuit ACTF[j]. The circuit ACTF[j] of FIG. 6B is a configuration example in which a conversion circuit TRF is provided in the circuit ACTF[j] of FIG. 6A, and the output terminals of the comparators CMPa and CMPb are electrically connected to the input terminals of the conversion circuit TRF. A specific example of the conversion circuit TRF is a digital-to-analog conversion circuit (in this case, a signal z j (k) is an analog value.)

[0113] Also, for example, in Fig. 6A, the wiring VrefL electrically connected to the second input terminals of the comparators CMPa and CMPb may be replaced with separate wirings, wiring Vref1L and wiring Vref2L. The circuit ACTF[j] in Fig. 6C has a configuration in which the second input terminal of the comparator CMPa included in the circuit ACTF[j] in Fig. 6A is electrically connected to the wiring Vref1L instead of the wiring VrefL, and the second input terminal of the comparator CMPb is electrically connected to the wiring Vref2L instead of the wiring VrefL. By setting the potentials input to the wiring Vref1L and the wiring Vref2L to different values, the reference potentials in the comparators CMPa and CMPb can be set separately.

[0114] Also, for example, an amplifier circuit or an impedance conversion circuit may be used as a configuration different from the circuit ACTF[j] in Figures 6A to 6C. For example, the circuit ACTF[j] shown in Figure 6D can be applied to the circuit AFP of the arithmetic circuit 110 in Figure 2. The circuit ACTF[j] in Figure 6D has a resistor RE, a resistor REB, and an operational amplifier OPa and an operational amplifier OPb, and functions as an amplifier circuit.

[0115] The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the non-inverting input terminal of the operational amplifier OPb. The inverting input terminal of the operational amplifier OPa is electrically connected to the output terminal of the operational amplifier OPa, and the inverting input terminal of the operational amplifier OPb is electrically connected to the output terminal of the operational amplifier OPb. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0116] In other words, the operational amplifiers OPa and OPb included in the circuit ACTF[j] in Fig. 6D are connected as voltage followers. As a result, the potential output from the output terminal of the operational amplifier OPa is approximately equal to the potential input to the non-inverting input terminal of the operational amplifier OPa, and the potential output from the output terminal of the operational amplifier OPb is approximately equal to the potential input to the non-inverting input terminal of the operational amplifier OPb. In this case, the output signal z j (k) are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminals of the comparator CMP. The output from the comparator CMP is then used as the output signal z j (k) It is also possible to use the following.

[0117] Also, for example, an integrating circuit or a current-voltage conversion circuit may be used as a configuration different from the circuit ACTF[j] of Figures 6A to 6D. Furthermore, an integrating circuit or a current-voltage conversion circuit may be configured using an operational amplifier. As an example, the circuit ACTF[j] shown in Figure 6E can be applied to the circuit AFP of the arithmetic circuit 110 of Figure 2. The circuit ACTF[j] of Figure 6E has an operational amplifier OPa, an operational amplifier OPb, a load LEa, and a load LEb.

[0118] The wiring OL[j] is electrically connected to a first input terminal (e.g., inverting input terminal) of the operational amplifier OPa and a first terminal of the load LEa, and the wiring OLB[j] is electrically connected to a first input terminal (e.g., inverting input terminal) of the operational amplifier OPb and a first terminal of the load LEb. In addition, the second input terminal (e.g., non-inverting input terminal) of the operational amplifier OPa is electrically connected to the wiring Vref1L, and the second input terminal (e.g., non-inverting input terminal) of the operational amplifier OPb is electrically connected to the wiring Vref2L. The second terminal of the load LEa is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load LEb is electrically connected to the output terminal of the operational amplifier OPb.

[0119] In addition, the wiring Vref1L and the wiring Vref2L function as wirings that supply voltages equal to or different from each other. Therefore, the wiring Vref1L and the wiring Vref2L may be combined into one wiring.

[0120] In the circuit ACTF[j] in FIG. 6E, the loads LEa and LEb can be, for example, resistors and capacitors. In particular, by using capacitors as the loads LEa and LEb, the operational amplifier OPa and the load LEa, and the operational amplifier OPb and the load LEb each function as an integrating circuit. That is, a charge is stored in each of the capacitors (load LEa, load LEb) according to the amount of current flowing through the wiring OL[j] or wiring OLB[j]. That is, the current flowing from the wiring OL[j] and wiring OLB[j] is integrated by the integrating circuit, and the amount of current is converted into a voltage, which is output as a signal z j (k) The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminals of the comparator CMP. Then, the output from the comparator CMP is output as the output signal z j (k)A circuit for initializing the charges stored in the capacitances of the loads LEa and LEb may be provided. For example, a switch may be provided in parallel with the load LEa (capacitor). That is, a second terminal of the switch may be connected to the output terminal of the operational amplifier OPa, and a first terminal of the switch may be connected to the wiring OL[j] and a first input terminal (for example, an inverting input terminal) of the operational amplifier OPa.

[0121] In addition, in the circuit ACTF[j] of FIG. 6E, when it is desired to convert the current flowing from the wiring OL[j] and wiring OLB[j] into a voltage and output it, the loads LEa and LEb can be resistors other than capacitors.

[0122] Also, for example, as a configuration different from the circuit ACTF[j] in Figures 6A to 6E, a circuit ACTF[j] shown in Figure 6F can be applied to the circuit AFP of the arithmetic circuit 110 in Figure 2. The circuit ACTF[j] in Figure 6F has a resistor RE, a resistor REB, an analog-digital conversion circuit ADCa, and an analog-digital conversion circuit ADCb.

[0123] The wiring OL[j] is electrically connected to the input terminal of the analog-digital conversion circuit ADCa and the first terminal of the resistor RE, and the wiring OLB[j] is electrically connected to the input terminal of the analog-digital conversion circuit ADCb and the first terminal of the resistor REB. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0124] In the circuit ACTF[j] in FIG. 6F, the potentials of the first terminals of the resistors RE and REB are determined according to the currents flowing from the wirings OL[j] and OLB[j]. The circuit ACTF[j] then converts the analog potentials into digital values ​​of two or more values ​​(e.g., 256 values) using the analog-digital conversion circuits ADCa and ADCb, and outputs the signal z j (k) It has the function of outputting as

[0125] The resistors RE and REB shown in Figures 6A to 6D and 6F can be replaced with the capacitors CE and CEB, or the diode elements DE and DEB, as in Figures 5B and 5C. In particular, when the resistors RE and REB shown in Figures 6A to 6D and 6F are replaced with the capacitors CE and CEB, the potentials input from the wirings OL[j] and OLB[j] can be held by providing switches S01a and S01b, as in Figure 5E.

[0126] 2 to 4 show examples in which wirings IL, ILB, OL, and OLB are arranged, but one embodiment of the present invention is not limited to this. For example, each of the arithmetic circuits 110, 120, and 130 may have a configuration in which the wirings IL and OL are combined into one wiring and the wirings ILB and OLB are combined into one wiring. FIG. 7 shows a specific configuration. The arithmetic circuit 140 shown in FIG. 7 includes switching circuits TW[1] to TW[n].

[0127] Each of the switching circuits TW[1] to TW[n] has a terminal TSa, a terminal TSaB, a terminal TSb, a terminal TSbB, a terminal TSc, and a terminal TScB.

[0128] The terminal TSa is electrically connected to the wiring OL[j], the terminal TSb is electrically connected to the circuit ILD, and the terminal TSc is electrically connected to the circuit ACTF[j]. The terminal TSaB is electrically connected to the wiring OLB[j], the terminal TSbB is electrically connected to the circuit ILD, and the terminal TScB is electrically connected to the circuit ACTF[j].

[0129] The switching circuit TW[j] has a function of bringing the terminal TSa into a conductive state between the terminal TSb and one of the terminals TSc and the terminal TSa and the other terminal TSb and the terminal TSc into a non-conductive state. The switching circuit TW[j] also has a function of bringing the terminal TSaB into a conductive state between the terminal TSbB and one of the terminals TScB and the terminal TSaB and the other terminal TSbB and the terminal TScB into a non-conductive state.

[0130] That is, the first data w, which is a weighting coefficient, is assigned to any one of the circuits MP[1,j] to MP[m,j]. 1 (k-1) 1 (k) Or even w m (k-1) n (k) When it is desired to input information (for example, a potential, a resistance value, a current value, or the like) corresponding to the first data w from the circuit ILD to any one of the circuits MP[1,j] to MP[m,j] via the wiring OL[j] or the wiring OLB[j], the first data w 1 (k-1) 1 (k) Or even w m (k-1) n (k) It is possible to provide information corresponding to the above (for example, potential, resistance value, current value, etc.).

[0131] Furthermore, when the circuit ACTF[j] wishes to obtain the result of the sum of products (equation (1.2)) of the weight coefficients and the neuron signals calculated by the circuits MP[1,j] to MP[m,j], the switching circuit TW[j] can supply information corresponding to the sum of products (e.g., potential, current value, etc.) from the wiring OL[j] and wiring OLB[j] to the circuit ACTF[j] by bringing the terminals TSa and TSc into a conductive state and bringing the terminals TSaB and TScB into a conductive state. Also, in the circuit ACTF[j], the value of the activation function is calculated from the input sum of products, and the signal z is output as the neuron's output signal.j (k) can be obtained.

[0132] Next, a description will be given of the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 140. Fig. 8A shows a configuration example of the switching circuit TW[j] and the circuit ILD that can be applied to the arithmetic circuit 140. Note that Fig. 8A also shows a wiring OL[j], a wiring OLB[j], and a circuit AFP in order to show the configuration of the electrical connection between the switching circuit TW[j] and the circuit ILD.

[0133] The switching circuit TW[j] includes, for example, a switch SWI, a switch SWIB, a switch SWO, a switch SWOB, a switch SWL, a switch SWLB, a switch SWH, and a switch SWHB.

[0134] The circuit ILD includes a current source circuit ISC as an example. However, one embodiment of the present invention is not limited thereto. For example, a voltage source circuit may be arranged instead of the current source circuit ISC. The current source circuit ISC has a function of causing a current corresponding to a weighting coefficient (first data) input to the circuit MP to flow to the wiring OL[j] and / or the wiring OLB[j]. Note that at least one current source circuit ISC may be arranged as a circuit for the wiring OL[j] and a circuit for the wiring OLB[j], as separate circuits. Alternatively, as shown in FIG. 8A, at least one current source circuit ISC may be provided for a pair of wirings, ie, the wiring OL[j] and the wiring OLB[j].

[0135] The current source circuit ISC has one or more constant current sources, and in FIG. 8A, as an example, the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant current source circuit ISC3 are included as the multiple constant current sources. The current source circuit ISC has, as an example, multiple switches to select the multiple constant current sources, and in FIG. 8A, as the multiple switches, the current source circuit ISC has a switch SWC1, a switch SWC2, and a switch SWC3. If the current source circuit ISC has only one constant current source, the current source circuit ISC does not need to have a switch. Alternatively, if the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant current source circuit ISC3 each have a function of controlling whether or not to output a current, the switch SWC1, the switch SWC2, and the switch SWC3 may not be provided.

[0136] Incidentally, it is preferable that the currents flowing through the wiring OL[j] and the wiring OLB[j] are generated by the same current source circuit ISC, as shown in FIG. 8A. When the currents flowing through the wiring OL[j] and the wiring OLB[j] are generated by different current source circuits, the characteristics of the transistors may vary due to the transistor manufacturing process, and the performance may differ between the different current source circuits. On the other hand, when the same current source circuit is used, it is possible to supply the same amount of current to the wiring OL[j] and the wiring OLB[j], improving the accuracy of the calculation.

[0137] As for the switches SWI, SWIB, SWO, SWOB, SWL, SWLB, SWH, SWHB, SWC1, SWC2, and SWC3 described in FIG. 8A, for example, analog switches, electrical switches such as transistors, mechanical switches, etc. can be used, similar to the switches S01a and S01b.

[0138] In one example of the switching circuit TW[j], the terminal TSa is electrically connected to a first terminal of the switch SWI, a first terminal of the switch SWO, a first terminal of the switch SWL, and a first terminal of the switch SWH. The terminal TSaB is electrically connected to a first terminal of the switch SWIB, a first terminal of the switch SWOB, a first terminal of the switch SWLB, and a first terminal of the switch SWHB. The second terminal of the switch SWI is electrically connected to a terminal TSb1. The second terminal of the switch SWIB is electrically connected to a terminal TSbB1. The second terminal of the switch SWO is electrically connected to a terminal TSc. The second terminal of the switch SWOB is electrically connected to a terminal TScB. The second terminal of the switch SWL is electrically connected to a terminal TSb2. The second terminal of the switch SWLB is electrically connected to a terminal TSbB2. The second terminal of the switch SWH is electrically connected to a terminal TSb3. The second terminal of the switch SWHB is electrically connected to a terminal TSbB3.

[0139] Terminals TSb1, TSb2, and TSb3 shown in Fig. 8A correspond to the terminal TSb shown in Fig. 7. Terminals TSbB1, TSbB2, and TSbB3 shown in Fig. 8A correspond to the terminal TSbB shown in Fig. 7.

[0140] In the current source circuit ISC included in the circuit ILD, the terminal TSb1 is electrically connected to the first terminal of the switch SWC1, the first terminal of the switch SWC2, and the first terminal of the switch SWC3. The terminal TSbB1 is electrically connected to the first terminal of the switch SWC1, the first terminal of the switch SWC2, and the first terminal of the switch SWC3. The second terminal of the switch SWC1 is electrically connected to the output terminal of the constant current source circuit ISC1, the second terminal of the switch SWC2 is electrically connected to the output terminal of the constant current source circuit ISC2, and the second terminal of the switch SWC3 is electrically connected to the output terminal of the constant current source circuit ISC3. The input terminal of the constant current source circuit ISC1, the input terminal of the constant current source circuit ISC2, and the input terminal of the constant current source circuit ISC3 are each electrically connected to the wiring VSO.

[0141] In FIG. 8A, the constant current source circuits ISC1, ISC2, and ISC3 are configured such that the output terminals are electrically connected to the terminals of the respective switches and the input terminals are electrically connected to the wiring VSO, but one embodiment of the present invention is not limited thereto. For example, the constant current source circuits ISC1, ISC2, and ISC3 may be configured such that the input terminals are electrically connected to the terminals of the respective switches and the output terminals are electrically connected to the wiring VSO. Note that a wiring VCN2 may be disposed in order to input a constant potential to the wiring OL[j] and the wiring OLB[j] before outputting a current from the circuit MP. The wiring VCN2 is connected to the wiring OL[j] via a switch SWH. The wiring VCN2 is also connected to the wiring OLB[j] via a switch SWHB. The wiring VCN2 can supply a potential different from the wiring VCN described later. For example, when VSS or a ground potential is supplied to the wiring VCN, VDD or the like may be supplied to the wiring VCN2. By applying the constant potential of the wiring VCN2 to the wiring OL[j] and the wiring OLB[j], the constant potential can be applied to each circuit element included in the circuit MP.

[0142] Specific configuration examples of the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant current source circuit ISC3 are shown in Figures 8B and 8C. The constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in Figure 8B has a p-channel transistor, a first terminal of the transistor is electrically connected to the wiring VSO, a second terminal of the transistor is electrically connected to the second terminal of the switch SWC1 (switch SWC2, switch SWC3), and a gate of the transistor is electrically connected to the wiring VB. The constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in Figure 8C has an n-channel transistor, a first terminal of the transistor is electrically connected to the wiring VSO, a second terminal of the transistor is electrically connected to the second terminal of the switch SWC1 (switch SWC2, switch SWC3), and a gate of the transistor is electrically connected to the wiring VB. In each of the constant current source circuits ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) in Figures 8B and 8C, the wiring VB functions as a wiring for inputting a bias voltage to the gate of each transistor. A pulse signal may be supplied to the wiring VB. This makes it possible to control whether or not a current is output from each constant current source circuit. In that case, the switches SWC1, SWC2, and SWC3 do not need to be provided. Alternatively, an analog voltage may be supplied to the wiring VB. This makes it possible to supply an analog current from the constant current source circuit.

[0143] The wiring VSO functions as a wiring that supplies a constant voltage to each of the constant current source circuits ISC1, ISC2, and ISC3. For example, when a current is supplied from the circuit ILD to the wiring OL or OLB via the switching circuit TW[j], the constant voltage is preferably a potential higher than the ground potential (e.g., VDD, etc.), and it is preferable to use the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in FIG. 8B. Also, for example, when a current is supplied from the circuit ILD to the wiring OL or OLB via the switching circuit TW[j], the constant voltage is preferably a potential higher than the ground potential and lower than the high-level potential, such as the ground potential, and it is preferable to use the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in FIG. 8C. In this specification, the current flowing from the circuit ILD to the wiring OL or OLB via the switching circuit TW[j] may be described as a positive current. Therefore, the current flowing from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j] may be referred to as a negative current.

[0144] 8B and 8C that can be applied to the constant current source circuits ISC1, ISC2, and ISC3, for example, the circuit configuration shown in Fig. 8D can be given. The constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in Fig. 8D has an n-channel transistor having a backgate, a first terminal of the transistor is electrically connected to the wiring VSO, and a second terminal of the transistor is electrically connected to the gate and backgate of the transistor and the second terminal of the switch SWC1 (switch SWC2, switch SWC3).

[0145] Here, when the constant voltage provided by the wiring VSO is set to a high-level potential, a high-level potential is input to the first terminal of the transistor illustrated in FIG. 8D. The potential of the second terminal of the transistor is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor functions as a drain, and the second terminal of the transistor functions as a source. Since the gate and second terminal of the transistor are electrically connected to each other, the gate-source voltage of the transistor is 0 V. Therefore, when the threshold voltage of the transistor is within an appropriate range, the transistor operates in the subthreshold region, and a current (drain current) of the subthreshold region flows between the first terminal and the second terminal of the transistor. When the transistor is an OS transistor, the amount of the current is, for example, 1.0×10 -8 A or less, and 1.0×10 -12 A or less is more preferable, and 1.0×10 -15 More preferably, the current is equal to or less than A. Also, for example, it is more preferable that the current is within a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor functions as a current source for supplying a current within the current range when operating in the subthreshold region.

[0146] Alternatively, in the case of FIG. 8B, if the wiring VSO side of the transistor in FIG. 8B is the source, the potential of the wiring VB may be the same as or higher than the potential of the wiring VSO. That is, by reducing the absolute value of the gate-source voltage, the transistor can be operated in the subthreshold region. Alternatively, by setting the gate-source voltage to a positive value or a voltage higher than the threshold voltage, the transistor can be operated in the subthreshold region. However, one embodiment of the present invention is not limited thereto. For example, the transistor illustrated in FIG. 8B may be operated in the saturation region. Alternatively, the transistor illustrated in FIG. 8B may be operated near the boundary between the saturation region and the subthreshold region.

[0147] In this specification and the like, the boundary between the saturation region and the subthreshold region refers to, for example, a region where the threshold voltage of a transistor is V th When the gate-source voltage is V th -1.0V or more, V th -0.5V or more, or V th -0.1V or more and V th +0.1V or less, V th +0.5V or less, or V th This includes cases where the voltage is equal to or lower than +1.0 V. The above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0148] Next, the case of FIG. 8C is similar to the case of FIG. 8B. That is, in the case of FIG. 8C, if the wiring VSO side of the transistor in FIG. 8C is the source, the potential of the wiring VB may be the same as the potential of the wiring VSO or lower than the potential of the wiring VSO. That is, by reducing the absolute value of the gate-source voltage, it is possible to operate in the subthreshold region. Alternatively, by setting the gate-source voltage to a negative value or a voltage lower than the threshold voltage, it is possible to operate in the subthreshold region. However, one embodiment of the present invention is not limited thereto. For example, the transistor illustrated in FIG. 8C may be operated in the saturation region. Alternatively, the transistor illustrated in FIG. 8C may be operated near the boundary between the saturation region and the subthreshold region.

[0149] By the way, the current flowing from the constant current source circuit ISC1 is I ut For example, the current flowing from the constant current source circuit ISC2 is 2I ut It is preferable that the current flowing from the constant current source circuit ISC3 is 4I ut In other words, when the current source circuit ISC has P constant current sources (P is an integer of 1 or more), the current flowing from the p-th constant current source (p is an integer of 1 or more and P or less) is preferably 2 (p-1) ×I ut In this manner, the magnitude of the current flowing from the current source circuit ISC can be changed.

[0150] For example, the number of constant current sources in the current source circuit ISC is three (P=3). ut If you want to pass a current of 5I, you should turn on the switch SWI, turn off the switch SWIB, turn on the switch SWC1, and turn off the switches SWC2 and SWC3. ut To pass a current of 1000 mA, the switches SWC1 and SWC3 should be turned on and the switch SWC2 should be turned off. In other words, the current output from the current source circuit ISC can be one of eight values ​​("0", "I ut ", "2I ut ", "3I ut ", "4I ut ", "5I ut ", "6I ut ", "7I ut ”). If it is desired to output a current with a value greater than eight values, the number of constant current sources should be four or more. Similarly, by turning the switch SWI off and the switch SWIB on, one of the eight current values ​​can be passed through the wiring OLB[j]. If no current is output from the current source circuit ISC, the switches SWC1 to SWC3 of the current source circuit ISC may not be turned off, and the switches SWI and SWIB of the switching circuit TW may be turned off. By arranging multiple constant current sources in this manner, the current source circuit ISC can output an amount of current corresponding to a control signal (digital value) that switches between the on and off states of each switch. In other words, the current source circuit ISC performs digital-to-analog (DA) conversion from the control signal to the amount of current. The current source circuit may be configured so that the current value output from the current source circuit can be freely changed as an analog value, and the circuit ILD may be configured to have only one current source circuit.

[0151] However, in the above example, if the current source circuit ISC has P constant current sources, the current flowing from the p-th constant current source is 2 (p-1) ×I utHowever, one aspect of the present invention is not limited to this. For example, the magnitudes of the currents flowing from the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant current source circuit ISC3 may all be the same. For example, when the current output from the current source circuit ISC has eight values, the number of constant current sources in the current source circuit ISC may be seven (P=7), the magnitudes of the currents of the constant current sources in the current source circuit ISC may all be the same, and the magnitude of the current output from the current source circuit ISC may be controlled by controlling how many current sources are used to output the current.

[0152] In the circuit ILD, the terminal TSb2 is electrically connected to the wiring VCN, and the terminal TSbB2 is electrically connected to the wiring VCN.

[0153] The wiring VCN functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) is supplied from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage provided by the wiring VCN is preferably a low-level potential (e.g., VSS, etc.). For example, when a current (negative current) is supplied from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j], the constant potential provided by the wiring VCN is preferably a high-level potential. Note that, as shown in FIG. 42 to FIG. 45, which will be described later, when the capacitance C3 is connected to a source terminal of the transistor M1 or the like and the source terminal is not connected to a power supply line or the like, when a positive current is supplied from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage provided by the wiring VCN is preferably a high-level potential (e.g., VDD, etc.). In other words, when a constant voltage is supplied from the wiring VCN, it is desirable that the potential difference between both ends of the capacitance C3 is close to zero. In other words, it is desirable to supply a potential to the wiring VCN such that no current is output from the circuit MC.

[0154] In the circuit ILD, the terminal TSb3 is electrically connected to the wiring VCN2, and the terminal TSbB3 is electrically connected to the wiring VCN2.

[0155] The wiring VCN2 functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) is supplied from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage provided by the wiring VCN is preferably a high-level potential (e.g., VDD). For example, when a current (negative current) is supplied from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j], the constant potential provided by the wiring VCN is preferably a low-level potential.

[0156] The switching circuit TW[j] can change the circuit that is in a conductive state with the wiring OL[j] and the wiring OLB[j] by switching each of the switches SWI, SWIB, SWO, SWOB, SWL, SWLB, SWH, and SWHB to an on or off state.

[0157] Here, the weighting coefficients input to the circuit MP will be described.

[0158] When a positive weighting factor is to be input to the circuit MP, a current corresponding to the weighting factor is input to the wiring OL[j], and a constant potential given by the wiring VCN is input to the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a non-conductive state, the circuit AFP and the wiring OL[j] are brought into a non-conductive state, the circuit AFP and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN and the wiring OL[j] are brought into a non-conductive state, the wiring VCN and the wiring OLB[j] are brought into a conductive state, the wiring VCN2 and the wiring OL[j] are brought into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] are brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWI and SWLB are turned on, and the switches SWIB, SWO, SWOB, SWL, SWH, and SWHB are turned off. This brings the current source circuit ISC and the wiring OL[j] into a conductive state, so that a current can be passed from the current source circuit ISC to the circuit MP via the wiring OL[j]. Now, when the number of constant current sources in the current source circuit ISC is P, the current is 2 P The positive weighting coefficient input to the MP circuit is determined according to the current, so the weighting coefficient is 2 P -1. In addition, since the wiring VCN and the wiring OLB[j] are in a conductive state, a constant voltage is input from the wiring VCN to the wiring OLB[j].

[0159] Also, when a negative weighting coefficient is to be input to the circuit MP, a current corresponding to the weighting coefficient is input to the wiring OLB[j], and a constant potential given by the wiring VCN is input to the wiring OL[j]. As an example, the current source circuit ISC and the wiring OL[j] are put into a non-conductive state, the current source circuit ISC and the wiring OLB[j] are put into a conductive state, the circuit AFP and the wiring OL[j] are put into a non-conductive state, the circuit AFP and the wiring OLB[j] are put into a non-conductive state, the wiring VCN and the wiring OL[j] are put into a conductive state, the wiring VCN and the wiring OLB[j] are put into a non-conductive state, the wiring VCN2 and the wiring OL[j] are put into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] are put into a non-conductive state. That is, in the switching circuit TW[j], the switches SWIB and SWL are turned on, and the switches SWI, SWO, SWOB, SWLB, SWH, and SWHB are turned off. This brings the current source circuit ISC and the wiring OLB[j] into a conductive state, so that a current can be passed from the current source circuit ISC to the circuit MP via the wiring OLB[j]. Now, when the number of constant current sources in the current source circuit ISC is P, the current is 2 P The negative weighting coefficient input to the MP circuit is determined according to the current, so the weighting coefficient is 2 P -1. In addition, since the wiring VCN and the wiring OL[j] are in a conductive state, a constant voltage is input from the wiring VCN to the wiring OL[j].

[0160] Also, when a weighting coefficient of 0 is to be input to the circuit MP, the constant potential provided by the wiring VCN may be input to each of the wiring OL[j] and the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] may be brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] may be brought into a non-conductive state, the circuit AFP and the wiring OL[j] may be brought into a non-conductive state, the circuit AFP and the wiring OLB[j] may be brought into a non-conductive state, the wiring VCN and the wiring OL[j] may be brought into a conductive state, the wiring VCN and the wiring OLB[j] may be brought into a conductive state, the wiring VCN2 and the wiring OL[j] may be brought into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] may be brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWL and SWLB are turned on, and the switches SWI, SWIB, SWO, SWOB, SWH, and SWHB are turned off. This brings the wiring VCN and the wiring OL[j] into a conductive state, and the wiring VCN and the wiring OLB[j] into a conductive state, so that the constant voltage from the wiring VCN is input to the wirings OL[j] and OLB[j].

[0161] In other words, by setting the number of constant current sources in the current source circuit ISC to P, the number of weighting coefficients (positive weighting coefficients, negative weighting coefficients, and zero weighting coefficients) that can be input to the circuit MP is 2 P+1 -1 piece.

[0162] Next, a case where information (for example, potential, current, etc.) is supplied from the circuit MP to the circuit AFP will be described.

[0163] Before supplying information (e.g., potential, current, etc.) from the circuit MP to the circuit AFP, it is preferable to set the wiring OL[j] and the wiring OLB[j] to a predetermined potential. For example, when a positive current flows from the circuit AFP to the circuit MP through the wiring OL or the wiring OLB, the predetermined potential is preferably a high-level potential. Also, for example, when a positive current flows from the circuit MP to the circuit AFP through the wiring OL or the wiring OLB, the predetermined potential is preferably a low-level potential. Therefore, before supplying information (for example, potential, current, etc.) from the circuit MP to the circuit AFP, for example, the current source circuit ISC and the wiring OL[j] may be in a non-conductive state, the current source circuit ISC and the wiring OLB[j] may be in a non-conductive state, the circuit AFP and the wiring OL[j] may be in a non-conductive state, the circuit AFP and the wiring OLB[j] may be in a non-conductive state, the wiring VCN and the wiring OL[j] may be in a non-conductive state, the wiring VCN and the wiring OLB[j] may be in a non-conductive state, the wiring VCN2 and the wiring OL[j] may be in a conductive state, and the wiring VCN2 and the wiring OLB[j] may be in a conductive state. That is, in the switching circuit TW[j], the switches SWH and SWHB may be in an on state, and the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB may be in an off state. As a result, a state of conduction is established between wiring OL[j] and wiring VCN2, and a state of conduction is established between wiring OLB[j] and wiring VCN2, so that a constant voltage from wiring VCN2 is input to wiring OL[j] and wiring OLB[j].

[0164] When information (for example, potential, current, etc.) is supplied from the circuit MP[i,j] to the circuit AFP, for example, the current source circuit ISC and the wiring OL[j] are put into a non-conductive state, the current source circuit ISC and the wiring OLB[j] are put into a non-conductive state, the circuit AFP and the wiring OL[j] are put into a conductive state, the circuit AFP and the wiring OLB[j] are put into a conductive state, the wiring VCN and the wiring OL[j] are put into a non-conductive state, the wiring VCN and the wiring OLB[j] are put into a non-conductive state, the wiring VCN2 and the wiring OL[j] are put into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] are put into a non-conductive state. That is, in the switching circuit TW[j], the switches SWO and SWOB are put into an on state, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are put into an off state. This brings the circuit AFP and the circuit MP[i,j] into a conductive state, so that information (for example, potential, current, etc.) can be supplied from the circuit MP[i,j] to the circuit AFP.

[0165] As described above, by configuring the circuit ILD and the switching circuit TW[j] as shown in FIG. 8A, the same current source circuit ISC can be used when passing a predetermined current through the wiring OL[j] and the wiring OLB[j]. This reduces the effect of variation in the characteristics of the current sources on each of the wiring OL[j] and the wiring OLB[j].

[0166] <<Circuit MP>> Next, a configuration example of the circuits MP[i,j] included in the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, and the arithmetic circuit 140 will be described.

[0167] FIG. 9A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 140, and the circuit MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of a weighting coefficient and an input signal (operation value) of a neuron in the circuit MP. The circuit MC can have the same configuration as the circuit MCr, or a different configuration from the circuit MCr. Therefore, the circuit MCr is given the symbol "r" to distinguish it from the circuit MC. In addition, the symbols of the circuit elements included in the circuit MCr, which will be described later, are also given the symbol "r".

[0168] For example, the circuit MC includes a circuit HC, and the circuit MCr includes a circuit HCr. The circuit HC and the circuit HCr each have a function of retaining information (e.g., potential, resistance, current, etc.). Note that the first data w i (k-1) j (k) is determined according to information (e.g., potential, resistance value, current value, etc.) held in each of the circuits HC and HCr. Therefore, each of the circuits HC and HCr is determined according to the first data w i (k-1) j (k) The wiring OL[j] and the wiring OLB[j] are electrically connected to each other and supply information (for example, a potential, a resistance value, a current value, or the like) corresponding to the input of ...

[0169] 9A, the circuit MP[i,j] is electrically connected to the wiring VE[j] and the wiring VEl[j]. The wiring VE[j] and the wiring VEl[j] function as wirings that supply a constant voltage. The wiring VE[j] also functions as a wiring that drains a current from the wiring OL via the circuit MC. The wiring VEl[j] also functions as a wiring that drains a current from the wiring OLB via the circuit MCr.

[0170] The wiring WL[i] shown in FIG. 9A corresponds to the wiring WL[i] in FIG. 7. The wiring WL[i] is electrically connected to each of the circuit HC and the circuit HCr. i (k-1) j (k) When writing information (for example, a potential, a resistance value, a current value, or the like) according to the first data w, a predetermined potential is supplied to the wiring WL[i] to bring the wiring OL[j] and the circuit HC into a conductive state, and also bring the wiring OLB[j] and the circuit HCr into a conductive state. i (k-1) j (k) By supplying a potential according to the data w, the potential can be input to each of the circuits HC and HCr. After that, a predetermined potential is supplied to the wiring WL[i] to bring the wiring OL[j] and the circuit HC into a non-conductive state and bring the wiring OLB[j] and the circuit HCr into a non-conductive state. Then, the first data w is input to each of the circuits HC and HCr. i (k-1) j (k) Each current according to the above is maintained.

[0171] For example, the first data i (k-1) j (k) Consider the case where the first data w can take one of the three values ​​"-1", "0", or "1". i (k-1) j (k) is "1", for example, a predetermined potential is maintained in the circuit HC so that a current corresponding to "1" flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a potential V 0 The first data w i (k-1) j (k)is "-1", for example, the circuit HC is provided with a potential V 0 is held, and a predetermined potential is held in the circuit HCr so that a current corresponding to "-1" flows from the wiring OLB[j] to the wiring VEl[j] via the circuit MCr. i (k-1) j (k) When is "0", for example, a potential V 0 is maintained, and a potential V 0 The potential V 0 can be the potential provided by the wiring VCN in the description of FIG. 8A.

[0172] As another example, the first data w i (k-1) j (k) Let us consider the case where the first data w is an analog value, specifically, a "negative analog value", "0", or a "positive analog value". i (k-1) j (k) is a "positive analog value", for example, a predetermined potential is held in the circuit HC so that an analog current corresponding to the "positive analog value" flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a potential V 0 The first data w i (k-1) j (k) is a "negative analog value", for example, the circuit HC is connected to a potential V 0A predetermined potential is held in the circuit HCr so that an analog current corresponding to a "negative analog value" flows from the wiring OLB[j] to the wiring VEl[j] via the circuit MCr. Then, the first data w i (k-1) j (k) When is "0", for example, a potential V 0 is maintained, and a potential V 0 The potential V 0 can be the potential provided by the wiring VCN in the description of FIG. 8A, similarly to the previous example.

[0173] Also, as an example, the circuit MC has a function of outputting a current corresponding to information (e.g., potential, resistance, or current) held in the circuit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current corresponding to information (e.g., potential, resistance, or current) held in the circuit HCr to the other of the wiring OL[j] or the wiring OLB[j]. For example, when a first potential is held in the circuit HC, the circuit MC flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when a second potential is held in the circuit HC, the circuit MC flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Similarly, when the circuit HCr holds a first potential, the circuit MCr flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VEl, and when the circuit HCr holds a second potential, the circuit MCr flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VEl. The magnitudes of the first current value and the second current value are each calculated using the first data w i (k-1) j (k)The first current value is determined by the value of the second current value. For example, the first current value may be greater than or less than the second current value. For further example, one of the first current value and the second current value may be zero current, i.e., the current value is 0. Alternatively, the current having the first current value and the current having the second current value may flow in different directions.

[0174] In particular, for example, the first data w i (k-1) j (k) It is preferable to configure the circuit MC and the circuit MCr so that when the first data w takes one of the three values ​​of "-1", "0", and "1", either the first current value or the second current value becomes zero. i (k-1) j (k) takes an analog value, for example, a “negative analog value”, “0”, or a “positive analog value”, the first current value or the second current value can also take an analog value, for example.

[0175] Incidentally, when a current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC is made equal to a current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MCr, the potential held in the circuit MC may not be equal to the potential held in the circuit MCr because the characteristics of the transistor may vary due to a manufacturing process of the transistor, etc. In the semiconductor device of one embodiment of the present invention, even if the characteristics of the transistor vary, the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC can be made approximately equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC.

[0176] In this specification, the current or voltage corresponding to the information (e.g., potential, resistance value, or current value) held in the circuit HC and the circuit HCr may be a positive current or voltage, a negative current or voltage, a zero current or zero voltage, or a mixture of positive, negative, and zero. In other words, for example, the above description "the circuit HC has a function of outputting a current or voltage corresponding to information (e.g., potential, resistance, or current value) held in the circuit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current or voltage corresponding to information (e.g., potential, resistance, or current value) held in the circuit HCr to the other of the wiring OL[j] or the wiring OLB[j]" can be rephrased as "the circuit HC has a function of discharging a current, voltage, etc. corresponding to information (e.g., potential, resistance, or current value) held in the circuit HC from one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of discharging a current, voltage, etc. corresponding to information (e.g., potential, resistance, or current value) held in the circuit HCr from the other of the wiring OL[j] or the wiring OLB[j]."

[0177] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 9A correspond to the wiring XLS[i] in FIG. 7. Note that the second data z i (k-1) For example, the second data z i (k-1) Each potential according to the above is input.

[0178] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j], and the circuit MCr is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MC and the circuit MCr transmit the first data wi (k-1) j (k) and the second data z i (k-1) A current or potential according to the product of x and x is output. As a specific example, the output destination of the current from the circuit MC and the circuit MCr is determined by the potential of the wiring X1L[i] and the wiring X2L[i]. For example, the circuit MC and the circuit MCr are configured such that the current output from the circuit MC flows to one of the wiring OL[j] and the wiring OLB[j], and the current output from the circuit MCr flows to the other of the wiring OL[j] and the wiring OLB[j]. In other words, the currents output from the circuit MC and the circuit MCr do not flow to the same wiring, but to different wirings. Note that, as an example, there are cases where the current does not flow from the circuit MC and the circuit MCr to either the wiring OL[j] or the wiring OLB[j].

[0179] For example, the second data z i (k-1) Consider the case where the second data z can take one of the three values ​​"-1", "0", or "1". i (k-1) When the second data z i (k-1) When the second data z i (k-1) When is "0", in order to prevent the currents output by the circuits MC and MCr from flowing through either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state.

[0180] Here is an example of the above operations. i (k-1)j (k) When the first data w is "1", a current may flow from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MC, and a current does not flow from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) When the second data z i (k-1) When the second data z is “1”, the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1) When the first data w is "-1", the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] are in a conductive state. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a positive value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, or a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a negative value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr, or a current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. i (k-1) j (k) and the second data z i (k-1)When the product is zero, no current flows from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j], and no current flows from the wiring OL[j] or the wiring OLB[j] to the wiring VEr[j].

[0181] To take the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "0", and the second data z i (k-1) When is "1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero.

[0182] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1)When the first data w is "-1", a current I1[i,j] having a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "0", and the second data z i (k-1) is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. At this time, the magnitude of the second current value is, for example, zero.

[0183] In addition, the second data z i (k-1) When the first data w is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, the first data w i (k-1) j (k) Whatever the value of is, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0184] Thus, as an example, the first data w i (k-1) j (k) and the second data z i (k-1)When the product of the first data w and the second data w is a positive value, a current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. i (k-1) j (k) When the value is positive, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the first data w is a negative value, a current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w and the second data w is negative, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. i (k-1) j (k) When the value is positive, a current flows from the circuit MC to the wiring OLB[j], and the first data w i (k-1) j (k)When is a negative value, a current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or the circuit MCr connected to the wiring OL[j] flows to the wiring OL[j]. That is, a current having a value obtained by summing up the positive values ​​flows in the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or the circuit MCr connected to the wiring OLB[j] flows to the wiring OLB[j]. That is, a current having a value obtained by summing up the negative values ​​flows in the wiring OLB[j]. As a result of the above operation, the total current value flowing in the wiring OL[j], that is, the sum of the positive values, and the total current value flowing in the wiring OLB[j], that is, the sum of the negative values, are used to perform a product-sum operation. For example, when the total current value flowing in the wiring OL[j] is greater than the total current value flowing in the wiring OLB[j], it can be determined that the product-sum operation results in a positive value. When the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a negative value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the product-sum operation is zero.

[0185] In addition, the second data z i (k-1) The same operation can be performed when the first data w is one of two values ​​of "-1", "0", and "1", for example, the two values ​​of "-1" and "1", or the two values ​​of "0" and "1". i (k-1) j (k) The same operation can be performed when the value is any one of the two values ​​"-1", "0", and "1", for example, when the value is "-1" or "1", or when the value is "0" or "1".

[0186] In addition, the first data i (k-1) j (k)may take an analog value or a multi-bit (multiple-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0187] Next, an example of a modification of the circuit MP[i,j] in Fig. 9A will be described. Note that, for the modification of the circuit MP[i,j], the parts different from the circuit MP[i,j] in Fig. 9A will be mainly described, and the parts common to the circuit MP[i,j] in Fig. 9A may be omitted.

[0188] The circuit MP[i,j] shown in FIG. 9B has a configuration in which the wiring X1L is replaced with a wiring WX1L. That is, in the circuit MP[i,j] in FIG. 9B, the wiring WX1L and the wiring WL function as wirings that supply a predetermined potential in order to switch the conductive state or non-conductive state between the wiring OL[j] and the circuit HC and to switch the conductive state or non-conductive state between the wiring OLB[j] and the circuit HCr. Also, in the circuit MP[i,j] in FIG. 9B, the wiring WX1L and the wiring X2L function as wirings that supply a predetermined potential in order to switch the conductive state or non-conductive state between the wiring OL[j] and the circuit HC and to switch the conductive state or non-conductive state between the wiring OLB[j] and the circuit HCr. i (k-1) It functions as wiring that provides current, voltage, etc. according to the

[0189] The circuit MP[i,j] in Fig. 9B can be applied to an arithmetic circuit that has a wiring WX1L like the arithmetic circuit 130 shown in Fig. 4 and does not have wirings IL and ILB like the arithmetic circuit 140 shown in Fig. 7. Specifically, for example, the circuit MP[i,j] in Fig. 9B can be applied to the circuit MP[i,j] of the arithmetic circuit 150 shown in Fig. 11.

[0190] Next, an example of modifying the circuit MP[i,j] in FIG. 9A, which is different from FIG. 9B, will be described. The circuit MP[i,j] shown in FIG. 9C is a modified example of the circuit MP[i,j] in FIG. 9A. Similar to the circuit MP[i,j] in FIG. 9A, the circuit MP[i,j] in FIG. 9C has a circuit MC and a circuit MCr. However, the circuit MP[i,j] in FIG. 9C is different from the circuit MP[i,j] in FIG. 9A in that the circuit HCr is not included in the circuit MCr.

[0191] Also, since the circuit MCr does not have the circuit HCr, the arithmetic circuit to which the circuit MP[i,j] in FIG. 9C is applied does not need to have the wiring ILB[j] for supplying the potential held in the circuit HCr. In addition, the circuit MCr does not necessarily need to be electrically connected to the wiring WL[i].

[0192] In the circuit MP[i,j] of FIG. 9C, the circuit HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP[i,j] of FIG. 9C is configured such that the circuit MCr and the circuit MC share the circuit HC with each other. As an example, an inverted signal can be supplied from the circuit HC to the circuit MCr for the signal held in the circuit HC. Thereby, it becomes possible for the circuit MC and the circuit MCr to perform different operations. Or, the internal circuit configurations of the circuit MC and the circuit MCr can be made different, and as a result, for the same signal held in the circuit HC, the magnitudes of the currents output by the circuit MC and the circuit MCr can be made different. Here, the circuit HC holds the potential corresponding to the first data w i (k-1) j (k) and supplies the potential corresponding to the second data z i (k-1) to the wirings X1L[i] and X2L[i]. By doing so, the circuit MP[i,j] can output a current corresponding to the product of the first data w i (k-1) j (k) and the second data z i (k-1) to the wirings OL[j] and OLB[j].

[0193] The arithmetic circuit 110 to which the circuit MP in FIG. 9C is applied can be modified to, for example, the circuit configuration of the arithmetic circuit 140 shown in FIG.

[0194] The circuit MP[i,j] shown in FIG. 9D is a modified example of the circuit MP[i,j] in FIG. 9A, and specifically, is a configuration example of the circuit MP[i,j] that can be applied to the arithmetic circuit 160 in FIG. 12 described later. Note that the arithmetic circuit 160 has a configuration in which the wirings ILB[1] to ILB[n] are removed from the arithmetic circuit 110 in FIG. 2. The circuit MP[i,j] in FIG. 9D includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in FIG. 9A. However, the circuit MP[i,j] in FIG. 9D and the circuit MP[i,j] in FIG. 9A have different configurations of wirings that are electrically connected.

[0195] The wiring W1L[i] and the wiring W2L[i] shown in Fig. 9D correspond to the wiring WLS[i] in Fig. 12. The wiring W1L[i] is electrically connected to the circuit HC, and the wiring W2L[i] is electrically connected to the circuit HCr.

[0196] In addition, the wiring IL[j] is electrically connected to the circuit HC and the circuit HCr.

[0197] In the circuit MP[i,j] of FIG. 9D, when the circuit HC and the circuit HCr store different information (e.g., voltage, resistance, current, etc.), it is preferable to store the information in the circuit HC and the circuit HCr sequentially, not simultaneously. For example, the first data w i (k-1) j (k)Consider a case where the first information can be expressed by holding the first information in the circuit HC and the second information in the circuit HCr. First, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] to bring the circuit HC and the wiring IL[j] into a conductive state and bring the circuit HCr and the wiring IL[j] into a non-conductive state. Next, the first information can be given to the circuit HC by supplying a current, a voltage, or the like corresponding to the first information to the wiring IL[j]. After that, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] to bring the circuit HC and the wiring IL[j] into a non-conductive state and bring the circuit HCr and the wiring IL[j] into a conductive state. Then, a current, a voltage, or the like corresponding to the second information is supplied to the wiring IL[j] to give the second information to the circuit HCr. As a result, the circuit MP[i,j] stores w i (k-1) j (k) can be set.

[0198] In addition, when the circuit HC and the circuit HCr each hold substantially the same information (for example, voltage, resistance, current, etc.) (the first data w i (k-1) j (k) is set by holding approximately equal information in each of the circuits HC and HCr), a predetermined potential can be applied to each of the wirings W1L[i] and W2L[i] so that the circuit HC and the wiring IL[j] are brought into electrical continuity and the circuit HCr and the wiring IL[j] are brought into electrical continuity, and then a current, voltage, or the like according to the information can be supplied from the wiring IL[j] to the circuit HC and the circuit HCr.

[0199] The circuit MP[i,j] in FIG. 9D stores the first data w i (k-1) j (k) The potential corresponding to the second data z i (k-1)9A , a potential corresponding to the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0200] The circuit MP[i,j] shown in Fig. 9E is a modified example of the circuit MP[i,j] in Fig. 9D. The circuit MP[i,j] in Fig. 9E includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in Fig. 9D. However, the circuit MP[i,j] in Fig. 9E and the circuit MP[i,j] in Fig. 9D have different configurations of electrically connected wiring.

[0201] Specifically, the circuit MP in Figure 9E is configured by adding wiring ILB[j] to the circuit MP in Figure 9D, and replacing the wiring W1L[i] and wiring W2L[i] electrically connected to the circuit MP in Figure 9D with wiring WL[i].

[0202] In the circuit MP of Fig. 9E, the wiring IL[j] is electrically connected to the circuit HC, and the wiring ILB[j] is electrically connected to the circuit HCr. In other words, in the circuit MP of Fig. 9D, the wiring IL[j] functions as a wiring that supplies a current, a voltage, etc. corresponding to information (for example, a voltage, a resistance value, a current, etc.) to each of the circuit HC and the circuit HCr, but in the circuit MP of Fig. 9E, the wiring IL[j] functions as a wiring that supplies a current, a voltage, etc. corresponding to the information to the circuit HC, and the wiring ILB[j] functions as a wiring that supplies a current, a voltage, etc. corresponding to the information to the circuit HCr.

[0203] In the circuit MP of FIG. 9E, the wiring IL[j] and the wiring ILB[j] are electrically connected to the circuit HC and the circuit HCr, respectively, so that a current, a voltage, or the like according to information (for example, a voltage, a resistance value, a current, or the like) can be simultaneously supplied to each of the circuits HC and HCr. Therefore, the conductive state or non-conductive state between the circuit HC and the wiring IL[j] can be switched, and the conductive state or non-conductive state between the circuit HCr and the wiring ILB[j] can be switched, simultaneously. In the circuit MP of FIG. 9D, the wiring W1L[i] is illustrated as a wiring that controls the conductive state or non-conductive state between the circuit HC and the wiring IL[j], and the wiring W2L[i] is illustrated as a wiring that controls the conductive state or non-conductive state between the circuit HCr and the wiring ILB[j], but in the circuit MP of FIG. 9E, the wiring WL[i] is illustrated as a wiring that combines the wiring W1L[i] and the wiring W2L[i].

[0204] The circuit MP in FIG. 9E can be applied to, for example, the arithmetic circuit 110 in FIG. 2 and the arithmetic circuit 120 in FIG.

[0205] The circuit MP[i,j] shown in Fig. 9F is a modified example of the circuit MP[i,j] in Fig. 9A. The circuit MP[i,j] in Fig. 9F includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in Fig. 9A. However, the circuit MP[i,j] in Fig. 9F differs from the circuit MP[i,j] in Fig. 9A in that the circuit MC is not electrically connected to the wiring OLB[j] and the circuit MCr is not electrically connected to the wiring OL[j].

[0206] The wiring WL[i] shown in Fig. 9F is electrically connected to the circuit HC and the circuit HCr, and the wiring XL[i] shown in Fig. 9F is electrically connected to the circuit MC and the circuit MCr.

[0207] As described above, in the circuit MP[i,j] in Fig. 9F, the circuit MC is not electrically connected to the wiring OLB[j], and the circuit MCr is not electrically connected to the wiring OL[j]. In other words, unlike the circuits MP[i,j] in Fig. 9A to Fig. 9E, the circuit MP[i,j] in Fig. 9F is configured such that the current output from the circuit MC does not flow to the wiring OLB[j], and the current output from the circuit MCr does not flow to the wiring OL[j].

[0208] Therefore, the circuit MP[i,j] of FIG. i (k-1) It is preferable to apply the second data z to the arithmetic circuit when the second data z i (k-1) is “1”, the circuit MP brings the circuit MC and the wiring OL[j] into a conductive state, and brings the circuit MCr and the wiring OLB[j] into a conductive state. i (k-1) When is "0", in order to prevent the currents output by the circuits MC and MCr from flowing through either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] into a non-conductive state.

[0209] The circuit MP[i,j] in FIG. 9F is applied to the arithmetic circuit 110 to obtain, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) The first data w can take two values, "0" and "1". i (k-1) j (k) The first data w can be operated even when it is one of two values, "-1", "0", and "1", for example, when it is one of two values, "-1" and "1", or when it is one of two values, "0" and "1". i(k-1) j (k) may take an analog value or a multi-bit (multiple-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0210] In the circuit MP[i,j] shown in FIG. 10A, the first data w i (k-1) j (k) and the second data z i (k-1) 10A is a circuit capable of outputting a current according to the product of and The circuit MP[i,j] in FIG.

[0211] The circuit MP[i,j] in FIG. 10A includes a circuit MC, a circuit MCr, and a transistor MZ.

[0212] A first terminal of the transistor MZ is electrically connected to a first terminal of the circuit MC and a first terminal of the circuit MCr. A second terminal of the transistor MZ is electrically connected to the wiring VL. A gate of the transistor MZ is electrically connected to the wiring XL[i].

[0213] For example, the wiring VL functions as a wiring that applies a constant voltage. The constant voltage is preferably determined by the configuration of the circuit MP[i,j], the arithmetic circuit 110, etc. The constant voltage may be, for example, a high-level potential VDD, a low-level potential VSS, a ground potential, or the like.

[0214] The wiring WL[i] shown in Fig. 10A corresponds to the wiring WLS[i] in the arithmetic circuit 110 in Fig. 2. The wiring WL[i] is electrically connected to the circuit HC and the circuit HCr.

[0215] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. The wiring OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0216] The wiring IL[j] is electrically connected to the circuit HC, and the wiring ILB[j] is electrically connected to the circuit HCr.

[0217] In the circuit MP[i,j] of Figure 10A, for the operation of holding a potential corresponding to the first data in each of the circuit HC and the circuit HCr, please refer to the explanation of the operation of holding a potential corresponding to the first data in the circuit MP[i,j] of Figure 9A.

[0218] In the circuit MP[i,j] of FIG. 10A, the circuit MC has a function of flowing a current corresponding to the potential held in the circuit HC between the first and second terminals of the circuit MC when a constant voltage provided by the wiring VL is supplied to the first terminal of the circuit MC. Also, the circuit MCr has a function of flowing a current corresponding to the potential held in the circuit HCr between the first and second terminals of the circuit MCr when a constant voltage provided by the wiring VL is supplied to the first terminal of the circuit MC. In other words, when the first data w i (k-1) j (k) By holding a potential according to the potential, it is possible to determine the amount of current flowing between the first terminal and the second terminal of the circuit MC and the amount of current flowing between the first terminal and the second terminal of the circuit MCr. Note that when the constant voltage provided by the wiring VL is not supplied to the first terminal of the circuit MC (circuit MCr), the circuit MC (circuit MCr) may, for example, not allow a current to flow between the first terminal and the second terminal of the circuit MC (circuit MCr).

[0219] For example, the first data w of "1" is stored in each of the circuits HC and HCr. i (k-1) j (k) When a potential according to is held, a constant voltage is applied to the circuit MC via the wiring VL, causing the circuit MC to pass a predetermined current between the first and second terminals of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. Note that, at this time, the circuit MCr does not pass a current between the first and second terminals of the circuit MCr. Therefore, no current flows between the circuit MCr and the wiring OLB. Also, for example, when the first data w of "-1" is applied to each of the circuits HC and HCr, i (k-1) j (k) When a potential according to is held, a constant voltage is applied to the circuit MC via the wiring VL, causing the circuit MCr to pass a predetermined current between the first and second terminals of the circuit MCr. Therefore, a current flows between the circuit MCr and the wiring OLB. Note that, at this time, the circuit MC does not pass a current between the first and second terminals of the circuit MC. Therefore, no current flows between the circuit MC and the wiring OL. Also, for example, when the first data w of "0" is applied to each of the circuits HC and HCr, i (k-1) j (k) When a potential according to is held, regardless of whether a constant voltage of the wiring VL is applied to the circuits MC and MCr, the circuit MC does not pass a current between the first and second terminals of the circuit MC, and the circuit MCr does not pass a current between the first and second terminals of the circuit MCr. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB.

[0220] In the circuit MP[i,j] of FIG. 10A, the first data w i (k-1) j (k)For a specific example of the potential corresponding to, please refer to the description of the circuit MP[i,j] in Fig. 9A. In the circuit MP[i,j] in Fig. 10A, the circuit HC and the circuit HCr may have a function of retaining information such as a current and a resistance value instead of a potential, similar to the circuit MP[i,j] in Fig. 9A, and the circuit MC and the circuit MCr may have a function of flowing a current corresponding to the information.

[0221] The wiring XL[i] shown in FIG. 10A corresponds to the wiring XLS[i] in the arithmetic circuit 110 in FIG. 2. Note that the second data z i (k-1) For example, the potential, current, etc. of the wiring XL[i] are determined. Therefore, the gate of the transistor MZ is connected to the second data z i (k-1) A potential according to the input is input.

[0222] For example, the second data z i (k-1) Consider the case where the second data z takes one of two values, “0” or “1”. i (k-1) When the second data z i (k-1) When the second data z i (k-1) When the second data z i (k-1) When is "0", the constant voltage is not applied to the circuit MC and the circuit MCr from the line VL.

[0223] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", a current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", no current flows between the circuit MC and the wiring OL, and a current flows between the circuit MCr and the wiring OLB. i (k-1) j (k) is "0", and the second data z i (k-1) When the second data z i (k-1) If is "0", the first data w i (k-1) j (k) Regardless of whether the signal level is "-1," "0," or "1," no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB.

[0224] That is, the circuit MP[i,j] in FIG. 10A is similar to the circuit MP[i,j] in FIG. 9F in that, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) 9F, the circuit MP[i,j] in FIG. 10A can perform an operation in which the first data w i (k-1) j (k)The first data w can be operated even when it is one of two values ​​of "-1", "0", and "1", for example, when it is two values ​​of "-1" and "1", or when it is two values ​​of "0" and "1". i (k-1) j (k) may take an analog value or a multi-bit (multiple-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0225] Note that the circuit MP[i,j] shown in FIG. 10A may be changed to a configuration in which the wirings IL[j] and OL[j] are combined into a single wiring OL[j], and the wirings ILB[j] and OLB[j] are combined into a single wiring OLB[j], as in the circuit MP[i,j] shown in FIG. 10B.

[0226] <Example of operation of the arithmetic circuit> Next, a description will be given of an example of the operation of the arithmetic circuit 140 in Fig. 7. In the description of this example of the operation, the arithmetic circuit 140 shown in Fig. 13 will be used as an example.

[0227] The arithmetic circuit 140 in Fig. 13 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 140 in Fig. 7. In other words, the arithmetic circuit 140 in Fig. 13 is a circuit that corresponds to the neuron N j (k) The input to neuron N 1 (k-1) Neuron N m (k-1) Signal z from 1 (k-1) ~z m (k-1) and the weighting factor w 1 (k-1) j (k) Or even w m(k-1) j (k) 13 corresponds to a circuit that performs a multiplication and accumulation operation of and an activation function operation using the result of the multiplication and accumulation operation. Furthermore, the circuit MP included in the array unit ALP of the arithmetic circuit 140 in FIG. 13 is assumed to be the circuit MP in FIG. 9B.

[0228] First, in the arithmetic circuit 140, the first data w 1 (k-1) j (k) Or even w m (k-1) j (k) The first data w i (k-1) j (k) The method of setting the first data is as follows: a predetermined potential is input to the wirings WLS[1] to WLS[m] by the circuit WLD, the circuits MP[1,j] to MP[m,j] are selected in order, and a potential, a current, or the like according to the first data is supplied from the circuit ILD to the circuits HC and HCr of the circuits MC and MCr included in the selected circuit MP via the switching circuit TW[j], wiring OL[j], and OLB[j]. After the potential, current, or the like is supplied, the circuits MP[1,j] to MP[m,j] are deselected by the circuit WLD, so that the first data w is supplied to the circuits HC and HCr of the circuits MC and MCr included in each of the circuits MP[1,j] to MP[m,j]. 1 (k-1) j (k) Or even w m (k-1) j (k) As an example, the first data w 1 (k-1) j (k) Or even w m (k-1) j (k)When each of the first data w takes a positive value, a value corresponding to the positive value is input to the circuit HC, and a value corresponding to zero is input to the circuit HCr. 1 (k-1) j (k) Or even w m (k-1) j (k) When each of the above takes a negative value, a value equivalent to zero is input to the circuit HC, and a value according to the absolute value of the negative value is input to the circuit HCr.

[0229] Next, the circuit XLD supplies second data z 1 (k-1) ~z m (k-1) As a specific example, the second data z 1 (k-1) is supplied. Note that the wiring X1L[i] and the wiring X2L[i] correspond to the wiring XLS[i] of the arithmetic circuit 140 shown in FIG.

[0230] The second data z input to each of the circuits MP[1,j] to MP[m,j] 1 (k-1) ~z m (k-1) In accordance with the second data z i (k-1) Depending on the second data z, the state may be one of the following: "the circuit MC and the wiring OL[j] are electrically connected, and the circuit MCr and the wiring OLB[j] are electrically connected," "the circuit MC and the wiring OLB[j] are electrically connected, and the circuit MCr and the wiring OL[j] are electrically connected," and "the circuit MC and the circuit MCr are not electrically connected to the wiring OL[j] and the wiring OLB[j], respectively." 1 (k-1)When the second data z 1 (k-1) When the second data z 1 (k-1) When the value of zero is taken for , a value that can bring about a non-conductive state between the circuit MC and the wiring OLB[j] and a non-conductive state between the circuit MCr and the wiring OL[j] is input to the wiring X1L[1]. Then, a value that can bring about a non-conductive state between the circuit MC and the wiring OL[j] and a non-conductive state between the circuit MCr and the wiring OLB[j] is input to the wiring X2L[1].

[0231] The second data z input to the circuit MP[i,j] i (k-1) In response to the first data w set in the circuit MP[i,j], a conductive state or a non-conductive state is determined between the circuit MC and the circuit MCr included in the circuit MP[i,j] and the wiring OL[j] and the wiring OLB[j], thereby inputting and outputting a current between the circuit MC and the wiring OL[j] and the wiring OLB[j]. Furthermore, the amount of the current is determined based on the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or second data z i (k-1) It depends on.

[0232] For example, in the circuit MP[i,j], the current flowing from the wiring OL[j] to the circuit MC or the circuit MCr is I[i,j], and the current flowing from the wiring OLB[j] to the circuit MC or the circuit MCr is I B [i,j]. Let I be the current flowing from the circuit ACTF[j] to the wiring OL[j]. out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] is I Bout [j], then I out [j] and I Bout [j] can be expressed by the following formula:

[0233]

number

[0234] In the circuit MP[i,j], for example, the first data w i (k-1) j (k) When the first data w is "+1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). i (k-1) j (k) When the first data w is "-1", the circuit MC outputs I(-1) and the circuit MCr outputs I(+1). i (k-1) j (k) When is "0", the circuit MC outputs I(-1) and the circuit MCr outputs I(-1).

[0235] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) is “+1”, a state is taken in which “the circuit MC and the wiring OL[j] are electrically connected, the circuit MCr and the wiring OLB[j] are electrically connected, the circuit MC and the wiring OLB[j] are not electrically connected, and the circuit MCr and the wiring OL[j] are not electrically connected” and the second data z i (k-1)is “−1”, a state is taken in which “the circuit MC and the wiring OLB[j] are electrically connected, the circuit MCr and the wiring OL[j] are electrically connected, the circuit MC and the wiring OL[j] are not electrically connected, and the circuit MCr and the wiring OLB[j] are not electrically connected” and the second data z i (k-1) is "0", the state is such that "there is no conduction between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]."

[0236] At this time, in the circuit MP[i,j], a current I[i,j] flows from the wiring OL[j] to the circuit MC or the circuit MCr, and a current I B [i,j] is as shown in the table below. In some cases, the circuit MP[i,j] may be configured so that the amount of current I(-1) is 0. The current I[i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0237] [Table 1]

[0238] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [j] and I Bout By inputting each of the inputs I[j] to the circuit ACTF[j], the circuit ACTF[j] can be configured as follows: out [j] and I Bout [j]. The circuit ACTF[j] may, for example, select neurons N j (k) The signal z sent to the (k+1)th layer neuron j (k) Output.

[0239] As an example, the arithmetic circuit 140 in FIG. j (k) The input to neuron N 1 (k-1) Neuron N m (k-1) Signal z from 1 (k-1) ~z m (k-1) and the weighting factor w 1 (k-1) j (k) Or even w m (k-1) j (k) 13, by providing n rows of circuits MP, a circuit equivalent to the arithmetic circuit 140 of FIG. 7 can be configured. In other words, the arithmetic circuit 140 of FIG. 7 can perform a multiplication and accumulation operation of neurons N 1 (k) Neuron N n (k) In each of the above, the product-sum operation and the operation of the activation function using the result of the product-sum operation can be performed simultaneously.

[0240] <<Examples of changes to circuits included in arithmetic circuits>> Each of the above-mentioned arithmetic circuits 110, 120, 130, 140, 150, and 160 can be changed to a circuit that performs the calculation of formula (1.3) instead of the calculation of formula (1.2). Formula (1.3) corresponds to a calculation in which a bias is applied to the product-sum result of formula (1.2). Therefore, a circuit that applies a bias value to the wiring OL and the wiring OLB may be provided in each of the arithmetic circuits 110, 120, 130, 140, 150, and 160.

[0241] The arithmetic circuit 170 shown in FIG. 14 has a circuit configuration in which circuits BS[1] to BS[n] are added to the array portion ALP of the arithmetic circuit 150 in FIG.

[0242] The circuit BS[j] is electrically connected to the wiring OL[j], the wiring OLB[j], the wiring WLBS, and the wiring WXBS.

[0243] The wiring WLBS functions as a wiring for supplying a signal for turning on or off the write switching elements included in the circuits BS[1] to BS[n], similar to the wirings WLS[1] to WLS[m] of the arithmetic circuit 110 in Fig. 2 and the wirings WL[1] to WL[m] of the arithmetic circuit 140 in Fig. 7. Therefore, the wiring WLBS is electrically connected to the circuit WLD, so that the signal can be supplied from the circuit WLD to the wiring WLBS.

[0244] The wire WXBS is connected to the neuron N in the same manner as the wires XLS[1] to XLS[m] of the arithmetic circuit 110 in FIG. i (k-1) The second data z output from i (k-1) The wiring WXBS functions as a wiring that supplies information (for example, a potential, a current value, and the like) corresponding to the circuit BS[1] to the circuit BS[n]. Therefore, the wiring WXBS is electrically connected to the circuit XLD, so that the information can be supplied from the circuit XLD to the wiring WXBS.

[0245] The wiring WXBS may also be used as a selection signal line for writing data to the circuits BS[1] to BS[n], similar to the wirings WX1L[1] to WX1L[n] of the arithmetic circuit 140 in Fig. 7. In the arithmetic circuit 170 in Fig. 14, the wiring WXBS is electrically connected to the circuit WLD. In such a configuration, the circuit WLD can supply a signal for turning on or off the write switching elements included in the circuits BS[1] to BS[n] to the wiring WLBS and the wiring WXBS, respectively.

[0246] In the jth column of the array portion ALP of the arithmetic circuit 170, the amount of current flowing from the circuits MP[1,j] to MP[m,j] to the wiring OL[j] or the wiring OLB[j] can be expressed by formula (1.5) and formula (1.6), respectively. In addition, since each of the wiring OL[j] and the wiring OLB[j] is electrically connected to the circuit BS[j], the current flowing from the circuit BS[j] to the wiring OL[j] is expressed by I BIAS [j], the current flowing from circuit BS[j] to wiring OLB[j] is I BIASB When [j], equations (1.5) and (1.6) can be rewritten as the equations below.

[0247]

number

[0248] This allows the calculation of equation (1.3) to include the bias I out [j] and I Bout [j] can be generated. Also, I out [j] and I Bout [j] is input to the circuit ACTF[j], which biases the neuron N j (k) Output signal z from j (k) can be generated.

[0249] 14, the circuits BS[1] to BS[n] are provided in one row in the array portion ALP, but one embodiment of the present invention is not limited to this. For example, the circuits BS[1] to BS[n] may be provided in two or more rows in the array portion ALP.

[0250] As an example, some or all of the transistors included in each of the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, the switching circuit TW, and the like described above are preferably OS transistors. For example, in the case of a transistor for which it is desired to reduce the off-current, as a specific example, a transistor having a function of retaining charge accumulated in a capacitor or the like is preferably an OS transistor. In particular, when an OS transistor is applied as the transistor, it is more preferable that the OS transistor has the structure of the transistor described in the fifth embodiment. The metal oxide included in the channel formation region of the OS transistor can be, for example, one or more materials selected from indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. In particular, a metal oxide made of indium, gallium, or zinc is a semiconductor that has a high band gap and is intrinsic (also referred to as I-type) or substantially intrinsic, and the carrier concentration of the metal oxide is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The off-state current of an OS transistor including a metal oxide in a channel formation region is preferably less than 10 aA (1×10 -17 A) or less, preferably 1 aA (1×10 -18 A) or less, and more preferably 10zA (1×10 -20 A) or less, and more preferably 1zA (1×10 -21 A) or less, and more preferably 100 yA (1 × 10 -22A) or less. In addition, since the carrier concentration of the metal oxide in the OS transistor is low, the off-state current of the OS transistor remains low even when the temperature of the OS transistor changes. For example, even when the temperature of the OS transistor is 150° C., the off-state current can be 100 zA per 1 μm of channel width.

[0251] However, one embodiment of the present invention is not limited to the above, and transistors included in the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, the switching circuit TW, etc. may not be OS transistors. As an example of a transistor other than the OS transistor, a transistor containing silicon in a channel formation region (Si transistor) may be used. As silicon, for example, single crystal silicon, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or the like can be used. As a transistor other than the OS transistor and the Si transistor, for example, a transistor containing Ge or the like in a channel formation region, a transistor containing a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, a transistor containing a carbon nanotube in a channel formation region, a transistor containing an organic semiconductor in a channel formation region, or the like can be used.

[0252] Note that, in the metal oxide of the semiconductor layer of the OS transistor, an n-type semiconductor can be fabricated using a metal oxide containing indium (e.g., In oxide) or a metal oxide containing zinc (e.g., Zn oxide), but it may be difficult to fabricate a p-type semiconductor in terms of mobility and reliability. Therefore, the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, the arithmetic circuit 140, the arithmetic circuit 150, the arithmetic circuit 160, and the arithmetic circuit 170 may be configured such that OS transistors are used as n-channel transistors included in the array unit ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, and the like, and Si transistors are used as p-channel transistors.

[0253] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0254] (Embodiment 2) In this embodiment mode, a specific configuration example of the circuit MP described in Embodiment Mode 1 will be described.

[0255] In addition, in embodiment 1, the symbols of the circuits MP are accompanied by [1,1], [i,j], [m,n], etc. to indicate their positions within the array section ALP, but in this embodiment, unless otherwise specified, the notations [1,1], [i,j], [m,n], etc. are omitted from the symbols of the circuits MP.

[0256] <Configuration example 1> First, an example of a circuit configuration applicable to the circuit MP of Fig. 9B will be described. The circuit MP shown in Fig. 15A is an example of the configuration of the circuit MP of Fig. 9B, and the circuit MC included in the circuit MP of Fig. 15A has, as an example, transistors M1 to M4 and a capacitance C1. For example, a circuit HC is formed by a transistor M2 and a capacitance C1.

[0257] 15A, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0258] The transistors M1 to M4 shown in FIG. 15A are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of the transistors M1 to M4 has a first gate and a second gate. In particular, for example, it is preferable that the sizes of the transistors M3 and M4 are equal. However, in this specification and the like, for convenience, the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification and the like, the term "gate" can be interchanged with the term "back gate". Similarly, the term "back gate" can be interchanged with the term "gate". As a specific example, a connection configuration in which "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring". For example, as shown in FIG. 15B, the back gate of the transistor M1 may be electrically connected to the first terminal of the capacitor C1 and the first terminal of the transistor M2.

[0259] Furthermore, the semiconductor device according to one embodiment of the present invention does not depend on the connection configuration of the backgate of the transistor. Although the backgates of the transistors M1 to M4 illustrated in FIG. 15A are illustrated, and the connection configuration of the backgates is not illustrated, the electrical connection destination of the backgates can be determined at the design stage. For example, in a transistor having a backgate, the gate and the backgate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the backgate of the transistor M2 may be electrically connected. For example, in a transistor having a backgate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring electrically connected to an external circuit or the like may be provided, and a fixed potential or a variable potential may be applied to the backgate of the transistor by the external circuit or the like. Note that this is true not only for FIG. 15A but also for transistors described in other parts of the specification or transistors illustrated in other drawings.

[0260] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the semiconductor device. For example, the transistors M1 to M4 illustrated in FIG. 15A may have a structure without a backgate, that is, a single-gate structure, as illustrated in FIG. 15C. Some of the transistors may have a backgate, and other transistors may not have a backgate. This applies not only to the circuit diagram illustrated in FIG. 15A, but also to transistors described elsewhere in the specification or illustrated in other drawings.

[0261] In addition, in this specification and the like, transistors with various structures can be used as the transistor. Therefore, the type of the transistor used is not limited. As an example of the transistor, a transistor having single crystal silicon, or a transistor having a non-single crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, or semi-amorphous) silicon, or the like can be used. Alternatively, a thin film transistor (TFT) in which such a semiconductor is thinned can be used. There are various advantages in using a TFT. For example, since the TFT can be manufactured at a lower temperature than the case of single crystal silicon, the manufacturing cost can be reduced or the manufacturing equipment can be enlarged. Since the manufacturing equipment can be enlarged, the TFT can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, the display devices can be manufactured at low cost. Alternatively, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, the transistor can be manufactured on a substrate having light-transmitting properties. Alternatively, the light transmission in the display element can be controlled by using a transistor on a substrate having light-transmitting properties. Alternatively, since the film thickness of the transistor is thin, a part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

[0262] As an example of the transistor, a transistor having a compound semiconductor (e.g., SiGe, GaAs, etc.) or an oxide semiconductor (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.) can be used. Alternatively, a thin film transistor in which these compound semiconductors or these oxide semiconductors are thinned can be used. This allows the manufacturing temperature to be lowered, so that it is possible to manufacture a transistor at room temperature, for example. As a result, a transistor can be formed directly on a substrate with low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, pixel electrodes, or electrodes having light-transmitting properties. Since they can be formed or deposited simultaneously with the transistor, costs can be reduced.

[0263] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. These methods allow manufacturing at room temperature, at a low degree of vacuum, or on a large substrate. Therefore, since manufacturing is possible without using a mask (reticle), the layout of the transistor can be easily changed. Alternatively, since manufacturing is possible without using a resist, material costs can be reduced and the number of steps can be reduced. Alternatively, since a film can be applied only to a necessary portion, materials are not wasted and costs can be reduced compared to a manufacturing method in which a film is formed on the entire surface and then etched.

[0264] As an example of a transistor, a transistor having an organic semiconductor, a carbon nanotube, or the like can be used. This allows a transistor to be formed on a substrate that can be bent. A device using a transistor having an organic semiconductor, a carbon nanotube, or the like can be made resistant to impact.

[0265] It should be noted that transistors of various other structures can be used as the transistors. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistors. By using MOS transistors as the transistors, the size of the transistors can be reduced. Thus, a large number of transistors can be mounted. By using bipolar transistors as the transistors, a large current can be passed. Thus, the circuit can be operated at high speed. It should be noted that MOS transistors and bipolar transistors may be mixed and formed on one substrate. This allows low power consumption, miniaturization, high speed operation, etc. to be realized.

[0266] As an example of a transistor, a transistor having a structure in which gate electrodes are arranged above and below an active layer can be applied. By adopting a structure in which gate electrodes are arranged above and below an active layer, a circuit configuration in which multiple transistors are connected in parallel is obtained. This increases the channel formation region, making it possible to increase the current value. Alternatively, by adopting a structure in which gate electrodes are arranged above and below an active layer, it becomes easier to form a depletion layer, making it possible to improve the S value.

[0267] As an example of a transistor, a transistor having a structure in which a gate electrode is disposed above an active layer, a structure in which a gate electrode is disposed below an active layer, a positive staggered structure, an inverted staggered structure, a structure in which a channel region is divided into a plurality of regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series can be used. Alternatively, the transistor can have various configurations, such as a planar type, a FIN type, a TRI-GATE type, a top gate type, a bottom gate type, a double gate type (gates are disposed above and below a channel), and the like.

[0268] As an example of the transistor, a transistor having a structure in which at least one of a source electrode and a drain electrode overlaps with an active layer (or a part of it) can be used. By using a structure in which at least one of a source electrode and a drain electrode overlaps with an active layer (or a part of it), it is possible to prevent the operation from becoming unstable due to accumulation of electric charges in a part of the active layer.

[0269] As an example of a transistor, a structure with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-current or improve the breakdown voltage (improve reliability) of the transistor. In addition, by providing the LDD region, even if the voltage between the drain and source changes when operating in the saturation region, the drain current does not change much, and it is possible to obtain voltage-current characteristics with a flat slope.

[0270] For example, in the present specification and the like, a transistor can be formed using various substrates. The type of substrate is not limited to a specific one. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, base films, and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, for example, there is a synthetic resin such as acrylic. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, a transistor with small variations in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

[0271] Alternatively, a flexible substrate may be used as the substrate, and the transistor may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistor. The peeling layer can be used to separate the semiconductor device from the substrate after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate. In this case, the transistor can be transferred to a substrate having poor heat resistance, a flexible substrate, or the like. Note that the above-mentioned peeling layer may be, for example, a laminated structure of inorganic films of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0272] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Examples of substrates onto which transistors are transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are not easily broken, impart heat resistance, and reduce weight or thickness.

[0273] It is possible to form all of the circuits required to realize a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). This makes it possible to reduce costs by reducing the number of components, or to improve reliability by reducing the number of connections to the circuit components.

[0274] It is possible that all of the circuits required to realize the predetermined function are not formed on the same substrate. That is, a part of the circuit required to realize the predetermined function is formed on one substrate, and another part of the circuit required to realize the predetermined function is formed on another substrate. For example, a part of the circuit required to realize the predetermined function is formed on a glass substrate, and another part of the circuit required to realize the predetermined function is formed on a single crystal substrate (or an SOI substrate). Then, the single crystal substrate (also called an IC chip) on which another part of the circuit required to realize the predetermined function is formed can be connected to the glass substrate by COG (Chip On Glass), and the IC chip can be arranged on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, by forming a part of the circuit on the same substrate as the pixel portion, it is possible to reduce the cost by reducing the number of components, or to improve the reliability by reducing the number of connections with the circuit components. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, such circuits are formed on a substrate (such as a single crystal substrate) separate from the pixel section to form an IC chip. By using this IC chip, it is possible to prevent an increase in power consumption.

[0275] In the circuit MP of FIG. 15A, a first terminal of the transistor M1 is electrically connected to the wiring VE. A second terminal of the transistor M1 is electrically connected to a first terminal of the transistor M3 and a first terminal of the transistor M4. A gate of the transistor M1 is electrically connected to a first terminal of the capacitor C1 and a first terminal of the transistor M2. A second terminal of the capacitor C1 is electrically connected to the wiring VE. A second terminal of the transistor M2 is electrically connected to the wiring OL. A gate of the transistor M2 is electrically connected to the wiring WL. A second terminal of the transistor M3 is electrically connected to the wiring OL, and a gate of the transistor M3 is electrically connected to the wiring WX1L. A second terminal of the transistor M4 is electrically connected to the wiring OLB, and a gate of the transistor M4 is electrically connected to the wiring X2L.

[0276] A connection configuration in the circuit MCr that is different from that in the circuit MC will be described. A second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and a second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. A first terminal of the transistor M1r and a first terminal of the capacitor C1r are electrically connected to the wiring VEl.

[0277] As shown in FIG. 16A, the first terminal of the transistor M1 may be electrically connected to the wiring VEm as a separate wiring, instead of the wiring VE. Similarly, the first terminal of the transistor M1r may be electrically connected to the wiring VEmr as a separate wiring, instead of the wiring VE. In the circuit diagrams of the other drawings as well as FIG. 16A, the first terminal of the transistor M1 may be electrically connected to the wiring VEm as a separate wiring, instead of the wiring VE, and / or the first terminal of the transistor M1r may be electrically connected to the wiring VEmr as a separate wiring, instead of the wiring VE.

[0278] In the circuit HC shown in FIG. 15A, the electrical connection point between the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as a node n1.

[0279] As described in the first embodiment, the circuit HC has a function of holding a potential corresponding to the first data, for example. The potential is held in the circuit HC included in the circuit MC in FIG. 15A by inputting a potential from the wiring OL and writing it in the capacitor C1 when the transistors M2 and M3 are turned on, and then turning off the transistor M2. This allows the potential of the node n1 to be held as a potential corresponding to the first data. At this time, a current is input from the wiring OL, and a potential having a magnitude corresponding to the magnitude of the current can be held in the capacitor C1. This allows the influence of variations in the current characteristics of the transistor M1 to be reduced.

[0280] In order to hold the potential of the node n1 for a long time, it is preferable to use a transistor with low off-state current as the transistor M1. For example, an OS transistor can be used as the transistor with low off-state current. Alternatively, a transistor having a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side and reduce the off-state current.

[0281] In an operation example described later, in order to simply explain the current flowing in and out of the circuit MP, both ends of the wiring OL shown in FIG. 15A are respectively referred to as node ina and node outa, and both ends of the wiring OLB are respectively referred to as node inb and node outb.

[0282] For example, the wiring VE functions as a wiring that supplies a constant voltage. When the transistor M3, the transistor M3r, the transistor M4, or the transistor M4r is an n-channel transistor and / or when the potential provided by the wiring VSO in FIG. 8A to FIG. 8D is a high-level potential, the constant voltage may be, for example, a low-level potential VSS, a ground potential, or other low-level potentials. Similarly to the wiring VE, each of the wirings VEm, VEr, and VEmr functions as a voltage line that supplies a constant voltage, and the constant voltage may be a low-level potential VSS, a low-level potential other than VSS, a ground potential, or the like. The constant voltage may be a high-level potential VDD. In this case, when any of Figures 5A to 5E, Figures 6A to 6D, and Figure 6F is applied as the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, the arithmetic circuit 140, the arithmetic circuit 150, and the arithmetic circuit 160, it is preferable that the constant voltage provided by the wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is a potential higher than the potential VDD provided by the wiring VE and the wiring VEr.

[0283] In addition, the constant voltages supplied by the wiring VE, wiring VEm, wiring VEl, and wiring VEmr may be different from each other, or may be partly or entirely the same. In addition, when the voltages supplied by each wiring are the same, those wirings may be selected and made the same wiring. For example, when the constant voltages supplied by the wiring VE, wiring VEm, wiring VEl, and wiring VEmr are almost equal, the wiring VEm, wiring VEl, and wiring VEmr can be made the same wiring as the wiring VE, as in the circuit MP of FIG. 16B. Alternatively, when the constant voltages supplied by the wiring VE and wiring VEl are almost equal, the wiring VE and wiring VEl can be made the same wiring. Alternatively, when the constant voltages supplied by the wiring VEm and wiring VEmr are almost equal, the wiring VEm and wiring VEmr can be made the same wiring. Similarly, in FIG. 16A, for example, the wiring VE and wiring VEl may be made the same wiring, and the wiring VEm and wiring VEmr may be made the same wiring. Alternatively, for example, the wiring VE and the wiring VEmr may be one and the same wiring, and the wiring VEm and the wiring VEr may be one and the same wiring.

[0284] Also, the configuration of the circuit MP in FIG. 15A can be changed depending on the situation. For example, as shown in FIG. 17A, the transistor M1, the transistor M1r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r in the circuit MP in FIG. 15A may be replaced with p-channel transistors, such as the transistor M1p, the transistor M1pr, the transistor M3p, the transistor M3pr, the transistor M4p, and the transistor M4pr. As an example, p-channel transistors having an SOI (Silicon On Insulator) structure can be applied as the transistors M3p, M3pr, M4p, and M4pr. Also, in this case, it is preferable that the constant voltage provided by the wiring VE and the wiring VEr is VDD, which is a high-level potential. 5A to 5E, 6A to 6D, and 6F are used as the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, the arithmetic circuit 140, the arithmetic circuit 150, and the arithmetic circuit 160, the constant voltage applied by the wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is preferably the ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of the current flow is also changed.

[0285] Similarly, the transistor M2 may be replaced with a p-channel transistor (not shown).

[0286] 17B, ​​the transistors M4 and M4r in the circuit MP in FIG. 15A may be replaced with p-channel transistors M4p and M4pr, respectively. By combining the wirings connected to the gates of the transistors M3, M3r, M4p, and M4pr into a single wiring WXL, the circuit MP can hold first data other than 0 (e.g., a weighting coefficient, etc.).

[0287] Also, for example, as shown in FIG. 17C, the transistors M3, M3r, M4, and M4r of the circuit MP in FIG. 15A may be replaced with analog switches AS3, AS4, AS3r, and AS4r, respectively. Note that FIG. 17C also illustrates wiring WX1LB and wiring X2LB for operating the analog switches AS3, AS4, AS3r, and AS4r. The wiring WX1LB is electrically connected to the analog switches AS3 and AS3r, and the wiring X2LB is electrically connected to the analog switches AS4 and AS4r. The wiring WX1LB receives an inverted signal of a signal input to the wiring WX1L, and the wiring X2LB receives an inverted signal of a signal input to the wiring X2L. Also, the wiring WX1L and the wiring X2L may be combined into one wiring, and the wiring WX1LB and the wiring X2LB may be combined into one wiring (not illustrated). As an example, the analog switch AS3, the analog switch AS4, the analog switch AS3r, and the analog switch AS4r may have a CMOS configuration using n-channel transistors and p-channel transistors.

[0288] Moreover, it is preferable that the sizes, for example, the channel length and the channel width, of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r shown in FIG. 15A to FIG. 15C, FIG. 16A, and FIG. 16B are equal to each other. By using such a circuit configuration, it is possible to efficiently layout the transistors. It is also possible to make the currents flowing through the transistors M3, the transistor M3r, the transistor M4, and the transistor M4r uniform. Similarly, it is preferable that the sizes of the transistors M1 and the transistors M1r shown in FIG. 15A to FIG. 15C, FIG. 16A, and FIG. 16B are equal to each other. Similarly, it is preferable that the sizes of the transistors M2 and the transistors M2r shown in FIG. 15A to FIG. 15C, FIG. 16A, and FIG. 16B are equal to each other. Similarly, it is preferable that the sizes of the transistors M1p and the transistors M1pr shown in FIG. 17A are equal to each other. Similarly, it is preferable that the sizes of the transistors M3p, the transistors M3pr, the transistors M4p, and the transistors M4pr shown in FIG. 17A are equal to each other.

[0289] <<Example of operation>> Next, an operation example of the circuit MP shown in Fig. 15A will be described. Figs. 18A to 18C, 19A to 19C, and 20A to 20C are timing charts showing an operation example of the circuit MP, each showing fluctuations in the potentials of the wiring WL, the wiring WX1L, the wiring X2L, the node n1, and the node n1r. Note that in Figs. 18A to 18C, 19A to 19C, and 20A to 20C, "high" indicates a high-level potential, and "low" indicates a low-level potential. In this operation example, the amount of current output from the wiring OL to the node outa (or from the node outa to the wiring OL) is I OL In addition, the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is I OLB In the timing charts shown in FIGS. 18A to 18C, 19A to 19C, and 20A to 20C, I OL , I OLB The change in is also shown.

[0290] In this operation example, the constant voltage applied by the wiring VE and the wiring VEl is VSS (low-level potential). In this case, in Fig. 8A to Fig. 8D, a high-level potential is applied to the wiring VSO, and a current flows from the wiring VSO to the wiring VE or the wiring VEl via the switching circuit TW and the wiring OL. Similarly, a current flows from the wiring VSO to the wiring VE or the wiring VEl via the switching circuit TW and the wiring OLB.

[0291] In this operation example, the potential applied by the wiring VCN in FIG. 8A is VSS. By bringing electrical continuity between the wiring VCN and the second terminal of the transistor M1, VSS is applied to the second terminal of the transistor M1. As will be described in detail later, at this time, the potential of the gate of the transistor M1 also becomes VSS, so that the transistor M1 is turned off. Similarly, by bringing electrical continuity between the wiring VCN and the second terminal of the transistor M1r, the potential of the second terminal and the gate of the transistor M1r becomes VSS, so that the transistor M1r is turned off.

[0292] In the circuit MP shown in FIG. 15A, when the transistors M2 and M3 are in an on state, the transistor M1 is in a diode-connected configuration. Therefore, when a current flows from the wiring OL to the circuit MC, the potentials of the second terminal of the transistor M1 and the gate of the transistor M1 are approximately equal. The potential is determined by the amount of current flowing from the wiring OL to the circuit MC and the potential of the first terminal of the transistor M1 (here, VSS), etc. Here, the potential of the gate of the transistor M1 is held in the capacitor C1, and then the transistor M2 is turned off, so that the transistor M1 functions as a current source that flows a current according to the potential of the gate of the transistor M1. Therefore, it is possible to reduce the influence of variations in the current characteristics of the transistor M1.

[0293] For example, when the transistors M2 and M3 are in an on state, a current I is applied from the wiring OL to the wiring VE via the circuit MC. 1When the current flows, the potential of the gate (node ​​n1) of transistor M1 is V 1 Here, by turning off the transistor M2, V 1 is held by the circuit HC. As a result, the transistor M1 is held at a potential VSS of the first terminal of the transistor M1 and a potential V 1 The current I 1 In this specification, this operation is referred to as "the transistor M1 controls the amount of current flowing between the source and drain of the transistor M1 to I 1 "The amount of current flowing between the source and drain of transistor M1 is set to I 1 This is referred to as "programmed into the system."

[0294] In this operation example, the amount of current flowing from the wiring OL to the circuit MC is 0, I 1 , I 2 Therefore, the amount of current set in the transistor M1 is 0, I 1 , I 2 For example, when the potential of the gate of transistor M1 held in the circuit HC is VSS, the potentials of the first and second terminals of transistor M1 are also VSS, so if the threshold voltage of transistor M1 is higher than 0, transistor M1 is turned off. Therefore, no current flows between the source and drain of transistor M1, so it can be said that the amount of current flowing between the source and drain of transistor M1 is set to 0. Also, for example, when the potential of the gate of transistor M1 held in the circuit HC is V 1 When the threshold voltage of transistor M1 is V 1 If the voltage is lower than -VSS, the transistor M1 is turned on. At this time, the amount of current flowing through the transistor M1 is I 1 Therefore, the gate potential of transistor M1 is V 1 When the current flowing between the source and drain of the transistor M1 is I 1For example, the potential of the gate of the transistor M1 held in the circuit HC is set to V 2 When the threshold voltage of transistor M1 is V 2 If the voltage is lower than -VSS, the transistor M1 is turned on. At this time, the amount of current flowing through the transistor M1 is I 2 Therefore, the gate potential of transistor M1 is V 2 When the current flowing between the source and drain of the transistor M1 is I 2 It can be said that it is set to.

[0295] In addition, I 1 The current flow is greater than 0 and I 2 Also, the potential V 1 is higher than VSS, and V 2 The threshold voltage of the transistor M1 is higher than 0 and V 1 -VSS or lower. Also, I 1 For example, in the description of FIG. 8A, I ut and I 2 For example, in the description of FIG. 8A, the constant current source circuit ISC2 generates 2I ut can be replaced with.

[0296] Before describing the operation example, the first data (here, a weighting coefficient, for example) held by the circuit MP is defined as follows. When VSS is held at node n1 of the circuit HC and VSS is held at node n1r of the circuit HCr, the circuit MP is assumed to hold "0" as the first data (weighting coefficient). When VSS is held at node n1 of the circuit HC, 1 When VSS is held at node n1r of circuit HCr, circuit MP holds “+1” as the first data (weighting coefficient). 2When VSS is held at node n1r of circuit HCr, circuit MP holds "+2" as the first data (weighting coefficient). 1 When the first data (weighting coefficient) is held, the circuit MP holds "-1". VSS is applied to the node n1 of the circuit HC, and V is applied to the node n1r of the circuit HCr. 2 is held, the circuit MP holds "-2" as the first data (weighting coefficient).

[0297] Moreover, the second data (for example, the value (computed value) of the neuron signal) input to the circuit MP is defined as follows, for example. When a high-level potential is applied to the wiring WX1L and a low-level potential is applied to the wiring X2L, "+1" is input to the circuit MP as the second data (value of the neuron signal). When a low-level potential is applied to the wiring WX1L and a high-level potential is applied to the wiring X2L, "-1" is input to the circuit MP as the second data (value of the neuron signal). When a low-level potential is applied to the wiring WX1L and a low-level potential is applied to the wiring X2L, "0" is input to the circuit MP as the second data (value of the neuron signal). Note that, as an example, the high-level potential is VDD or a potential that is 10% or more higher than VDD, or 20% or more higher.

[0298] In addition, in this specification and the like, unless otherwise specified, the transistor M1 and the transistor M1r are assumed to include a case where they finally operate in the saturation region when they are in an on state. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are assumed to include a case where they are appropriately biased to a voltage within a range in which they operate in the saturation region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude value of the voltage supplied, the transistor M1 and the transistor M1r may operate in a linear region. In addition, in order to reduce the amount of current flowing through the transistor M1 and the transistor M1r, the transistor M1 and the transistor M1r may operate in a subthreshold region. Alternatively, the transistor M1 and the transistor M1r may be operated near the boundary between the saturation region and the subthreshold region. In addition, when the first data (weighting coefficient) is an analog value, for example, the transistor M1 and the transistor M1r may operate in a linear region, a saturation region, and a subthreshold region depending on the magnitude of the first data (weighting coefficient). Alternatively, the transistor M1 and the transistor M1r may operate in a linear region and a saturation region in a mixed manner, or may operate in a subthreshold region and a linear region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner.

[0299] In addition, in this specification and the like, unless otherwise specified, the transistor M2, the transistor M2r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r include a case where they finally operate in a linear region when they are in an on state. That is, the gate voltage, the source voltage, and the drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within a range in which they operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistor M2, the transistor M2r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r may operate in a saturation region or a subthreshold region when they are in an on state. Alternatively, the transistor M2, the transistor M2r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r may be operated near the boundary between the saturation region and the subthreshold region. Alternatively, transistor M2, transistor M2r, transistor M3, transistor M3r, transistor M4, and transistor M4r may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a subthreshold region and a linear region, or may operate in a linear region, a saturation region, and a subthreshold region.

[0300] In the following, an example of the operation of the circuit MP will be described for each combination of values ​​that the first data (for example, hereinafter referred to as a weighting coefficient) and the second data (for example, hereinafter referred to as the value (calculated value) of the neuron signal) can take.

[0301] [Condition 1] First, as an example, consider a case where the first data (weighting coefficient) is "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "+1." Figure 18A is a timing chart of the circuit MP in this case.

[0302] Between time T1 and time T2, the circuits HC and HCr are held at initial potentials. In Fig. 18A, for example, it is assumed that the nodes n1 and n1r are held at initial potentials that are higher than the potential VSS.

[0303] A low-level potential is applied to the wiring WL, the wiring WX1L, and the wiring X2L. As a result, a low-level potential is input to each of the gates of the transistor M2, the transistor M2r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r, so that each of the transistor M2, the transistor M2r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r is turned off.

[0304] Between time T2 and time T3, a high-level potential is applied to the wiring WL and the wiring WX1L, so that the high-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, and the transistors M2, M2r, M3, and M3r are turned on.

[0305] Although not shown in FIG. 18A, the wiring OL and the wiring OLB are each supplied with an initialization potential V ini Since the transistors M2, M2r, M3, and M3r are in an on state, the potentials of the node n1 of the circuit HC and the node n1r of the circuit HCr are V ini That is, during the period from time T2 to time T3, the potentials of the node n1 of the circuit HC and the node n1r of the circuit HCr are initialized.

[0306] In addition, the initialization potential V ini For example, it is preferable to set the potential V iniThe initial potential V may be VSS, a potential higher than the ground potential, or a potential lower than the ground potential. ini Note that the wirings OL and OLB may be supplied with an initialization potential V ini It is not necessary to input the time T2. It is not necessary to provide a period from time T2 to time T3. Also, it is not necessary to perform the initialization from time T2 to time T3.

[0307] Between time T3 and time T4, the potential VSS is input from the wiring OL to the circuit MC, and the potential VSS is input from the wiring OLB to the circuit MCr. This is done by turning on the switches SWL and SWLB and turning off the switches SWI, SWIB, SWO, SWOB, SWH, and SWHB in FIG. 8A. As a result, the potential of the node n1 in the circuit HC becomes VSS, and the potential of the node n1r in the circuit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 is set to pass 0 as the amount of current, so that no current flows from the wiring OL to the wiring VE through the circuit MC. Also, in the circuit MCr, the transistor M1r is set to pass 0 as the amount of current, so that no current flows from the wiring OLB to the wiring VE through the circuit MCr. In other words, between time T3 and time T4, the transistor M1 and the transistor M1r are in the off state, so that there is no conduction between the wiring OL and the wiring VE, and there is no conduction between the wiring OLB and the wiring VEr.

[0308] Between time T4 and time T5, a low-level potential is applied to the wiring WL and the wiring WX1L. As a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, so that the transistors M2, M2r, M3, and M3r are turned off. As the transistors M2 and M2r are turned off, the potential VSS of the node n1 of the circuit HC is maintained, and the potential VSS of the node n1r of the circuit HCr is maintained. As the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE through the circuit MC. Similarly, as the transistor M3r is turned off, no current flows from the wiring OLB to the wiring VE through the circuit MCr.

[0309] By the operation from time T1 to time T5, "0" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB in FIG. 8A may be turned off. After the weighting coefficient is set in the circuit MP (for example, between time T4 and time T5), the switches SWH and SWHB may be turned on to precharge the potentials of the wirings OL and OLB to a potential (for example, a high-level potential) provided by the wiring VCN2. After the wirings OL and OLB are precharged to a high-level potential, the switches SWH and SWHB may be turned off.

[0310] After time T5, a high-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of a neuron signal (computation value) "+1" to the circuit MP. At this time, a high-level potential is input to the gates of the transistors M3 and M3r, and a low-level potential is input to the gates of the transistors M4 and M4r. Therefore, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. That is, this operation causes a conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a non-conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0311] At this time, in FIG. 8A, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, so that the wiring OL and wiring OLB are electrically connected to the circuit AFP. Note that since the transistor M1 is turned off (since the amount of current is set to 0), no current flows from the wiring OL and wiring OLB to the wiring VE in the circuit MC. Similarly, since the transistor M1r is turned off (since the amount of current is set to 0), no current flows from the wiring OL and wiring OLB to the wiring VE in the circuit MCr. From the above, the current I output from the node outa of the wiring OL is OL , and the current I output from node outb of wiring OLB OLB does not change before and after time T5. Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0312] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "+1", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that, in the operation of the circuit MP, the current I OL and current I OLB In addition, the result of the product of the first data (weighting coefficient) and the second data (value of the neuron signal) being "0" corresponds to the case where the signal z j (k) will be output as:

[0313] Once the first data (e.g., weighting coefficient, etc.) is input, multiple product-sum operations can be performed by changing only the second data (neuron signal value, calculated value, etc.) without updating the first data (weighting coefficient, etc.). In this case, since there is no need to update the first data (weighting coefficient), power consumption can be reduced. In order to reduce the number of updates to the first data (weighting coefficient), it is necessary to hold the first data (weighting coefficient) for a long period of time. In this case, for example, if an OS transistor is used, it is possible to hold the first data (weighting coefficient) for a long period of time by taking advantage of its low off-current.

[0314] [Condition 2] Next, as an example, consider a case where the first data (weighting coefficient) is "+1" and the second data (value (calculated value) of the neuron signal) input to the circuit MP is "+1". Figure 18B is a timing chart of the circuit MP in this case.

[0315] The operation from time T1 to time T3 is similar to the operation from time T1 to time T3 in condition 1, so the explanation of the operation from time T1 to time T3 in condition 1 shall be taken into consideration.

[0316] Between time T3 and time T4, the current from wiring OL to circuit MC is I 1 is input to the circuit MCr, and the potential VSS is input from the wiring OLB to the circuit MCr. This is done by turning on the switches SWI and SWLB and turning off the switches SWIB, SWO, SWOB, SWH, and SWHB in FIG. 8A. As a result, the potential of the node n1 of the circuit HC becomes V 1 As a result, the potential of the node n1r of the circuit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 has a current I 1 Therefore, the current is set to I from the wiring OL through the circuit MC to the wiring VE. 1 In the circuit MCr, the transistor M1r is set to pass a current of 0, so that no current flows from the wiring OLB to the wiring VEl via the circuit MCr.

[0317] Between time T4 and time T5, a low-level potential is applied to the wiring WL and the wiring WX1L. As a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, and the transistors M2, M2r, M3, and M3r are turned off. With the transistors M2 and M2r turned off, the potential V 1 is held, and the potential VSS of the node n1r of the circuit HCr is held. In addition, because the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE through the circuit MC. Similarly, because the transistor M3r is turned off, no current flows from the wiring OLB to the wiring VE through the circuit MCr.

[0318] By the operation from time T1 to time T5, "+1" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB in FIG. 8A may be turned off. After the first data (weighting coefficient) is set in the circuit MP, the switches SWH and SWHB may be turned on to precharge the wirings OL and OLB to a potential (for example, a high-level potential) provided by the wiring VCN2. After the wirings OL and OLB are precharged to a high-level potential, the switches SWH and SWHB may be turned off.

[0319] After time T5, a high-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of second data (neuron signal value (computed value)) "+1" to the circuit MP. At this time, a high-level potential is input to the gates of the transistors M3 and M3r, and a low-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a non-conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0320] 8A, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, so that the wirings OL and OLB are electrically connected to the circuit AFP. In the circuit MC, the transistor M3 is turned on, and the transistor M1 is turned on (the amount of current is I 1current flows from the wiring OL to the wiring VE. In the circuit MC, the transistor M4 is in the off state, so no current flows from the wiring OLB to the wiring VE. Meanwhile, in the circuit MCr, the transistor M3r is in the on state, but the transistor M1r is in the off state (since the transistor M3r is set to pass a current of 0), so no current flows from the wiring OLB to the wiring VE. In the circuit MCr, the transistor M4r is in the off state, so no current flows from the wiring OLB to the wiring VE. In the circuit MCr, the transistor M4r is in the off state, so no current flows from the wiring OL to the wiring VE. From the above, the current I OL After time T5, 1 The current I OLB does not change before and after time T5. Therefore, the amount of current I 1 The current I OL flows, and the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0321] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value) input to the circuit MP is set to "+1", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1" is that in the operation of the circuit MP, the current I OL I 1 The current I OLB This corresponds to the case where the product of the first data (weighting coefficient) and the second data (neuron signal value) is “+1”, as shown in FIG. 8A, the signal z j (k) will be output as:

[0322] In addition, during the period from time T3 to time T4 under this condition, for example, the current flowing from the wiring OL to the circuit MC is I 1Not I 2 By setting 2 This sets the first data (weighting coefficient) of the circuit MP to "+2". By setting the first data (weighting coefficient) to "+2" and the neuron signal input to the circuit MP to "+1", the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+2" according to equation (1.1). The product of the first data (weighting coefficient) and the second data (neuron signal value) being "+2" results in the operation of the circuit MP being such that, from time T5 onwards, the current I OL I 2 The current I OLB In this way, in the circuit MCr, VSS is held in the circuit HCr, and the amount of current I 1 By setting a value other than "+1", it is possible to set a positive value other than "+1" as the first data (weighting coefficient) of the circuit MP.

[0323] [Condition 3] Next, as an example, consider a case where the first data (weighting coefficient) is "-1" and the second data (value (calculated value) of the neuron signal) input to the circuit MP is "+1." Figure 18C is a timing chart of the circuit MP in this case.

[0324] The operation from time T1 to time T3 is similar to the operation from time T1 to time T3 in condition 1, so the explanation of the operation from time T1 to time T3 in condition 1 shall be taken into consideration.

[0325] Between time T3 and time T4, a potential VSS is input from the wiring OL to the circuit MC, and a current I flows from the wiring OLB to the circuit MCr. 1 8A, this is done by turning on the switches SWIB and SWL and turning off the switches SWI, SWO, SWOB, SWLB, SWH, and SWHB. As a result, the potential of the node n1 of the circuit HC becomes VSS, and the potential of the node n1r of the circuit HCr becomes VSS.1 As a result, in the circuit MC, the transistor M1 is set to pass a current of 0, so no current flows from the wiring OL to the wiring VE via the circuit MC. Also, in the circuit MCr, the transistor M1r passes a current of I 1 Therefore, the current is set to I from the wiring OLB through the circuit MCr to the wiring VEl. 1 flows.

[0326] Between time T4 and time T5, a low-level potential is applied to the wiring WL and the wiring WX1L. As a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, and the transistors M2, M2r, M3, and M3r are turned off. With the transistors M2 and M2r turned off, the potential VSS of the node n1 of the circuit HC is held, and the potential V 1 is maintained. In addition, when the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, when the transistor M3r is turned off, no current flows from the wiring OLB to the wiring VE through the circuit MCr.

[0327] By the operation from time T1 to time T5, "-1" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB in FIG. 8A may be turned off. After the first data (weighting coefficient) is set in the circuit MP, the switches SWH and SWHB may be turned on to precharge the wirings OL and OLB to a potential (for example, a high-level potential) provided by the wiring VCN2. After the wirings OL and OLB are precharged to a high-level potential, the switches SWH and SWHB may be turned off.

[0328] After time T5, a high-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of second data (neuron signal value (computed value)) "+1" to the circuit MP. At this time, a high-level potential is input to the gates of the transistors M3 and M3r, and a low-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a non-conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0329] At this time, in FIG. 8A, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, the transistor M3 is turned on, but the transistor M1 is turned off (set to pass 0 as a current amount), so no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the transistor M4 is turned off, so no current flows from the wiring OLB to the wiring VE. Meanwhile, in the circuit MCr, the transistor M3r is turned on and the transistor M1r is turned on (set to pass I 1 (Because the second terminal of the transistor M1r is set to pass the potential of the wiring OLB and the potential of the wiring OLB is input to the second terminal of the transistor M1r), a current flows from the wiring OLB to the wiring VEl. In addition, in the circuit MCr, because the transistor M4r is in the off state, no current flows from the wiring OL to the wiring VEl. From the above, the current I OL does not change before and after time T5, and the current I OLB After time T5, 1Therefore, the current I OL does not flow, and the current I 1 The current I OLB flows.

[0330] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "+1". Therefore, when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is that, in the operation of the circuit MP, the current I OL does not change, and the current I OLB I 1 In addition, the result of the product of the first data (weighting coefficient) and the second data (value of the neuron signal) being "-1" corresponds to the signal z j (k) will be output as:

[0331] In addition, during the period from time T3 to time T4 under this condition, for example, the current flowing from the wiring OLB to the circuit MCr is I 1 Not I 2 By setting the V 2 This sets "-2" as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "-2" and the second data (neuron signal value) input to the circuit MP to "+1", the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-2" according to equation (1.1). The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-2" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB I 2 In this way, in the circuit MC, VSS is held in the circuit HC, and the amount of current in the circuit MCr is I 1By setting a value other than "-1", it is possible to set a negative value other than "-1" as the weighting coefficient of the circuit MP.

[0332] [Condition 4] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 19A is a timing chart of the circuit MP in this case.

[0333] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 1, so the explanation of the operation from time T1 to time T5 in condition 1 shall be taken into consideration.

[0334] After time T5, a low-level potential is input to the wiring WX1L and a high-level potential is input to the wiring X2L as an input of the second data (value (computed value) of the neuron signal) "-1" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3 and M3r, and a high-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are each turned off, and the transistors M4 and M4r are each turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0335] At this time, in Fig. 8A, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, and SWLB are turned off, so that the wirings OL and OLB are electrically connected to the circuit AFP. Note that since the transistor M1 is turned off (since the transistor M1 is set to pass a current of 0), no current flows from the wirings OL and OLB to the wiring VE in the circuit MC. In other words, the current I output from the node outa of the wiring OL is OL, and the current I output from node outb of wiring OLB OLB does not change before and after time T5. Similarly, since the transistor M1r is in the off state (since the transistor M1r is set to pass a current of 0), no current flows through the wiring OL and from the wiring OLB to the wiring VEl in the circuit MCr. In other words, the current I OL , and the current I output from node outb of wiring OLB OLB The current I OL does not flow, and the current I OLB does not flow.

[0336] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "-1". Therefore, when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0", in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) are changed, which is consistent with the circuit operation result under condition 1. Note that, as in condition 1, the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the result of the signal z j (k) will be output as:

[0337] [Condition 5] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "+1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 19B is a timing chart of the circuit MP in this case.

[0338] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 2, so the explanation of the operation from time T1 to time T5 in condition 2 shall be taken into consideration.

[0339] After time T5, a low-level potential is input to the wiring WX1L and a high-level potential is input to the wiring X2L as an input of the second data (value (computed value) of the neuron signal) "-1" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3 and M3r, and a high-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are each turned off, and the transistors M4 and M4r are each turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0340] At this time, in FIG. 8A, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, since the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the transistor M4 is turned on, and the transistor M1 is turned on (the amount of current is I 1flow and the potential of the wiring OL is input to the second terminal of the transistor M1), so a current flows from the wiring OLB to the wiring VE. Meanwhile, in the circuit MCr, the transistor M3r is in the off state, so no current flows from the wiring OLB to the wiring VEl. Also, in the circuit MCr, the transistor M4r is in the on state, but the transistor M1r is in the off state (since the transistor M4r is set to flow a current of 0), so no current flows from the wiring OL to the wiring VEl. From the above, the current I OL does not change before and after time T5, and the current I OLB After time T5, 1 Therefore, the current I OL does not flow, and the current I 1 The current I OLB flows.

[0341] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "-1". Therefore, when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is that, in the operation of the circuit MP, the current I OL does not change, and the current I OLB I 1 This corresponds to the case where the signal z increases, which is consistent with the circuit operation result of condition 3. Note that the result where the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1" is the same as in condition 3, and is the result where the signal z j (k) will be output as:

[0342] As described in Condition 2, during the period from time T3 to time T4 under this condition, for example, the current flowing from the wiring OL to the circuit MC is I 1 Not I 2and set the circuit HC to V 2 As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "+2" and the neuron signal input to the circuit MP to "-1", the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-2" according to formula (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB I 2 In this way, in the circuit MCr, VSS is held in the circuit HCr, and the amount of current I 1 By setting a value other than "+1", it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0343] [Condition 6] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 19C is a timing chart of the circuit MP in this case.

[0344] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 3, so the explanation of the operation from time T1 to time T5 in condition 3 shall be referred to.

[0345] After time T5, a low-level potential is input to the wiring WX1L and a high-level potential is input to the wiring X2L as an input of the second data (value (computed value) of the neuron signal) "-1" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3 and M3r, and a high-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are each turned off, and the transistors M4 and M4r are each turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a conductive state between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0346] At this time, in FIG. 8A, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, the transistor M3 is turned off, so no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the transistor M4 is turned on, but the transistor M1 is turned off (set to pass a current of 0), so no current flows from the wiring OLB to the wiring VE. Meanwhile, in the circuit MCr, the transistor M3r is turned off, so no current flows from the wiring OLB to the wiring VE. Also, in the circuit MCr, the transistor M4r is turned on, and the transistor M1r is turned on (set to pass a current of I 1 Since the transistor M1r is set to pass the potential of the wiring OLB and the potential of the wiring OLB is input to the second terminal of the transistor M1r, a current flows from the wiring OL to the wiring V Er. OL After time T5, 1 The current I OLBdoes not change before and after time T5. Therefore, the amount of current I 1 The current I OL flows, and the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0347] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "-1". Therefore, when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1", in the operation of the circuit MP, the current I OL changes, and the current I OLB does not change, which is consistent with the circuit operation result of condition 2. Note that the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1" is the same as condition 2, as shown in FIG. 8A when the signal z j (k) will be output as:

[0348] As described in Condition 3, during the period from time T3 to time T4 under this condition, for example, the current flowing from the wiring OLB to the circuit MCr is I 1 Not I 2 and set the circuit HCr to V 2 As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "-2" and the second data (value of the neuron signal) input to the circuit MP to "-1", the product of the first data (weighting coefficient) and the second data (value of the neuron signal) is "+2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (value of the neuron signal) being "+2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB I 2In this way, in the circuit MC, VSS is held in the circuit HC, and the amount of current I 1 By setting a value other than "-1", it is possible to set a negative value other than "-1" as the weighting coefficient of the circuit MP.

[0349] [Condition 7] In this condition, as an example, the operation of the circuit MP is considered under the condition 7 where the first data (weighting coefficient) is "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0". Fig. 20A is a timing chart of the circuit MP in this case.

[0350] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 1, so the explanation of the operation from time T1 to time T5 in condition 1 shall be taken into consideration.

[0351] After time T5, a low-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of second data (neuron signal value (computed value)) "0" to the circuit MP. At this time, a low-level potential is input to the gates of each of transistors M3, M3r, M4, and M4r. As a result, each of transistors M3, M3r, M4, and M4r is turned off. In other words, this operation causes a non-conductive state to be established between the circuit MC and the wiring OL, between the circuit MCr and the wiring OLB, between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0352] Therefore, in the circuit MC, regardless of the set amount of current flowing through the transistor M1, no current flows from the wiring OL to either the wiring VE or the wiring VEl. Similarly, in the circuit MCr, regardless of the set amount of current flowing through the transistor M1r, no current flows from the wiring OLB to the other of the wiring VE or the wiring VEl. In other words, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLBOLB do not change before and after time T5.

[0353] In addition, in FIG. 8A, even if the switches SWO and SWOB are turned on and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off to establish electrical continuity between the wiring OL and the wiring OLB and the circuit AFP, as described above, the current I OL does not flow, and the current I OLB does not flow.

[0354] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that, in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) are changed, which is consistent with the circuit operation results under conditions 1 and 4. Note that, as with conditions 1 and 4, the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the result of the signal z j (k) will be output as:

[0355] [Condition 8] In this condition, as an example, the operation of the circuit MP is considered under the condition 8 where the first data (weighting coefficient) is "+1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0". Figure 20B is a timing chart of the circuit MP in this case.

[0356] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 2, so the explanation of the operation from time T1 to time T5 in condition 2 shall be taken into consideration.

[0357] After time T5, a low-level potential is input to the wire WX1L and a low-level potential is input to the wire X2L as an input of the second data (value (computed value) of the neuron signal) "0" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3, M3r, M4, and M4r. Therefore, the transistors M3, M3r, M4, and M4r are each turned off. That is, as in condition 7, this operation results in a non-conductive state between the circuit MC and the wire OL, between the circuit MCr and the wire OLB, between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL, regardless of the set amount of current flowing through each of the transistors M1 and M1r. Therefore, no current flows from the wire OL to either the wire VE or the wire VEl, and no current flows from the wire OLB to the other of the wire VE or the wire VEl, so that the current I OL , and the current I output from node outb of wiring OLB OLB do not change before and after time T5.

[0358] In addition, in FIG. 8A, even if the switches SWO and SWOB are turned on and the switches SWI, SWIB, SWL, and SWLB are turned off to establish electrical continuity between the wiring OL and the wiring OLB and the circuit AFP, as described above, the current I OL does not flow, and the current I OLB does not flow.

[0359] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that, in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) are changed, which is consistent with the circuit operation results under conditions 1, 4, and 7. Note that the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the same as in conditions 1, 4, and 7, in FIG. 8A, when the signal z j (k) will be output as:

[0360] [Condition 9] In this condition, as an example, the operation of the circuit MP is considered under the condition 9 where the first data (weighting coefficient) is "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0". Fig. 20C is a timing chart of the circuit MP in this case.

[0361] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 3, so the explanation of the operation from time T1 to time T5 in condition 3 shall be referred to.

[0362] After time T5, a low-level potential is input to the wire WX1L and a low-level potential is input to the wire X2L as an input of the second data (value (computed value) of the neuron signal) "0" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3, M3r, M4, and M4r. Therefore, the transistors M3, M3r, M4, and M4r are each turned off. That is, as in condition 7, this operation results in a non-conductive state between the circuit MC and the wire OL, between the circuit MCr and the wire OLB, between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL, regardless of the set amount of current flowing through each of the transistors M1 and M1r. Therefore, no current flows from the wire OL to either the wire VE or the wire VEl, and no current flows from the wire OLB to the other of the wire VE or the wire VEl, so that the current I OL , and the current I output from node outb of wiring OLB OLB do not change before and after time T5.

[0363] In addition, in FIG. 8A, even if the switches SWO and SWOB are turned on and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off to establish electrical continuity between the wiring OL and the wiring OLB and the circuit AFP, as described above, the current I OL does not flow, and the current I OLB does not flow.

[0364] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (computed value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that, in the operation of the circuit MP, the current IOL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) are changed, which is the same as the results of the circuit operation under conditions 1, 4, 7, and 8. Note that the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the result of the signal z j (k) will be output as:

[0365] The results of the operation examples under the above-mentioned conditions 1 to 9 are summarized in the table below. Note that in the table below, a high level potential is described as "high" and a low level potential is described as "low."

[0366] [Table 2]

[0367] Here, a case where one circuit MC and one circuit MCr are connected to the wiring OL and wiring OLB is shown as an example. In this regard, as shown in Figs. 2, 3, 4, 7, 11, 12, 14, etc., when multiple circuits MC and multiple circuits MCr are connected to the wiring OL and wiring OLB, the currents output from each circuit MC and circuit MCr are added together based on Kirchhoff's current law. As a result, a sum operation is performed. In other words, a product operation is performed in the circuit MC and the circuit MCr, and a sum operation is performed by adding together the currents from the multiple circuits MC and the circuit MCr. As a result of the above, a product-sum operation is performed.

[0368] By the way, in the operation of circuit MP, by performing calculations with the first data (weighting coefficient) having only two values, "+1" and "-1", and the second data (neuron signal value) having only two values, "+1" and "-1", circuit MP can perform operations similar to an exclusive OR negation circuit (match circuit).

[0369] Furthermore, in the operation of circuit MP, by performing calculations in which the first data (weighting coefficient) has only two values, “+1” and “0”, and the second data (neuron signal value) has only two values, “+1” and “0”, circuit MP can perform operations similar to a logical AND circuit.

[0370] In this operation example, the potentials held in the circuit MC of the circuit MP and the circuits HC and HCr of the circuit MCr are VSS, V 1 , V 2 However, the circuits HC and HCr may hold potentials indicating two values ​​or analog values. For example, when the first data (weighting coefficient) is a "positive analog value," a high-level analog potential is held at node n1 of the circuit HC, and a low-level potential is held at node n1r of the circuit HCr. When the first data (weighting coefficient) is a "negative analog value," for example, a low-level potential is held at node n1 of the circuit HC, and a high-level analog potential is held at node n1r of the circuit HCr. Then, the current I OL and current I OLB The magnitude of the current is in accordance with the analog potential. In addition, the holding of the potential indicating the analog value in the circuit HC and the circuit HCr is not limited to the operation example of the circuit MP in FIG. 15A, and may be performed in other circuits MP shown in this specification.

[0371] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0372] <Configuration example 2> Next, an example of a circuit configuration that is different from each of the circuit configurations in FIGS. 15A to 15C, 16A, and 16B and that can be applied to the circuit MP shown in FIG. 9B will be described.

[0373] The circuit MP shown in Figure 21A shows an example configuration of the circuit MP of Figure 9B, and differs from the circuit MP of Figure 15A in that the second terminal of transistor M2 is electrically connected to the second terminal of transistor M1, the first terminal of transistor M3, and the first terminal of transistor M4 rather than to wiring OL, and that the second terminal of transistor M2r is electrically connected to the second terminal of transistor M1r, the first terminal of transistor M3r, and the first terminal of transistor M4r rather than to wiring OLB.

[0374] The circuit MP of FIG. 21A can operate similarly to the circuit MP of FIG. 15A.

[0375] Also, another example of a circuit configuration that can be applied to the circuit MP shown in Fig. 9B, which is different from Fig. 21A, will be described. The circuit MP shown in Fig. 21B shows a configuration example of the circuit MP of Fig. 9B, and is different from the circuit MP of Fig. 15A in that the circuit MC includes a transistor M1c, and the first terminal of the transistor M4 is electrically connected to the transistor M1c, not to the second terminal of the transistor M1 and the second terminal of the transistor M3, and that the circuit MCr includes a transistor M1cr, and the first terminal of the transistor M4r is electrically connected to the transistor M1cr, not to the second terminal of the transistor M1r and the second terminal of the transistor M3r.

[0376] In this specification and the like, unless otherwise specified, the transistor M1c and the transistor M1cr include a case where they finally operate in the saturation region when they are on. That is, the gate voltage, the source voltage, and the drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within a range in which they operate in a linear region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude value of the voltage supplied, the transistor M1c and the transistor M1cr may operate in the linear region. Alternatively, in order to reduce the amount of current flowing through the transistor M1c and the transistor M1cr, the transistor M1c and the transistor M1cr may operate in the subthreshold region. Alternatively, they may be operated near the boundary between the saturation region and the subthreshold region. In addition, when the first data (for example, a weighting coefficient here) is an analog value, for example, the transistor M1c and the transistor M1cr may operate in a linear region, a saturation region, and a subthreshold region depending on the magnitude of the first data (weighting coefficient). Alternatively, the transistor M1c and the transistor M1cr may operate in a linear region and a saturation region in a mixed manner, or may operate in a subthreshold region and a linear region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner.

[0377] In the circuit MP of FIG. 21B, a first terminal of the transistor M1c is electrically connected to the wiring VE. A gate of the transistor M1c is electrically connected to a gate of the transistor M1, a first terminal of the transistor M2, and a first terminal of the capacitor C1. In addition, a second terminal of the transistor M1c is electrically connected to a first terminal of the transistor M4.

[0378] 21B, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0379] Furthermore, explanations of the circuit MP in FIG. 21B and the circuit MP in FIG. 15A that have the same connection configuration will be omitted.

[0380] In the circuit MP of FIG. 21B, the currents flowing through the transistors M3 and M4 are determined by the gate potentials of the transistors M1 and M1c, respectively. As an example, it is preferable that the sizes, for example, the channel length and channel width, of the transistors M1 and M1c are equal to each other. By configuring the circuit in this way, there is a possibility that an efficient layout can be achieved. In addition, there is a possibility that the currents flowing through the transistors M3 and M4 can be made uniform.

[0381] The circuit MP of FIG. 21B can operate similarly to the circuit MP of FIG. 15A.

[0382] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0383] <Configuration example 3> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIG. 9E will be described.

[0384] The circuit MP shown in Figure 22A shows an example configuration of the circuit MP of Figure 9E, and differs from the circuit MP of Figure 15A in that the circuit MC includes a transistor M5 and the circuit MCr includes a transistor M5r, and the circuit MP is electrically connected to the wiring IL and the wiring ILB.

[0385] In this specification and the like, unless otherwise specified, the transistor M5 and the transistor M5r are considered to include a case where they finally operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to include a case where they are appropriately biased to a voltage within a range in which they operate in a linear region. However, one embodiment of the present invention is not limited to this. The transistor M5 and the transistor M5r may operate in a saturation region or a subthreshold region. Alternatively, they may be operated near the boundary between the saturation region and the subthreshold region. Alternatively, the transistor M5 and the transistor M5r may operate, for example, in a linear region, a saturation region, and a subthreshold region. Alternatively, the transistor M5 and the transistor M5r may operate in a linear region and a saturation region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner, or may operate in a subthreshold region and a linear region in a mixed manner.

[0386] In the circuit MP of Fig. 22A, a first terminal of the transistor M5 is electrically connected to a second terminal of the transistor M2 and a wiring IL. A second terminal of the transistor M5 is electrically connected to a second terminal of the transistor M1, a first terminal of the transistor M3, and a first terminal of the transistor M4. A gate of the transistor M5 is electrically connected to a wiring WL.

[0387] 22A, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0388] Furthermore, explanations of the circuit MP in FIG. 22A and the circuit MP in FIG. 15A that have the same connection configuration will be omitted.

[0389] In the circuit MP of FIG. 22A, similarly to the configuration examples 1 and 2, the sizes, for example, channel length and channel width, of the transistors M1, M2, M3, and M4 are preferably equal to the sizes of the transistors M1r, M2r, M3r, and M4r, respectively. By configuring the circuit in this way, there is a possibility that an efficient layout can be achieved. In addition, the size of the transistor M5 is preferably equal to the size of the transistor M5r.

[0390] The currents in the circuits MC and MCr are set by applying a high-level potential to the wiring WL to turn on the transistors M2, M2r, M5, and M5r. After the currents are set in the circuits MC and MCr, a low-level potential may be applied to the wiring WL to turn off the transistors M2, M2r, M5, and M5r in order to hold the potentials set in the circuits HC and HCr.

[0391] In the circuit MP described in the configuration examples 1 and 2, the wiring for transmitting the second data (for example, the value of the neuron signal here) and the wiring for supplying or holding information (for example, voltage, current, etc.) corresponding to the first data (for example, weighting coefficient here) to the circuit MP are collectively defined as the wiring WX1L, but by configuring the circuit MP as shown in FIG. 22A, the wiring for transmitting the second data (the value of the neuron signal) can be defined as the wiring X1L, and the wiring for supplying or holding information (for example, voltage, current, etc.) corresponding to the first data (weighting coefficient) to the circuit MP can be defined as the wiring WL. In other words, the circuit MP in FIG. 22A can be said to have a configuration in which the wiring WX1L of the circuit MP in the configuration examples 1 and 2 is divided by function.

[0392] FIG. 22B shows a circuit configuration different from the circuit MP of FIG. 22A.

[0393] The circuit MP shown in Fig. 22B has a configuration in which the electrical connections of the first terminals of the transistors M5 and M5r in the circuit MP in Fig. 22A are changed. Specifically, in the circuit MP in Fig. 22B, the first terminal of the transistor M5 is electrically connected to the first terminal of the transistor M2, the gate of the transistor M1, and the first terminal of the capacitor C1.

[0394] With the configuration shown in FIG. 22B, the circuit MP operates in substantially the same manner as the circuit MP of FIG. 22A.

[0395] Note that the circuits MP shown in each of FIGS. 22A and 22B may be configured such that the wirings IL are combined into a wiring OL and the wirings ILB are combined into a wiring OLB. For example, in the circuit MP shown in FIG. 22A, the wirings IL are combined into a wiring OL and the wirings ILB are combined into a wiring OLB, thereby making it possible to obtain the configuration of the circuit MP shown in FIG. 23A. For example, in the circuit MP shown in FIG. 22B, the wirings IL are combined into a wiring OL and the wirings ILB are combined into a wiring OLB, thereby making it possible to obtain the configuration of the circuit MP shown in FIG. 23B. Note that each of the circuits MP shown in FIGS. 23A and 23B has a circuit configuration that can be applied to the circuit MP shown in FIG. 9A, and the operation of each of the circuits MP shown in FIGS. 23A and 23B should be described with reference to the description of the operation of the circuit MP in FIG. 15A.

[0396] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0397] <Configuration Example 4> The circuit MP shown in FIG. 24 is an example of a circuit that differs from the circuit MP in FIG. 15A in that it includes not only a circuit HC and a circuit HCr but also a circuit HCs and a circuit HCsr.

[0398] The circuit MC included in the circuit MP of Fig. 24 has a transistor M1s, a transistor M2s, a transistor M6, a transistor M6s, and a capacitance C1s in addition to the circuit elements of the circuit MP of Fig. 21A. The circuit MCr included in the circuit MP of Fig. 24 has the same circuit elements as the circuit MC, and therefore has a transistor M1sr, a transistor M2sr, a transistor M6r, a transistor M6sr, and a capacitance C1sr corresponding to the transistor M1s, the transistor M2s, the transistor M6, the transistor M6s, and the capacitance C1s of the circuit MC, respectively. The transistor M2s and the capacitance C1s are included in the circuit HCs, and the transistor M2sr and the capacitance C1sr are included in the circuit HCsr.

[0399] In this specification and the like, unless otherwise specified, the transistors M1s and M1sr include a case where they finally operate in a saturation region when they are on, similarly to the transistors M1 and M1r. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within a range where they operate in a saturation region. However, one embodiment of the present invention is not limited to this. In order to reduce the amplitude value of the supplied voltage, the transistors M1s and M1sr may operate in a linear region. In addition, in order to reduce the amount of current flowing through the transistors M1s and M1sr, the transistors M1s and M1sr may operate in a subthreshold region. Alternatively, they may be operated near the boundary between the saturation region and the subthreshold region. In addition, when the first data (weighting coefficient) is an analog value, for example, the transistor M1s and the transistor M1sr may operate in a linear region, a saturation region, and a subthreshold region in a mixed manner depending on the magnitude of the first data (weighting coefficient). Alternatively, the transistor M1s and the transistor M1sr may operate in a linear region and a saturation region in a mixed manner, or may operate in a subthreshold region and a linear region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner.

[0400] In addition, in this specification and the like, the transistor M2s, the transistor M2sr, the transistor M6, the transistor M6s, the transistor M6r, and the transistor M6sr include a case where they finally operate in a linear region when they are on, similar to the transistor M2, the transistor M3, the transistor M4, and the like, unless otherwise specified. That is, the gate voltage, the source voltage, and the drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within a range in which they operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistor M2s, the transistor M2sr, the transistor M6, the transistor M6s, the transistor M6r, and the transistor M6sr may operate in a saturation region or a subthreshold region when they are on. Alternatively, the transistor M2s, the transistor M2sr, the transistor M6, the transistor M6s, the transistor M6r, and the transistor M6sr may be operated near the boundary between the saturation region and the subthreshold region. Alternatively, transistor M2s, transistor M2sr, transistor M6, transistor M6s, transistor M6r, and transistor M6sr may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a subthreshold region and a linear region, or may operate in a linear region, a saturation region, and a subthreshold region.

[0401] Next, a description will be given of the configuration of the circuit MP in Fig. 24. Note that in the circuit MP in Fig. 24, parts that have the same configuration as the circuit MP in Fig. 21A will be omitted.

[0402] In the circuit MP of FIG. 24, the second terminal of the transistor M1 is electrically connected to the second terminal of the transistor M2 and the first terminal of the transistor M6. The second terminal of the transistor M6 is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. The gate of the transistor M6 is electrically connected to the wiring S1L. The first terminal of the transistor M1s is electrically connected to the wiring VE. The second terminal of the transistor M1s is electrically connected to the first terminal of the transistor M6s. The gate of the transistor M1s is electrically connected to the first terminal of the capacitance C1s and the first terminal of the transistor M2s. The second terminal of the capacitance C1s is electrically connected to the wiring VE. The second terminal of the transistor M2s is electrically connected to the second terminal of the transistor M1s and the first terminal of the transistor M6s. The second terminal of the transistor M6s is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. The gate of the transistor M6s is electrically connected to the wiring S2L.

[0403] 24, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0404] The wiring S1L functions as a voltage line that supplies a potential for turning on or off the transistor M6 and the transistor M6r, and the wiring S2L functions as a voltage line that supplies a potential for turning on or off the transistor M6s and the transistor M6sr.

[0405] In the circuit MP of Fig. 24, it is preferable that the sizes, for example, the channel lengths and channel widths, of the transistors M6, M6s, M6r, and M6sr are equal to one another. By configuring the circuit in this way, it is possible to achieve an efficient layout.

[0406] For example, by applying the configuration shown in the circuit MP of FIG. 24 to the arithmetic circuit 150 shown in FIG. 11, the circuit MP of the arithmetic circuit 150 can hold two pieces of first data (for example, weighting coefficients here). Specifically, the circuit MP of FIG. 24 can hold a potential corresponding to the first piece of first data (weighting coefficient) in the circuit HC of the circuit MC and the circuit HCr of the circuit MCr, and can hold a potential corresponding to the second piece of first data (weighting coefficient) in the circuit HCs of the circuit MC and the circuit HCsr of the circuit MCr. In addition, the circuit MP of FIG. 24 can switch the first data (weighting coefficient) used in the arithmetic operation by potentials applied from the wirings S1L and S2L. For example, when the first data (weighting coefficient) w 1 (k-1) j (k) Or even w m (k-1) j (k) The first data (weighting coefficient) w is stored in each of the circuits HCs and HCsr included in the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 150. 1 (k-1) h (k) Or even w m (k-1) h (k) (here, h is an integer not less than 1 and not equal to j) is held, and a signal z 1 (k-1) ~z m (k-1) At this time, a high-level potential is applied to the wiring S1L to turn on the transistors M6 and M6r, and a low-level potential is applied to the wiring S2L to turn off the transistors M6s and M6sr. As a result, the circuits MP[1,j] to MP[m,j] in the arithmetic circuit 150 are configured to receive the weight coefficient w 1 (k-1) j (k) Or even wm (k-1) j (k) and signal z 1 (k-1) ~z m (k-1) A low-level potential is applied to the wiring S1L to turn off the transistors M6 and M6r, and a high-level potential is applied to the wiring S2L to turn on the transistors M6s and M6sr. In this way, the circuits MP[1,j] to MP[m,j] in the arithmetic circuit 150 can calculate the sum of products of the weight coefficients w 1 (k-1) h (k) Or even w m (k-1) h (k) and signal z 1 (k-1) ~z m (k-1) It is possible to perform product-sum and activation function calculations with

[0407] As described above, by applying the circuit MP of Fig. 24 to the arithmetic circuit 150, two weight coefficients can be held, and the weight coefficients can be switched to perform calculations of product sums and activation functions. The arithmetic circuit 150 including the circuit MP of Fig. 24 is effective, for example, when the number of neurons in the k-th layer is greater than n, when calculations are performed in a hidden layer different from the k-th layer, etc. In addition, in the circuit MP of Fig. 24, the circuit MC and the circuit MCr each have two holding units, but each of the circuit MC and the circuit MCr may have three or more holding units depending on the situation.

[0408] The circuit MP included in the semiconductor device of one embodiment of the present invention is not limited to the circuit MP in Fig. 24. As the circuit MP of the semiconductor device of one embodiment of the present invention, the circuit configuration of the circuit MP in Fig. 24 can be changed depending on the situation.

[0409] For example, the circuit MP shown in FIG. 25 has a circuit configuration obtained by modifying the circuit MP shown in FIG. 24. Specifically, the circuit MP shown in FIG. 25 is obtained by adding a transistor M3s, a transistor M4s, a transistor M3sr, and a transistor M4sr to the circuit MP shown in FIG. 24, and by modifying the electrical connections. The first terminal of the transistor M3s is electrically connected to the second terminal of the transistor M6s and the first terminal of the transistor M4s, the second terminal of the transistor M3s is electrically connected to the wiring OL, and the gate of the transistor M3s is electrically connected to the wiring WX1L. The second terminal of the transistor M4s is electrically connected to the wiring OLB, and the gate of the transistor M4s is electrically connected to the wiring X2L.

[0410] 25, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are marked with "r" to distinguish them from the circuit elements of the circuit MC. In the circuit MCr, the second terminal of the transistor M3sr is electrically connected to the wiring OLB, and the second terminal of the transistor M4sr is electrically connected to the wiring OL.

[0411] In the circuit MP of Fig. 25, it is preferable that the sizes, for example, channel lengths and channel widths, of the transistors M3, M3s, M3r, M3sr, M4, M4s, M4r, and M4sr are equal to one another. By configuring the circuit in this way, it is possible to achieve an efficient layout.

[0412] The circuit MP in Fig. 25 can hold two pieces of first data (weighting coefficients) by performing the same operation as the circuit MP in Fig. 24, and can perform calculations of product sums and activation functions by switching the first data (weighting coefficients). In addition, in the circuit MP in Fig. 25, the circuit MC and the circuit MCr each have two holding units, but each of the circuit MC and the circuit MCr may have three or more holding units depending on the situation.

[0413] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0414] <Configuration Example 5> 21A, the circuit MP shown in Fig. 26 includes, as examples, transistors M1, M1-2b, and M1-3b, each of which has a different ratio of channel width (hereinafter referred to as W length) to channel length (hereinafter referred to as L length) in the circuit MC. Note that the circuit may include more transistors than just transistor M1, M1-2b, and M1-3b, and may not include transistors M1-3b, M1-2b, etc.

[0415] The circuit MC included in the circuit MP in FIG. 26 further includes a transistor M3-2b, a transistor M4-2b, a transistor M3-3b, and a transistor M4-3b, in addition to the circuit elements included in the circuit MP in FIG. 21A.

[0416] In this specification and the like, the transistor M1-2b and the transistor M1-3b, like the transistor M1, include a case where they finally operate in the saturation region when they are on unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within a range where they operate in the saturation region. However, one embodiment of the present invention is not limited to this. In order to reduce the amplitude value of the supplied voltage, the transistor M1-2b and the transistor M1-3b may operate in a linear region. In addition, in order to reduce the amount of current flowing through the transistor M1-2b and the transistor M1-3b, the transistor M1-2b and the transistor M1-3b may operate in a subthreshold region. Alternatively, they may be operated near the boundary between the saturation region and the subthreshold region. In addition, when the first data (for example, a weighting coefficient here) is an analog value, depending on the magnitude of the first data (weighting coefficient), for example, the transistors M1-2b and M1-3b may operate in a linear region, a saturation region, and a subthreshold region. Alternatively, the transistors M1-2b and M1-3b may operate in a linear region and a saturation region, or may operate in a subthreshold region and a linear region, or may operate in a saturation region and a subthreshold region.

[0417] In this specification and the like, the transistors M3-2b, M4-2b, M3-3b, and M4-3b, like the transistors M3 and M4, include the case where they finally operate in the linear region when they are on, unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors include the case where they are appropriately biased to a voltage within the range in which they operate in the linear region. However, one embodiment of the present invention is not limited to this. For example, the transistors M3-2b, M4-2b, M3-3b, and M4-3b may operate in the saturation region or the subthreshold region when they are on. Alternatively, the transistors M3-2b, M4-2b, M3-3b, and M4-3b may be operated near the boundary between the saturation region and the subthreshold region. Alternatively, transistors M3-2b, M4-2b, M3-3b, and M4-3b may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a subthreshold region and a linear region, or may operate in a linear region, a saturation region, and a subthreshold region.

[0418] Next, a description will be given of the configuration of the circuit MP in Fig. 26. Note that in the circuit MP in Fig. 26, parts that have the same configuration as the circuit MP in Fig. 21A will be omitted.

[0419] In the circuit MC of the circuit MP of FIG. 26, the first terminal of the transistor M1-2b is electrically connected to the wiring VE. The second terminal of the transistor M1-2b is electrically connected to the first terminal of the transistor M3-2b and the first terminal of the transistor M4-2b. The gate of the transistor M1-2b is electrically connected to the first terminal of the transistor M2 and the first terminal of the capacitor C1. The second terminal of the transistor M3-2b is electrically connected to the wiring OL. The gate of the transistor M3-2b is electrically connected to the wiring X1L2b. The second terminal of the transistor M4-2b is electrically connected to the wiring OLB. The gate of the transistor M4-2b is electrically connected to the wiring X2L2b. The first terminal of the transistor M1-3b is electrically connected to the wiring VE. The second terminal of the transistor M1-3b is electrically connected to the first terminal of the transistor M3-3b and the first terminal of the transistor M4-3b. The gate of the transistor M1-3b is electrically connected to the first terminal of the transistor M2 and the first terminal of the capacitor C1. The second terminal of the transistor M3-3b is electrically connected to the wiring OL. The gate of the transistor M3-3b is electrically connected to the wiring X1L3b. The second terminal of the transistor M4-3b is electrically connected to the wiring OLB. The gate of the transistor M4-3b is electrically connected to the wiring X2L3b.

[0420] In the circuit MP of Fig. 26, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are marked with "r" to distinguish them from the circuit elements of the circuit MC. The second terminal of the transistor M3-2br is electrically connected to the wiring OLB, the second terminal of the transistor M4-2br is electrically connected to the wiring OL, the second terminal of the transistor M3-3br is electrically connected to the wiring OLB, and the second terminal of the transistor M4-3br is electrically connected to the wiring OL.

[0421] In the circuit MP of Fig. 26, it is preferable that the sizes, for example, channel lengths and channel widths, of the transistors M3, M3-2b, M3-3b, M3r, M3-2br, M3-3br, M4, M4-2b, M4-3b, M4r, M4-2br, and M4-3br are equal to each other. By configuring the circuit in this way, there is a possibility that an efficient layout can be achieved.

[0422] The wiring X1L2b is a wiring for switching the transistors M3-2b and M3-2br between the on and off states, the wiring X2L2b is a wiring for switching the transistors M4-2b and M4-2br between the on and off states, the wiring X1L3b is a wiring for switching the transistors M3-3b and M3-3br between the on and off states, and the wiring X2L3b is a wiring for switching the transistors M4-3b and M4-3br between the on and off states.

[0423] When the ratio of the W length to the L length of the transistor M1 is W / L, the ratio of the W length to the L length of the transistor M1-2b is preferably 2×W / L, and the ratio of the W length to the L length of the transistor M1-3b is preferably 4×W / L. Since the current flowing between the source and drain of a transistor is proportional to the channel width / channel length, when the structures and...

Claims

[Claim 1] A first circuit and an array section electrically connected to the first circuit, The array unit is a semiconductor device having a plurality of pixels arranged in a matrix, the first circuit has a function of inputting first image data to each of the plurality of pixels; each of the pixels has a function of holding a filter value of a weighting filter and a function of performing a product-sum operation on the filter value and the first image data to generate second image data.

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