Via connection structure having multiple vias and substrate having the same

Abstract

To provide a via connection structure having a plurality of vias and a substrate having the same that ensures excellent electrical conductivity while preventing mechanical defects of a glass substrate or the like.SOLUTION: A via connection structure includes a plurality of vias 100 arranged in an insulating layer 3, the plurality of vias 100 include first vias 120 and second vias 140 arranged vertically stacked on each other, the first vias 120 and the second vias 140 are configured to contact each other on the same surface, and the second vias 140 and the first vias 120 are arranged in different numbers.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Patent Application No. 63 / 242,625, filed September 10, 2021, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to a via connection structure having a plurality of vias and a substrate having the same. [Background technology]

[0003] To achieve high efficiency and performance in semiconductor packaging, electrical conductivity between the semiconductor chip and the main board is important. A typical semiconductor packaging process involves forming vias in a substrate and filling the vias with a conductive metal such as copper to form a conductive layer, thus forming a channel for communication.

[0004] In recent years, efforts have been made to apply inorganic substrates such as flat glass as package substrates. In particular, in the case of flat glass, it is desired to prevent warping while maintaining the rigidity of the glass substrate at an appropriate level. Therefore, a solution is desired that can ensure excellent electrical conductivity while preventing mechanical defects of the glass substrate, etc. Summary of the Invention

[0005] This Summary is provided to introduce some concepts in a simplified form that are described later in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0006] The present invention provides a via connection structure comprising a plurality of vias arranged in an insulating layer, the plurality of vias comprising first and second vias arranged vertically stacked on each other, the first and second vias configured to contact each other on the same surface, and the second vias and the first vias arranged in different numbers.

[0007] The vias are configured to transmit electrical signals in an up and down direction.

[0008] The present invention provides a substrate comprising a through hole penetrating the substrate in a thickness direction, a core substrate in which the through hole is disposed, and a redistribution layer formed on a first surface of the core substrate, the substrate comprising an electrically conductive layer disposed in a predetermined shape, the electrically conductive layer comprising a core conductive layer and a redistribution conductive layer, the core conductive layer comprising a first conductive layer disposed in contact with the first surface of the core substrate, a through conductive layer disposed in the through hole, and a second conductive layer disposed in contact with the second surface of the core substrate, the redistribution conductive layer being embedded in the redistribution layer, the core conductive layer and the redistribution conductive layer being electrically connected to each other, and the redistribution conductive layer comprising a connection structure of an insulating layer and a via.

[0009] The second via is disposed on the first via, the first via includes a first via ball and a first via pad that are connected to each other, the second via is connected to the first via through the first via hole and the first via pad, and two or more second vias are disposed for each first via that contacts the first via pad.

[0010] The distance between the second vias in contact with the first via pads is 0.2 μm or more.

[0011] The size of the second via in contact with the first via pad is 10 μm to 100 μm. .

[0012] The second vias include a plurality of vias arranged in a row over the first vias.

[0013] Three or more of the second vias are arranged on the first via pad; The second vias include vias arranged in a polygonal shape surrounding the center of the via pad.

[0014] The core substrate is any one of a silicon-based ceramic substrate, a glass-based ceramic substrate, a glass substrate, or a combination thereof.

[0015] The present invention provides an electronic device board comprising: a through hole penetrating the board in a thickness direction; a core board in which the through hole is arranged; and an upper redistribution layer arranged on a first surface of the core board, the board comprising an electrically conductive layer arranged in a predetermined shape and configured to transmit an electrical signal, the electrically conductive layer being configured to electrically connect an upper part of the core board and a lower part of the core board via at least a part of the through hole, the upper redistribution conductive layer being an electrically conductive layer arranged in the upper redistribution layer, the redistribution conductive layer of the electrically conductive layer comprising a plurality of vias configured to transmit an electrical signal in a vertical direction, the plurality of vias comprising first and second vias arranged in a vertical stack, the first and second vias being configured to be in contact on the same surface, and the second and first vias being arranged in different numbers.

[0016] Other features and aspects will become apparent from the following detailed description, the drawings, and the claims. [Brief description of the drawings]

[0017] [Figure 1A] 1 illustrates an example of a substrate in accordance with one or more embodiments. [Figure 1B] 1 illustrates an example of a semiconductor package in accordance with one or more embodiments. [Diagram 2] This shows an enlarged view of part U in FIG. [Figure 3A] 3 illustrates an example of a plurality of vias (cross-sectional view along line AA' of FIG. 2) in accordance with one or more embodiments. [Figure 3B] 3 illustrates an example of a plurality of vias (cross-sectional view along line AA' of FIG. 2) in accordance with one or more embodiments. [Figure 4A] 3 illustrates an example of a plurality of vias (cross-sectional view along line AA' of FIG. 2) in accordance with one or more embodiments. [Figure 4B] 3 illustrates an example of a plurality of vias (cross-sectional view along line AA' of FIG. 2) in accordance with one or more embodiments. [Figure 4C] 3 illustrates an example of a plurality of vias (cross-sectional view along line AA' of FIG. 2) in accordance with one or more embodiments. [Diagram 5] 3 illustrates an example of a plurality of vias (cross-sectional view along line AA' of FIG. 2) in accordance with one or more embodiments. [Figure 6] FIG. 1 is a perspective view of an example semiconductor package in accordance with one or more embodiments. [Figure 7] FIG. 1 illustrates a perspective view of an example packaging substrate in accordance with one or more embodiments. [Figure 8] 1 illustrates an example of a cross-section of a packaging substrate in accordance with one or more embodiments. [Figure 9] 9 is an enlarged view of an example of a rewiring layer in a U portion of FIG. 8. [Figure 10] 1 illustrates an example cross-section of a microlayer of a packaging substrate in accordance with one or more embodiments. [Figure 11] 1 illustrates an example cross-section of multiple vias in accordance with one or more embodiments. [Figure 12] 1 illustrates an example cross-section of multiple vias in accordance with one or more embodiments. [Figure 13] 1 illustrates an example of a plurality of vias in accordance with one or more embodiments. [Figure 14] 1 illustrates an example of a plurality of vias in accordance with one or more embodiments. [Figure 15] 1 illustrates an example of a plurality of vias in accordance with one or more embodiments. [Figure 16]FIG. 2 is a perspective view of a portion of a packaging substrate in accordance with one or more embodiments. [Figure 17] 1 illustrates a cross-section of a packaging substrate in accordance with one or more embodiments.

[0018] In the drawings and detailed description, like numerals refer to like elements. The drawings may not be to scale, and the relative scale, proportions, and descriptions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following detailed description is provided to assist the reader in a comprehensive understanding of the method, device, and / or system described herein. However, various changes, modifications, and equivalents of the method, device, and / or system described herein will become apparent upon understanding the present disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those described herein, and may be changed as becomes apparent upon understanding the present disclosure, except that the operations are necessarily performed in a certain order. It should also be noted that the description of features that are well known to those skilled in the art may be omitted for clarity and conciseness, but the omission of features and their description are not intended to acknowledge their general knowledge.

[0020] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways of implementing the methods, apparatus, and / or systems described herein that will become apparent after understanding the present disclosure.

[0021] In this specification, terms such as "first," "second," and "third" are used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections. Rather, these terms are used only to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in an embodiment described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0022] In the specification, when an element, such as a layer, region, or substrate, is described as being "on" or "connected" or "coupled" to another element, it is directly "on," "connected" or "coupled" to the other element, or there are one or more other elements between them. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled" to another element, there are no other intervening elements between them. Similarly, expressions such as "between," "just between," "adjacent to," and "directly adjacent to" can be interpreted as above.

[0023] The terms used herein are intended to describe particular examples only and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly dictates otherwise. As used herein, the term "and / or" includes any one and any two or more of the associated listed items in any combination. As used herein, the terms "including," "comprising," and "having" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the term "may" in an example or embodiment (e.g., with respect to what an example or embodiment may include or may perform) means that there is at least one example or embodiment in which such feature is included or performed. However, not all examples are limited to this.

[0024] In this specification, the meaning of "B is located on A" means that B is located on A in direct contact therewith, or that B is located on A with another layer located therebetween, and should not be interpreted as being limited to B being located in direct contact with A, unless otherwise clearly stated in the specification.

[0025] Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs, consistent with the understanding of this disclosure. Terms as defined in commonly used dictionaries are interpreted to have a meaning consistent with the meaning in the context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this specification.

[0026] In one or more examples, the term "A and / or B" means "A, B, or A and B."

[0027] In one or more instances, terms such as "first," "second," or "A," "B" are used to distinguish identical terms from one another, unless otherwise specified.

[0028] In one or more instances, the singular term "a" or "an" is to be construed as including the singular or plural as the context requires, unless specifically stated otherwise.

[0029] In one or more examples, a via connection structure comprising a plurality of vias can provide a high performance substrate for application in semiconductor packaging by improving conduction efficiency while maintaining mechanical properties of the substrate.

[0030] In one example, the via connection structure and the substrate to which the multiple vias are applied can improve the conduction efficiency of the substrate and minimize defects that may occur in the vias during the plating process. Furthermore, by optionally applying the connection structure to the multiple vias, an efficient semiconductor package substrate can be provided.

[0031] FIG 1A illustrates an example of a substrate in cross section according to one or more embodiments, and FIG 1B illustrates an example of a semiconductor package according to one or more embodiments. FIG 2 is an enlarged view of a portion U in FIG 1, and FIG 3A and FIG 3B each illustrate an example of a plurality of vias according to one or more embodiments. FIG 4A, FIG 4B, and FIG 4C each illustrate another example, and FIG 5 illustrates an example of a plurality of vias according to one or more embodiments.

[0032] One or more examples are described in detail below with reference to FIGS. 1A-5.

[0033] Via connection structure As shown in FIG. 2, a via structure according to one or more embodiments includes a plurality of vias 100.

[0034] The vias 100 are disposed in the insulating layer 3 and transmit electrical signals in the vertical direction. The vias 100 may include a first via 120 and a second via 140 disposed above and below each other or in a vertical relationship with each other, and the first via 120 and the second via 140 may be in contact with each other on one surface.

[0035] As one feature, in the plurality of vias 100, the second vias 140 and the first vias 120 that face each other on one surface may be arranged in different numbers (see FIG. 2).

[0036] In an example, the second via 140 may be disposed above the first via 120 or may be disposed below the first via 120 .

[0037] In the following, for example, a case where the second via 140 is disposed above the first via 120 will be described as a reference.

[0038] The first via 120 may include a first via hole 120a and a first via pad 120b that are connected to each other.

[0039] The second via 140 may be connected to the first via hole 120a and the first via pad 120b. Specifically, the second via 140 may have a structure that enables conduction between a redistribution conductive layer disposed in the first via hole 120a in contact with the first via pad 120b and a redistribution conductive layer of the second via 140 in contact with the first via pad 120b.

[0040] The number of the second vias 140 per one first via 120 in contact with the first via pad 120b may be, for example, 2 or more, 3 or more, or 4 or more. The number of the second vias 140 may be, for example, 150 or less, or 100 or less. The number of the second vias 140 per one first via 120 may be, for example, 15 or less, or 8 or less.

[0041] When multiple second vias 140 are applied per one first via 120, a more precisely designed redistribution layer design can be realized in a given space, making it possible to provide efficient current flow while applying high frequency power.

[0042] The first via hole 120a and the second via hole may have a redistribution conductive layer disposed independently, and the redistribution conductive layer may be disposed only in a part of the inner region of the via hole (see FIGS. 3A, 4A, and 4B), or may be disposed so as to fill the entire inner region of the via hole (see FIGS. 3B and 4C). When the redistribution conductive layer is disposed only in a part of the via hole 120 or 140, an insulating layer may be disposed only in a part of the via hole 120 or 140.

[0043] The second via 140 may be formed by forming a plurality of second via holes, selectively forming an electrically conductive layer in the via holes located at the required locations, and filling the other via holes with an insulating layer. Further, the second via 140 may be formed by selectively forming second via holes at the required locations, and then forming an electrically conductive layer.

[0044] The interval between the second vias 140 in contact with the first via pads 120b may be, for example, 0.2 μm or more, 0.5 μm or more, or 0.7 μm or more. The interval may be, for example, 2 μm or less, 1 μm or less, or 0.8 μm or less.

[0045] The size of the second via 140 in contact with the first via pad 120b may be 10 μm or more, 15 μm or more, 20 μm or more, or 25 μm or more. The size may be, for example, 100 μm or less, 80 μm or less, or 70 μm or less. In such an example, efficient current flow can be provided while applying high frequency power.

[0046] If the cross section of the second via 140 is circular, the size may be a diameter.

[0047] When the cross section of the second via 140 is polygonal, the size may be the average length of each side.

[0048] The second vias 140 may be arranged in a row on the first via pads 120b (see FIGS. 3A and 3B). In FIGS. 3A and 3B, the first via pads 120b may have, for example, a rectangular shape. However, the shape of the first via pads 120b is not limited thereto. Furthermore, as in the example of FIGS. 3A and 3B, a separate conductor may not be connected to the second vias 140. However, as shown in FIG. 5, the second vias 140 connected to a conductor may be applied, and some vias may be connected to a conductor and other vias may not be connected to a conductor depending on the embodiment.

[0049] As an example, the second vias 140 may be arranged in three or more numbers and may be arranged at vertices constituting a polygon on the first via pad 120b (see FIG. 4A). Furthermore, the second vias 140 may be further arranged within the polygon as necessary (see FIG. 4B and FIG. 4C). FIGS. 4A, 4B, and 4C show the first via pad 120b having a circular shape. However, the shape of the first via pad 120b is not limited thereto. Furthermore, in FIGS. 4A, 4B, and 4C, the second vias 140 are not connected to a separate conductor, but as shown in FIG. 5, the second vias 140 may be connected to a conductor. Depending on the embodiment, some of the vias 140 may be connected to a conductor and other vias 140 may not be connected to a conductor.

[0050] The multiple vias in the example can be applied to the redistribution layer of a substrate, etc., and are more useful in efficiently transmitting electrical signals in the vertical direction.

[0051] A substrate to which one or more of the exemplary via connection structures are applied is more advantageously applied to semiconductor packaging applications. In an embodiment, a typical interposer having multiple steps applied to the substrate can be combined into a single packaging substrate on which a redistribution layer is disposed, minimizing the volume while helping to accommodate the scale change of the redistribution layer required at the top and bottom of the packaging.

[0052] Furthermore, the via connection structure of the embodiment may be applied to a redistribution layer on the upper or lower part of a substrate, and the influence of the skin effect that is likely to occur due to high frequency alternating current can be minimized.

[0053] Substrate 800 and use of substrate 800 as a packaging substrate As shown in FIG. 1A, a substrate 800 according to one or more embodiments may include a through hole 1 that penetrates the substrate in the thickness direction, a core substrate 5 in which the through hole is disposed, and a redistribution layer 400 formed on one surface of the core substrate.

[0054] The substrate 800 includes a conductive layer 10 arranged in a predetermined shape, the conductive layer 10 including a core conductive layer 510 and a redistribution conductive layer 410 .

[0055] The core conductive layer 510 is a conductive layer disposed in contact with one surface of the core substrate, and refers to the case where no other conductive layer is interposed between the substrate and the core conductive layer.

[0056] The core conductive layer 510 includes a first surface conductive layer 510a disposed in contact with the first surface of the core substrate, a through-hole conductive layer 510b disposed within a through hole, and a second surface conductive layer 510c disposed on the underside of the substrate 800 and in contact with the second surface of the core substrate.

[0057] For example, the through conductive layer 510b may be formed in the inner region of a through hole penetrating the core substrate. Specifically, the through conductive layer may be disposed on the inner diameter surface of the through hole. Specifically, the through conductive layer may be disposed so as to fill the inner diameter surface of the through hole. A buffer layer may be provided between the inner diameter surface of the through hole and the through conductive layer to facilitate bonding and plating processes. An insulating layer may be filled in the empty portion of the through hole.

[0058] The redistribution conductive layer 410 may be disposed embedded within the redistribution layer 400 .

[0059] The redistribution layer may comprise an insulating layer overlying a redistribution conductive layer.

[0060] The insulating layer and the redistribution layer may be formed in multiple layers in the manufacturing process, but since the same material is applied to the upper and lower portions, the boundary between them may not be observed.

[0061] The core conductive layer 510 and the redistribution conductive layer 410 are partially electrically connected to each other.

[0062] A detailed description of the multiple vias and the via connection structure overlaps with the above description, so further description will be omitted.

[0063] The core substrate 5 may be a ceramic substrate.

[0064] The core substrate 5 may be any one selected from the group consisting of a silicon-based ceramic substrate, a glass-based ceramic substrate, a glass substrate, and combinations thereof.

[0065] The ceramic substrate may be, for example, a silicon-based ceramic substrate or a glass-based ceramic substrate. The silicon-based ceramic substrate may be a substrate that is partly or entirely made of a silicon substrate, a silicon carbide substrate, or the like. The glass-based ceramic substrate may be a substrate that is partly or entirely made of a quartz substrate, a sapphire substrate, or the like.

[0066] Examples of the glass substrate include alkali borosilicate plate glass, non-alkali borosilicate plate glass, non-alkali alkaline earth borosilicate plate glass, and the like. Any plate glass applicable to electronic components may be used.

[0067] The thickness of the core substrate 5 may be, for example, 50 μm or more, 100 μm or more, 250 μm or more, 400 μm or more, or 500 μm or more. The thickness of the core substrate may be, for example, 3000 μm or less, or 1000 μm or less. When the core substrate having such a thickness range is used, it is expected to be widely used as a substrate for a semiconductor package.

[0068] A substrate as a semiconductor packaging substrate of the embodiment is a semiconductor packaging substrate including a through hole which is a hole penetrating the substrate in a thickness direction, a core substrate in which the through hole is disposed, and an upper redistribution layer formed on one surface of the core substrate. The substrate for an electronic device includes an electrically conductive layer disposed in a predetermined shape for transmitting an electrical signal, the electrically conductive layer connects an upper portion and a lower portion of the core substrate through a through hole, the upper redistribution conductive layer is an electrically conductive layer disposed embedded in the upper redistribution layer, the redistribution conductive layer includes a plurality of vias for transmitting an electrical signal in a vertical direction, the plurality of vias include first and second vias disposed above and below each other, the first and second vias are in contact with each other on one surface, and the second and first vias facing each other on a contact surface are disposed in different numbers.

[0069] A detailed description of the multiple vias and the substrate overlaps with the above description, so further description will be omitted.

[0070] Semiconductor Package 920 In one general aspect, a semiconductor package 920 according to one or more embodiments includes the aforementioned substrate 800 and a semiconductor device 20 mounted on the substrate (see FIG. 1B). A detailed description of the substrate overlaps with the above description, and will not be repeated here.

[0071] The semiconductor device 20 may be disposed on a substrate, for example, but not limited to, as shown in Figure 1B. Multiple semiconductor devices may be disposed on the substrate, in a cavity in the substrate (not shown), under the substrate, or a combination thereof.

[0072] The semiconductor may be an active element or a passive element.

[0073] For example, a computing element such as a CPU or GPU, a memory element such as a memory chip, etc. may be applied, and these may be arranged or stacked.

[0074] The semiconductor element may be a high-frequency semiconductor element. In the case of a high-frequency semiconductor element, it is preferable to use a glass substrate or a glass-based ceramic substrate as the core substrate. In such an example, unlike a ceramic substrate made of silicon or silicon carbide, the phenomenon of parasitic elements does not occur at high frequencies, and there is a possibility that dissipation of electrical power, heat, etc. is reduced.

[0075] In FIG. 1B, bumps 700 are shown as an example for connecting the semiconductor element 20 and the substrate 800, but the connection method is not limited to using bumps.

[0076] FIG. 6 is a perspective view of an example of a semiconductor package according to one or more embodiments, and FIG. 7 is a perspective view of an example of a packaging substrate according to one or more embodiments. FIG. 8 is a cross-sectional view of an example of a packaging substrate according to one or more embodiments, and FIG. 9 is an enlarged view of a U portion of a redistribution layer in FIG. 8. FIG. 10 is a cross-sectional view of a fine layer of a packaging substrate according to one or more embodiments, and FIG. 11 is a cross-sectional view of a plurality of vias according to one or more embodiments. FIG. 12 is a cross-sectional view of a plurality of vias according to one or more embodiments, and FIG. 13 is a cross-sectional view of a plurality of vias according to one or more embodiments. FIG. 14 is a cross-sectional view of a plurality of vias according to one or more embodiments, and FIG. 15 is a cross-sectional view of a plurality of vias according to one or more embodiments. FIG. 16 is a perspective view of a part of a packaging substrate according to one or more embodiments, and FIG. 17 is a cross-sectional view of a packaging substrate according to one or more embodiments. Hereinafter, the present disclosure will be described with reference to FIG. 6 to FIG. 17.

[0077] Via Structure The via structure of one or more embodiments transmits electrical signals vertically from within a redistribution layer of a packaging substrate 200, the packaging substrate may comprise a glass substrate, the via structure may comprise a plurality of vias 255, and the plurality of vias 255 may comprise at least two or more small vias 255a adjacent to each other.

[0078] The packaging substrate 200 and the vias 255 are the same as those described above, and therefore a duplicated description will be omitted.

[0079] By applying such a via structure, the packaging substrate 200 can improve the conduction efficiency, maintain the mechanical properties of the glass substrate, and minimize defects that occur during a plating process.

[0080] Packaging Substrate 200 8, in one general aspect, a packaging substrate according to one or more embodiments may include a core substrate 21 including a through hole 23, a redistribution layer 250 formed on a first surface 213 of the core substrate, a core conductive layer having a conductive layer formed on a part of the first surface 213, a part of the second surface 215, and the through hole of the core substrate, and a redistribution conductive layer formed in the redistribution layer, the core substrate 21 may include a glass substrate, and the core conductive layer and the redistribution conductive layer may be electrically connected at least in part. The redistribution conductive layer may include a plurality of vias 255 for transmitting electrical signals in a vertical direction, and the plurality of vias 255 may include two or more small vias 255a adjacent to each other.

[0081] Further, in a general aspect, the packaging substrate according to the embodiment may include a core substrate 21 having a through hole 23 and a redistribution layer 250 formed on a first surface 213 of the core substrate. The core substrate may include a glass substrate, and the packaging substrate may have a multi-layer structure, and the multi-layer structure may include a fine layer 253 and a coarse layer 257 arranged vertically. The coarse layer may include a coarse layer via 257b for transmitting an electrical signal in a vertical direction, a coarse layer via conductive layer formed in the coarse layer via, and a coarse layer upper pad 257c arranged on an upper portion of the coarse layer via. The fine layer may include a fine layer via 253b for transmitting an electrical signal in a vertical direction and a fine layer via conductive layer formed in the fine layer. The coarse layer upper pad and the fine layer via conductive layer are electrically connected to each other, and the size of the fine layer difference may be smaller than the size of the coarse layer upper pad. The fine layer via may include a small via, and two or more of the small vias may be disposed on one coarse layer upper pad.

[0082] Any one or more of the coarse layer vias 257b and the fine layer vias 253b may comprise a plurality of vias 255, which may comprise two or more small vias 255a.

[0083] Any glass substrate applicable in the semiconductor field can be used as the core substrate 21, for example, but not limited to, a borosilicate glass substrate, an alkali-free glass substrate, etc. The core substrate may be a commercially available product, or a product from a manufacturer such as CORNING, SCHOTT, or AGC.

[0084] Referring to FIG. 8, the through hole 22 penetrates the first surface 213 and the second surface 215 of the core substrate 21, is called a TGV (through glass via), etc., and may be formed at a predetermined position of the core substrate by a method such as etching.

[0085] The through holes 22 efficiently connect a semiconductor element that may be mounted on the first surface 213 to the second surface 215 while maintaining the role of supporting the core substrate. "Connection" may mean electrical connection via a conducting wire.

[0086] The core substrate 21 may further selectively include a cavity (not shown) at a predetermined position. For example, a passive element may be disposed in the cavity.

[0087] The redistribution layer 250 may include conductive lines 24 having a predetermined pattern and insulating material 22, where the conductive lines are disposed within the insulating material.

[0088] 9, which is an enlarged view of part U in FIG. 8, the redistribution layer 250 may include a fine layer 253 and a coarse layer 257 disposed one above the other. "Disposed one above the other" may mean that the fine layer is disposed on the top and the coarse layer is disposed on the bottom.

[0089] The fine layer 253 and the coarse layer 257 may differ from each other in size, such as diameter of the conductive wire, via, or vias.

[0090] The ratio of the thickness of the coarse layer 257 to that of the fine layer 253 may be about 0.8 to 5 times, or about 1 to 3 times. In such instances, the redistribution layer may be implemented more efficiently.

[0091] The fine layer 253 may have a predetermined pattern and may include fine layer conductors 253a having a thickness d1u and fine layer vias 253b connecting the conductors to the upper and lower sides.

[0092] The coarse layer 257 may include coarse layer conductors 257a and coarse layer vias 257b connecting the conductors to the upper and lower sides. The coarse layer conductors shown in FIG. 9 may be coarse layer via pads.

[0093] The fine layer vias 253b and the coarse layer vias 257b may be subdivided into through-hole vias, blind vias, buried vias, and the like.

[0094] As shown in FIG. 10, the fine layer 253 may include a fine layer via (fine layer blind via) 253b having one end blocked, a fine layer buried via 253b' having both ends blocked, and a fine layer through hole via 253b'' having both ends open.

[0095] The fine layer 253 and the coarse layer 257 except for the conductive wires may be filled with an insulating material, and this insulating material does not need to be clearly distinguished in cross section.

[0096] The fine layer 253 may further include a passivation layer thereon.

[0097] The thickness d1u of the fine layer conductor 253a may be smaller than the thickness d2u of the coarse layer conductor 257a.

[0098] The ratio of d1u to the thickness d2u of the coarse layer conductor 257a may be about 0.7 or less, or 0.1 or more.

[0099] The thickness d1u of the fine layer conductor 253a may be the width of a conductor pattern that may be formed on the fine layer 253, and the thickness d2u of the coarse layer conductor 257a may be the width of a conductive pattern that may be formed on the coarse layer 257.

[0100] The thickness d1u of the fine layer 253a may be about 5 μm or less, or 1 μm or more.

[0101] The vias 255 for transmitting electrical signals from the redistribution layer 250 in the vertical direction may be provided in the coarse layer vias 257b or the fine layer vias 253b. A plurality of vias may be provided instead of the coarse layer vias and the fine layer vias.

[0102] 12 and 13, the vias 255 may be, for example, at least 2 or more, or 9 or more, or 100 or more small vias 255a arranged at regular intervals, and the number of the vias 255 may be unlimited as long as they have regular intervals. Among the small vias 255a of the vias 255, one small via and another small via may have a minimum interval of about 0.5 μm to 25 μm, or about 1 μm to 15 μm. By having such an interval, the inside of the via can be plated well and the occurrence of defects can be reduced. If the small vias are arranged without any intervals to form one hole, concave dimples or voids may be generated when the conductive metal is filled in the plating process, and the electrical characteristics may be deteriorated.

[0103] For example, as shown in Fig. 12, the small vias 255a may be arranged in one direction, or as shown in Fig. 13, the small vias or their centers may be gathered as a close-packed plane. The close-packed plane may have a shape similar to or identical to a 0001 plane of a hexagonal close-packed structure of an atomic crystal structure. In one example, the small vias may be gathered with a minimum spacing of 1 µm to 3 µm, and one small via may be adjacent to 3 to 8 small vias.

[0104] Additionally, the plurality of small vias 255a may have monomers grouped into shapes, such as, by way of example only, triangles, equilateral triangles, squares, diamonds, pentagons-octagons, etc., to form the plurality of vias 255.

[0105] The vias 255 may include via pads 255 arranged at the height of one of the small vias 255a. A small via conductive layer arranged inside the small via may be electrically connected to the via pads, and the conductive via pads may be connected to a redistribution conductive layer having a similar height arranged in the same layer.

[0106] The size of the via pads 255b may be about 10 μm to 200 μm, or about 15 μm to 150 μm. By having such a size, the small via conductive layer inside the small vias 255a of the vias 255 can be easily electrically connected to other components through the via pads.

[0107] The cross section of the via pads 255b viewed from above may be, for example, a square, a circle, or an ellipse. When the cross section of the via pads is rectangular, the small vias 255a may be arranged along the longitudinal direction. When the via pads are circular, three to eight small vias adjacent to one small via may be arranged together. For example, the small vias may be arranged so that multiple vias are formed into multiple rectangular via pads, as shown in FIG. 14, or may be arranged so that multiple vias are formed into multiple square via pads.

[0108] As shown in FIG. 13, when the small vias 255 have small via pads at their ends and are each electrically connected to a separate small via wiring 255c, the multiple via pads may be conductive or may be composed of non-conductive via pads 255b'.

[0109] A conductive layer may be formed along the inner diameter surface inside the small vias 255a of the plurality of vias 255, and then the vacant space may be filled with insulating material 22 or the like, and all the internal spaces may be filled with conductive metal, conductive layer, etc. In this way, the plurality of vias and the small vias may transmit electrical signals in the vertical direction.

[0110] The small vias 255a may comprise a small via conductive layer that may be connected to a redistribution conductive layer or to other components depending on the type of vias.

[0111] As shown in FIG. 16 , the small vias 255a of the plurality of vias 255 may include a first set (e.g., first row) whose interior is completely filled with a conductive layer, a second set (e.g., middle row) whose inner surface is formed with a conductive layer and the remaining space is filled with an insulating material or the like, and a third set (e.g., third row) whose inner surface is only formed with a conductive layer.

[0112] In one example, the size of the small vias 255a may be about 3 μm to 20 μm, or about 5 μm to 15 μm, or about 8 μm to 14 μm. By making the small vias have such a size, it is possible to prevent defects such as concave dimples and voids from occurring during the plating process, and it is possible to effectively achieve conductivity.

[0113] The cross-sectional shape of the small via 255a as viewed from above may be a circle, an ellipse, a polygon such as a triangle to an octagon having curved sides, or a simple closed curve. The periphery of the small via may include an arc, an elliptical arc, a curve, etc., but does not have to include angled sides. If an angled side is included, there is a risk of seam voids occurring.

[0114] The ratio of the cross-sectional diameter of the small via 255a when viewed from above to the cross-sectional depth may be 0.01 to 1:1, or 0.02 to 0.5:1.

[0115] The small via 255a may have a cross-sectional side profile with an upper opening that is equal to or larger than a lower opening.

[0116] FIG. 17 shows a cross-sectional side view of a number of vias 255, some of which may be provided within the re-distribution layer 250, some of which may or may not be provided in a lower re-distribution layer, etc.

[0117] Additionally, the plurality of vias 255 may comprise medium sized vias.

[0118] The size of the medium-sized via may be, for example, 75 μm to 200 μm, or 100 μm to 125 μm.

[0119] The cross-sectional shape of the medium-sized via 255a as viewed from above may be, for example, a circle, an ellipse, a polygon such as a triangle to an octagon having curved sides, or a simple closed curve. The periphery of the medium-sized via may include, for example, an arc, an elliptical arc, a curve, or the like that satisfies the above-mentioned size range, but may not include an angled side. If an angled side is included, there is a risk of seam voids occurring.

[0120] When the medium-sized via has an angled side, the side may have a certain radius of curvature, for example, the radius of curvature may be 15 μm or more and 40 μm or less. In such an example, the occurrence of seam voids can be substantially suppressed.

[0121] The insulating material 22 that may be filled in the through holes 23 and the vias 255 of the core substrate 21 may include a polymer resin and inorganic particles. The inorganic particles may include, but are not limited to, silica particles. For example, the inorganic particles may have an average particle size of 100 nm or less or 20 nm or more, and may include a mixture of inorganic particles with a difference in average particle size of 10 nm to 20 nm.

[0122] The polymer resin may be, but is not limited to, an epoxy resin that is UV curable. In one example, the epoxy resin may be an epoxy resin to which a phenol-based hardener is applied, or an epoxy resin to which a cyanate ester is applied, or an epoxy resin to which a phenol ester-based hardener is applied.

[0123] The insulating material 22 may be applied in the form of inorganic particles dispersed in an uncured or semi-cured polymer resin. The insulating material contains inorganic particles of different sizes in a normal ratio to obtain sufficient insulating effect. The insulating material flows well even in fine gaps, and is arranged in the redistribution layer 250 so as to form substantially no voids, and can then be fixed by the curing of the polymer resin.

[0124] The insulating material 22 may be a build-up film ABF manufactured by Ajinomoto Co., but is not particularly limited as long as it is an insulating material that can be used to form a redistribution layer.

[0125] The insulating material 22 may be applied by placing a build-up film on the formed conductor and laminating it under reduced pressure, but the method is not limited to this.

[0126] The packaging substrate 200 may further include a lower redistribution layer 290 under the second surface 215. The lower redistribution layer 290 may include a lower partial wiring (not shown). The lower redistribution wiring may include lower conductors (not shown) having a predetermined pattern and a predetermined thickness, and lower vias (not shown) connecting the conductors above and below.

[0127] The lower vias may include or replace the vias 255 described above.

[0128] The packaging substrate 200 may further include a lower passivation layer located below the lower re-distribution layer 290. The lower passivation layer may include solder or the like, and may thereby be electrically connected to a main board or the like.

[0129] The packaging substrate 200 may further include a passivation layer located on top of the re-distribution layer 250. The passivation layer may further include bumps or the like to transmit signals to the devices 30.

[0130] 7, the packaging substrate 200 may further include a lid 70 located on the upper surface of the redistribution layer 250. The lid may release heat from the device or substrate to the external environment and protect the core substrate 21 from external impact. One side of the lid may be formed with a hole or slot that can be combined with a pin, which can improve the convenience of fixing the packaging substrate during or after the manufacturing process.

[0131] The packaging substrate 200 may include a power transmission element 35 on or inside the packaging substrate 200. The power transmission element may be, for example, a passive element, but is not necessarily limited thereto. The power transmission element may be a capacitor, for example, a multilayer ceramic capacitor (MLCC).

[0132] The power transfer elements 35 may be disposed on the re-distribution layer 250, or may be disposed within cavities formed in the core substrate 21. The power transfer elements may also be disposed within cavities formed in the re-distribution layer.

[0133] Semiconductor Package 900 In one general aspect, a packaging substrate 800 according to an embodiment may include a packaging substrate 200 and a device 30 mounted on the packaging substrate.

[0134] FIG. 6 illustrates a semiconductor package 900 .

[0135] The element 30 may be, for example, a computing element such as a central processing unit (CPU) or a graphics processing unit (GPU), or a memory element such as a memory chip, and these may be applied in combination by arranging or stacking them.

[0136] The element 30 may be a high-frequency semiconductor element. When a high-frequency semiconductor element is applied together with a packaging substrate, unlike a silicon substrate, parasitic elements are not substantially generated in a high-frequency environment, so that efficiency can be improved. In this example, a redistribution layer of a compact size different from that of a prepreg substrate can be realized.

[0137] The description of the packaging substrate 200 is similar to that above, so further description will be omitted.

[0138] Manufacturing method of the packaging substrate 200 In a general aspect, a manufacturing method of a packaging substrate according to an embodiment includes step A of preparing a core substrate as a glass substrate in which a through hole 23 is formed, step B of forming a coarse layer 257 on the core substrate, and step C of forming a fine layer 253 on the coarse layer.

[0139] Step B may include forming a coarse layer via 257b and forming a conductive layer in the coarse layer via.

[0140] The step of forming the conductive layer in the coarse layer via 257b may form the coarse layer top pad 257c simultaneously with forming the conductive layer in the coarse layer via, or may form each separately. The step of forming the coarse layer top pad may form a coarse layer conductor with the conductive layer so as to be located at the same height as the coarse layer top pad.

[0141] The step of forming a conductive layer in the coarse layer via 257b may be performed by filling the inside of the via with a conductive metal, or by forming a partial conductive layer and then filling the inside of the via with an insulating material. Depending on the embodiment, the inside of the via may be filled with an insulating material without forming a conductive layer.

[0142] Step C may include forming fine layer vias 253b and forming a conductive layer within the fine layer vias.

[0143] The step of forming the conductive layer in the fine layer via 257b may be performed simultaneously with forming the fine layer top pad and forming the conductive layer in the fine layer via, or may be performed separately. The step of forming the fine layer top pad may be performed by forming the fine layer conductor with the conductive layer so as to be located at the same height as the fine layer top pad.

[0144] The step of forming the conductive layer in the fine layer via 253b may be performed by filling the inside of the via with a conductive metal, or by forming a portion of the conductive layer and then filling the via with an insulating material.

[0145] The fine layer 253 may include fine layer conductors 253a having a predetermined pattern and a thickness d1u.

[0146] The coarse layer 257 may include coarse layer conductors 257a having a predetermined pattern and a thickness d2u.

[0147] Step B may include step B-1 of forming a plurality of vias 255 as coarse layer vias at predetermined positions in the first layer of insulating material on the core substrate 21, step B-2 of forming a coarse layer conductor 257a having a predetermined pattern and thickness d2u in the first layer of insulating material on the core substrate 21, and step B-3 of stacking insulating material layers by repeating steps B-1 and / or B-2 depending on the desired number of layers.

[0148] Furthermore, the step B may further include a step of forming a coarse layer through hole via as a coarse layer via at a predetermined position of the insulating material after the steps B-2 and / or B-3.

[0149] The step C may include step C-1 of forming fine layer vias 253b at predetermined positions in the first layer of insulating material on the coarse layer 257, step C-2 of forming fine layer conductors 253 having a predetermined pattern and a thickness d1u in the first layer of insulating material using a plating method, and step B-3 of stacking insulating material layers by repeatedly performing steps C-1 and / or C-2.

[0150] Furthermore, the step C may further include a step of forming a fine layer through hole via as a fine layer via at a predetermined position of the insulating material after the steps C-2 and / or C-3.

[0151] The formation of the vias in step B-1 may be performed by laser etching and / or plasma etching. The vias are formed by adjusting the positions and intervals of the small vias, and the specific shapes and intervals are as described above.

[0152] The formation of the plurality of vias in step B-1 may be performed simultaneously with step C or independently.

[0153] The formation of the fine layer via 253b in step C-1 may be performed by laser etching and / or plasma etching, and instead of forming the fine layer via, a plurality of vias may be formed.

[0154] The steps B-2 and C-2 may further include a process of deburring and desmearing before forming the plating. The desmearing may be a dry or wet process, and may be a method of removing residual smears with plasma, or a chemical process may be performed in the order of a swelling agent, a permanganate, and a neutralizing agent.

[0155] The steps B-2 and C-2 may further include a step of performing a primer treatment on the surface of the target before forming the plating. The primer treatment may apply a silane compound or an imidazole compound. The silane compound may be one that can be used as a silane coupling agent, or the former may have a functional group added thereto. For example, the silane compound may have a hydrolase functional group such as a methoxy group and / or an ethoxy group at one end. The silane compound may also have an amino group, a vinyl group, an epoxy group, a methacryloxy group, an acryloxy group, a ureido group, a mercapto group, a sulfide group, or an isocyanate group. For example, the primer may include imidazole, 3-glycidoxy-propyltrimethoxysilane, or tetramethyl orthosilicate.

[0156] Specifically, the primer treatment can be carried out by coating and curing.

[0157] In forming the plating in steps B-2 and C-2, the coarse layer conductor 257a and the fine layer conductor 253a may be formed by a pattern forming method using normal exposure and development, or a copper plating method.

[0158] In the plating formation in steps B-2 and C-2, the via filling of the coarse layer via (the vias) and the fine layer via may be performed by electroless copper plating and / or electrolytic copper plating. For example, depending on the embodiment, some small vias among the vias may be filled early with an insulating material or the like.

[0159] The electroless copper plating may be performed by applying a conductive colloidal solution to the surface of the object to be plated, so that the colloid adheres to the inner surface of the via, or by pretreating the surface to form ions and catalytic metal complexes, after which a solution containing copper ions and a reducing agent may be added to form or fill the conductive layer.

[0160] The electrolytic copper plating may be performed by immersing the surface of the plating target in an electroplating solution and applying a current to the electroplating solution via an electrode. The electroplating solution may contain a water-soluble copper salt, sulfuric acid, chloride ions, an accelerator, an inhibitor, a leveler, a wetting agent, and a brightener. The leveler may contain, for example, a polyvinylimidazole-containing compound, a polyvinylpyrrolidone-containing compound, a polyethyleneimine and imidazole-based compound, 3-diethylamino-7-(4-dimethylaminophenylazo)-5-phenylphenazinium chloride, and the concentration may be 0.01 g / L to 3 g / L, or 0.02 g / L to 0.8 g / L based on the entire plating solution.

[0161] The brightener may include, for example, sodium 3-mercapto-1-propanesulfonate, bipyridine, and the concentration may be 0.01 g / L to 3 g / L, or 0.02 g / L to 0.5 g / L.

[0162] By adjusting the concentrations of brighteners, accelerators, suppressors, levelers, etc. appropriately, the plating speed can be controlled by mechanisms such as physically blocking the plating solution or disrupting chemical bonds, allowing multiple vias to be filled to the desired shape.

[0163] The current density for electrolytic copper plating is 3mA / cm 2 ~50mA / cm 2 The treatment time may be 500 to 2000 seconds.

[0164] Via filling with copper plating of multiple vias allows small vias to have a consistent size with a defined spacing, minimizing the occurrence of dimples or voids.

[0165] Furthermore, the electrolytic copper plating may be performed by forming a barrier on the surface to be plated and on the inner surfaces of the vias, plating the copper so as to cover the outer surfaces of the vias, and then etching the copper by chemical mechanical polishing.

[0166] Although the present disclosure includes specific embodiments, it will be apparent to those skilled in the art after reading the disclosure of this application that various changes in form and details can be made in these embodiments without departing from the spirit and scope of the claims and their equivalents. The embodiments described herein should be considered in an illustrative sense only and not for the purpose of limitation. The description of a feature or aspect in each embodiment shall be deemed applicable to the same feature or aspect in other embodiments. Appropriate results may be achieved when the described techniques are performed in different orders and / or when the components in the described systems, architectures, devices, or circuits are combined in different ways and / or when other components or their equivalents are substituted or supplemented.

[0167] Therefore, the scope of the disclosure is defined by the claims and their equivalents, rather than the detailed description, and all changes that come within the scope of the claims and their equivalents are intended to be embraced by the disclosure.

Claims

1. A multiple via disposed in an insulating layer, the multiple vias include a first via and a second via arranged in a vertically stacked relationship to one another; the first via and the second via are in contact with each other on the same surface, the second vias and the first vias are arranged in different numbers from each other, the first via includes a first via hole and a first via pad connected to each other; The second via is connected to the first via hole through the first via pad, forming a via connection structure.

2. The connection structure according to claim 1 , wherein the multiple vias are arranged to transmit electrical signals in an up-down direction.

3. 2. The connection structure according to claim 1, wherein the number of said second vias per said first via in contact with said first via pad is 2 to 15.

4. a through hole penetrating the substrate in a thickness direction; a core substrate in which the through hole is disposed; a redistribution layer formed on one surface of the core substrate, The substrate includes an electrically conductive layer disposed in a predetermined shape; the electrically conductive layer includes a core conductive layer and a redistribution conductive layer; the core conductive layer includes a first-surface conductive layer disposed in contact with one surface of the core substrate, a through-hole conductive layer disposed in the through-hole, and an other-surface conductive layer disposed in contact with the underside of the other surface of the core substrate; The redistribution conductive layer is disposed embedded within the redistribution layer; the core conductive layer and the redistribution conductive layer are electrically connected to each other; the redistribution conductive layer includes an insulating layer and a via connection structure; The substrate, wherein the via connection structure is as defined in claim 1 .

5. The substrate of claim 4 , wherein the second via is disposed above the first via.

6. The substrate according to claim 4 , wherein the distance between the second vias in contact with the first via pads is 0.2 μm or more.

7. 5. The substrate according to claim 4, wherein the size of the second via in contact with the first via pad is 10 μm to 100 μm.

8. The substrate of claim 4 , wherein the second via comprises a plurality of vias arranged in a line over the first via.

9. Three or more of the second vias are arranged on the first via pad; The substrate according to claim 4 , wherein the second vias include vias arranged in a polygonal shape surrounding a center of a via pad.

10. The substrate of claim 4 , wherein the core substrate is any one of a silicon-based ceramic substrate, a glass-based ceramic substrate, a glass substrate, or a combination thereof.

11. A semiconductor comprising the substrate according to claim 4 and a semiconductor element mounted on the substrate.

Images