Display device

Abstract

To provide a display device with an improved image quality.SOLUTION: The present invention includes a first circuit, a pixel, and a wire. The first circuit has a function of supplying data to the wire and a function of storing the data by using the wire as a floating. The pixel has a function of drawing data twice from the wire and adding the data. The pixel performs the first writing of data when the data is being supplied to the wire, and performs the second writing of the data when the data is being held in the wire. One-time charge of data to a source line can thus supply a data potential of at least an output voltage of a source driver to a display element.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors have been attracting attention. Examples of oxide semiconductors include: Not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals It is known that In-Ga-Zn oxide (hereinafter referred to as IG) is a multi-component metal oxide. There is a lot of research being done on ZO.

[0005] Research on IGZO has revealed that, among oxide semiconductors, CAA is neither single-crystalline nor amorphous. C (c-axis aligned crystalline) structure and nc (nan A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, a transistor is formed using an oxide semiconductor having a CAAC structure. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with low crystallinity have been shown to have minute crystals, as reported in Non-Patent Document 4 and Non-Patent Document 5. This is shown in reference 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non-unique 6), and LSIs and displays that utilize these properties have been reported (Non-Patent Document 1). See patent literature 7 and non-patent literature 8).

[0007] In addition, a memory device using a transistor with extremely low off-state current as a memory cell is disclosed in the patent document This is disclosed in JP 2003-203363 A. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2011-119674 A [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0010] Display devices are becoming increasingly high-resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware capable of displaying at even higher resolutions is being developed. The introduction of HDR (High Dynamic Range) display technology, which improves image quality through adjustments, is also progressing. There is.

[0011] To display a clear gray scale, the range of data potentials that can be supplied to the display element must be made wide. On the other hand, for example, the output voltage of a source driver for a liquid crystal display device is about 15V. To supply a voltage higher than this to the display element, a high-output source driver must be used. A high-output source driver consumes a lot of power, so a new driver IC must be developed. Sometimes it has to be.

[0012] In addition, to display moving images more smoothly, it is necessary to increase the frame frequency. As the number of pixels increases, the horizontal period becomes shorter, making it difficult to increase the frame frequency. By realizing a structure that makes it easy to increase the frame frequency, field sequential This also makes it easier to apply the invention to liquid crystal display devices.

[0013] Therefore, one aspect of the present invention is to provide a display device capable of improving image quality. One of the purposes is to supply a voltage equal to or higher than the output voltage of the source driver to the display element. It is an object of the present invention to provide a display device capable of displaying an image with high brightness. Another object of the present invention is to provide a display device that can improve the display quality. An object of the present invention is to provide a display device capable of increasing the wave number.

[0014] Another object is to provide a display device with low power consumption. One of the objectives is to provide a display device that is easy to use. Another objective is to provide a new display device, etc. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0015] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0016] One aspect of the present invention relates to a display device capable of improving image quality.

[0017] One embodiment of the present invention includes a first circuit, a pixel, and a wiring. The first circuit includes a pixel and a wiring. It has a function to supply data and a function to hold data by floating the wiring. The element has the function of taking in data twice from the wiring and adding them, and the pixel has the function of taking in data twice from the wiring and adding them. The first data is written while the data is being supplied to the pixel, and the data is stored in the wiring. This is a display device in which data can be written for the second time during the period in which the display device is in a standby state.

[0018] Another embodiment of the present invention is a semiconductor device including a first circuit, a first pixel, a second pixel, a first wiring, and a second wiring. a first circuit having a function of supplying first data to the first wiring; The first circuit has a function of holding first data by making the first wiring floating. A function of supplying second data to the second wiring, and a function of floating the second wiring to supply the second data to the second wiring. The first pixel has a function of holding the first data from the first wiring twice. The second pixel has a function of taking in the second data twice from the second wiring and adding them up. The first pixel has a function of adding the first data to the first wiring. The first data is written in the first time during the period, and the first pixel writes the first data to the first wiring. The second first data is written during the period in which the second pixel is held. The first second data is written while the second data is being supplied to the wiring. The second pixel receives the second data for the second time during the period in which the second data is held in the second wiring. A period during which the first pixel writes the first data for the second time, and a period during which the second pixel writes the first data for the second time. The display device can overlap the period during which the element writes the first second data.

[0019] The pixel further includes a third wiring, a fourth wiring, and a fifth wiring. The third wiring is connected to the first pixel. The fourth wiring has a function of supplying a signal potential to select the first pixel. The fourth wiring has a function of supplying a signal potential for selecting the second pixel. the fifth wiring may have a function of supplying a signal potential for selecting the second pixel. stomach.

[0020] Another embodiment of the present invention is a semiconductor device including a first circuit, a first pixel, a second pixel, and a first wiring. a second wiring, a third wiring, a fourth wiring, and a fifth wiring, and the first circuit , electrically connected to the first wiring, the first circuit is electrically connected to the second wiring, and the first The pixel and the second pixel include a first transistor, a second transistor, and a third transistor. a first capacitance element and a circuit block, Or one of the drains is electrically connected to one of the source or drain of the second transistor. One of the source and drain of the second transistor is connected to one of the first capacitance elements. The other electrode of the first capacitor is electrically connected to the source electrode of the third transistor. the source or drain of the third transistor; One of the first transistors is electrically connected to the circuit block, and the first transistor is connected to the first pixel. The other of the source and drain of the third transistor is electrically connected to the first wiring. The other of the source and drain of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the fourth wiring, and the gate of the second transistor is electrically connected to the third wiring. The gate of the third transistor is electrically connected to the third wiring. In the second pixel, the other of the source and the drain of the first transistor is connected to a second The other of the source and the drain of the third transistor is electrically connected to the wiring. The gate of the first transistor is electrically connected to the fifth wiring. The gate of the second transistor is electrically connected to a fourth wiring, and the gate of the third transistor is electrically connected to a fourth wiring. The gate of the display element is electrically connected to the fourth wiring, and the circuit block includes a display element. It is a device.

[0021] The semiconductor device further includes a second capacitance element and a third capacitance element, and one electrode of the second capacitance element is connected to the first capacitance element. One electrode of the third capacitor element is electrically connected to the first wiring, and one electrode of the third capacitor element is electrically connected to the second wiring. This is also fine.

[0022] The first circuit can be electrically connected to a source driver. The fifth wiring can be electrically connected to a gate driver.

[0023] The first circuit includes a fourth transistor and a fifth transistor. One of the source and drain of the fifth transistor is electrically connected to the first wiring. Either the source or the drain of the transistor is electrically connected to the second wiring. The other of the source or drain of the fifth transistor and the other of the source or drain of the fifth transistor The other side can be electrically connected.

[0024] The circuit block includes a sixth transistor, a seventh transistor, a fourth capacitance element, and a surface The organic EL element is connected to a seventh transistor as a display element. the source or drain of the seventh transistor; The other of the drains is electrically connected to one electrode of the fourth capacitor element. One electrode of the first transistor is electrically connected to one of the source and drain of the sixth transistor. The gate of the sixth transistor is electrically connected to the other electrode of the fourth capacitor. The other electrode of the fourth capacitor element is electrically connected to one electrode of the first capacitor element. It is possible.

[0025] In the above configuration, the other of the source and the drain of the sixth transistor is connected to the second transistor. The source or drain of the transistor can be electrically connected to the other of the source or drain of the transistor.

[0026] The circuit block also includes an eighth transistor, a fifth capacitor, and a liquid crystal display as a display element. a liquid crystal element, one electrode of which is electrically connected to one electrode of the fifth capacitor element; One electrode of the fifth capacitance element is connected to one of the source and drain of the eighth transistor. The other of the source and drain of the eighth transistor is electrically connected to the first capacitor. The capacitance element may be electrically connected to one of the electrodes of the capacitance element.

[0027] In the above structure, the other electrode of the fifth capacitor element is connected to the source or It can be electrically connected to the other of the drains.

[0028] The liquid crystal element may be a light scattering type liquid crystal element having a resin portion and a liquid crystal portion between a pair of electrodes. can.

[0029] In the case where a liquid phase element is provided, a light emitting element that emits red (R) light and a light emitting element that emits green (G) light are further provided. The liquid crystal display has a light emitting element that emits blue (B) light and a light emitting element that emits blue (B) light. The light emitting elements are sequentially turned on and off to Display may be performed by emitting the light to the outside via the element.

[0030] The third transistor has a metal oxide in a channel formation region, and the metal oxide includes In and Zn and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) It is preferred that Effect of the Invention

[0031] To provide a display device capable of improving image quality by using one embodiment of the present invention. Alternatively, a voltage higher than the output voltage of the source driver can be supplied to the display element. Alternatively, it is possible to provide a display device capable of increasing the brightness of a displayed image. Alternatively, a display device capable of increasing the frame frequency can be provided. can be provided.

[0032] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. It is also possible to provide a method for driving the display device. It can be provided. [Brief description of the drawings]

[0033] [Figure 1] 1A and 1B are diagrams illustrating a display device. [Diagram 2] 1A and 1B are diagrams illustrating a display device. [Diagram 3] 4 is a timing chart illustrating the operation of the display device. [Figure 4] FIG. 2 is a diagram for explaining a circuit block. [Diagram 5] FIG. 2 is a diagram for explaining a circuit block. [Figure 6] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 7] 1A and 1B are diagrams illustrating a display device. [Figure 8] 4 is a timing chart illustrating the operation of the display device. [Figure 9] FIG. 13 is a diagram illustrating a configuration of a display device used in a simulation. [Figure 10] 4 is a timing chart used in the simulation. [Figure 11] FIG. 13 is a diagram for explaining the results of a simulation. [Figure 12] FIG. 13 is a diagram for explaining the results of a simulation. [Figure 13] 1A and 1B are diagrams illustrating a display device. [Figure 14] FIG. 2 is a diagram illustrating a touch panel. [Figure 15]1A and 1B are diagrams illustrating a display device. [Figure 16] 1A and 1B are diagrams illustrating a display device. [Figure 17] 1A and 1B are diagrams illustrating a display device. [Figure 18] 1A and 1B are diagrams illustrating a display device. [Figure 19] 1A and 1B are diagrams illustrating a display device. [Figure 20] 1A to 1C are diagrams illustrating transistors. [Figure 21] 1A to 1C are diagrams illustrating transistors. [Figure 22] 1A to 1C are diagrams illustrating transistors. [Diagram 23] 1A to 1C are diagrams illustrating transistors. [Figure 24] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0035] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0036] One embodiment of the present invention is a display device having a function of adding image data within a pixel. A storage node is provided in the first image data storage node. Then, the second image data is capacitively coupled to the storage node and supplied to the display element. That is, a data potential equal to or higher than the output voltage of the source driver can be supplied to the display element.

[0037] In the display device, the same data is used for the first image data and the second image data. First, the first write is performed while image data is being supplied to the source line. Then, during the period in which the image data is held in the source line, the second write is performed. Therefore, data charging to the source line can be done only once, which reduces power consumption. In addition, by using two source lines and writing to two pixels in parallel, This can improve the reading speed.

[0038] FIG. 1 illustrates a display device according to one embodiment of the present invention. The display device includes a pixel 10 and a circuit The display device includes a display driver 11, a source driver 12, and a gate driver 13.

[0039] The pixel 10 has the function of capturing image data twice through different paths. The pixel 10 is electrically connected to one source line via two wirings.

[0040] Two source lines (a first source line and a second source line) are provided for each column, and the source lines are alternated for each row. For example, the pixels 10 in the first row are electrically connected to the first source line. The pixel 10 in the second row is electrically connected to the second source line, the pixel 10 in the third row is electrically connected to the 0 is electrically connected to the first source line.

[0041] The circuit 11 is electrically connected to the source driver 12 and the two source lines. The image data supplied from the driver 12 is supplied to the first source line or the second source line. In addition, the circuit 11 can make the two source lines floating. and image data can be held in the first source line and the second source line.

[0042] Image data can be stored more stably in the source line by electrically connecting a capacitance element to the source line. The number of the capacitance elements is not limited to one, and a plurality of capacitance elements may be connected in parallel. In addition, the wiring capacitance (parasitic capacitance) of the source line is sufficiently larger than the data storage capacitance of one pixel 10. If the capacitance is very large, the capacitance element need not be provided.

[0043] One pixel 10 is electrically connected to two gate lines, and the first image data is written The timing of writing the second image data is controlled to be different from that of the first image data. The timing of writing the second image data to the pixel 10 in the nth row (n is a natural number equal to or greater than 1) This allows the timing of writing the first image data to pixel 10 in the (n+1)th row to be overlapped. Therefore, the pixel 10 in the nth row and the pixel 10 in the n+1th row can share one gate line. can be done.

[0044] Therefore, the number of gate lines to which the pixels 10 in the first row and the last row are electrically connected is 1.5 (1 +0.5 lines), but the other pixels 10 are electrically connected to one gate line ( 0.5 + 0.5) In other words, one pixel 10 is essentially controlled by one gate line. This allows the number of signals required to write image data to be reduced. In addition, gate drivers that require complex control are no longer necessary. Also, the number of gate lines is small. Therefore, the aperture ratio of the pixel 10 can be improved.

[0045] Data is written to the pixel 10 for the first time while image data is being supplied to the source line. Then, a second time is performed while image data is being held on the same source line. The source line only needs to be charged with image data once. By using two lines, the pixel 10 in the nth row and the pixel 10 in the n+1th row can be operated in parallel. Therefore, the image data can be written at high speed.

[0046] FIG. 2 shows a circuit 11 and a circuit diagram of the m-th column, n-th row to n+2-th row (m and n are natural numbers of 1 or more). A specific example of a pixel 10 in this embodiment is shown below.

[0047] The circuit 11[m] is configured to include a transistor 107 and a transistor 108. The gate of the transistor 107 is electrically connected to the wiring 124. The gate of the transistor 108 is electrically connected to the wiring 123. One of the source and drain of the transistor 108 is electrically connected to the wiring 125[m]. One of the source and the drain is electrically connected to the wiring 126[m]. The other of the source or drain of transistor 07 and the source or drain of transistor 108 The other end is electrically connected to the output line of the source driver 12 for the m-th column.

[0048] The wiring 123 and the wiring 124 are connected to the transistor 108 or the transistor 107. The wiring 125 [m] and the wiring 126 [m] function as signal lines for controlling the has a function as a source line.

[0049] One electrode of the capacitor 105 is electrically connected to the wiring 125[m]. One electrode of the capacitor 106 is electrically connected to the terminal 126[m]. The other electrode of the capacitor 106 is connected to a wiring 135 to which a fixed potential is supplied. As described above, the capacitance elements 105 and 106 are electrically connected to each other. Alternatively, the capacitors 105 and 106 may be omitted. This may also be configured.

[0050] When the transistor 107 is conductive, the image data (D ATA) is output to the wiring 126[m]. When the transistor 108 is conductive, The image data (DATA) output from the switch driver is output to a wiring 125[m]. In addition, after the image data is output, if the transistor 107 is turned off, the wiring 126[m ] is floating, and image data (DATA) is held in wiring 126[m]. When the transistor 108 is turned off, the wiring 125[m] is floating, and the wiring 1 Image data (DATA) is stored in 25[m].

[0051] The above description of the configuration of the circuit 11 is merely an example. and a function of selectively supplying data through the wiring 125 and the wiring 126. Other configurations may be used as long as they have the function of filtering.

[0052] The pixel 10 includes a transistor 101, a transistor 102, a transistor 103, and a capacitor. The circuit block 110 includes a transistor, The display element may include a capacitance element and a display element, and will be described in detail later.

[0053] The source or drain of the transistor 101 is connected to the source or drain of the transistor 102. The source or drain of the transistor 102 is electrically connected to one of the drains. One of the electrodes is electrically connected to one of the electrodes of the capacitor 104. The electrode is electrically connected to one of the source and drain of the transistor 103. Either the source or the drain of the transistor 103 is electrically connected to the circuit block 110. do.

[0054] Here, one of the source and drain of the transistor 103 and the other of the capacitor 104 The pole and the wiring to which the circuit block is connected are called nodes NM. The display element operates according to the potential of the node NM. The elements of block 110 allow node NM to float.

[0055] In the pixel 10[n,m] in the nth row, the gate of the transistor 101 is connected to the wiring 121[ n+1]. The gate of transistor 102 and the gate of transistor 103 are electrically connected to each other. The gate of the transistor 101 is electrically connected to the wiring 121[n]. The other of the drain and the other of the source or drain of the transistor 103 are connected to the wiring 12 The other of the source and drain of the transistor 102 is electrically connected to A specific potential “V ref The signal line 11 is electrically connected to a wiring that can supply a signal.

[0056] In addition, in the pixel 10[n+1,m] in the (n+1)th row, the gate of the transistor 101 The gate and the gate of the transistor 102 are electrically connected to the wiring 121[n+2]. The gate of the transistor 103 is electrically connected to the wiring 121[n+1]. The other of the source or drain of the transistor 101 and the source or drain of the transistor 103 The other end of the transistor 102 is electrically connected to the wiring 126[m]. The other drain is at a specific potential, V ref " and electrically connect to the wiring that can supply To be continued.

[0057] The wiring 121 functions as a gate line and is electrically connected to the gate driver 13 (see FIG. 1). Connected.

[0058] As described above, the pixels 10 are connected to source lines (wiring 125 or wiring 12) that are alternately connected to different rows. 6). The gate lines (wirings 121) are connected to two adjacent It is electrically connected to the pixel 10 .

[0059] "V ref The wiring that can supply "" is, for example, an element of the circuit block 110 and A power supply line or the like for electrical connection can be used.

[0060] In order to perform the capacitive coupling operation described later, the data supplied to the pixel 10 for the first time is Ta and “V ref " must be supplied for the same period. ref " to the source line When supplying data from the V ref " or 2 A source line is required to supply the second data.

[0061] In one aspect of the present invention, ref " is supplied from the power line, etc., so the timing is switched By this, the first data supply and the second data supply can be done from one source line. That is, the display device can be configured with a small number of wirings.

[0062] The node NM is a storage node. When the transistor 103 is turned on, Alternatively, data supplied to the wiring 126 can be written to the node NM. By making the register 103 non-conductive, the data can be held in the node NM. When a transistor with extremely low off-state current is used as the transistor 103, The transistor can hold a potential for a long time. The transistor used in the channel formation region (hereinafter, referred to as OS transistor) can be used. do.

[0063] In addition to the transistor 103, other transistors constituting the pixel 10 are also Alternatively, the transistors constituting the circuit 11 may be OS transistors. In addition, the pixel 10 and the circuit 11 may have a Si channel forming region. Alternatively, an OS transistor may be used. Alternatively, both a silicon transistor and a silicon transistor may be used. , amorphous silicon transistors, crystalline silicon (typically low-temperature polysilicon Examples include transistors using silicon (polysilicon, single crystal silicon).

[0064] The semiconductor material used for the OS transistor is preferably a material having an energy gap of 2 eV or more. Alternatively, a metal oxide having a polarization of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium. -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Since it exhibits high mobility characteristics, it is suitable for use in transistors that operate at high speed.

[0065] Since the OS transistor has a large energy gap, it exhibits extremely low off-state current characteristics. In addition, OS transistors have the following drawbacks: impact ionization, avalanche breakdown, and short-channel Unlike silicon transistors, it has characteristics such as no effect on the semiconductor, and can form highly reliable circuits. It can be achieved.

[0066] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The membrane can be made of a material having a thickness of 100 nm or less.

[0067] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, the In-M-Zn oxide The atomic ratio of metal elements in the sputtering target used to deposit a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0068] The semiconductor layer is made of an oxide semiconductor having a low carrier density. Carrier density is 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Further details are below. Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 The following is further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a high-purity intrinsic or This is called a substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low impurity concentration and is stable. It can be said that the oxide semiconductor has stable characteristics.

[0069] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer are determined. It is preferable to appropriately set the density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. stomach.

[0070] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of cations and carbon (obtained by secondary ion mass spectrometry) were calculated using a ratio of 2×10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0071] In addition, alkali metals and alkaline earth metals generate carriers when bonded to oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration that can be obtained is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 To the following:

[0072] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, the electrons that serve as carriers This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5×10 18 atoms / cm 3 It is preferable to do the following:

[0073] The semiconductor layer may also have a non-single crystal structure. The non-single crystal structure may have a c-axis oriented structure. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystal structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0074] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not contain a crystalline component. Alternatively, the oxide film having an amorphous structure is, for example, a completely amorphous structure having no crystal parts. stomach.

[0075] In addition, the semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC structure region, or a crystalline structure region. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminate structure. It may have a structure.

[0076] In the following, we will discuss a CAC (Cloud-Aligned Crystalline) semiconductor layer, which is one form of a non-single crystal semiconductor layer. This article explains the configuration of the omposite OS.

[0077] CAC-OS is, for example, an oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region having the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixture of particles with sizes of 2 nm or more or less, or close to that size, in a mosaic or patch pattern It is also called.

[0078] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more of the following: tantalum, tungsten, or magnesium. It may be included.

[0079] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide is one of the CAC-OS) a-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0.) or indium zinc oxide In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0) . ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0. The material is separated into a mosaic shape. Mosaic InO X1 , or In X2 Zinc Y2 O Z2 was distributed uniformly in the film. This is a cloud-like configuration.

[0080] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than in region 2.

[0081] IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of the crystalline compounds include those which are

[0082] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0083] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. In a material composition containing a, Zn, and O, some of the nanoparticles are observed to be mainly composed of Ga. The regions where the In nanoparticles are observed are the same as those where the In nanoparticles are observed as the main component. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0084] It should be noted that the CAC-OS does not include a laminated structure of two or more films having different compositions. For example, a structure consisting of two layers, a film mainly made of In and a film mainly made of Ga, is not included. do not have.

[0085] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the region of the main component and the region of the main component may not be observed.

[0086] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected types of sodium, etc. are included, CAC-OS will The region observed is a nanoparticle of the metal element as the main component, and the region observed is a nanoparticle of In as the main component. The nanoparticle-like regions are randomly distributed in a mosaic pattern. say.

[0087] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas and The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. Or, it is preferable to set it to 0% or more and 10% or less.

[0088] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, no clear peaks are observed from the X-ray diffraction measurement. It can be seen that the orientation of the regions in the ab plane direction and the c-axis direction is not observed.

[0089] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample, a ring-shaped region of high brightness and the corresponding Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that the CAC- The crystal structure of OS has no orientation in the planar and cross-sectional directions. It can be seen that the crystalline structure is o-crystal.

[0090] For example, in the CAC-OS of In-Ga-Zn oxide, the energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) The EDX mapping obtained using scopy revealed that GaO X3 The area where is the main component And, In X2 Zinc Y2 O Z2 , or InO X1 The areas where the main component is It can be confirmed that the compound has a structure similar to that shown in FIG.

[0091] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from ZO compounds. That is, CAC-OS is GaO X3 The main ingredients are In a certain area, X2 Zinc Y2 O Z2 , or InO X1 The region where is the main component and The phase is separated into two layers, and the regions each containing one element as a main component are arranged in a mosaic pattern.

[0092] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y 2O Z2 , or InO X1 The carriers flow through the area where the main component is oxidized. Therefore, the In X2 Zinc Y2 O Z2 , or In O X1 The region in which the main component is distributed in a cloud-like shape in the oxide semiconductor is a region in which a high electric field Effective mobility (μ) can be achieved.

[0093] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching performance. Switching operation can be achieved.

[0094] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (Ion ) and high field-effect mobility (μ This can be done.

[0095] In addition, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0096] An example of the operation of adding two image data will be explained using the timing chart shown in Figure 3. In the following explanation, high potential is represented by "H" and low potential is represented by "L". The image data supplied when writing to the pixels in the 1st row is “D1”, and when writing to the pixels in the 2nd row is “D2”. The image data to be supplied is “D2”, and the image data to be supplied when writing to the pixels in the third row is “D 3". "V ref For example, 0V, GND potential, or a specific reference potential can be used as the " There can be.

[0097] First, the operation of writing “D1” to the node NM[n,m] of the pixel 10[n,m] on the nth row is performed. In this section, we will explain the distribution, coupling, and loss of potential, taking into account the circuit configuration and operation type. The detailed changes due to the supply voltage, such as the capacitance coupling, are not taken into account. However, for clarity, the capacitance of node NM is assumed to be sufficiently large. Assume a small value for

[0098] First, at time T1, the potential of the wiring 123 is set to “H” and the potential of the wiring 124 is set to “L”. Transistor 108 is made conductive so that "D1" is supplied to 5[m].

[0099] Also, when the potential of the wiring 121[n] is set to “H” at time T1, in the pixel 10[n,m], As a result, the transistor 102 becomes conductive, and the potential of one electrode of the capacitor 104 becomes “V ref "and This operation is a reset operation for the subsequent addition operation (capacitive coupling operation). In addition, the transistor 103 is turned on, and the potential of the wiring 125[m] is written to the node NM[n,m]. This is the first write operation, and the potential of the node NM[n,m] is D1”.

[0100] After that, when the potential of the wiring 121[n] is set to “L”, the transistor 102 and the transistor The capacitor 103 is turned off, and "D1" is held at the node NM[n,m]. The element 104 is labeled “D1-V ref " is retained.

[0101] This is the write operation of “D1” in pixel 10[n,m]. Addition of “D1” at pixel 10[n,m] and writing of “D2” at pixel 10[n+1,m] The loading operation will now be described.

[0102] At time T2, the potential of the wiring 123 is set to "L" and the potential of the wiring 124 is set to "H." ] is floating and “D1” is held. Also, “D2” is connected to the wiring 126[m]. This causes transistor 107 to conduct so that the input voltage Vcc is supplied.

[0103] Also, when the potential of the wiring 121[n+1] is set to “H” at time T2, In this state, the transistor 101 is turned on, and the node NM[n The potential “D1” held in the wiring 125[m] is added to the potential of the wiring 125[m]. is the second write operation, and the potential of node NM[n,m] is “D1-V ref +D1 " At this time, "V ref If "=0, the potential of node NM[n,m] is "D 1+D1”. In other words, the data supplied to and held on the source line is added up within the pixel. This can be done.

[0104] In addition, in the pixel 10[n+1,m], the transistor 102 is turned on, and the capacitor 104 The potential of one electrode is “V ref " Also, the transistor 103 becomes conductive, and the node The potential of the wiring 126[m] is written to NM[n+1,m]. This operation is the first write. This is a write operation, and the potential of the node NM[n+1,m] becomes “D2”.

[0105] This is the write operation of “D1+D1” in pixel 10[n,m] and the write operation of pixel 10 This is the write operation of “D2” in pixel 10[n+1,m]. The addition of “D2” in pixel 10[n+2,m] and the writing operation of “D3” in pixel 10[n+2,m] are explain.

[0106] At time T3, the potential of the wiring 123 is set to “H”, the potential of the wiring 124 is set to “L”, and the wiring 126 is turned on. In addition, "D3" is supplied to the wiring 125 [m]. This causes transistor 108 to conduct so that

[0107] Also, when the potential of the wiring 121[n+2] is set to “H” at time T3, In this state, the transistor 101 is turned on, and the node NM[n The potential “D2” held in the wiring 126[m] is added to the potential of the wiring 126[m]. The operation is the second write operation, and the potential of node NM[n+1,m] is “D2-V re f +D2”. At this time, “V ref If ”=0, then the node NM[n+1,m] The potential becomes "D2+D2".

[0108] In addition, in the pixel 10[n+2,m], the transistor 102 is turned on, and the capacitor 104 The potential of one electrode is “V ref " Also, the transistor 103 becomes conductive, and the node The potential of the wiring 125[m] is written to NM[n+2,m]. This operation is the first write. This is a write operation, and the potential of the node NM[n+2,m] becomes “D3”.

[0109] This is the write operation of “D2+D2” in pixel 10[n+1,m] and the This is the write operation of “D3” in pixel 10[n+2,m]. In this case, the same operation as described above is performed according to the timing chart shown in FIG. , "D3+D3" can be written.

[0110] As described above, in one aspect of the present invention, the operation of adding two image data is performed at high speed. By adding image data, a potential higher than the maximum output voltage of the source driver can be obtained. This allows the display element to receive more light, improving display brightness and expanding the dynamic range. In addition, when performing a standard display, the output voltage of the source driver can be set to approximately It can also be halved, reducing power consumption.

[0111] In addition, writing operations to the pixels in the nth row and the n+1th row can be performed in parallel. Therefore, the frame frequency can be increased. In addition, even if the time is short, the frame frequency can be easily increased. It is also suitable for field sequential liquid crystal display devices that require this.

[0112] 4A to 4C are applicable to the circuit block 110 and include an EL element as a display element. This is an example of a configuration that includes

[0113] The structure shown in FIG. 4A includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain of the transistor 111 is connected to one of the EL elements 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to a node NM. do.

[0114] The other of the source and the drain of the transistor 111 is electrically connected to the wiring 128. The other electrode of the EL element 114 is electrically connected to a wiring 129. For example, the wiring 128 can supply high potential power. In addition, the wiring 129 can supply a low potential power source.

[0115] Here, the “V ref " or The other of the drains can be electrically connected to the wiring 128. ref " is 0V, Since it is preferable that the potential is GND or a low potential, the wiring 128 is at least one of these potentials. The wiring 128 also has a function of supplying either one of the following: In the imagining,ref " is supplied, and a high potential is supplied at the timing when the EL element 114 is to emit light. The other of the source and drain of the transistor 102 is V ref ” may be electrically connected to a common wiring that supplies the

[0116] In the configuration shown in FIG. 4A, the potential of the node NM is equal to or higher than the threshold voltage of the transistor 111. When this occurs, a current flows through the EL element 114. Therefore, as shown in the timing chart of FIG. In some cases, the EL element 114 may start emitting light at the first writing stage shown in FIG. 1, and this may limit the applications. This may be the case.

[0117] FIG. 4B shows a configuration in which a transistor 112 is added to the configuration in FIG. One of the source or drain of the transistor 112 is connected to the source or drain of the transistor 111. The other of the source and drain of the transistor 112 is electrically connected to The gate of the transistor 112 is electrically connected to the wiring 127. The wiring 127 serves as a signal line for controlling the conduction of the transistor 112. It can have a function.

[0118] In this configuration, the potential of the node NM is equal to or higher than the threshold voltage of the transistor 111. When the transistor 112 is conductive, a current flows through the EL element 114. The EL element 114 starts emitting light after the second write shown in the timing chart. can be done.

[0119] FIG. 4C shows a configuration in which a transistor 115 is added to the configuration of FIG. 4B. One of the source or drain of the transistor 115 is connected to the source or drain of the transistor 111. The other of the source and drain of the transistor 115 is electrically connected to The gate of the transistor 115 is electrically connected to the wiring 131. The wiring 131 functions as a signal line for controlling the conduction of the transistor 115. may have the following structure:

[0120] The wiring 130 can be electrically connected to a source of a particular potential, such as a reference potential. A specific potential is applied to either the source or drain of the transistor 111 from the line 130. This also makes it possible to stabilize the writing of image data.

[0121] In addition, the wiring 130 can be connected to the circuit 120 and has a function as a monitor line. The circuit 120 controls the specific potential sources and the electrical characteristics of the transistor 111. The correction data generating unit may have one or more of the functions of acquiring and generating correction data.

[0122] 5A to 5C are applicable to the circuit block 110 and include a liquid crystal element as a display element. This is an example of a configuration that includes

[0123] The structure shown in FIG. 5A includes a capacitor 116 and a liquid crystal element 117. One electrode of the capacitor 7 is electrically connected to one electrode of the capacitor 116. One electrode of the transistor is electrically connected to a node NM.

[0124] The other electrode of the capacitor 116 is electrically connected to the wiring 132. One electrode is electrically connected to a wiring 133. The wirings 132 and 133 serve to supply power. For example, the wirings 132 and 133 can be connected to a reference potential such as GND or 0V or an arbitrary potential. can be supplied.

[0125] Here, the “V ref " or The other drain can be electrically connected to the wiring 132. The other of the source or drain of 02 is “V ref Electrically connected to the common wiring that supplies You may do so.

[0126] In this configuration, when the potential of the node NM becomes equal to or higher than the threshold voltage for operating the liquid crystal element 117, the liquid crystal element The operation of the crystal element 117 is started. Therefore, the first time shown in the timing chart of FIG. The display operation may start at the writing stage, and the usage may be limited. In the case of a transmission type liquid crystal display device, the timing is as shown in the timing chart of FIG. By combining this with other operations such as turning off the backlight, the display is safe even when unnecessary display operations are performed. This can suppress recognition.

[0127] FIG. 5B shows a configuration in which a transistor 118 is added to the configuration of FIG. 5A. One of the source and drain of the transistor 118 is electrically connected to one electrode of the capacitor element 116. The other of the source and drain of the transistor 118 is electrically connected to the node NM. The gate of the transistor 118 is electrically connected to the wiring 127. 27 can function as a signal line for controlling the conduction of the transistor 118. .

[0128] In this configuration, when the transistor 118 is turned on, the potential of the node NM is applied to the liquid crystal element 117. Therefore, the liquid crystal is The operation of the element can be started.

[0129] When the transistor 118 is off, the capacitance element 116 and the liquid crystal element 117 are not supplied with Since the supplied potential is held, the capacitor elements 116 and It is preferable to reset the potential supplied to the liquid crystal element 117. For example, a reset potential is supplied to a source line (wiring 125 or wiring 126) to which a pixel is connected. In this case, the transistor 102 and the transistor 118 may be simultaneously turned on.

[0130] FIG. 5C shows a configuration in which a transistor 119 is added to the configuration of FIG. 5B. One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and the drain of the transistor 119 is electrically connected to a wiring 130. The gate of the transistor 119 is electrically connected to the wiring 131. The reference numeral 31 can function as a signal line for controlling the conduction of the transistor 119 .

[0131] The circuit 120 electrically connected to the wiring 130 is similar to that described above with reference to FIG. In addition, the potential supplied to the capacitor element 116 and the liquid crystal element 117 is reset. It may be possible.

[0132] In addition, in Figs. 4 and 5, ref In the above example, " is supplied from the power supply line. For example, in the pixel 10[n,m] shown in FIG. Wire 121 to “V refAs shown in FIG. 3, the write of “D1” When the transistor 103 is turned on, the wiring 121[n+1] is supplied with a potential corresponding to “L”. Since the potential is supplied, ref " can be used.

[0133] As shown in FIG. 6B and FIG. 6C, the transistors 101, 102, and 103 are back-coupled. FIG. 6B shows a structure in which a back gate is electrically connected to the front gate. FIG. 6(C) shows a structure in which the transistors are electrically connected to each other, which has the effect of increasing the on-state current. The gate is electrically connected to a wiring 134 that can supply a constant potential. The threshold voltage of the transistor can be controlled. The transistors included in the circuit blocks 110 shown in FIGS. may be provided.

[0134] A display device having pixels that hold data in source lines and use the data in an addition operation. may have a configuration as shown in FIG.

[0135] In the display device shown in FIG. 7, the basic pixel configuration is the same as that of the display device shown in FIG. The difference is that there is one line per column and two gate lines per row. In place of the path 11, a circuit 14 is provided.

[0136] As gate lines, wiring 121 and wiring 122 are provided. The gate of the transistor 102 and the gate of the transistor 103 are electrically connected to each other. A gate of the transistor 101 is electrically connected to the gate.

[0137] The circuit 14 includes a transistor 109. The gate of the transistor 109 is connected to a wiring 123. The source or drain of the transistor 109 is electrically connected to the wiring 125. The other of the source and drain is electrically connected to a source driver 12. Therefore, by controlling the conduction of the transistor 109, 25 can supply or hold image data (DATA).

[0138] In the configuration shown in FIG. 7, the first write is performed when image data is supplied to the source line. The second write is performed when image data is stored in the source line. Since all pixels are connected to a single source line, the writing speed can be improved by parallel operation. On the other hand, when image data is held on the source line, the output of the source driver Power gating can be performed on the circuit to reduce power consumption due to leakage current, etc. do.

[0139] Using the timing chart shown in FIG. 8, the operation of adding two image data and the source An example of power gating of a driver will now be described.

[0140] First, write image data “D1” to node NM[n,m] of pixel 10[n,m] on the nth row. In this section, we will explain the operation of the circuit configuration in the distribution, coupling, or loss of potential. It does not take into account detailed changes due to factors such as the timing of operations.

[0141] At time T1, the potential of the wiring 123 is set to “H” so that “D1” is supplied to the wiring 125[m]. This causes transistor 109 to conduct.

[0142] Also, when the potential of the wiring 121[n] is set to “H” at time T1, in the pixel 10[n,m], The transistor 103 is turned on, and the potential of one electrode of the capacitor 104 is set to “V ref "and This operation is a reset operation for the subsequent addition operation (capacitive coupling operation). In addition, the transistor 102 is turned on, and the potential of the wiring 125[m] is written to the node NM[n,m]. This is the first write operation, and the potential of node NM[n,m] is “D 1”.

[0143] At time T2, when the potential of the wiring 121[n] is set to “L” and the potential of the wiring 123 is set to “L”, The transistor 102 and the transistor 103 become non-conductive, and the node NM[n,m] is set to “D 1” is held in the capacitance element 104. ref " is retained. Also , the wiring 125[m] becomes floating and "D1" is held.

[0144] This is the write operation of “D1” in pixel 10[n,m]. The addition operation of “D1” in [n, m] is explained below.

[0145] When the potential of the wiring 122[n] is set to “H” at time T2, a transistor is turned on in the pixel 10[n,m]. The transistor 101 becomes conductive, and the voltage of the node NM[n,m] is increased by the capacitive coupling of the capacitance element 104. The potential “D1” held on the wiring 125[m] is applied to the potential. This is a write operation, and the potential of node NM[n,m] is “D1-V ref +D1”. At this time, “V ref If "=0, the potential of node NM[n,m] is "D1+D1" In other words, the data supplied to and held on the source line can be added within the pixel. .

[0146] After time T3, the same operation as above is repeated to transfer the image data to the pixels 10 in the next row and thereafter. The image data (DATA) is written.

[0147] Here, during the period from time T2 to time T3, data is held in the source line, so The output operation of the source driver 12 is no longer necessary. The operation of the output circuit of the pixel 10 can be stopped during this period. This reduces the data writing period by approximately half, resulting in a significant reduction in power consumption.

[0148] Next, a configuration in which the circuit block shown in FIG. 5(A) is applied to the pixel 10 of the display device shown in FIG. The simulation results of the above (see Figure 9) are explained. The parameters are as follows: The transistor size is L / W=4 μm / 200 μm (transistor in circuit 11), = 4 μm / 4 μm (transistor of pixel 10), the resistance value of the source line is 1 kΩ (circuit The capacitance of the capacitance element Csl is 100 pF (corresponding to the resistance between the source line (equivalent to 1000 100fF capacitive elements connected to the F, the capacitance of the capacitance element Cs is 100 fF, the capacitance of the liquid crystal element Clc is 40 fF, and the image data DATA is 5V maximum, “V ref " is 0V, and the common electrodes CsCOM and TCOM are The voltage applied to the gate of the transistor was +20V for “H” and + L” was set to -20V. SPICE was used as the circuit simulation software. Used.

[0149] A simulation of the circuit shown in Figure 9 operating according to the timing chart shown in Figure 10. The simulation results are shown in FIG. 11. SMP1 and SMP2 are gate lines that control the operation of the circuit 11. SL1 is a source line connected to pixel 10[n], and SL2 is a source line connected to pixel 10[n+1]. GL[n] is the source line connected to pixel 10[n], GL[n+2 ] is a gate line connected to pixel 10[n+1], GL[n+1] is a pixel 10[n] and D1 is the gate line connected to pixel 10[n+1]. D2 is the image data supplied to pixel 10[n]. D1 corresponds to the image data (DATA) supplied to pixel 10[n+1]. D3 corresponds to the image data (DATA) supplied to pixel 10[n+2] (not shown). Equivalent.

[0150] Figure 11 shows the state of the node NM[n] and The voltages at the nodes NM[n+1] and NM[n ], the first write is performed when GL[n] is set to “H”, and GL[n+ 1] is set to “H” for the second write, and image data (DATA) is It has been confirmed that the number has been added. The same is true for node NM[n+1].

[0151] FIG. 12 shows the state of the node NM when −5V to +5V is input as image data (DATA). The simulation results of the voltage at node NM[n] and node NM[n+1] are shown in Fig. It was confirmed that image data (DATA) was added in both cases.

[0152] From the above simulation results, the potential held in the source line capacitance is It has been confirmed that the source driver is applied as a voltage in the display device according to one embodiment of the present invention. This allows the write period from the monitor to the pixel to occur essentially once per horizontal period, resulting in high-speed operation. It is preferable to apply the present invention to a display device requiring the above.

[0153] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0154] (Embodiment 2) In this embodiment, a configuration example of a display element using a liquid crystal element and a display device using an EL element are described. A configuration example will be described. In this embodiment, the display device described in the first embodiment will be Descriptions of the elements, operations and functions of the device are omitted.

[0155] 13A to 13C show the structure of a display device in which one embodiment of the present invention can be used. FIG.

[0156] In FIG. 13A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display unit 215 is disposed between the sealant 4005 and the second substrate 4. Sealed by 006.

[0157] The display unit 215 may include the pixels 10 and the like described in the first embodiment. The scanning line driver circuit, which will be explained below, corresponds to the gate driver, and the signal line driver circuit corresponds to the source driver. do.

[0158] In FIG. 13A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The common line driving circuit 241a is formed of a semiconductor. , 129, 132, 133, 135, etc., each of which has a function of supplying a predetermined potential.

[0159] A scanning line driving circuit 221a, a common line driving circuit 241a, a signal line driving circuit 231a, and a signal Various signals and potentials are applied to the line driver circuit 232a via a flexible printed circuit (FPC). The signal is supplied via a digital signal processor (DPC) 4018.

[0160] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 of the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. The device is implemented in a different area than the area in which it is installed.

[0161] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0162] FIG. 13B shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. The circuit 4042 is implemented by the COG method. The display unit 215 and the display unit 216 can be integrally formed on the same substrate to form a system on panel. Cut.

[0163] In FIG. 13B, the scanning line driving circuit 221a and the common line driving circuit 241a are In this example, the driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0164] In FIG. 13B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided to surround the drive circuit 221a and the common line drive circuit 241a. A display unit 215, a scanning line driving circuit 221a, and a common line driving circuit A second substrate 4006 is provided on the display unit 215 and the scanning line driver 241a. The driving circuit 221a and the common line driving circuit 241a are disposed between the first substrate 4001 and the sealing material 40. The display element is sealed by the second substrate 4005 and the second substrate 4006 .

[0165] In addition, in FIG. 13B, a signal line driver circuit 231a and a signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. A scanning line driver circuit or a common line driver circuit may be separately formed and mounted. A part of the driving circuit, a part of the scanning line driving circuit, or a part of the common line driving circuit is separately formed and mounted. Also, as shown in FIG. 13C, the signal line driving circuit 231a and the signal line driving The circuit 232 a may be formed on the same substrate as the display unit 215 .

[0166] The display device includes a panel in which a display element is sealed, and a controller for the panel. The term "IC" may also refer to a module in which an IC or the like including the above is mounted.

[0167] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment may be used as the transistor. can be done.

[0168] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit are all the same or different. The transistors may have the same structure, or may have two or more types of transistor structures. Similarly, the transistors in the pixel circuit may all have the same structure. Alternatively, the semiconductor device may have transistors with two or more different structures.

[0169] In addition, an input device can be provided on the second substrate 4006. The display device shown in FIG. 1 is provided with an input device 4200, and the display device 4200 functions as a touch panel. can be done.

[0170] There is no limitation on a detection element (also referred to as a sensor element) included in a touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0171] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or a pressure-sensitive method.

[0172] In this embodiment, a touch panel having a capacitance type sensing element will be described as an example. .

[0173] The capacitive touch sensor includes a surface capacitive touch sensor and a projected capacitive touch sensor. The electrostatic capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0174] The touch panel according to one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is provided on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0175] 14(A) and (B) show an example of a touch panel. FIG. 14(A) shows a touch panel 4 FIG. 14B is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0176] The touch panel 4210 is constructed by bonding a display device and a sensing element that are separately manufactured. be.

[0177] The touch panel 4210 includes an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0178] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. , and electrically connects to each of the plurality of wirings 4238 and the plurality of wirings 4239. 72b may be provided with IC4273b.

[0179] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also used. may be applied.

[0180] 15(A) and (B) are cross-sectional views of the portion indicated by the chain line N1-N2 in FIG. 13(B). The display device shown in FIG. 15(A) and (B) has an electrode 4015. It is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. 15(A) and (B), the electrode 4015 is formed by insulating layers 4112 and 4111. and electrically connected to the wiring 4014 in an opening formed in the insulating layer 4110. do.

[0181] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The conductive layer is made of the same material.

[0182] The display unit 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are In FIG. 15(A) and (B), the transistors included in the display unit 215 are 4010 and a transistor 4011 included in the scanning line driver circuit 221a. In addition, in FIG. 15(A) and (B), the transistor 4010 and the transistor Although a bottom-gate transistor is shown as an example of the transistor 4011, a top-gate transistor It may also be a transistor.

[0183] In FIG. 15(A) and (B), an insulating layer is provided on a transistor 4010 and a transistor 4011. 15B, a partition wall 451 is provided over the insulating layer 4112. 0 is formed.

[0184] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The semiconductor device has an electrode 4017 formed thereon. The electrode 4017 functions as a back gate electrode. It is possible.

[0185] The display device shown in FIGS. 15A and 15B includes a capacitor 4020. 020 is an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source electrode and the drain electrode. The poles overlap via an insulating layer 4103 .

[0186] In general, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set so that the charge can be held for a predetermined period of time, taking into consideration the leakage current of the capacitor. The capacitance of the capacitance element may be set in consideration of the off-state current of the transistor and the like.

[0187] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. FIG. 15(A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 serving as a display element includes a first electrode layer 4030 and a second electrode layer 40 31, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between the alignment films 31 and 32. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as a A first electrode layer 4030 and a second electrode layer 4031 are provided on the second substrate 4006 side. Overlapping via layer 4008.

[0188] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0189] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. In addition, the above-mentioned backlight and sidelight may be used. Micro LEDs or the like may be used as the light.

[0190] In the display device shown in FIG. 15A, between the second substrate 4006 and the second electrode layer 4031, A light blocking layer 4132, a colored layer 4131, and an insulating layer 4133 are provided.

[0191] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, etc. Examples of the material for the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, a laminated film of a film containing the material of the colored layer may be used for the light-shielding layer. A film containing a material for a colored layer that transmits light of a certain color and a material for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0192] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, or dyes. The light-shielding layer and the colored layer are formed by, for example, an ink-jet method. The electrode can be formed using:

[0193] The display device shown in FIGS. 15A and 15B includes an insulating layer 4111 and an insulating layer 4104. The insulating layer 4111 and the insulating layer 4104 are made of insulating layers that are not easily permeated by impurity elements. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, It is possible to prevent the infiltration of impurities.

[0194] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element can be applied. An EL element is a light-emitting compound placed between a pair of electrodes. A layer including a voltage lower than the threshold voltage of the EL element is provided between a pair of electrodes. When a large potential difference is generated, holes are injected into the EL layer from the anode side and electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, forming luminescent The compound emits light.

[0195] EL elements are also classified according to whether the luminescent material is an organic compound or an inorganic compound. In general, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0196] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer. Then, the carriers (electrons and holes) recombine. This causes the light-emitting organic compound to form an excited state, which then returns to the ground state. Due to this mechanism, this type of light-emitting element is called a current-excited light-emitting element. is called a child.

[0197] In addition to the light-emitting compound, the EL layer may be formed by using a material having a high hole-injecting property and a material having a high hole-transporting property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The insulating layer may include a material having high electron-transporting and hole-transporting properties.

[0198] The EL layer can be formed by a variety of methods, including deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0199] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0200] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes must be transparent. A transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission structure, which emits light from the top surface of the substrate, and bottom emission structure, which emits light from the bottom surface of the substrate. (bottom emission) structure and dual emission (double emission) structure that emits light from both sides There are light emitting elements having a light-emitting (emission) structure, and light emitting elements having any of the emission structures can be applied.

[0201] FIG. 15(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513, which is a display element, is provided in the display portion 215. The light-emitting element 4513 is electrically connected to the transistor 4010. This is a laminated structure of an electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 13 can be changed as appropriate.

[0202] The partition 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is continuous. It is preferable to form the inclined surface so as to have a curvature.

[0203] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0204] The color of light emitted by the light-emitting element 4513 can be white, red, green, or blue depending on the material that constitutes the light-emitting layer 4511. , cyan, magenta, or yellow, etc.

[0205] As a method for realizing color display, a light-emitting element 4513 that emits white light is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light-emitting element 4513 with a different light-emitting color for each pixel. The first method has higher productivity than the latter method. On the other hand, the latter method requires a light-emitting layer 4511 for each pixel. However, the latter method is less productive than the former method because it requires separate production of In addition to the latter method, it is possible to obtain a luminescent color with higher color purity than the former method. By adding a microcavity structure to element 4513, color purity can be further improved. can be done.

[0206] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. The child dots can be used in a light-emitting layer to function as a light-emitting material.

[0207] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode layer A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond-Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealant 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (lamination film) that is highly airtight and has little outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0208] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Also, filler 4514 may contain a desiccant.

[0209] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0210] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is placed on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. can be installed as needed. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0211] In addition, by making the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves visibility of the displayed image.

[0212] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the reflecting property can be selected depending on the pattern structure of the electrode layer.

[0213] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0214] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof. .

[0215] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, Its derivatives are also included.

[0216] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0217] As shown in FIG. 16, the transistors and the capacitor elements are arranged so as to have an overlapping area in the height direction. For example, the transistors 4011 and 4021 that form the driver circuit may have a stack structure. By overlapping the transistor 4021 and the transistor 4022, a display device with a narrow frame can be obtained. In addition, a transistor 4010, a transistor 4023, and a capacitor element 402 If the 0s and 1s are arranged so that they overlap, the aperture ratio and resolution can be improved. In FIG. 16, a stack structure is applied to the liquid crystal display device shown in FIG. However, the present invention may be applied to the EL display device shown in FIG.

[0218] In addition, in the pixel circuit, a transparent conductive film with high transparency to visible light is used for electrodes and wiring. By doing so, it is possible to increase the light transmittance within the pixel, and thus to substantially improve the aperture ratio. In addition, when an OS transistor is used, the semiconductor layer also has a light-transmitting property. The aperture ratio can be increased. This is because the transistors are not stacked. It is also effective in

[0219] Furthermore, a display device may be configured by combining a liquid crystal display device and a light emitting device.

[0220] The light emitting device is disposed on the opposite side of the display surface or on the edge of the display surface. The light emitting device emits light to the display element. The light emitting device can also be called a backlight.

[0221] Here, the light emitting device is a plate- or sheet-shaped light guide portion (also called a light guide plate) that emits light of different colors. The light emitting element may be disposed near a side surface of the light guide portion. Then, light can be emitted from the side of the light guide to the inside. The light guide has a mechanism for changing the light path ( This allows the light-emitting device to emit light to the pixel area of ​​the display panel. It is possible to irradiate light uniformly. Alternatively, a light-emitting device can be placed directly under the pixel without providing a light guide section. The configuration may be such that the

[0222] The light emitting device preferably has light emitting elements of three colors, red (R), green (G), and blue (B). It is preferable that the light emitting element further includes a white (W) light emitting element. It is preferable to use LEDs (Light Emitting Diodes). .

[0223] Furthermore, the light emitting element has a full width at half maximum (FWHM) of its emission spectrum. at Half Maximum) is 50 nm or less, preferably 40 nm or less, Preferably, the wavelength is 30 nm or less, more preferably 20 nm or less, and the emission wavelength is extremely high in color purity. It is preferable that the full width at half maximum of the emission spectrum is as small as possible. However, it can be set to, for example, 1 nm or more. It is possible to provide a vivid display with high color reproducibility.

[0224] In addition, the red light emitting element has an emission spectrum peak wavelength of 625 nm or more and 650 nm or less. It is preferable to use an element located in the range below. Use an element whose spectral peak wavelength is in the range of 515 nm to 540 nm. It is preferable that the blue light emitting element has an emission spectrum having a peak wavelength of 445 nm or more. It is preferable to use elements that lie in the 70 nm range or less.

[0225] The display device sequentially blinks the three color light emitting elements and drives the pixels in sync with them. The color display can be achieved based on the sequential additive color mixing method. This can also be called sequential driving.

[0226] Field sequential driving allows for the display of vivid color images. In addition, by using the above driving method, it is possible to display smooth moving images. This eliminates the need to configure a pixel with multiple sub-pixels of different colors, and reduces the effective reflective area (effective surface area) of a single pixel. Since the display area (also called the aperture ratio) can be increased, a bright display can be achieved. Since there is no need to provide a color filter to the pixel, the transmittance of the pixel can also be improved. Furthermore, the manufacturing process can be simplified, and the manufacturing cost can be reduced. It can be reduced.

[0227] 17(A) and (B) are schematic cross-sectional views of a display device capable of field sequential driving. The display device has a backlight capable of emitting RGB colors on the substrate 4001 side. In the field sequential drive, the time division of each color of RGB is Since colors are expressed through split emission, color filters are not required.

[0228] The backlight unit 4340a shown in FIG. 17(A) has a diffusion plate 4352 directly under the pixels. A plurality of light emitting elements 4342 are provided through the light emitting elements 4342. 42 toward the substrate 4001 side, and the function of making the brightness uniform within the display surface. A polarizing plate may be provided between the light emitting element 4342 and the diffusion plate 4352 as necessary. In addition, the diffusion plate 4352 may not be provided if it is not necessary. It may be omitted.

[0229] The backlight unit 4340a can be disposed directly under the display unit, so that the light-emitting element 4 342, it is possible to mount many, and a bright display is possible. In addition, a light guide plate is not required. This has the advantage that the light efficiency of the light emitting element 4342 is not easily impaired. A lens 4344 for diffusing light may be provided in 4342 .

[0230] The backlight unit 4340b shown in FIG. 17(B) has a diffusion plate 4352 directly under the pixels. The light guide plate 4341 is provided at the end of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffusion plate 4352. The guided light can be scattered by the uneven surface and emitted in the direction of the diffusion plate 4352.

[0231] The light emitting element 4342 can be fixed to a printed circuit board 4347. ), the light emitting elements 4342 of each color of R, G, and B are illustrated overlapping each other, but The light emitting elements 4342 of the respective colors B and B can be arranged side by side. A reflective layer 4348 that reflects visible light is provided on the side opposite to the light emitting element 4342. It is okay.

[0232] The backlight unit 4340b can reduce the number of light-emitting elements 4342. It can be made low cost and thin.

[0233] The liquid crystal element may be a light scattering type liquid crystal element. It is preferable to use an element having a composite material of a liquid crystal and a polymer. For example, a polymer dispersed liquid crystal (PDLC(Polymer Dispersed Liquid Crystal)) Alternatively, a polymer network liquid crystal (PNLC) A liquid crystal (LC) network element may also be used.

[0234] The light-scattering liquid crystal element is a liquid crystal layer in a three-dimensional network structure of a resin part sandwiched between a pair of electrodes. The liquid crystal portion is made of a material such as nematic liquid crystal. The resin portion can be made of a photocurable resin. For example, monofunctional monomers such as acrylates and methacrylates, diacrylates, triacrylates, etc. Multifunctional monomers such as acrylates, dimethacrylates, and trimethacrylates, or A polymerizable compound in which these are mixed can be used.

[0235] Light-scattering liquid crystal elements utilize the anisotropy of the refractive index of liquid crystal materials to transmit or scatter light. The resin portion may also have anisotropy in refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the substrate, the refraction between the liquid crystal section and the resin section occurs. A direction occurs in which the difference in the refractive index becomes smaller, and the light incident along that direction is scattered by the liquid crystal section. Therefore, the light scattering type liquid crystal element is visually perceived as transparent from that direction. On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, the liquid crystal part and the resin Since there is no significant change in the refractive index difference in the liquid crystal part, the incident light is scattered by the liquid crystal part. Therefore, the light scattering type liquid crystal element remains opaque regardless of the viewing direction.

[0236] FIG. 18A shows a case where the liquid crystal element 4013 of the display device of FIG. 17A is replaced with a light scattering type liquid crystal element 401. The light scattering type liquid crystal element 4016 has a liquid crystal portion and a resin portion. The field sequence includes a composite layer 4009, and electrode layers 4030 and 4031. The elements related to the liquid crystal display are the same as those in FIG. 17(A), but a light scattering type liquid crystal element 4016 is used. In this case, the alignment film and the polarizing plate are not necessary. 1, but may be columnar.

[0237] FIG. 18B shows a case where the liquid crystal element 4013 of the display device of FIG. 17B is replaced with a light scattering type liquid crystal element 401. 18B, the light scattering type liquid crystal element 4016 is replaced with a voltage It operates in a mode where it transmits light when no voltage is applied and scatters light when a voltage is applied. By adopting this configuration, the normal state (the state where no display is made) ) can be used as a transparent display device. In this case, when the light scattering operation is performed, It is possible to display in color.

[0238] Modified examples of the display device shown in FIG. 18(B) are shown in FIGS. 19(A) to 19(E). In A) to E), for the sake of clarity, some elements of FIG. 18B are used, and other elements are omitted. It is omitted in the illustration.

[0239] FIG. 19A shows a structure in which a substrate 4001 functions as a light guide plate. The outer surface of the light guide plate may be provided with an uneven shape. This reduces the manufacturing cost. In addition, the light guide plate does not attenuate light. Therefore, the light emitted from the light emitting element 4342 can be utilized efficiently.

[0240] FIG. 19B shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. The total reflection at the interface between the composite layer 4009 and the substrate 4001 and the interface between the composite layer 4009 and the substrate 4001 are By using the light scattering type liquid crystal element, light can be emitted to the outside. The portion is made of a material having a refractive index larger than that of the substrate 4001 and the substrate 4006 .

[0241] Note that the light-emitting element 4342 may be provided not only on one side of the display device but also on the other side as shown in FIG. Alternatively, the light emitting element 43 may be provided on two sides facing each other. Furthermore, the light emitting element 43 may be provided on three or four sides. By providing 42 on multiple sides, it is possible to compensate for light attenuation and to accommodate large-area display elements. It is possible.

[0242] FIG. 19(D) shows a display device in which light emitted from a light emitting element 4342 passes through a mirror 4345. This configuration makes it easier to guide light to the display device from a certain angle. Therefore, the total reflected light can be obtained efficiently.

[0243] FIG. 19(E) shows a configuration having a stack of layers 4003 and 4004 on a composite layer 4009. One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other is an inorganic The composite layer 40 may be formed of a film, an organic resin coating film, or a film. The resin portion of the layer 4009 is made of a material having a refractive index larger than that of the layer 4004. The layer 4002 is made of a material having a refractive index larger than that of the layer 4003 .

[0244] A first interface is formed between composite layer 4009 and layer 4004, and layer 4004 and layer 400 A second interface is formed between the first interface and the second interface. The light that passes through can be totally reflected at the second interface and returned to the composite layer 4009. Therefore, the light emitted by the light emitting element 4342 can be utilized efficiently.

[0245] The configurations in FIG. 18(B) and FIG. 19(A) to (E) can be combined with each other. can be done.

[0246] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0247] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0248] The display device of one embodiment of the present invention includes a bottom-gate transistor or a top-gate transistor. The present invention can be fabricated using various types of transistors, such as transistors. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0249] [Bottom-gate transistor] FIG. 20(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 20(A1) is a cross-sectional view of a transistor 810 in the channel length direction. The transistor 810 is formed on the substrate 771. An electrode 746 is provided with an insulating layer 772 interposed therebetween. The semiconductor layer 742 is an insulating layer that can function as a gate electrode. It can function as a gate insulating layer.

[0250] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. 42, and has an electrode 744a and an electrode 744b on the insulating layer 726. Electrode 744a can function as either a source electrode or a drain electrode. A part of the electrode 744a and the electrode 744b can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0251] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs during the formation of the electrode 744a and the electrode 744b is suppressed. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor having good electrical characteristics can be realized.

[0252] The transistor 810 includes an insulating layer 741 and an electrode 744a. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0253] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742 to fill the oxygen vacancies. Examples of materials that can produce this include tungsten and titanium. do.

[0254] The source region and the drain region are formed in the semiconductor layer 742, whereby the electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0255] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a between the semiconductor layer 742 and the electrode 744b, and between the semiconductor layer 742 and the electrode 744b, It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0256] The insulating layer 729 has a function of preventing or reducing diffusion of impurities from the outside into the transistor. It is preferable to form the insulating layer 729 using a material having the above structure. It is also possible.

[0257] The transistor 811 shown in FIG. 20A2 has an insulating layer 729 over which a back gate electrode is formed. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. It can be formed from the same materials and by the same method as 746.

[0258] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the potential of the back electrode, the transistor threshold The voltage can be varied.

[0259] Both the electrode 746 and the electrode 723 can function as a gate electrode. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate insulating layer. This is also fine.

[0260] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as the "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0261] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, 6 and the electrode 723 are set to the same potential, the region in which carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility increases.

[0262] Therefore, the transistor 811 is a transistor having a large on-current relative to its occupancy area. That is, the area occupied by the transistor 811 is set to a desired on-current. According to one aspect of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0263] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0264] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This can prevent light from entering the semiconductor layer from the side. This prevents the semiconductor layer from being deteriorated by light. This can prevent degradation of electrical characteristics, such as a shift in the threshold voltage of a transistor. .

[0265] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0266] FIG. 20B1 shows a channel protection transistor 82 having a different structure from that shown in FIG. 20A1. 8 is a cross-sectional view of the transistor 820 in the channel length direction. It has a similar structure, but differs in that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, an opening is formed by selectively removing a part of the insulating layer 741 that overlaps the semiconductor layer 742. In the portion, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 741 overlapping with the semiconductor layer 42, The insulating layer 741 is electrically connected to the electrode 744b. The overlapping region can function as a channel protection layer.

[0267] The transistor 821 shown in FIG. 20B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0268] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. This can prevent the layer 742 from being exposed. Therefore, when the electrodes 744a and 744b are formed, In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0269] In addition, the transistors 820 and 821 are the same as the transistors 810 and The distance between the electrodes 744a and 746 and the distance between the electrodes 744b and 746 are smaller than the distance between the electrodes 744a and 746 and the distance between the electrodes 744b and 746. Therefore, the distance between the electrodes 744a and 746 is increased. In addition, the parasitic capacitance between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0270] FIG. 20(C1) shows a channel-etched type transistor, which is one of the bottom-gate type transistors. 1 is a cross-sectional view in the channel length direction of a transistor 825. The transistor 825 has an insulating layer 7 The electrodes 744a and 744b are formed without using the electrode 41. In addition, a part of the semiconductor layer 742 that is exposed during the formation of the electrode 744b may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0271] A transistor 826 shown in FIG. 20C2 has an insulating layer 729 over which a back gate electrode is formed. It differs from transistor 825 in that it has a functioning electrode 723 .

[0272] In FIG. 21(A1) to (C2), transistors 810, 811, 820, 821, 825, 826 are cross-sectional views in the channel width direction.

[0273] In the structures shown in FIGS. 21(B2) and (C2), the gate electrode and the back gate electrode are connected. The gate electrode and the back gate electrode have the same potential. The gate electrode is sandwiched between the gate electrode and the back gate electrode.

[0274] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is 726, 741, 728, and 729 are sandwiched between the gate electrode or back gate electrode. This is a structure.

[0275] With this structure, the semiconductor layer 742 included in the transistor is The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0276] Like the transistor 821 or the transistor 826, the gate electrode and the back gate The electric field of the electrode electrically surrounds the semiconductor layer 742 in which the channel formation region is to be formed. The device structure of a transistor is called the Surrounded channel (S-channel el) structure.

[0277] By adopting an S-channel structure, either one of the gate electrode and the back gate electrode By both, an electric field is effectively applied to the semiconductor layer 742 to induce a channel. This improves the current drive capability of the transistor and makes it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, it is possible to miniaturize transistors. In addition, the S-channel structure makes it possible to mechanically Strength can be increased.

[0278] [Top-gate transistor] The transistor 842 illustrated in FIG. 22A1 is a top-gate transistor. The electrode 744a and the electrode 744b are formed on the insulating layer 728 and the insulating layer 729. The insulating layer 742 is electrically connected to the semiconductor layer 742 in the opening.

[0279] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer By introducing impurities into the semiconductor layer 742 using the mask 726, the semiconductor layer 742 It is possible to form an impurity region in a self-aligned manner. The sintered body 842 has an area where the insulating layer 726 extends beyond the edge of the electrode 746. The impurity concentration in the region of the layer 742 into which the impurity is introduced through the insulating layer 726 is The semiconductor layer 742 has an electrode 746. A LDD (Lightly Doped Drain) region is formed in the area where it does not overlap with the do.

[0280] The transistor 843 shown in FIG. 22A2 has an electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0281] In addition, the transistor 844 shown in FIG. 22B1 and the transistor As in the case of the electrode 845, the insulating layer 726 may be entirely removed from areas that do not overlap with the electrode 746. In addition, the transistor 846 shown in FIG. 22C1 and the transistor shown in FIG. Insulating layer 726 may be left behind, as may layer 847.

[0282] After forming the electrode 746, the transistors 843 to 847 are also By introducing impurities into the semiconductor layer 742 using the mask, According to one aspect of the present invention, the impurity region can be formed in a self-aligned manner. According to one embodiment of the present invention, a highly integrated transistor can be realized. Therefore, a semiconductor device having a high resistance can be realized.

[0283] In FIG. 23(A1) to (C2), transistors 842, 843, 844, 845, 846, 847 are cross-sectional views in the channel width direction.

[0284] The transistors 843, 845, and 847 are The S-channel structure described above is the same as that described above. However, the present invention is not limited to this. 3. The transistors 845 and 847 are not of S-channel structure. This is also fine.

[0285] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0286] (Embodiment 4) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproducing device equipped with a recording medium, a mobile phone, Game consoles, portable data terminals, e-book terminals, video cameras, digital cameras, etc. Camera, goggle-type display (head-mounted display), navigation system systems, audio playback devices (car audio, digital audio players, etc.), copiers, Fax machines, printers, multi-function printers, automated teller machines (ATMs), vending machines Specific examples of these electronic devices are shown in Figure 24.

[0287] FIG. 24A shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed. The following display can be made.

[0288] FIG. 24B shows a digital signage with a large display unit 922. The display device of one embodiment of the present invention is used for the display portion 922. , various images can be displayed.

[0289] FIG. 24C shows an example of a mobile phone. The mobile phone has a housing 951, a display unit 952, an operation button 953, The mobile phone has an external connection terminal 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone has a touch sensor on the display unit 952. All operations, such as touching the display 952 with a finger or a stylus, can be performed. In addition, the housing 901 and the display unit 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, It is possible to display various images.

[0290] FIG. 24D shows a video camera, which includes a first housing 901, a second housing 902, a display unit 903, The operation key 904, the lens 905, the connection part 906, the speaker 907, etc. The lens 905 and the display unit 904 are provided in the first housing 901, and the display unit 903 is provided in the second housing 902. By using the display device of one embodiment of the present invention for the display portion 903, It is possible to display a suitable image.

[0291] FIG. 24E shows a television set, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 9 The display unit 973 has a touch sensor 975, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using this, various images can be displayed.

[0292] FIG. 24F shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, and a camera. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed. The following display can be made.

[0293] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. [Explanation of symbols]

[0294] 10: pixel, 11: circuit, 12: source driver, 13: gate driver, 14: circuit, 101: transistor, 102: transistor, 103: transistor, 104: capacitance element 105: capacitance element; 106: capacitance element; 107: transistor; 108: transistor 109: transistor, 110: circuit block, 111: transistor, 112: transistor, 113: capacitance element, 114: EL element, 115: transistor, 116: capacitance 117: liquid crystal element; 118: transistor; 119: transistor; 120: circuit route, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125: wiring, 126 : wiring, 127: wiring, 128: wiring, 129: wiring, 130: wiring, 131: wiring, 1 32: Wiring, 133: Wiring, 134: Wiring, 135: Wiring, 215: Display, 221a: Scanning line driving circuit, 231a: signal line driving circuit, 232a: signal line driving circuit, 241a: common Wiring drive circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 74 1: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 77 1: substrate, 772: insulating layer, 810: transistor, 811: transistor, 820: transistor Transistor, 821: transistor, 825: transistor, 826: transistor, 8 42: transistor, 843: transistor, 844: transistor, 845: transistor sta, 846: transistor, 847: transistor, 901: housing, 902: housing, 9 03: Display unit, 904: Operation keys, 905: Lens, 906: Connection unit, 907: Speaker ,911: housing, 912: display unit, 913: speaker, 919: camera, 921: pillar, 9 22: display unit, 951: housing, 952: display unit, 953: operation button, 954: external connection Terminal, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: 963: microphone, 965: display, 966: operation keys, 967: speaker 968: Zoom lever, 969: Lens, 971: Housing, 973: Display, 974: Operation keys, 975: speaker, 976: communication connection terminal, 977: optical sensor, 1000: Capacitive element, 4001: substrate, 4003: layer, 4004: layer, 4005: sealing material, 400 6: substrate, 4008: liquid crystal layer, 4009: composite layer, 4010: transistor, 4011: Transistor, 4013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4016: Light diffusion Disordered liquid crystal element, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020 : Capacitor element, 4021: Electrode, 4022: Transistor, 4023: Transistor, 40 30: electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: Insulating layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: coloring layer, 4132: light-shielding layer, 4133: insulating layer, 4200: input device, 421 0: touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring , 4239: Wiring, 4263: Board, 4272b: FPC, 4273b: IC, 4340 a: backlight unit, 4340b: backlight unit, 4341: light guide plate, 4 342: Light emitting element, 4344: Lens, 4345: Mirror, 4347: Printed circuit board, 4 348: Reflection layer, 4352: Diffusion plate, 4510: Partition wall, 4511: Light-emitting layer, 4513: Light-emitting layer Optical elements, 4514: Filling material

Claims

[Claim 1] a source driver, a first circuit, a first pixel, and a second pixel; the first pixel is electrically connected to the first circuit via a first wiring, the second pixel is electrically connected to the first circuit via a second wiring, the first circuit is electrically connected to the source driver; the first circuit has a function of controlling conduction or non-conduction between the source driver and the first pixel; the first circuit has a function of controlling conduction or non-conduction between the source driver and the second pixel; the first pixel has a function of acquiring data supplied from the source driver twice via the first wiring and adding the acquired data, the first pixel writes the data when the source driver is in a conductive state with the first pixel via the first circuit and the first wiring; The display device writes the data held in the first wiring to the first pixel when the source driver and the first pixel are in a non-conductive state.

Images