Prefetch kill and revival in instruction cache

Abstract

To provide a method for efficiently performing cache control relating to prefetch.SOLUTION: In a processor (100) including a hierarchical cache subsystem, a memory controller subsystem (101) speculatively determines a hit or miss condition of a virtual address in a first memory cache (130) and speculatively translates a virtual address to a physical address; associated with the hit or miss condition and the physical address, configures a status to a valid state; responsive to receipt of a first indication from a CPU core (102) that no program instructions associated with the virtual address are needed, reconfigures the status to an invalid state; and responsive to receipt of a second indication from the CPU core (102) that a program instruction associated with the virtual address is needed, reconfigures the status back to a valid state.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Some memory systems include multi-level cache systems. When a request for a particular memory address is received from a processor core by the memory controller, the memory controller determines whether data associated with that memory address is present in a first level cache (L1). If the data is present in the L1 cache, the data is returned from the L1 cache. If the data associated with the memory address is not present in the L1 cache, the memory controller accesses a second level cache (L2). The L2 is larger than the L1 cache and may therefore hold more data. If the data is present in the L2 cache, the data is returned from the L2 cache to the processor core and a copy is also kept in the L1 cache in case the same data is requested again. Additional memory level hierarchies are possible. Summary of the Invention

[0002] In one example, a system includes a processor, the processor including a CPU core, a first and a second memory cache, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss status of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. In association with the hit or miss status and the physical address, the memory controller subsystem configures a status to a valid state. In response to receiving a first indication from the CPU core that a program instruction associated with the virtual address is not needed, the memory controller subsystem reconfigures the status to an invalid state, and in response to receiving a second indication from the CPU core that a program instruction associated with the first virtual address is needed, the memory controller subsystem reconfigures the status to a valid state without additional accesses to the TAGRAM or address translation logic. [Brief description of the drawings]

[0003] [Figure 1] 1 illustrates a processor according to an example.

[0004] [Diagram 2] 1 illustrates the promotion of an L1 memory cache access to a full L2 cache line access, according to an example.

[0005] [Diagram 3] 1 is a flow chart illustrating performance improvement according to an example.

[0006] [Figure 4] 11 is another flowchart illustrating another performance improvement according to an example.

[0007] [Diagram 5] 2 illustrates a system including the processor of FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] 1 illustrates an example of a processor 100 including a hierarchical cache subsystem. The processor 100 in this example includes a central processing unit (CPU) core 102, a memory controller subsystem 101, an L1 data cache (L1D) 115, an L1 program cache (L1P) 130, and an L2 memory cache 155. In this example, the memory controller subsystem 101 includes a data memory controller (DMC) 110, a program memory controller (PMC) 120, and a unified memory controller (UMC) 150. In this example, at the L1 cache level, data and program instructions are split into separate caches. Instructions executed by the CPU core 102 are stored in the L1P 130 and then provided to the CPU core 102 for execution. Meanwhile, data is stored in the L1D 115. CPU core 102 can read data from and write data to L1D 115, and has read access to L1P 130 (but no write access to L1P 130). L2 memory cache 155 can store both data and program instructions.

[0009] While the sizes of L1D 115, L1P 130, and L2 memory cache 155 may vary depending on the implementation, in one example, the size of L2 memory cache 155 is larger than the size of either L1D 115 or L1P 130. For example, the size of L1D 115 may be 32 kilobytes and the size of L1P may also be 32 kilobytes, while the size of the L2 memory cache may be between 64 kilobytes and 4 MB. Also, the cache line size of L1D 115 is the same as the cache line size of L2 memory cache 155 (e.g., 128), while the cache line size of L1P 130 is smaller (e.g., 64 bytes).

[0010] When data is needed by the CPU core 102, the DMC 110 receives an access request from the CPU core 102 for the target data. The access request may include an address (e.g., a virtual address) from the CPU core 102. The DMC 110 determines whether the target data resides in the L1D 115. If the data resides in the L1D 115, the data is returned to the CPU core 102. However, if the data requested by the CPU core 102 does not reside in the L1D 115, the DMC 110 provides an access request to the UMC 150. The access request may include a physical address generated by the DMC 110 based on a virtual address (VA) provided by the CPU core 102. The UMC 150 determines whether the physical address provided by the DMC 110 resides in the L2 memory cache 155. If the data resides in the L2 memory cache 155, the data is returned from the L2 memory cache 155 to the CPU core 102 and a copy is stored in the L1D 115. Additional hierarchies of cache subsystems may also exist. For example, the L3 memory cache or system memory may be available to be accessed, so if data requested by CPU core 102 is not present in either L1D 115 or L2 memory cache 155, the data may be accessed in an additional cache level.

[0011] When the CPU core 102 needs additional instructions to execute relative to a program instruction, the CPU core 102 provides a VA 103 to the PMC 120. The PMC responds to the VA 103 provided by the CPU core 102 by initiating a workflow to return a prefetch packet 105 of the program instruction to the CPU 102 for execution. The prefetch size packet varies by implementation, but in one example, the size of the prefetch packet is equal to the size of a cache line of the L1P 130. If the L1P cache line size is, for example, 64 bytes, the prefetch packet returned to the CPU core 102 may also include 64 bytes of the program instruction.

[0012] The CPU core 102 also provides a prefetch count 104 to the PMC 120. In some implementations, the prefetch count 104 is provided to the PMC 120 after the CPU core 102 provides the VA 103. The prefetch count 104 indicates the number of prefetch units of program instructions following the prefetch unit beginning with the VA 103. For example, the CPU core 102 may provide a VA of 200h. This VA is associated with a 64-byte prefetch unit beginning with virtual address 200h. If the CPU core 102 wants the memory controller subsystem 101 to send additional instructions for execution following the prefetch unit associated with virtual address 200h, the CPU core 102 presents a prefetch count having a value greater than 0. A prefetch count of 0 means that the CPU core 102 does not need any more prefetch units. For example, a prefetch count of 6 would cause CPU core 102 to request that an additional 6 prefetch units' worth of instructions be retrieved and sent back to CPU core 102 for execution. The returned prefetch units are shown in FIG. 1 as prefetch packets 105.

[0013] Continuing with the example of FIG. 1, PMC 120 includes TAGRAM 121, address translator 122, and registers 123. TAGRAM 121 contains a list of virtual addresses whose contents (program instructions) are cached in L1P 130. Address translator 122 translates the virtual addresses to physical addresses (PAs). In one example, address translator 122 generates a physical address directly from a virtual address. For example, the lower 12 bits of the VA may be used as the least significant 12 bits of the PA, and the most significant bits of the PA (above the lower 12 bits) are generated based on a set of tables configured in main memory prior to program execution. In this example, L2 memory cache 155 is addressable using physical addresses rather than virtual addresses. Register 123 stores a hit / miss indicator 124 from the TAGRAM 121 lookup, a physical address 125 generated by address converter 122, and a valid bit 126 (also referred to herein as a status bit) that indicates whether the corresponding hit / miss indicator 124 and physical address 125 are valid or invalid.

[0014] Upon receiving a VA 103 from the CPU 102, the PMC 120 performs a TAGRAM 121 lookup to determine whether the L1P 130 contains the program instruction associated with that virtual address. The result of the TAGRAM lookup is a hit or miss indicator 124. A hit means that the VA is present in the L1P 130, and a miss means that the VA is not present in the L1P 130. In the case of an L1P 130 hit, the target prefetch unit is retrieved from the L1P 130 by the PMC 120 and returned to the CPU core 102 as a prefetch packet 105.

[0015] In the event of an L1P 130 miss, the PA (generated based on the VA) is provided by the PMC 120 to the UMC 150, as shown at 142. A byte count 140 is also provided from the PMC 120 to the UMC 150. The byte count indicates the number of bytes in the L2 memory cache 155 to be retrieved (if any) beginning with the PA 142. In one example, the byte count 140 is a multi-bit signal that encodes the number of bytes desired from the L2 memory cache 155. In one example, the line size of the L2 memory cache is 128 bytes, with each line divided into an upper half (64 bytes) and a lower half (64 bytes). Thus, the byte count 140 may encode the number 64 (if only the upper or lower 64 bytes are needed from a given L2 memory cache line) or 128 (if the entire L2 memory cache line is needed). In another example, the byte count may be a single bit signal where one state (e.g., 1) implicitly encodes an entire L2 memory cache line and another state (e.g., 0) implicitly encodes half an L2 memory cache line.

[0016] UMC 150 also includes TAGRAM 152. PA 142 received by UMC 150 from PMC 120 is used to perform a lookup into TAGRAM 152 to determine whether the target PA is a hit or a miss in L2 memory cache 155. If there is a hit in L2 memory cache 155, the target information, which may be a half of a cache line or an entire cache line depending on byte count 140, is returned to CPU core 102 and a copy is stored in L1P 130 from where it is provided to CPU 102 with the same program instruction the next time CPU core 102 attempts to fetch the same program instruction.

[0017] 1, CPU core 102 provides VA 103 and prefetch count 104 to PMC 120. PMC 120 initiates the workflow for retrieving prefetch packets from L1P 130 or L2 memory cache 155, as described above. Using prefetch count 104 and original VA 103, PMC 120 calculates additional virtual addresses and begins retrieving prefetch packets corresponding to those calculated VAs from L1P 130 or L2 memory cache 155. For example, if the prefetch count is 2 and VA 103 from CPU core 102 is 200h, PMC 120 calculates the next two VAs as 240h and 280h, rather than CPU core 102 providing each such VA to PMC 120.

[0018] 2 illustrates a specific example where optimizations result in improved performance of processor 100. As previously discussed, the line width of L2 memory cache 155 is greater than the line width of L1P. In one example, L1P is 64 bytes wide and L2 memory cache 155 has a line width of 128 bytes, as shown in FIG. 2. L2 memory cache 155 is organized as an upper half 220 and a lower half 225. UMC 150 may read an entire 128-byte cache line from L2 memory cache 155 or only one half of the L2 memory cache (upper half 220 or lower half 225).

[0019] A given VA, when present in L2 memory cache 155, may translate to a particular PA that maps to the lower half 225 or upper half 220 of a given line of the L2 memory cache. Based on the addressing scheme used to represent the VA and PA, PMC 120 may determine whether a given VA maps to the lower half 225 or upper half 220. For example, a particular bit (e.g., bit 6) in the VA may be used to determine whether the corresponding PA maps to the upper half or lower half of a line of the L2 memory cache. For example, bit 6 being 0 may indicate the lower half, and bit 6 being 1 may indicate the upper half.

[0020] Reference numeral 202 illustrates an example of a VA of 200h provided by CPU core 102 to PMC 120, with a corresponding prefetch count of 6. Reference numeral 210 illustrates that the list of VAs running through the cache pipeline described above includes 200h (received from CPU core 102) and the next six consecutive virtual addresses 240h, 280h, 2c0h, 300h, 340h, and 380h (calculated by PMC 120).

[0021] Each address from 200h through 380h is processed as described above. Any or all of the VAs may be misses in L1P 130. PMC 120 may coalesce two consecutive VAs that miss in L1P 130 into a single L2 cache line access attempt. Thus, if 200h and 240h both miss in L1P 130, and the physical address corresponding to 200h corresponds to the lower half 225 of a particular cache line in L2 memory cache 155, and the physical address corresponding to 240h corresponds to the upper half 225 of the same cache line in L2 memory cache, PMC 120 may issue a single PA 142 to UMC 150 with a byte count 140 that identifies the entire cache line from the L2 memory cache. Thus, two consecutive VA misses in L1P 130 may be promoted to one full-line L2 memory cache lookup.

[0022] If the last VA in the series of VAs initiated by the CPU core 102 (e.g., VA380h in the VA series 210) maps to the lower half 225 of the cache line of the L2 memory cache 155, the entire cache line of the L2 memory cache 155 is retrieved, according to the described example, even if only the lower half 225 was needed. The same reaction occurs if the CPU provides the VA 103 to the PMC 120 with a prefetch count of 0, which means that the CPU 102 only needed a single prefetch unit. There is very little, if any, additional overhead, time, or power consumption spent to retrieve the entire cache line and provide the entire cache line to the L1P 130. Because program instructions are often executed in linear order, it is generally more likely that the program instructions in the upper half 220 will be executed following the execution of the instructions in the lower half 225 anyway. Therefore, the next set of instructions is received at very little cost, and such instructions are more likely to be needed anyway.

[0023] 2 illustrates, via arrow 213, that VA380h maps to the lower half 225 of cache line 260 in L2 memory cache 155. PMC 120 determines this mapping, for example, via inspection of one or more bits of the VA or its corresponding physical address following translation by address translator 122. PMC 120 promotes the lookup process to the full cache line with UMC 150 by presenting the PA associated with VA380h along with a byte count 104 that identifies the entire cache line. The entire 128-byte cache line is then retrieved (if present in L2 memory cache 155) and written to L1P 130 in two separate 64-byte cache lines, as shown at 265.

[0024] However, if the last VA in the series of VAs (or if there is only one VA for a prefetch count of 0) maps to the top half 220 of a cache line in L2 memory cache 155, PMC 120 requests UMC 150 to look up in its TAGRAM 152 and return only the top half of the cache line to CPU core 102 and L1P 130. The next PA may be in the bottom half 225 of the next cache line in L2 memory cache 155, and additional time, overhead, and power may be consumed to speculatively retrieve the next cache line, without certainty that CPU core 102 will need to execute these instructions.

[0025] 3 shows an example of a flow chart 300 for the method described above. The operations may be performed in the order shown or in another order. Also, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0026] At 302, the method includes receiving, by memory controller subsystem 101, a request to access N prefetch units of program instructions. In one implementation, this operation is performed by CPU core 102, which provides an address and a count value to PMC 120. The address may be a virtual address or a physical address, and the count value may indicate the number of additional prefetch units required by CPU core 102.

[0027] At 304, an index value I is initialized to a value of one. This index value is used to determine when the last virtual address in a series of consecutive virtual addresses should be processed by PMC 120. At 306, the method determines whether prefetch unit I is a hit or a miss to L1P 130. This determination is made, in some instances, by determining whether the virtual address is present in the PMC's TAGRAM 121. Two outcomes are possible from determination 306: a hit or a miss.

[0028] If the virtual address is a hit to L1P 130, then at 308, the corresponding line of L1P 130 containing the desired prefetch unit is returned from L1P 130 and provided to CPU core 102 as a prefetch packet 105. Then, at 310, the index is incremented (I=I+1). If I has not yet reached N+1 (as determined in decision operation 312), the VA of the last one of the prefetch units has not yet been evaluated for a hit / miss decision, and control loops back to 306 to evaluate the next Ith prefetch unit for a hit or miss in L1P 130. When I reaches N+1, all N prefetch units have been evaluated and the corresponding program instructions have been provided to CPU core 102, and the process stops.

[0029] For a given Ith prefetch unit, if PMC 120 determines at 306 that there is a miss in L1P 130, then a determination is made at 314 as to whether I has reached a value of N. If I is not equal to N (indicating that the last VA in the series of VAs has not been reached), then at 316 the method includes memory controller subsystem 101 obtaining the program instruction from L2 memory cache 155 (if present therein, or if not, from a third level cache or system memory). The index value I is then incremented at 318 and control loops back to decision 306.

[0030] If I reaches N at 314 (indicating that the last VA in the series of VAs has been reached), the method includes determining, at 320, whether the VA of the Ith prefetch unit maps to the lower half or the upper half of a cache line in the L2 memory cache 155. An example of how this determination may be made is provided above. If the VA of the Ith prefetch unit maps to the upper half, the method includes, at 322, obtaining program instructions from only the upper half of a cache line in the L2 memory cache.

[0031] However, if the VA of the Ith prefetch unit maps to the lower half, the method includes, at 324, promoting the L2 memory cache access to a full cache line access and, at 326, obtaining the program instructions from the full cache line of the L2 memory cache.

[0032] 1, following presentation of VA 103 from CPU core 102 to PMC 120, as described above, CPU core 102 may also provide PMC 120 with a prefetch count 104. The prefetch count may be 0, meaning that CPU core 102 no longer requires instructions other than those contained in the prefetch unit beginning with VA 103. However, between receipt of VA 103 and the subsequent prefetch count, PMC 120 may be performing some work, as described below.

[0033] Upon receiving VA 103, PMC 120 performs a lookup in TAGRAM 121 to determine whether the first VA (provided by CPU core 102) is a hit or miss in L1P, and further performs a VA to PA translation using address translator 122. PMC 120 also calculates a second VA (the next consecutive VA following the VA provided by the CPU core) before receiving prefetch count 104. PMC 120 speculatively accesses TAGRAM 121, determines the hit / miss status of the second VA using address translator 122, and populates register 123 with hit / miss indication 124 and PA 125. Valid bit 126 in register 123 is set to a valid state, thereby allowing further processing of the second VA as described above (e.g., retrieving the corresponding cache line from L1P 130, if present, or from L2 memory cache 155, if necessary).

[0034] However, before further processing of the second VA occurs, it is possible that CPU core 102 may send a prefetch count of 0 to PMC 120, meaning that the CPU core does not require any prefetch units other than those beginning with the original VA 103. At this point, PMC 120 is provided with a prefetch count of 0, and therefore no prefetch units are required associated with the second VA. However, the PMC has also already determined the hit / miss status of the second VA and generated a corresponding PA. Both hit / miss indicator 124 and PA 125 are stored in register 123 by the time the 0 prefetch count is received by PMC 120. PMC 120 changes the status of valid bit 126 to indicate an invalid state, thereby precluding further processing of the second VA. This situation (valid bit set to an invalid state) is referred to as a "kill," and so PMC 120 kills the processing of the second VA.

[0035] However, in some cases, CPU core 102 may determine that, despite the previous termination, the prefetch unit associated with the second VA should in fact be retrieved from L1P 130 or L2 memory cache 155 as described above. For example, if CPU core 102 does not have further internal prediction information to inform the next requested instruction address, CPU core 102 informs PMC 120 that it should continue prefetching linearly starting from the last requested address. This situation may arise, for example, due to a misprediction of branch prediction logic in CPU core 102. CPU core 102 thus issues resume signal 106 to PMC 120. PMC 120 responds to the resume signal by returning valid bit 126 to a valid state, thereby enabling continued processing of the second VA through the memory subsystem pipeline as described above. In this manner, CPU 102 does not need to directly present the second VA to PMC 120. Instead, the PMC 120 may, for example, hold the second VA in a register 123 and also hold its hit / miss indicator 124, thereby avoiding the power consumption and time that would be expended to again determine the hit / miss status of the second VA and convert the second VA to a PA.

[0036] 4 shows an example of a flowchart 400 for initiating, terminating, and resuming a memory address lookup. The operations may be performed in the order shown or in another order. Also, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0037] At 402, the method includes receiving, by memory controller subsystem 101, a request for access at a first VA. In one implementation, the operation is performed by CPU core 102 providing the first VA to PMC 120. The method includes, at 404, determining whether the first VA is a hit or a miss at L1P 30. In one example, the operation is done by accessing TAGRAM 121 of the PMC to determine the hit / miss status of the first VA. The first VA is translated, at 406, to a first PA, for example, by using address translator 122.

[0038] At 408, the method includes calculating a second VA based on the first VA. The second VA may be calculated by incrementing the first VA by a value to generate an address of a byte that is 64 bytes following the byte associated with the first VA. The method includes determining, at 410, whether the second VA is a hit or a miss in the L1P 30. In one example, this operation is accomplished by accessing the TAGRAM 121 of the PMC to determine the hit / miss status of the second VA. The second VA is translated, at 412, to a second PA by using the address translator 122 as described above. At 414, the method includes updating a register (e.g., register 123) with the hit / miss indicator 124 and the second PA. Also, the valid bit 126 is configured to be in a valid state.

[0039] PMC 120 then receives the prefetch count at 416. If the prefetch count is then greater than zero at 418, then the program instructions from L1P 130 or L2 memory cache 155 (or additional levels) are retrieved as described above at 420. However, if the prefetch count is zero, then valid bit 126 is changed to an invalid state at 422. Thus, despite having provided PMC 120 with a prefetch count of zero, CPU core 102 may provide a resume indication to PMC 120 (424). PMC 120 returns valid bit 126 to a valid state at 426, and memory controller subsystem 101 then obtains (428) the program instructions associated with the second PA from L1P, L2 memory cache, etc., as appropriate.

[0040] 5 illustrates an exemplary use of the processor 100 described herein. In this example, the processor 100 is part of a system-on-chip (SoC) 500 that includes the processor 100 and one or more peripheral ports or devices. In this example, the peripherals include a universal asynchronous transmitter (UART) 502, a universal serial bus (USB) port 504, and an Ethernet controller 506. The SoC 500 may perform any of a variety of functions implemented, for example, by program instructions executed by the processor 100. Multiple processors 100 may be provided, and within a given processor 100, multiple CPU cores 102 may be included.

[0041] In this description, the term "couple" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. Also, in this description, "based on" means "based at least in part on." Thus, if X is based on Y, X may be a function of Y and any number of other factors.

[0042] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. An apparatus comprising: Central Processing Unit (CPU) core, a first memory cache for storing instructions for execution by the CPU core; a second cache for storing instructions for execution by the CPU core, the second cache accessible in response to a miss in the first memory cache; and a memory controller subsystem coupled to said CPU core and to said first and second memory caches; Including, the memory controller subsystem: determining whether a first virtual address received from the CPU core is a miss or a hit in the first memory cache; generating a second virtual address based on the first virtual address; determining a miss or a hit in the first memory cache for the second virtual address; translating the second virtual address into a physical address; setting a status bit associated with a miss or hit determination of the physical address and the second virtual address to a valid state; changing said status bit to an invalid state in response to receiving a count value of zero from said CPU core; returning the status bit to a valid state in response to receiving a resume indication from the CPU core; The apparatus is configured so as to

2. 2. The apparatus of claim 1, the memory controller subsystem is configured to retrieve program instructions from a second memory cache using the physical address translated from the second virtual address.

3. 2. The apparatus of claim 1, The apparatus, wherein receiving the count value occurs after translating the second virtual address into the physical address.

4. 2. The apparatus of claim 1, The apparatus, wherein receiving the count value from the CPU core occurs before receiving the resume indication from the CPU core.

5. 2. The apparatus of claim 1, The apparatus further comprises a register in which the physical address and the status bits are stored.

6. 6. The apparatus of claim 5, An indication of a hit or miss of the second virtual address in the first memory cache is stored in the register along with the physical address and the status bits.

7. 2. The apparatus of claim 1, The apparatus, wherein the first memory cache is for storing program instructions rather than data.

8. An apparatus comprising: Central Processing Unit (CPU) core, a first memory cache for storing instructions for execution by said CPU core; a second memory cache for storing instructions for execution by the CPU core, the second memory cache for retrieving instructions in response to a miss in the first memory cache; a memory controller subsystem coupled to the CPU core and to first and second memory caches; Including, the memory controller subsystem: speculatively determining a hit or miss status of a first virtual address in the first memory cache; speculatively translating the first virtual address into a physical address; setting a status to a valid state in association with the hit or miss condition and the physical address; resetting the status to an invalid state in response to receiving a first indication from the CPU core that the program instructions associated with the first virtual address are not needed; resetting the status to a valid state in response to receiving a second indication from the CPU core that a program instruction associated with the first virtual address is required. The apparatus is configured so as to

9. 9. The apparatus of claim 8, the memory controller subsystem is configured to speculatively generate the first virtual address from a second virtual address sent from the CPU core to the memory controller subsystem.

10. 9. The apparatus of claim 8, 11. The apparatus of claim 10, wherein the first indication from the CPU core that a program instruction associated with the first virtual address is not needed comprises a count value, the count value having a value of zero.

11. 9. The apparatus of claim 8, the second indication from the CPU core that a program instruction associated with the first virtual address is required comprises a signal instructing the memory controller subsystem to continue retrieving program instructions beginning at the first virtual address.

12. 12. The apparatus of claim 11, the memory controller subsystem is configured, upon receiving the second indication, to continue retrieving program instructions beginning at the first virtual address without again determining the hit or miss status of the first virtual address in the first memory cache.

13. 13. The apparatus of claim 12, the memory controller subsystem is configured, upon receiving the second indication, to continue retrieving program instructions beginning at the first virtual address without translating the first virtual address back to the physical address.

14. 9. The apparatus of claim 8, the CPU core is configured to provide the second indication without providing the first virtual address to the memory controller subsystem.

15. 9. The apparatus of claim 8, 20. The apparatus of claim 19, wherein receiving the first indication occurs after speculatively determining the hit or miss condition and speculatively translating the first virtual address into the physical address.

16. A system on chip (SoC), comprising: Input / output devices, and a processor coupled to the input / output device; Including, The processor, a central processing unit (CPU) core, a first memory cache for storing instructions for execution by the CPU core, a second memory cache, and a memory controller subsystem coupled to the CPU core and the first and second memory caches, the memory controller subsystem comprising: speculatively determining a hit or miss status of a first virtual address in the first memory cache; speculatively translating the first virtual address into a physical address; setting a status to a valid state in association with the hit or miss condition and the physical address; resetting the status to an invalid state in response to receiving a first indication from the CPU core that the program instructions associated with the first virtual address are not needed; resetting the status to a valid state in response to receiving a second indication from the CPU core that a program instruction associated with the first virtual address is required. The SoC is configured as follows.

17. 17. The SoC of claim 16, The memory controller subsystem is configured to speculatively generate the first virtual address from a second virtual address sent from the CPU core to the memory controller subsystem.

18. 17. The SoC of claim 16, The SoC, wherein the first indication from the CPU core that a program instruction associated with the first virtual address is not needed comprises a count value, the count value having a value of zero.

19. 17. The SoC of claim 16, the CPU core is configured to provide the second indication without providing the first virtual address to the memory controller subsystem.

20. 17. The SoC of claim 16, the memory controller subsystem is configured, upon receiving the second indication, to continue retrieving program instructions beginning at the first virtual address without again determining the hit or miss status of the first virtual address in the first memory cache and without again translating the first virtual address to the physical address.

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