Imaging device

Abstract

To provide an imaging device that is integrated three-dimensionally.SOLUTION: An imaging device includes a first layer including a first transistor containing metal oxide in a channel formation region, a first insulating layer, and a second insulating layer, and a second layer including a photodiode. With a conductor penetrating the first insulating layer and the second insulating layer, a conductive layer in contact with the metal oxide and one of a cathode and an anode of the photodiode are in electric connection.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Oxide semiconductors have been attracting attention as a semiconductor material that can be used in transistors. Transistors are made using zinc oxide or In-Ga-Zn oxide semiconductors as the oxide semiconductor. Techniques for producing such a capacitor have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, an imaging device in which a transistor including an oxide semiconductor is used as part of a pixel circuit is It is disclosed in patent document 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0007] In semiconductor integrated circuits, while there is a demand for higher density and capacity, there is also a demand for miniaturization. The shift from single-chip integration to three-dimensional integration is underway. Although this may lead to a rough design, it allows for greater freedom in terms of materials and design rules for each layer, making it ideal for It is possible to fabricate high-performance semiconductor integrated circuits that would be difficult to fabricate through multi-dimensional integration.

[0008] The pixel circuit of the imaging device includes a photoelectric conversion element and a transistor for controlling the photoelectric conversion element. The photoelectric conversion element is required to have high light sensitivity, and the transistor has an off-current The photoelectric conversion element and the transistor are required to have low noise characteristics. By using a structure that efficiently integrates the components and a manufacturing process that uses materials suitable for each component, It is possible to fabricate a functional imaging element.

[0009] For example, photodiodes that use a silicon substrate as a photoelectric conversion layer have high light sensitivity and are used in imaging devices. However, transistors formed on the same silicon substrate have a relatively large off-state current. The company had a problem.

[0010] Therefore, an object of one aspect of the present invention is to provide a three-dimensionally integrated imaging device. Alternatively, a photodiode using a silicon substrate and a photodiode using an oxide semiconductor may be used. Another object of the present invention is to provide an imaging device having a transistor having a noise Another object of the present invention is to provide an imaging device capable of capturing an image with less noise. It is one of the objects of the present invention to provide an imaging device having a high resolution. It is one of the objects to provide an imaging device that can be used in a wide temperature range. One of the objects of the present invention is to provide a highly reliable imaging device. Another object of the present invention is to provide a novel imaging device and the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention includes a first layer and a second layer, the first layer being in a channel forming region. A first transistor having a metal oxide, a first insulating layer, and a second insulating layer; The first transistor is provided between a first insulating layer and a second insulating layer. The photodiode includes a first conductive layer in contact with a metal oxide, and a second conductive layer includes a photodiode. The first conductive layer and one of the cathode or anode of the photodiode are connected to a first insulating layer. and an imaging device electrically connected via a conductor penetrating the second insulating layer.

[0013] In the above aspect, the photodiode may be provided on a single crystal silicon substrate. good.

[0014] In the above-mentioned embodiment, the third layer is provided, and the third layer has silicon in a channel forming region. a second transistor having a first insulating layer, a third insulating layer, and a fourth insulating layer; the first transistor and the second transistor are arranged such that upper surfaces of the gates face each other, A second conductive layer is provided having a region buried in the third insulating layer, and a second transistor is formed. The source, drain or gate of the transistor and the second conductive layer are connected to a conductor that penetrates the fourth insulating layer. and a third photodiode is electrically connected to the single crystal silicon substrate on the light receiving surface side of the photodiode through the third photodiode. The second conductive layer and the third conductive layer are formed on the first insulating layer, the second insulating layer, the third insulating layer, and the third insulating layer. The electrical connection may be made via a conductor penetrating the single crystal silicon substrate.

[0015] In the above embodiment, the first conductive layer and the cathode or anode of the photodiode The first insulating layer is electrically connected to the second insulating layer through a conductor that penetrates the first insulating layer, the metal oxide, and the second insulating layer. The electrodes may be electrically connected.

[0016] In the above aspect, the first layer includes a first transistor, a second transistor, and a third transistor, a fourth transistor, a first wiring, and a second wiring; The first transistor is provided in the pixel circuit and the second transistor is provided in the row driver. The third transistor is provided in the column driver, and the fourth transistor is an analog switch. The second to fourth transistors may have a metal oxide in a channel formation region. good.

[0017] In the above-mentioned embodiment, the A / D converter is provided, and the analog switch is connected to the first wiring. The analog switch is electrically connected to the second wiring, and the first wiring is the first wiring is electrically connected to the pixel circuit, and the second wiring is electrically connected to the A / D converter; Even if an A / D converter has a transistor that uses silicon for the channel formation region, good.

[0018] In the above embodiment, the metal oxide is a mixture of In, Zn, and M (M is Al, Ga, Y, or may have Sn).

[0019] In addition, a module including the imaging device according to one embodiment of the present invention and a lens is also an embodiment of the present invention. be.

[0020] Further, an electronic device including the imaging device according to one embodiment of the present invention and a display device according to one embodiment of the present invention is also an embodiment of the present invention. be. Effect of the Invention

[0021] By using one embodiment of the present invention, a three-dimensionally integrated imaging device can be provided. Alternatively, a photodiode using a silicon substrate and a transistor using an oxide semiconductor Alternatively, it is possible to provide an imaging device having a low noise level. Alternatively, it is possible to provide an imaging device having a high resolution. Alternatively, an imaging device with a high aperture ratio can be provided. It is possible to provide an imaging device that can be used in a wide range of imaging angles. Alternatively, a novel imaging device or the like can be provided.

[0022] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0023] [Figure 1] 1A and 1B are a diagram and a circuit diagram illustrating a pixel of an imaging device. [Diagram 2] FIG. 2 is a diagram illustrating a pixel circuit. [Diagram 3] FIG. 1 shows the 1 / f noise characteristics of an OS transistor. [Figure 4] FIG. 2 illustrates the structure of a photoelectric conversion element. [Diagram 5] 1A and 1B are diagrams illustrating a connection structure between a photoelectric conversion element and a transistor. [Figure 6] 1A and 1B are diagrams illustrating a connection structure between a photoelectric conversion element and a transistor. [Figure 7] 1A and 1B are diagrams illustrating a connection structure between a photoelectric conversion element and a transistor. [Figure 8] 2A and 2B are diagrams illustrating pixels of an imaging device. [Figure 9] 2A and 2B are diagrams illustrating pixels of an imaging device. [Figure 10] FIG. 2 is a diagram illustrating peripheral circuits of the imaging apparatus. [Figure 11] 1A and 1B are a block diagram of an image sensor, a block diagram of an A / D converter, and a diagram showing the connection between the image sensor and the A / D converter. [Figure 12] FIG. 2 is a diagram showing a configuration of a shift register. [Figure 13] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 14] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 15]FIG. 2 is a diagram illustrating a pixel circuit. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 19] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 23] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 24] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 30] FIG. 1 is a top view illustrating a transistor. [Diagram 31] 1A and 1B are diagrams illustrating the range of atomic ratios of oxide semiconductors. [Diagram 32] A diagram explaining the InMZnO4 crystal. [Diagram 33] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Diagram 34] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Diagram 35]Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Diagram 36] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 37] Cross-sectional TEM image of a-like OS. [Figure 38] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 39] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 40] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 41] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0025] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. and the ordinal numbers used to identify an aspect of the invention may not match.

[0026] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0027] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0028] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0029] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0030] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.) voltage sources, current sources, switching circuits, amplifier circuits (which output large signal amplitudes or current amounts, etc.) (common circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal One or more circuits (generator, memory, control circuit, etc.) can be connected between X and Y. For example, even if there is another circuit between X and Y, the output from X is If a signal is transmitted to Y, then X and Y are said to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected, and cases where X and Y are functionally connected. and Y are electrically connected.

[0031] In addition, if it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., there is another element or circuit between X and Y), When X and Y are functionally connected (i.e., when X and Y are (X and Y are connected functionally with another circuit between them) and (X and Y are connected directly (That is, when X and Y are connected without any other element or circuit between them.) ) is considered to be disclosed in the present specification. If it is explicitly stated, it is simply stated as connected. The same contents as those in the above case are deemed to be disclosed in the present specification and the like.

[0032] For example, if the source (or the first terminal, etc.) of the transistor is connected to the ), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through (or without) Z2, or the transistor The source (or first terminal, etc.) of Z1 is directly connected to a part of Z1 and another part of Z1. is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to In the case where a part of Z1 is directly connected to Y and another part of Z2 is directly connected to Y, It can be expressed as follows.

[0033] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., of the transistor are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. "The source of the transistor is electrically connected to the (or the first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor, The transistor's drain (or second terminal, etc.), and Y are electrically connected in that order. "X is connected to the source ( or the first terminal, etc.) and the drain (or the second terminal, etc.) X is the source (or first terminal, etc.) of the transistor, and The second terminal (or terminal 2, etc.), Y, is provided in this connection order. Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal.

[0034] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor" ) is electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second The first connection path is a path via Z1, and the second connection path is a path between the The drain (or second terminal, etc.) of the transistor is connected to the Y, the third connection path does not have the second connection path, and The third connection path is a path via Z2." or " The source (or first terminal, etc.) of the transistor is connected to the , electrically connected to X via Z1, and the first connection path has a second connection path the second connection path has a connection path passing through a transistor, The drain (or second terminal, etc.) of and the third connection path does not include the second connection path. "The source (or first terminal) of the transistor is etc.) is electrically connected to X through Z1 by at least a first electrical path; The first electrical path does not have a second electrical path, and the second electrical path is The source (or first terminal, etc.) of a transistor is connected to the drain (or third terminal, etc.) of a transistor. 2) and the drain (or second terminal, etc.) of the transistor. ) is electrically connected to Y through Z2 by at least a third electrical path, The third electrical path does not have a fourth electrical path, and the fourth electrical path is a The drain (or second terminal, etc.) of a transistor is connected to the source (or first terminal, etc.) of a transistor. The electrical path to the terminal of the By using the current method, the connection paths in the circuit configuration are defined, and the transistor Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of The technical scope can be determined based on the above.

[0035] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0036] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0037] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0038] Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. The size is determined by the distance between the ground and the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit potential. In such cases, positive and negative potentials are defined based on that potential. This results in:

[0039] (Embodiment 1) In this embodiment, a structure of an imaging device which is one embodiment of the present invention will be described.

[0040] One embodiment of the present invention is an imaging device including a photoelectric conversion element and a transistor. The elements and transistors are integrated in a three-dimensional structure, and the appropriate materials are used for each. By carrying out the manufacturing process in this way, it is possible to manufacture an image sensor with higher performance.

[0041] FIG. 1A is a cross-sectional view of a pixel 20 included in an imaging device of one embodiment of the present invention, and shows three pixels ( 2 shows the configuration of pixels 20a, 20b, and 20c.

[0042] FIG. 1B is a circuit diagram of the pixel 20. In this embodiment, the transistor is An example in which the transistor is an h-type transistor is shown, but the present invention is not limited to this. may be replaced with a p-channel transistor.

[0043] As shown in FIG. 1B, one electrode of the photoelectric conversion element PD is connected to the source of a transistor 41. The source or drain of the transistor 41 is electrically connected to the The other terminal is electrically connected to one of the source and drain terminals of the transistor 42. The other of the source and drain of the transistor 41 is electrically connected to the gate of the transistor 43. One of the source and drain of the transistor 43 is connected to the source of the transistor 44. The transistor is electrically connected to either the source or the drain.

[0044] Here, the other of the source or drain of the transistor 41 and the source or drain of the transistor 42 A node FD to which the drain of the transistor 41 or the gate of the transistor 42 is connected is used as a charge storage section. As shown in FIG. 2A, in the configuration in which a capacitor is connected to the node FD, Good too.

[0045] The other electrode of the photoelectric conversion element PD is electrically connected to a wiring 71 (VPD). The other of the source and the drain of the transistor 42 is electrically connected to a wiring 72 (VRS). The other of the source and the drain of the transistor 43 is electrically connected to the wiring 73 (VPI). The other of the source and drain of the transistor 44 is connected to a wiring 91 (OUT1). are electrically connected.

[0046] Note that the connection between the elements such as the transistors and the photoelectric conversion elements and the wiring is an example. Each element may be electrically connected to a different wiring, or multiple elements may be electrically connected to the same wiring. In some cases, they may be electrically connected.

[0047] The wiring 71 (VPD), the wiring 72 (VRS), and the wiring 73 (VPI) serve as power supply lines. For example, the wiring 71 (VPD) functions as a low-potential power supply line. The line 72 (VRS) and the wiring 73 (VPI) function as high-potential power supply lines.

[0048] The gate of the transistor 41 is electrically connected to the wiring 61 (TX). The gate of the transistor 44 is electrically connected to the wiring 62 (RS). It is electrically connected to the wiring 63 (SE).

[0049] The wiring 61 (TX), the wiring 62 (RS), and the wiring 63 (SE) are connected to each other. It functions as a signal line that controls the conduction of a transistor.

[0050] The transistor 41 is a transistor for transferring the potential of the cathode of the photoelectric conversion element PD to the node FD. The transistor 42 resets the potential of the node FD. The transistor 43 functions as a transistor for detecting the potential of the node FD. The transistor 44 functions as a transistor for outputting an output corresponding to It functions as a transistor for selecting the pixel 20 .

[0051] As shown in FIG. 2B, the pixel 20 has a photoelectric conversion element PD facing in the opposite direction to that in FIG. 1B. In this case, the region 510 may be an anode (p-type region) and the region 520 may be a cathode. For example, an n-type single crystal silicon substrate may be used, and region 5 may be formed. By adding a dopant such as boron to 10, it can be made p-type.

[0052] The above-described configuration of the pixel 20 is merely an example. In some cases, the capacitance element or some of the wirings may not be included. In some cases, the circuit may include a transistor, a capacitor, a wiring, etc. The topology may differ from the above configuration.

[0053] As shown in FIG. 1A, the pixel 20 includes a layer 1100, a layer 1200, and a layer 1300. For example, the layer 1100 may be configured to include transistor 4 that constitutes a pixel circuit. 1 to 44, etc. The layer 1200 includes a photoelectric conversion element PD, etc. The layer 1300 includes It has a color filter and a microlens array.

[0054] In the cross-sectional views described in this embodiment mode, each layer is provided with a protective film, an interlayer insulating film, or a flat Insulating layers 81a to 81e, which function as insulating films, are provided. For example, insulating layer 81 81a to 81e are chemical vapor deposition (CVD) methods. Inorganic insulating films such as silicon oxide films and silicon oxynitride films formed by using a method such as the above-mentioned can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. The upper surfaces of the layers 81a to 81e etc. may be etched by chemical mechanical polishing (CMP) if necessary. A planarization process may be performed using a method such as ical polishing.

[0055] The transistors 41 to 44 provided in the layer 1100 each have a channel formation region formed of an oxide semiconductor. It is preferable to use an OS transistor. The transistor is a type that uses silicon for the channel formation region (hereafter, Si transistor). Therefore, the off-current is smaller than that of the conventional MOSFETs, and the off-current is smaller than that of the conventional MOSFETs. It is possible to apply a global shutter method in which charge accumulation is performed simultaneously on the The imaging device according to one embodiment of the present invention can also be operated by a rolling shutter method.

[0056] In this specification and the like, when an oxide semiconductor is referred to as a metal oxide, There is.

[0057] OS transistors have smaller temperature dependence of electrical characteristics fluctuations than Si transistors. It can be used in a very wide temperature range. The imaging and semiconductor devices are also suitable for installation in automobiles, aircraft, spacecraft, and the like.

[0058] In addition, OS transistors have better 1 / f noise characteristics than Si transistors. is the 1 / f noise of OS transistors and Si transistors (n-ch type, p-ch type). This data compares the speed characteristics.

[0059] The vertical axis is S. id / Id 2 L W [m 2 / Hz], the spectral density of the drain current is The value is normalized by the in-current and the channel size of the transistor, and is used at frequencies from 1 Hz to The measurements were performed in the range of 10 kHz. L is the channel length of the transistor, W is the The channel width of the OS transistor is L / W=30nm / 30nm or L / W=30nm / 60nm, and Si transistors have L / W=0.8μm / 10μm. The measurement conditions for the OS transistor were Vd = 1.0 V, Id = 1 μA, and Si transistor The measurement conditions for the capacitor were Vd = 0.1 V and Id = 1 μA.

[0060] Figure 3 shows the results of the deposition of IGZO using an In:Ga:Zn=4:2:4.1 (atomic ratio) target. An OS transistor (L The 1 / f noise of the OS transistor is n- It is smaller than a ch-type Si transistor. Furthermore, compared with a p-ch-type Si transistor, Then, in the range of 1 Hz to 500 Hz, the noise is small, and in the range of frequencies above that, The results are almost the same. That is, the logarithmic frequency axis of Figure 3 shows that the range from 1 Hz to 10 kHz In the range of 60% or more below, the 1 / f noise is higher than that of p-ch type Si transistors. Therefore, it can be said that the OS transistor is smaller in size.

[0061] That is, an IGZO target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. The OS transistors fabricated using this method have better 1 / f noise characteristics than Si transistors. Therefore, for example, the OS transistor can be used as a pixel of a CMOS image sensor. By using it in a wide range of applications, it is possible to obtain clearer images with less noise than when using Si transistors. It is possible to obtain images. In:Ga:Zn=3:1:4 or 5:1:6 ( The OS transistor may be fabricated using an IGZO target having a ratio of 1:1 to 1:1. Incidentally, the vicinity of the above atomic ratio is also included in this category.

[0062] FIG. 1A illustrates a transistor 41. As shown in FIG. The OS transistor 41 may be, for example, a top-gate type OS transistor. The transistor is provided on an insulating layer 81c formed on the layer 1200, and the oxide semiconductor layer 130 a conductive layer 140 serving as one of a source electrode and a drain electrode; A conductive layer 150 serving as the other of the gate and drain electrodes and an insulating layer 152 serving as a gate insulating layer. The insulating layer 81c has an insulating layer 160 and a conductive layer 170 that functions as a gate electrode. It can also function as a gate insulating layer on the back gate side, which will be described later.

[0063] In FIG. 1A, a conductive layer 173 serving as a back gate electrode is provided in the transistor 41. The pixel circuit is configured as a top-gate transistor. In the case of using a stencil as the stencil, the light transmitted through the layer 1200 may enter the layer 1100. It is preferable to provide a back gate electrode for light shielding. If the thickness is sufficient and the amount of light transmission is within an allowable range, a configuration without providing a back gate electrode may be adopted. Also, even if a light-shielding layer or the like is provided separately, it is possible to provide a back gate electrode. It is also possible to adopt a configuration in which this is not necessary.

[0064] The photoelectric conversion element PD provided in the layer 1200 is a photodiode provided on a single crystal silicon substrate. The photodiode has excellent photoelectric conversion characteristics. In this photodiode, the base material, a single crystal silicon substrate, functions as a photoelectric conversion layer, The single crystal silicon substrate can be polished as necessary, for example, The thickness may be 3 to 30 μm.

[0065] In addition, FIG. 1(A) shows a pn junction type photodiode, and the circuit shown in FIG. 1(B) According to the diagram, region 510 is the cathode (n-type region) and region 520 is the anode (p-type region). For example, a p-type single crystal silicon substrate may be used, and phosphorus or the like may be added to the region 510. The dopant can be added to make the material n-type.

[0066] Also, the photodiode provided in the layer 1200 is insulated from the region 510 as shown in FIG. A region 530 having a conductivity type opposite to that of the region 510 may be provided in a portion between the edge layer 81d. As shown in FIG. 4B, a region 530 is formed in the entire area between the region 510 and the insulating layer 81d. With this configuration, the photodiode is a buried type. Therefore, noise generated at the interface between the silicon and the insulating layer can be suppressed.

[0067] In addition, the photodiodes provided in the layer 1200 are arranged with partitions between the pixels as shown in FIG. The partition wall may have a groove between the pixels, and the groove may be filled with an insulating layer 81e. By using such a configuration, the light incident from an oblique direction This can prevent the intrusion of stray light.

[0068] It is preferable to use a material having a refractive index lower than that of silicon for the partition wall. For example, The insulating layer 81e may be made of the above-mentioned materials. Alternatively, a material that easily absorbs light may be used. For example, carbon black or other carbon-based black pigments, titanium dioxide, etc. may be used to form the partition walls. Titanium-based black pigments such as black, iron oxides, copper and chromium oxides, copper, chromium Alternatively, a resin containing a material such as a composite oxide of rubber and zinc may be used.

[0069] Also, the photodiode provided in the layer 1200 is insulated from the region 520 as shown in FIG. Between the edge layer 81e and the region 520, there is a region of the same conductivity type as the region 520 and having a higher dopant concentration than the region 520. A region 540 may be provided. With this configuration, the carriers can be collected efficiently. This can be done.

[0070] Also, the photodiode provided in the layer 1200 is adjacent to the region 530 as shown in FIG. Adjacent areas 540 may be provided.

[0071] In the configurations of FIG. 1A, FIG. 4A, FIG. 4B, and FIG. 4C, a region 520 is formed for each of a plurality of pixels. In the configuration of FIG. The region 540 and the wiring 71 may be electrically connected to each other via the region 545 for each pixel. In addition, like the region 540, the region 545 has the same conductivity type as the region 520 and is more conductive than the region 520. In the configuration of FIG. 4(E), each region 540 is connected to the wiring 7. 1.

[0072] In the imaging device of one embodiment of the present invention, as shown in FIG. The electrical connection between one of the drains and one of the electrodes of the photoelectric conversion element PD is made by a conductor 82. The conductor 82 is formed by stacking the insulating layer 81b, the conductive layer 140, the oxide semiconductor layer 130, and the insulating The insulating layer 81c and the insulating layer 81d are provided so as to penetrate therethrough.

[0073] With this configuration, a bridge using a plurality of conductors 82 and connection wiring, etc. The electrical connection can be achieved without performing any electrical connection, and the process can be simplified. In addition, before the transistor 41 is formed, it is necessary to provide openings in the insulating layers 81c, 81d, etc. Therefore, the occurrence of process defects due to the shape of steps or the like can be suppressed.

[0074] The electrical connection between the conductor 82 and one of the electrodes of the photoelectric conversion element PD is as shown in FIG. The conductive layer 550 may be formed of, for example, W, Ta, or Al. The conductive layer 550 may be a metal layer such as Ti, Ni, SUS, or Pd. In addition to acting as an electrode for the conversion element PD, it also serves as an edge when forming a through hole for providing the conductor 82. It also acts as a light blocking layer for transistors and a photoelectric conversion layer. It also functions as a reflective electrode for the switching element PD.

[0075] As shown in FIG. 5B, the conductor 82 is formed by bonding the conductive layer 140 and the oxide semiconductor layer 130. The conductive layer 140 is connected to the upper surface and the side surface of the oxide semiconductor layer 130 without penetrating the conductive layer 140 and the side surface of the oxide semiconductor layer 130. The conductive layer 140 may be made of a material that is difficult to etch. Since a metal layer is used, this structure makes it possible to reduce the etching time required for forming the through hole. The process load can be reduced.

[0076] As shown in FIG. 5C, a photoelectric conversion element PD is electrically connected to one of the electrodes. The conductive layer 560 and the conductor 82 may be electrically connected. After the opening is provided in the insulating layer 81d, the conductive layer 173 may be formed in the same process. The numeral 560 serves as an etching stopper when forming a through hole for providing the conductor 82. do.

[0077] In addition, for example, the back gate electrodes of the transistors 41 in the pixel 20 can be made common. In this case, the pixel 20 can be configured as shown in FIG. For example, the backgate of each transistor provided in the layer 1100 other than the transistor 41 is In the pixel 20 having the above-described configuration, the conductive layer 173 This can improve the light blocking effect on the transistor.

[0078] As shown in FIG. 6B, the conductive layer 173 and the wiring 71 are electrically connected to each other. In FIG. 6B, the conductive layer 17 of the pixel 20a, the pixel 20b, and the pixel 20c 3 is electrically connected to the wiring 71. The potential of the wiring 71 and the back gate potential of the transistor included in the pixel 20 are controlled at the same time. Since the pixel 20 can be controlled by the control circuit 14, the operation of the pixel 20 can be easily controlled.

[0079] In the pixel 20 having the configuration shown in FIGS. 6A and 6B, the conductor 82 and the conductive layer 173 The configuration is such that it does not intersect with the

[0080] The pixel 20 may have a configuration as shown in FIG. A region 143 and a region 153 are provided on a single crystal silicon substrate 500. Region 153, like region 510, may be doped with a dopant such as phosphorus. The n-type region may be formed by

[0081] The oxide semiconductor layer 130 is provided in contact with the region 143 and the region 153. The conductive layer 140 is provided to overlap the region 143, and the conductive layer 150 is provided to overlap the region 15. In this configuration, the region 143 and the conductive layer 140 and the region 1 The region between 43 functions as either the source or the drain, and the region 153 and the conductor The region between the electrode layer 150 and the region 153 functions as the other of the source or drain. In other words, the transistor 41 includes a single crystal silicon substrate 500 in addition to the oxide semiconductor layer 130. Therefore, the channel region of the transistor 41 is formed by the oxide This results in a laminated structure of semiconductor and silicon. This increases the on-current of the transistor 41. It can be made easier.

[0082] Region 143 also extends to form region 510, which allows transistor 41 Either the source or the drain is electrically connected to one electrode of the photoelectric conversion element PD. That is, one of the source and drain of the transistor 41 and the photoelectric conversion element PD There is no need to provide a conductive layer or the like for electrically connecting the other electrode. The manufacturing process of the imaging device according to the above aspect can be simplified.

[0083] The OS transistor used in one embodiment of the present invention may have a structure shown in FIG. The transistor shown in FIG. 7B is in contact with the region 510 of the photoelectric conversion element PD and has a source potential. 1, the conductive layer 140 that functions as one of the electrode or drain electrodes and the region 510 are exposed. The oxide semiconductor layer 130 covers the opening provided in the insulating layer 81j. a conductive layer 150 serving as the other of the source electrode and the drain electrode provided on the first insulating film 10; A gate insulating layer 160 is formed on the oxide semiconductor layer 130. The gate insulating layer 160 functions as a gate insulating layer. It has a conductive layer 170 which functions as an electrode.

[0084] Such a configuration can also be called a vertical transistor. In a vertical transistor, the insulating The region including the sidewall of the opening provided in the layer 81j becomes the channel region, so that the transistor The area occupied by the sensor can be reduced.

[0085] In the pixel 20 having the configuration shown in FIGS. 7A and 7B, the insulating layer 81c and the insulating layer 81d is not provided.

[0086] The layer 1300 includes a light-shielding layer 1530, optical conversion layers 1550a, 1550b, and 1550c, and a A microlens array 1540 or the like may be provided.

[0087] An insulating layer 81e is formed in the region in contact with the layer 1200. The insulating layer 81e is A highly transparent silicon oxide film can be used as the passivation film. A silicon nitride film may be laminated on the anti-reflection film. Alternatively, a dielectric film such as aluminum may be laminated.

[0088] A light-shielding layer 1530 may be provided on the insulating layer 81e. The light-shielding layer 1530 may be formed to shield adjacent pixels. It is placed at the boundary between the substrates and has the function of blocking stray light entering from an oblique direction. The metal layer, such as aluminum or tungsten, and the metal layer and the function as an anti-reflective film are included. The dielectric film may be laminated.

[0089] On the insulating layer 81e and the light-shielding layer 1530, optical conversion layers 1550a, 1550b, and 1550c are provided. For example, the optical conversion layers 1550a, 1550b, and 1550c may be provided with R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By applying a filter, a color image can be obtained.

[0090] If a filter that blocks light with wavelengths shorter than visible light is used in the optical conversion layer, it can be used as an infrared imaging device. In addition, if a filter that blocks light with wavelengths shorter than near-infrared is used in the optical conversion layer, For example, a far-infrared imaging device can be used. By using a blocking filter, it can be made into an ultraviolet imaging device.

[0091] In addition, if a scintillator is used in the optical conversion layer, it is possible to detect the intensity of radiation, which is used in X-ray imaging devices, etc. The imaging device can obtain an image that visualizes radiation such as X-rays that has passed through the subject. When light enters the scintillator, it is converted into visible light, ultraviolet light, etc. by the photoluminescence phenomenon. The light is then converted into fluorescent light (fluorescence). This light is then detected by the photoelectric conversion element PD. Image data is acquired. Also, an imaging device having this configuration may be used as a radiation detector or the like.

[0092] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and These include substances that emit visible light or ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C eF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used. Cut.

[0093] A microlens array 1540 is disposed on the optical conversion layers 1550a, 1550b, and 1550c. The light passing through each lens of the microlens array 1540 may be The light passes through the optical conversion layers 1550a, 1550b, and 1550c directly below and reaches the photoelectric conversion element PD. It will become more common.

[0094] As shown in FIG. 8, the pixel 20 includes layers 1100, 1200, and 1300, as well as layers The layer 1400 may include, for example, a column driver and Driving circuits such as row drivers, data conversion circuits such as A / D converters, CDS (Cor Noise reduction circuits, such as EMIF (Electronic Related Double Sampling) circuits, and The imaging device has external circuits other than the pixel circuits, such as a control circuit for the entire device.

[0095] Layer 1400 includes transistors 46, 47, and The insulating layers 81f, 81g, 81h, etc. are provided on the transistors 46 and 47.

[0096] Water in the insulating layer provided near the active regions of the transistors 46 and 47 The hydrogen terminates the dangling bonds of silicon. Therefore, the hydrogen 6 and transistor 47. Hydrogen in an insulating layer provided in the vicinity of an oxide semiconductor layer that is a channel formation region, such as in the case of This hydrogen is one of the factors that generate carriers in the oxide semiconductor layer. This may cause a decrease in the reliability of the Si transistor 41. When a layer having an OS transistor and a layer having an OS transistor are stacked, It is preferable to provide an insulating layer 81h between the insulating layer 81 and the insulating layer 81h, which has a function of preventing diffusion of hydrogen. 1h, hydrogen is trapped in one layer, and transistor 46 and transistor 4 7. In addition, the diffusion of hydrogen from one layer to another can be improved. By suppressing this, the reliability of the transistor 41 and the like can be improved.

[0097] The conductive layer 64 and the conductive layer 94 are formed so as to have a region buried in the insulating layer 81g. The conductive layer 64 is a conductive layer provided to fill an opening formed in the insulating layer 81f. The conductive layer 94 is electrically connected to the gate of the transistor 47 through the insulating layer 8. The transistor 47 is connected to the conductive layer 1f through the conductive layer 1f. It is electrically connected to either the source or the drain.

[0098] The transistors 46 and 47 are connected to the gate of the transistor 41. The surfaces of the microlens array 81a and the microlens array 81b are arranged to face each other. The conductive layer 84 is provided so as not to have an area overlapping with the conductive layer 1540. 84 is provided on the single crystal silicon substrate 500 on the light receiving surface side of the photoelectric conversion element PD.

[0099] The conductive layer 94 and the conductive layer 84 are electrically connected via a conductor 83. The conductor 83 does not have an area overlapping with the microlens array 1540. The layer 81a to the insulating layer 81e, the insulating layer 81g, the insulating layer 81h, and the single crystal silicon substrate 50 0. That is, the conductor 83 is provided so as to fill the opening formed in the pixel 20. The layer 1100 and the layer 1200 are provided outside the region having the structure. By forming the imaging device in this manner, the manufacturing process of the imaging device of one embodiment of the present invention can be simplified.

[0100] An insulating layer 81e is filled in the opening provided in the single crystal silicon substrate 500. The conductor 83 is provided so as to be in contact with the insulating layer 81e. There is no region in contact with the crystalline silicon substrate 500. This can prevent electrical conduction between 83 and the photoelectric conversion element PD.

[0101] An imaging device according to one embodiment of the present invention can have a configuration shown in FIG. The conductor 83 fills the opening formed in the insulating layer 81f and the single crystal silicon substrate 600. In other words, the conductor 83 is provided so as to be in contact with the outside of the region having the pixel 20. It is installed through 1400.

[0102] In addition, in FIG. 8 and FIG. 9, the transistor 46 and the transistor 47 have a fin-type structure. However, as shown in FIG. 10(A), it may be a planar type. As shown in FIG. 10B, a transistor having a channel forming region 660 of a silicon thin film is The channel forming region 660 may be formed of polycrystalline silicon or SOI (Silicon). The silicon substrate may be made of single crystal silicon (N on Insulator).

[0103] FIG. 11A is a block diagram of an image sensor 11 according to one embodiment of the present invention. A pixel array 21, a column driver 23, a row driver 24, an analog switch 25, and a It has a current source circuit 26 and a terminal 30 .

[0104] The pixel array 21 includes pixels 20 arranged in a matrix and various wirings. In FIG. 1(A), the wiring 63 (SE) and the wiring 91 (OUT1) are shown, but the other The wiring is omitted.

[0105] The column driver 23 and the row driver 24 can be configured as a shift register circuit. The analog switch 25 and the power supply 26 can be configured with only the OS transistor. The current source circuit 26 can be made of OS transistors. A circuit for outputting image data to the outside can also be provided.

[0106] In the configuration shown in FIG. 11(A), the output is sent to the terminal 30 via the wiring 92 (OUT2). The data to be converted is analog data. The analog data is converted into digital data. In order to do this, the analog data is output to an A / D converter provided outside the image sensor 11. do.

[0107] FIG. 11B is a block diagram showing an example of the A / D converter 12. The counter 12 includes a comparator 28, a counter circuit 29, etc., and has a multi-bit data line 93. Digital data can be output.

[0108] The comparator 28 detects the signal potential input from the terminal 30 to the terminal 31 and the rising or falling The reference potential (VREF) is compared to the reference potential (VREF) which is swept so as to The counter circuit 29 operates according to the output of the OUT3, and a digital signal is output to the wire 93 (OUT3). Be encouraged.

[0109] Here, the A / D converter 12 is configured as a CMOS circuit for high speed operation and power saving. It is preferable to form the transistor from a silicon transistor which can be used.

[0110] The image sensor 11 and the A / D converter 12 are connected, for example, as shown in FIG. Terminal 30 and terminal 31 may be connected with a wire by using a wire bonding method or the like.

[0111] Here, the structure of a unipolar shift register that can be formed using OS transistors will be described. This will be explained using FIG.

[0112] The shift register 700 shown in FIG. 12A outputs n pulses (n is a natural number of 2 or more). In this specification, the first stage pulse output circuit 710 is referred to as a "pulse output Circuit 710 _ 1," and the n-th stage pulse output circuit 710 may be referred to as the "pulse output circuit 710_n". Also, the pulse of the i-th stage (i is a natural number between 1 and n). The output circuit 710 is referred to as "pulse output circuit 710 _ In addition, the pulse output circuit The terminals and output signal OUT of the circuit 710 may also be described in the same manner as above. For example, when the output signal OUT of the pulse output circuit 710_i is referred to as the “output signal OUT_i”, There is.

[0113] The shift register 700 also includes a wiring 705 to which a reset signal RES is supplied, and a clock The wiring 701 includes a first clock signal. A first clock signal CLK1 is supplied to the wiring 701, a second clock signal CLK2 is supplied to the wiring 702, A third clock signal CLK3 is supplied to the wiring 703, and a fourth clock signal CLK4 is supplied to the wiring 704. The signal CLK4 is provided.

[0114] The clock signal is a signal that changes between H potential and L potential at regular intervals. The fourth clock signal CLK1 to the fourth clock signal CLK4 are delayed by 1 / 4 period in order. In the embodiment, the first clock signal CLK1 to the fourth clock signal CLK4 are used to Controls the pulse output circuit, etc.

[0115] The pulse output circuit 710 has terminals 711 to 716 (see FIG. 12B). The terminals 711 and 712 are electrically connected to any of the wirings 701 to 704. For example, in FIG. 12A, a pulse output circuit 710_1 has a terminal 711. The terminal 712 is electrically connected to the wiring 702. In addition, the pulse output circuit 710_2 has a terminal 711 electrically connected to the wiring 702, and a terminal 12 is electrically connected to the wiring 703. Also, the terminal 714 is electrically connected to the wiring 705. is connected.

[0116] A start signal SP is supplied to a terminal 713 of the pulse output circuit 710_1, and a terminal 716 An output signal OUT_1 is output from the terminal 71 of the pulse output circuit 710_i. 3 is a terminal 71 of a pulse output circuit 710_i-1 (a pulse output circuit 710 of the (i-1)th stage). 5. The terminal 715 of the pulse output circuit 710_i is electrically connected to the pulse The pulse output circuit 710 is electrically connected to the terminal 713 of the output circuit 710_i+1. An output signal OUT_i is output from a terminal 716 of the nth stage pulse output An output signal OUT_n is output from a terminal 716 of the circuit 710_n.

[0117] The pulse output circuit 710_n does not necessarily have to include the terminal 715. If 10_n has a terminal 715, the terminal 715 (terminal 715_n) is connected to the first stage In some cases, the terminal 713 (terminal 713_1) of the pulse output circuit 710_1 may be electrically connected to the .

[0118] Next, the configuration of the pulse output circuit 710 will be described (see FIG. 12(C)). The output circuit 710 includes a transistor 721, a transistor 722, a transistor 724, and a transistor 726. A transistor 729, a transistor 731, a transistor 732, a capacitor 733, and It has a capacitor 734 .

[0119] One of the source and the drain of the transistor 721 is electrically connected to the wiring 741. The other of the source and drain is electrically connected to a node 762, and the gate is electrically connected to a terminal 712. One of the source and drain of the transistor 722 is electrically connected to the wiring 741. and the other of the source and drain is electrically connected to a node 762. The gate is electrically connected to the terminal 714. One of the inputs is electrically connected to the wiring 741, and the other of the source or drain is connected to the node 76 The transistor 7 has a gate electrically connected to a terminal 713 and a gate electrically connected to a terminal 714. 25 is electrically connected to a node 763, and The other end of the drain is electrically connected to the wiring 746, and the gate is electrically connected to a node 762. The source or drain of the transistor 726 is electrically connected to the terminal 711. The other of the source and drain is electrically connected to a terminal 715, and the gate is connected to a node One of the source and drain of the transistor 727 is electrically connected to the The other of the source and drain is electrically connected to a terminal 715 and a wiring 746. The source of transistor 728 is electrically connected to node 762. Alternatively, one of the drains is electrically connected to the terminal 711, and the other of the source or drain is The transistor is electrically connected to the terminal 716 and the gate is electrically connected to the node 761. One of the source and drain of the transistor 729 is electrically connected to the terminal 716. Alternatively, the other of the drains is electrically connected to the wiring 746, and the gate is electrically connected to the node 762. One of the source and drain of the transistor 731 is connected to a node 762. The other of the source and drain is electrically connected to the wiring 746, and the gate The terminal 713 is electrically connected to the source or drain of the transistor 732. One of the source and drain is electrically connected to node 763, and the other of the source and drain is connected to node 761. and the gate is electrically connected to a wiring 741. One electrode is electrically connected to a node 762, and the other electrode is electrically connected to a wiring 746. It has been done.

[0120] As shown in FIG. 13A, the transistor used in the pixel 20 is a transistor 41. A circuit configuration in which a back gate is provided in each of the first to fourth embodiments may be used. This allows the threshold voltage to be controlled.

[0121] The wirings 75 to 78 connected to the back gates are supplied with different potentials. Alternatively, as shown in FIG. 13B, a transistor 41 and a transistor The wiring connected to the back gate of the gate electrode 42 may be electrically connected. The wiring connected to the back gates of the transistors 43 and 44 is a The electrodes may be electrically connected.

[0122] In an n-channel transistor, when a potential lower than the source potential is applied to the back gate, On the other hand, if the back gate is applied with a potential higher than the source potential, the threshold voltage shifts in the positive direction. When a potential is applied, the threshold voltage shifts in the negative direction. When controlling the on / off of each transistor with a gate voltage, the source voltage is applied to the back gate. When a potential lower than the back gate potential is applied, the off-state current can be reduced. When a potential higher than the source potential is applied to the gate, the on-current can be reduced.

[0123] In the circuits shown in Fig. 1(B), Fig. 4(A), (B), Fig. 13(A), (B), the node FD Since it is desirable for the transistors 41 and 42 to have a high potential holding capability, as described above, It is preferable to use OS transistors with low buffer current. By applying a potential to the gate that is lower than the source potential, the off-current can be reduced. Therefore, the potential holding capability of the node FD can be improved.

[0124] As described above, transistors 43 and 44 are made of transistors with high on-state current. It is preferable that the back gates of the transistors 43 and 44 are supplied with a potential higher than the source potential. By applying the voltage, the on-current can be increased. UT1) can be quickly determined, i.e., It can be operated at any wave number.

[0125] As shown in FIG. 13C, the transistor 44 has a back gate with the same potential as the front gate. The voltage may be applied to the input gate.

[0126] In addition to the power supply potentials, the image pickup device also includes a signal potential and a potential to be applied to the back gate. When multiple potentials are supplied from the outside of the imaging device, the number of terminals increases. In order to meet the increasing demands for power supplies, the imaging device must have a power supply circuit that generates multiple potentials. is preferred.

[0127] The operation of the pixel circuit shown in FIG. 13(A) will be described with reference to the timing chart shown in FIG. In the timing chart, "V1" is a potential higher than the reference potential, for example, It can be the power supply potential (VDD). “V0” is the reference potential, i.e., the source potential. For example, it can be 0V, a GND potential, or a low power supply potential (VSS).

[0128] First, at time T1, the potential of the wiring 62 (RS) and the wiring 61 (TX) is set to "V1". Then, the transistors 41 and 42 become conductive, and the node FD becomes a reset potential (for example, VDD). At this time, the wiring 75 and the wiring 76 are reset to "V0" (reset operation). By setting the potential to high (>“V0”), the on-current of the transistors 41 and 42 is increased. The reset operation can be performed quickly.

[0129] When the potential of the wiring 62 (RS) is set to “V0” at time T2, the transistor 42 is turned off. At this time, the wiring 76 is connected to "V0" and the accumulation operation is started. By setting the potential to low, the off-state current of the transistor 42 can be reduced, and the leakage current At time T2, the supply of charge to the node FD by the The potential of the line 75 may be "V0."

[0130] When the potential of the wiring 61 (TX) is set to “V0” at time T3, the transistor 41 is turned off. At this time, the potential of the node FD is determined and held (holding operation). By setting the potential lower than "V0", the off-state current of the transistor 41 can be reduced. This makes it possible to prevent charge from flowing out of the node FD due to leakage current.

[0131] At time T4, when the potential of the wiring 63 (SE) is set to "V1", the transistor 44 is turned on. The potential of the wiring 91 (OUT1) changes according to the current flowing through the transistor 43 (read At this time, the wiring 77 and the wiring 78 are set to a potential higher than “V0” (>“V0”). This increases the on-state current of the transistors 43 and 44, and the wiring 91 (OUT1 ) can be determined.

[0132] When the potential of the wiring 63 (SE) is set to "V0" at time T5, the transistor 44 is turned off. The read operation is then completed. Note that the potential of the node FD is The potential of the wiring 75 and 76 is kept lower than “V0” (<“V0”) so that the In the above description, it is preferable that the wiring 76 is connected at the same timing as the wiring 75. The potential may be changed by

[0133] In this way, a signal according to the potential of the node FD can be read out. The pixel 20 shown in FIG. 14 is configured by omitting the control of the wirings 75 to 78 in the timing chart shown in FIG. The pixel 20 shown in FIG. 13B is operated in accordance with the timing chart shown in FIG. This can be achieved by omitting the control of the wires 76 and 78.

[0134] In addition, the pixel circuit of one embodiment of the present invention is a transistor having a plurality of pixels as shown in FIGS. The transistors may be shared.

[0135] In the transistor-sharing type pixel shown in FIG. 15(A), pixels 20h to 20k are photoelectric The conversion element PD and the transistor 41 are individually included, and the transistors 42, 43, 44 and The transistors of the pixels 20h to 20k are The operation of each of the pixels 41 is controlled by wiring 61h to 61k. It can perform reset, accumulation, retention, and readout operations in sequence. This is suitable for imaging using a fast shutter method.

[0136] In the transistor-sharing type pixel shown in FIG. 15B, pixels 20h to 20k are photoelectric The conversion element PD and the transistors 41 and 45 are individually provided. 4 and the capacitance element C1 are shared. A transistor 45 controlled by the transistor 45 is provided between the photoelectric conversion element PD and the wiring 71 (VPD). This allows the cathode of the photoelectric conversion element PD to be held at a potential. The reset operation, accumulation operation, and retention operation are performed simultaneously on each pixel, and the readout operation is performed for each pixel. This is suitable for imaging using a global shutter method.

[0137] The pixel circuit shown in FIGS. 15A and 15B is arranged in a direction in which the wiring 91 (OUT1) extends (hereinafter, A transistor is formed in multiple pixels (pixels 20h, 20i, 20j, and 20k) arranged in a vertical direction. In the figure, the wiring 63 (SE) is shared in the direction in which it extends (hereinafter, the horizontal direction). A transistor may be shared by a plurality of pixels arranged in a row. A transistor may be shared by a plurality of pixels arranged in a line.

[0138] In addition, the number of pixels that share a transistor is not limited to four pixels, but can be two, three, or five pixels. It may be more than that.

[0139] In FIGS. 15A and 15B, the wiring 72 (VRS) and the wiring 73 (V PI) and omitting the wiring 72 (VRS). The other electrode of the capacitance element C1 may be connected to a wiring 73 (VPI ) is shown, it may be connected to the wiring 71 (VPD).

[0140] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0141] (Embodiment 2) In this embodiment, an OS transistor that can be used in one embodiment of the present invention will be described with reference to drawings. In the drawings in this embodiment, some elements are illustrated for clarity. The drawings may be enlarged, reduced, or omitted.

[0142] 16A and 16B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 16(A) is a top view, and FIG. 16(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 16(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 18(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0143] The transistor 101 includes an insulating layer 120 in contact with a substrate 119 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0144] The conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is a gate insulator. The insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0145] In FIG. 16B, a region 231 is a source region, a region 232 is a drain region, and a region 233 is The region 231 and the region 232 can function as a channel forming region. 40 and conductive layer 150, respectively, as conductive layer 140 and conductive layer 150. By using a conductive material that easily bonds with oxygen, the resistance of the regions 231 and 232 can be reduced. can be done.

[0146] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0147] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0148] The conductive layer 170 is illustrated as being formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The same can be applied to transistors.

[0149] Although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as a laminate of two or more layers. This structure can be applied to other transistors described in this embodiment. .

[0150] The insulating layer 175 mainly suppresses diffusion of impurities from the outside into the oxide semiconductor layer 130. It acts as a blocking layer, but by selecting an appropriate material, it can prevent oxidation of the conductive layer 170. Furthermore, the oxide semiconductor layer 130 also functions as a hydrogen supply source that reduces the resistance of part of the oxide semiconductor layer 130.

[0151] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 16(C) is a top view of the transistor 102, and the dashed line C1-C The cross sections in the two directions correspond to FIG. 16(D). Also, the dashed line C3-C4 shown in FIG. The cross section in the direction corresponds to FIG. 18(B). The direction of the dashed dotted line C3-C4 is referred to as the channel width direction.

[0152] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0153] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. This makes it easier to form small transistors.

[0154] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 16(E) is a top view of the transistor 103, and the dashed line D1-D1 in FIG. The cross sections in the two directions correspond to FIG. 16(F). Also, the dashed line D3-D4 shown in FIG. The cross section in the direction corresponds to FIG. 18(A). The direction of the dashed dotted line D1-D2 is the channel rectangular direction. The direction of the dashed dotted line D3-D4 is referred to as the channel width direction.

[0155] The transistor 103 includes an insulating layer 120 in contact with a substrate 119 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0156] The conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is a gate insulator. The insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0157] In FIG. 16(F), a region 231 is a source region, a region 232 is a drain region, and a region 233 is The region 231 and the region 232 can function as a channel forming region. 75. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region 231 And the resistance of the region 232 can be reduced.

[0158] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0159] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 17(A) is a top view of the transistor 104, and the dashed line E1-E The cross sections in the two directions correspond to FIG. 17(B). Also, the dashed line E3-E4 shown in FIG. The cross section in the direction corresponds to FIG. 18(A). The direction of the dashed dotted line E1-E2 is the channel rectangular direction. The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0160] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0161] Regions 331 and 334 shown in FIG. 17B are source regions, regions 332 and 3 The region 35 can function as a drain region, and the region 333 can function as a channel forming region.

[0162] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. As with 2, the resistance can be reduced.

[0163] Regions 334 and 335 correspond to regions 231 and 232 in transistor 103. In addition, the resistance of the region 334 and the region 335 in the channel length direction can be reduced in the same manner as in the region 2. When the length of the region 335 is 100 nm or less, preferably 50 nm or less, the gate electric field The on-current does not decrease significantly due to the contribution of the low In some cases, resistance may not be achieved.

[0164] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0165] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 17(C) is a top view of the transistor 105, and the dashed line F1-F in FIG. The cross sections in the two directions correspond to FIG. 17(D). Also, the dashed line F3-F4 shown in FIG. The cross section in the direction corresponds to FIG. 18(A). The direction of the dashed line F1-F2 is the channel rectangular direction. The direction of the dashed dotted line F3-F4 is referred to as the channel width direction.

[0166] The transistor 105 includes an insulating layer 120 in contact with a substrate 119 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0167] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and in contact with the side surfaces of the oxide semiconductor layer 130. This is not a structure that can be used in this way.

[0168] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0169] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 17(E) is a top view of the transistor 106, and the dashed line G1-G The cross sections in the two directions correspond to FIG. 17(F). Also, the dashed line G3-G4 shown in FIG. The cross section in the direction corresponds to FIG. 18(A). The direction of the dashed line G1-G2 is the channel length. The direction of the dashed dotted line G3-G4 is referred to as the channel width direction.

[0170] The transistor 106 includes an insulating layer 120 in contact with a substrate 119 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0171] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and in contact with the side surfaces of the oxide semiconductor layer 130. This is not a structure that can be used in this way.

[0172] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0173] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0174] Regions 231 and 232 in transistor 103, transistors 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the electrical conductivity. As the impurity that forms oxygen vacancies in the oxide semiconductor layer, Examples of these elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, etc. A deposition ion implantation method or the like can be used.

[0175] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0176] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0177] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0178] The transistor of one embodiment of the present invention is shown in FIG. 18(C) and (D) are cross-sectional views in the channel length direction and the channel width direction, respectively. As shown in the cross-sectional view of the first embodiment, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 119. By using the conductive layer as a second gate electrode layer (back gate), It is possible to increase the on-state current and control the threshold voltage. In the cross-sectional views shown in (C), (D), (E), and (F), the width of the conductive layer 173 is set to 0.1 mm. The conductive layer 173 may be shorter than the conductive layer 130. may also be shortened.

[0179] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0180] In the transistors 101 to 106 in FIG. 16 and FIG. 17, an oxide semiconductor Although an example in which the conductor layer 130 is a single layer is illustrated, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 20C or the oxide semiconductor layer 130 shown in FIG. 20D or FIG. 20E. Cut.

[0181] FIG. 20A is a top view of the oxide semiconductor layer 130, and FIGS. 20B and 20C are top views of the oxide semiconductor layer 130 having a two-layer structure. 20(D) and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0182] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0183] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 21(A) is a top view of the transistor 107, and the dashed line H1-H The cross sections in the two directions correspond to FIG. 21(B). Also, the dashed line H3-H4 shown in FIG. 23(A) corresponds to the cross section in the direction. Also, the dashed line H1-H2 direction corresponds to the channel length direction. The direction of the dashed dotted line H3-H4 is referred to as the channel width direction.

[0184] The transistor 107 includes an insulating layer 120 in contact with a substrate 119 and an oxide semiconductor layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0185] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0186] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 21(C) is a top view of the transistor 108, and the dashed line I1-I The cross sections in the two directions correspond to FIG. 21(D). Also, the dashed line I3-I4 shown in FIG. 23B. The direction of the dashed dotted line I1-I2 corresponds to the channel length direction. The direction of the dashed dotted line I3-I4 is referred to as the channel width direction.

[0187] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0188] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 21(E) is a top view of the transistor 109, and the dashed line J1-J shown in FIG. The cross sections in the two directions correspond to FIG. 21(F). Also, the dashed line J3-J4 shown in FIG. 21(E) 23A. The dashed line J1-J2 direction corresponds to the channel length direction. The direction of the dashed dotted line J3-J4 is referred to as the channel width direction.

[0189] The transistor 109 includes an insulating layer 120 in contact with a substrate 119 and an oxide semiconductor layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0190] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0191] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 22(A) is a top view of the transistor 110, and the dashed line K1-K The cross sections in the two directions correspond to FIG. 22(B). Also, the dashed line K3-K4 shown in FIG. 23A. The direction of the dashed line K1-K2 corresponds to the channel length direction. The direction of the dashed dotted line K3-K4 is referred to as the channel width direction.

[0192] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0193] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 22(C) is a top view of the transistor 111, and the dashed line L1-L The cross sections in the two directions correspond to FIG. 22(D). Also, the dashed line L3-L4 shown in FIG. 22(C) 23(A) corresponds to the cross section in the direction of the dashed dotted line L1-L2. The direction of the dashed dotted line L3-L4 is referred to as the channel width direction.

[0194] The transistor 111 includes an insulating layer 120 in contact with a substrate 119 and an oxide semiconductor layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0195] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0196] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 22(E) is a top view of the transistor 112, and the dashed line M1-M The cross sections in the two directions correspond to FIG. 22(F). Also, the dashed line M3-M4 shown in FIG. 22(E) 23A. The direction of the dashed dotted line M1-M2 corresponds to the channel length direction. The direction of the dashed dotted line M3-M4 is referred to as the channel width direction.

[0197] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0198] The transistor of one embodiment of the present invention is shown in FIG. 23(C) and (D) are cross-sectional views in the channel length direction and the channel width direction, respectively. As shown in the cross-sectional view of the first embodiment, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 119. The conductive layer may be used as a second gate electrode layer (back gate). It is possible to increase the on-current and control the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0199] The transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 25(A) is a top view, and FIG. 25(B) is a diagram showing the structure of the dotted line shown in FIG. 25(A). 25(C) is a cross-sectional view corresponding to the dashed line N3 shown in FIG. 25(A). In addition, in the top view of FIG. 25(A), for clarity of the drawing, Some elements are omitted in the figure.

[0200] In the transistor 113, the oxide semiconductor layer 130c and the insulating layer 160 are The transistor 111 has a structure similar to that of the transistor 111 except that the insulating layer 112 covers the conductive layer 151 . With this configuration, the oxide semiconductor layer 130c acts as a blocking layer and provides insulation. Impurities such as hydrogen, water, and halogens diffuse from the layer 175 into the oxide semiconductor layer 130b. Note that the structure of the transistor 113 is the same as that of one embodiment of the present invention. The present invention can also be applied to transistors having any of the configurations.

[0201] As shown in the cross-sectional views of FIGS. 25D and 25E, the oxide semiconductor layer 130 and the substrate 119 A conductive layer 173 that functions as a second gate electrode layer (back gate) is provided between the first gate electrode 172 and the second gate electrode 173. Good too.

[0202] The transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 26(A) is a top view, and FIG. 26(B) is a diagram showing the structure of the dotted line shown in FIG. 26(A). 26(C) is a cross-sectional view corresponding to O1-O2, and FIG. 26(C) is a cross-sectional view corresponding to the dashed line O3 shown in FIG. 26(A) is a cross-sectional view corresponding to -O4. Note that in the top view of FIG. Some elements are omitted in the figure.

[0203] The transistor 114 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, a conductive layer 14 1 and the side of the conductive layer 151 are not in contact with the insulating layer 175. 11. That is, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b The sides of the conductive layer 141 and the conductive layer 151 are in contact with the insulating layer 180 .

[0204] By adopting this configuration, the effect of preventing oxidation of the conductive layer 170 by the insulating layer 175 is maintained. Therefore, oxygen contained in the insulating layer 180 can be efficiently supplied to the oxide semiconductor layer 130b. .

[0205] As shown in the cross-sectional views of FIGS. 26D and 26E, the oxide semiconductor layer 130 and the substrate 119 A conductive layer 173 that functions as a second gate electrode layer (back gate) is provided between the first gate electrode 172 and the second gate electrode 173. Good too.

[0206] The transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 27(A) is a top view, and FIG. 27(B) is a diagram showing the structure of the dotted line shown in FIG. 27(A). FIG. 27(C) is a cross-sectional view corresponding to P1-P2, and FIG. 27(A) shows a cross-sectional view of the dashed line P3 27(A) is a cross-sectional view corresponding to -P4. Some elements are omitted in the figure.

[0207] The transistor 115 shown in FIGS. 27A, 27B, and 27C includes a substrate 119 and a The insulating layer 120 on the upper side and the oxide semiconductor layer 130 on the insulating layer 120 (the oxide semiconductor layer 130a , oxide semiconductor layer 130b, oxide semiconductor layer 130c), and , the conductive layer 140 and the conductive layer 150 arranged at an interval, and the oxide semiconductor layer 130c The insulating layer 160 is in contact with the insulating layer 160, and the conductive layer 170 is in contact with the insulating layer 160. The conductor layer 130c, the insulating layer 160 and the conductive layer 170 are formed on the insulating layer 1 on the transistor 115. 90, openings reaching the oxide semiconductor layer 130a and the oxide semiconductor layer 130b The insulating layer 190 is formed of the same material as the insulating layer 180. It is possible.

[0208] The configuration of transistor 115, compared to the other transistor configurations described above, has a source Or, since the overlapping area between the drain conductor and the gate conductor is small, parasitic Therefore, the transistor 115 is required to operate at high speed. The transistor 115 is suitable as an element of a circuit for implementing the above-mentioned method. Chemical Mechanical Polishing (CMP) method is used. It is preferable to flatten the surface of the substrate by the flattening process, but it is also possible to adopt a structure in which the flattening process is not performed.

[0209] As shown in the cross-sectional views of FIGS. 27D and 27E, the oxide semiconductor layer 130 and the substrate 119 A conductive layer 173 that functions as a second gate electrode layer (back gate) is provided between the first gate electrode 172 and the second gate electrode 173. Good too.

[0210] The transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 28(A) is a top view, and FIG. 28(B) is a diagram showing the structure of the dotted line shown in FIG. 28(A). FIG. 28(C) is a cross-sectional view corresponding to Q1-Q2, and FIG. 28(A) shows the dashed line Q3 28(A) is a cross-sectional view corresponding to -Q4. Note that in the top view of FIG. 28(A), Some elements are omitted in the figure.

[0211] The transistor 116 includes an insulating layer 120, an oxide semiconductor layer 130a, and an oxide semiconductor layer 130b. b. The oxide semiconductor layer 130c, the conductive layer 140, and the conductive layer 150 are in contact with the oxide semiconductor layer 130c. A conductor layer 130d is formed and is connected to the oxide semiconductor layer 130c and the oxide semiconductor layer 130d. The transistor has a similar structure to the transistor 115, except that an insulating layer 190 is formed so as to The oxide semiconductor layer 130d may be formed of the same material as the oxide semiconductor layer 130c. With this structure, the oxide semiconductor layer 130d can be used as a blocking layer. impurities such as hydrogen, water, and halogen from the insulating layer 190 to the oxide semiconductor layer Diffusion to 130b can be suppressed.

[0212] As shown in the cross-sectional views of FIGS. 28D and 28E, the oxide semiconductor layer 130 and the substrate 119 A conductive layer 173 that functions as a second gate electrode layer (back gate) is provided between the first gate electrode 172 and the second gate electrode 173. Good too.

[0213] The transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 29(A) is a top view, and FIG. 29(B) is a diagram showing the structure of the dotted line shown in FIG. 29(A). FIG. 29(C) is a cross-sectional view corresponding to R1-R2, and FIG. 29(A) shows the dashed line R3 In addition, in the top view of FIG. 29(A), for clarity of the drawing, Some elements are omitted in the figure.

[0214] The transistor 117 includes an oxide semiconductor layer 130c, an insulating layer 160, a conductive layer 170, and an insulating The transistor 115 and the transistor 116 are the same except that an insulating layer 191 is provided over the border layer 190. The insulating layer 191 has a similar structure. For example, the insulating layer 175 may be made of the same material. This structure can prevent the conductive layer 170 from being oxidized. In addition, oxygen contained in the insulating layer 190 can be efficiently supplied to the oxide semiconductor layer 130b. do.

[0215] As shown in the cross-sectional views of FIGS. 29D and 29E, the oxide semiconductor layer 130 and the substrate 119 A conductive layer 173 that functions as a second gate electrode layer (back gate) is provided between the first gate electrode 172 and the second gate electrode 173. Good too.

[0216] The conductive layer 140 (source electrode layer) and the conductive layer 15 in the transistor according to one embodiment of the present invention 0 (drain electrode layer) is the top view shown in FIG. 30 (oxide semiconductor layer 130, As shown in FIG. 1, only the conductive layer 140 and the conductive layer 150 are shown. O S ) of the conductive layer 140 and the conductive layer 150. SD ) may be formed long However, it may be formed short. OS ≧W SD (W SD W OS (below) The gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor are improved. As shown in FIG. 30(C), the conductive layer 140 and the conductive layer The insulating film 150 may be formed only in the region overlapping with the oxide semiconductor layer 130 .

[0217] In the transistors of one embodiment of the present invention (transistors 101 to 114), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0218] A transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, and The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are included. In the transistor, the material of the two-layer or three-layer that constitutes the oxide semiconductor layer 130 is appropriately By appropriately selecting the oxide semiconductor layer 130b, a current can be passed through the oxide semiconductor layer 130b. By passing current through 130b, the effect of interface scattering is reduced and a high on-current can be obtained. Therefore, the on-current can be improved by thickening the oxide semiconductor layer 130b. There is a match.

[0219] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0220] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0221] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0222] The substrate 119 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A metal substrate with a surface treatment can be used. Alternatively, a transistor or a photodiode can be used. A silicon substrate on which a metal oxide film is formed, and an insulating layer, wiring, contact plug, etc. are formed on the silicon substrate. A conductive material having a function as a guide may be used. When forming a p-ch type transistor on the substrate, n - Silicon substrate having a conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-ch transistor on the (110) surface to increase the mobility. It is possible.

[0223] The insulating layer 120 serves to prevent the diffusion of impurities from elements contained in the substrate 119. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. For example, the surface temperature of the film is 100° C. or more and 700° C. or less. In the TDS method, which is preferably performed by heat treatment at 100°C to 500°C, The converted oxygen release rate is 1.0 x 10 19 atoms / cm 3 The membrane is as above. In the case where the substrate 119 is a substrate on which other devices are formed, the insulating layer 120 is an interlayer insulating film. In that case, planarization processing such as CMP is performed to make the surface flat. It is preferable to do so.

[0224] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0225] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The organic semiconductor layer 130c can be stacked in order from the insulating layer 120 side to form a three-layer structure.

[0226] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0227] When the oxide semiconductor layer 130 has two layers, the layer corresponding to the oxide semiconductor layer 130a and the oxide A lamination structure in which layers corresponding to the organic semiconductor layer 130b are stacked in order from the insulating layer 120 side may be used. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can be interchanged. It is also possible.

[0228] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). A compound semiconductor is used.

[0229] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that the nucleus has a region that functions in a specific manner.

[0230] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are The oxide semiconductor that can be used preferably contains at least In or Zn. Alternatively, it is preferable that both In and Zn are contained. In order to reduce the variation in the electrical characteristics of the transistors, Al, Ga, Y, or It is preferable to include a stabilizer such as Sn.

[0231] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0232] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and a single layer or a laminate of a material selected from the group consisting of an alloy of said metallic material and a conductive nitride. In addition, a laminate of low-resistance Cu or Cu-Mn alloy and the above materials can be used. The transistor 105, the transistor 106, the transistor 111, and the transistor In the transistor 112, for example, the conductive layer 141 and the conductive layer 151 are made of W, and the conductive layer 14 2 and the conductive layer 152 may be a laminated film of Ti and Al, for example.

[0233] The above material has a property of extracting oxygen from the oxide semiconductor layer. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0234] When W is used for the conductive layer 140 and the conductive layer 150, they may be doped with nitrogen. By doping with nitrogen, the oxygen-pulling property can be weakened to an appropriate degree, resulting in an n-type structure. In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding into the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer is in contact with the oxide semiconductor layer. This also makes it possible to prevent the n-type region from expanding into the channel region. For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, and indium oxide were used. Indium, tin oxide, indium tin oxide, etc. can be used.

[0235] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0236] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0237] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0238] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0239] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 cm -3 5×10 or more 19 cm -3 The amount of ammonia released is as follows: The surface temperature is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. The amount of release is the amount of

[0240] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0241] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine atom.

[0242] The conductive layer 170 may be made of In-Ga-Zn oxide, zinc oxide, indium oxide, or tin oxide. Alternatively, a conductive oxide layer such as indium tin oxide may be used.

[0243] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0244] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. .

[0245] An insulating layer 180 is preferably formed on the insulating layer 175. The insulating layer 180 may include an oxide. magnesium oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide The insulating film contains one or more of neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0246] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0247] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. The electrical characteristics of transistors tend to deteriorate as the channel width decreases. If the on-state current is increased, the on-state current decreases.

[0248] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0249] As described above, in the transistor of one embodiment of the present invention, the channel width of the oxide semiconductor layer 130 is Since the gate electrode layer (conductive layer 170) is formed so as to electrically surround the In addition to the gate electric field from the direction perpendicular to the top surface of the compound semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is also applied to the compound semiconductor layer 130. In other words, the gate electric field is applied from the entire direction to the channel forming layer. Since a large electric field is applied, the effective channel width is enlarged, and the on-current is further increased. can be.

[0250] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically The thin film can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atom These include the ic Layer Deposition method.

[0251] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0252] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0253] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0254] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0255] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0256] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0257] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0258] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0259] For example, an oxide semiconductor layer, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming an In-O layer, In(CH3)3 gas and O3 gas are introduced in sequence to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. Alternatively, a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer may be formed. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0260] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using a facing target sputtering device is called VDSP (vapor deposition sputtering). It can also be called the "Synopsis of the Transformation SP."

[0261] By forming an oxide semiconductor layer using a facing target sputtering apparatus, This reduces plasma damage during the deposition of the semiconductor layer. In addition, by using a facing target sputtering device, low pressure Since it is possible to form the oxide semiconductor layer at low temperature, the impurity concentration (e.g., hydrogen, dilute Gases (such as argon), water, etc.) can be reduced.

[0262] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0263] (Embodiment 4) In this embodiment, a material of an oxide semiconductor that can be used in one embodiment of the present invention will be described. Reveal.

[0264] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0265] Here, a case where the oxide semiconductor contains indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, etc. Other elements Applicable elements for M include boron, silicon, titanium, iron, nickel, and germanium. , Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum, Tungsten, magnesium, etc. However, the element M can be a combination of multiple of the above elements. There are cases where it is okay to match them.

[0266] First, with reference to FIG. 31(A), FIG. 31(B), and FIG. 31(C), the oxide according to the present invention A preferred range of the atomic ratio of indium, element M, and zinc contained in the semiconductor will be explained. Note that the atomic ratio of oxygen is not shown in FIG. The atomic ratios of indium, element M, and zinc are [In], [M], and Let it be [Zn].

[0267] In Figures 31(A), 31(B), and 31(C), the dashed lines indicate [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2, [I n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio line, and [ This line represents the atomic ratio of In:M:Zn=(1+α):(1-α):5. .

[0268] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atoms The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents the

[0269] In addition, the atomic ratio of [In]:[M]:[Zn]=0:2:1 or close to it, as shown in FIG. The oxide semiconductors in question tend to have a spinel type crystal structure.

[0270] 31A and 31B show the indium-ion doped oxide semiconductor of one embodiment of the present invention. 1 shows an example of a preferable range of the atomic ratio of element M, element C, and zinc.

[0271] As an example, FIG. 32 shows InMZnO, where [In]:[M]:[Zn]=1:1:1. 4. Also, FIG. 32 shows the crystal structure of InMZn The crystal structure of the layer having M, Zn, and oxygen shown in FIG. The metal element in layer n) represents element M or zinc. In this case, element M and zinc The ratio of elements M and zinc is equal. The elements M and zinc can be substituted, and the arrangement is random. .

[0272] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 32. The layer containing indium and oxygen (hereinafter referred to as the In layer) is 1, while the element M, zinc, and The (M,Zn) layer containing oxygen is called 2.

[0273] Indium and the element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, the In layer It has a layered structure with one layer and two (In,M,Zn) layers.

[0274] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is For [In] and [M], the (M,Zn) layer is three. When [Zn] is large, when the oxide semiconductor crystallizes, the (M,Zn ) layer increases.

[0275] However, in the oxide semiconductor, the number of (M, Zn) layers for one In layer is a non-integer. In this case, multiple types of layered structures are used, each with an In layer and an integer number of (M, Zn) layers. For example, when [In]:[M]:[Zn]=1:1:1.5, A layered structure with 1 In layer and 2 (M,Zn) layers, and a layered structure with 3 (M,Zn) layers. In some cases, the resulting structure may be a layered structure in which a crystalline structure and a crystalline structure are mixed.

[0276] For example, when forming an oxide semiconductor film using a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the ratio of the number of atoms in the target may change. [Zn] of the film may be smaller than [Zn].

[0277] In addition, multiple phases may coexist in an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In this case, two phases, a spinel type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, In oxide semiconductors, two phases, a cubic crystal structure and a layered crystal structure, tend to coexist. When they coexist, grain boundaries form between the different crystal structures. It may be formed.

[0278] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor is improved. This is an oxide semiconductor having indium, element M, and zinc. In the body, the s-orbitals of heavy metals are mainly responsible for carrier conduction, and the indium content is By increasing the concentration, the area where the s orbitals overlap becomes larger, so the indium content Oxide semiconductors with a high indium content have higher carrier mobility than oxide semiconductors with a low indium content. This is because it will be more expensive.

[0279] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and In the atomic ratio having a value close to 0.01 (for example, region C shown in FIG. 31C), the insulating property becomes high.

[0280] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio shown in region A in FIG. 31(A) is such that a layered structure is easily formed. stomach.

[0281] Also, in region B shown in FIG. 31(B), [In]:[M]:[Zn]=4:2:3 to 4. 1 and its neighboring values. For example, the atomic ratio [In]:[M] :[Zn]=5:3:4. The oxide semiconductor having the atomic ratio shown in region B is In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0282] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. The illustrated region is a region showing an atomic ratio in which the oxide semiconductor has a layered structure. The boundaries between areas A and C are not strict.

[0283] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0284] By using the oxide semiconductor in a transistor, carrier scattering at grain boundaries can be prevented. This allows the realization of transistors with high field effect mobility. In addition, a highly reliable transistor can be realized.

[0285] In addition, it is preferable to use an oxide semiconductor with low carrier density for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That should be enough.

[0286] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. Since the carrier density can be reduced, the high purity intrinsic or substantially high purity Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0287] In addition, it takes a long time for the charges trapped in the trap states of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0288] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the adjacent film. These include potassium metal, alkaline earth metals, iron, nickel, silicon, etc.

[0289] Here, the influence of each impurity in an oxide semiconductor will be described.

[0290] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, it becomes an oxide. Defect levels are formed in the semiconductor. This causes the silicon and carbon in the oxide semiconductor to The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( By SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0291] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may form carriers. A transistor using an oxide semiconductor containing such a metal oxide tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, the alkali metal or alkali metal in the oxide semiconductor obtained by SIMS is preferably The concentration of alkaline earth metals is increased by 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 To the following:

[0292] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using this oxide semiconductor is likely to be normally on. For example, the nitrogen concentration in the oxide semiconductor is The degree is 5×10 in SIMS. 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following is further Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0293] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, it is necessary to use an oxide semiconductor that contains hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that the SIM is reduced as much as possible. The hydrogen concentration obtained by S is 1×10 20 atoms / cm 3 Less than 1x1 0 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than, More preferably, 1×10 18 atoms / cm 3 Less than.

[0294] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor Thus, stable electrical characteristics can be imparted.

[0295] Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A stacked structure of a semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3, and The band diagram of the adjacent insulator, the stacked structure of the oxide semiconductor S2 and the oxide semiconductor S3, and The band diagram of the insulator in contact with the laminated structure will be explained with reference to FIG. The oxide semiconductor S1 is the oxide semiconductor layer 130a, and the oxide semiconductor S2 is the oxide semiconductor layer 130b. The oxide semiconductor S3 corresponds to the oxide semiconductor layer 130c.

[0296] FIG. 33A shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3. FIG. 33( B) is a multilayer structure having an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. 1 is an example of a band diagram in the thickness direction of a layer structure. Note that the band diagram is shown in insulating form for ease of understanding. The insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2 The energy level (Ec) at the bottom of the conduction band is shown.

[0297] The oxide semiconductors S1 and S3 have a lower energy of the conduction band than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level at the bottom of the conduction band of the oxide semiconductor S1 and the oxide semiconductor S3 is 0. 15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less In other words, the oxide semiconductor S1 has a higher electron affinity than the oxide semiconductor S3. The electron affinity of the semiconductor S2 is large, and the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 are , the difference between the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more, It is also preferable that the electron transport potential is 2 eV or less, or 1 eV or less.

[0298] As shown in FIG. 33(A) and FIG. 33(B), an oxide semiconductor S1, an oxide semiconductor S2 In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. Then, it can be said that the band changes continuously or that the junction is continuous. In order to have such a property, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor S The defect level density of the mixed layer formed at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is reduced. stomach.

[0299] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S 3) A mixture with a low defect level density due to the common element (main component) other than oxygen. For example, the oxide semiconductor S2 may be an In-Ga-Zn oxide semiconductor. In this case, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors, It is preferable to use a Ga-Zn oxide semiconductor, gallium oxide, or the like.

[0300] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with the semiconductor S2 and at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0301] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level can be moved away from the oxide semiconductor S2. By adopting this configuration, the threshold voltage of the transistor is shifted in the positive direction. This can prevent the above from happening.

[0302] The oxide semiconductors S1 and S3 have sufficiently high electrical conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S1 are used. The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the interface between the oxide semiconductor S3 and the channel region are mainly For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following structure: Therefore, it is sufficient to use an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high. Region C shown in 1(C) is [In]:[M]:[Zn]=0:1:0 or its neighboring values. The atomic ratio is shown as:

[0303] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, In the compound semiconductor S1 and the oxide semiconductor S3, [M] / [In] is 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor having a sufficient conductivity as the oxide semiconductor S3. An oxide semiconductor with a high insulating property, [M] / ([Zn]+[In]) of 1 or more, is used. It is preferable to use a conductor.

[0304] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0305] (Embodiment 5) A structure of an oxide semiconductor that can be used in one embodiment of the present invention will be described below.

[0306] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0307] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0308] Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned (CAAC-OS) crystalline oxide semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor and amorphous oxide semiconductor. do.

[0309] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- Examples of such materials include OS, polycrystalline oxide semiconductors, and nc-OS.

[0310] Amorphous structures are generally isotropic, have no inhomogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and the short-range order is not fixed. It is said that...

[0311] That is, the stable oxide semiconductor is transformed into a completely amorphous In addition, it is not isotropic (for example, it does not have a periodic structure in a small region). On the other hand, an oxide semiconductor having an a-li structure cannot be called a completely amorphous oxide semiconductor. The ke OS is not isotropic, but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0312] First, let me explain about CAAC-OS.

[0313] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0314] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. As shown in FIG. 34(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the upper surface. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the center are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not show such a peak.

[0315] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is assigned to the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. Even if the measurement is performed, no clear peak appears as shown in FIG. When φ is scanned with 2θ fixed at around 56° for nO4, as shown in Figure 34(C). As shown in Fig. 1, six peaks are observed that are attributable to crystal planes equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0316] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the CAAC-OS surface. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in FIG. This is also called the limited-area electron diffraction pattern.) may appear. This diffraction pattern includes In The spots are due to the (009) plane of the GaZnO4 crystal. In some cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the material is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident vertically is shown in Figure 34(E). A ring-shaped diffraction pattern is confirmed in FIG. 34(E). Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the pellets in the CAAC-OS It can be seen that the a-axis and b-axis of the slit have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is considered that the second ring in Figure 34(E) is due to the (110) plane, etc. It is possible.

[0317] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. In some cases, it may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0318] Figure 35(A) shows a high-resolution T The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, the atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that.

[0319] From FIG. 35(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned nan The pellets are also called oxide semiconductors with CAAC -OS surface or top surface unevenness, and CAAC-OS surface or top surface unevenness is parallel to the surface.

[0320] In addition, Fig. 35(B) and Fig. 35(C) show CAAC images observed from a direction approximately perpendicular to the sample surface. 35(D) and 35(E) show Cs-corrected high-resolution TEM images of the -OS plane. These are images obtained by processing the images of Figures 35(B) and 35(C), respectively. First, the method of performing the fast Fourier transform (FFT) on FIG. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the FFT image, the origin is used as the reference point, and the distance is 2.8 nm. -1 From 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT: Inverse Fast Fourier Transform (IFFT) processing is used to The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0321] In FIG. 35(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the dashed line is the connection between the pellets. The broken line indicates a hexagonal shape, so it can be seen that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0322] In FIG. 35(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different lattice arrangement. Even in the vicinity of the dotted line, no clear grain boundaries can be confirmed. When you connect the neighboring lattice points, you can get a distorted hexagon, pentagon, or / and heptagon. In other words, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. This is because the arrangement of oxygen atoms in the ab-plane direction of CAAC-OS is Due to the lack of density and the change in the bond distance between atoms due to the substitution of metal elements, It is believed that this is because distortion can be tolerated.

[0323] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an ane-anchored crystal. do.

[0324] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. CAAC-OS is a material that can be degraded by impurities and defects ( It can also be said that the oxide semiconductor has few oxygen vacancies.

[0325] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0326] Next, we will explain nc-OS.

[0327] The following describes the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of the nc-OS do not have any orientation.

[0328] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region shown in FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nm) when an electron beam with a probe diameter of 1 nm was incident on the same sample was The electron diffraction pattern (BEM pattern) is shown in FIG. 36(B). From FIG. 36(B), a ring-shaped region Therefore, nc-OS has a probe diameter of 50 nm. Although no order was observed by irradiating the electron beam, the order was observed by irradiating the electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0329] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 36(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals have highly crystalline regions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0330] FIG. 36(D) shows the Cs-corrected high resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. As shown in Fig. 1, there are areas where crystals can be confirmed, and areas where no clear crystals can be confirmed. The crystal part in the nc-OS has a size of 1 nm to 10 nm. In particular, the size of the crystal part is often between 1 nm and 3 nm. An oxide semiconductor having a diameter of more than 0 nm and less than 100 nm is called a microcrystalline oxide semiconductor. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be called a pellet.

[0331] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0332] In addition, since the crystal orientation between pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor can be called an oxide semiconductor.

[0333] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0334] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0335] Figure 37 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 Electrons (e - ) High a-like OS after irradiation 37(A) and 37(B) show that the a-like OS It can be seen that from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. It can be seen that the shape of the bright regions changes after electron irradiation. It is estimated to be in the degree range.

[0336] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0337] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0338] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0339] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that the structure has a total of nine layers, including six O layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. In the figure below, the areas where the lattice spacing is between 0.28 nm and 0.30 nm are InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0340] Figure 38 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 38, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was a nucleus (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the nc The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from The size of the crystalline parts of the nc-OS and CAAC-OS was The results show that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. Electron beam irradiation conditions The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0341] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. That is, compared with the nc-OS and CAAC-OS, the a-like OS It is clear that this is an unstable structure.

[0342] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0343] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0344] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions. The density can be estimated by using a weighted average. It is preferable to estimate them together.

[0345] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0346] Next, the carrier density of an oxide semiconductor will be described below.

[0347] Factors that affect the carrier density in oxide semiconductors include oxygen vacancies in the oxide semiconductor ( Vo), or impurities in the oxide semiconductor.

[0348] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen bonds to the oxygen vacancies (this state is called VoH). When the oxide semiconductor is heated, the density of defect states increases. When the impurities are added, the density of defect states increases. By controlling the potential density, the carrier density of the oxide semiconductor can be controlled.

[0349] Here, a transistor in which an oxide semiconductor is used for a channel region will be considered.

[0350] Suppression of negative shift of the threshold voltage of a transistor or suppression of the off-state current of a transistor In order to reduce the carrier density, it is preferable to reduce the carrier density of the oxide semiconductor. In order to reduce the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor is In this specification and the like, the impurity concentration is low and the defect level density is low. A low density of recessed states is called high purity intrinsic or substantially high purity intrinsic. The carrier density of semiconductors is 8×10 15 cm -3 Less than 1 x 10 11 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm- 3 That should be enough.

[0351] On the other hand, the improvement of the on-state current of a transistor or the field effect mobility of a transistor In this case, it is preferable to increase the carrier density of the oxide semiconductor. In order to increase the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor is slightly Alternatively, the defect state density of the oxide semiconductor may be increased slightly. It is better to make the band gap of the semiconductor smaller. For example, the Id-Vg In the range where the on / off ratio of the characteristic can be obtained, the impurity concentration is slightly high or the defect level Oxide semiconductors with slightly higher density can be considered essentially intrinsic. As a result, the band gap becomes smaller, and the thermally excited electrons (capacitors) The oxide semiconductor with an increased density of valence oxides can be considered to be essentially intrinsic. When an oxide semiconductor with high resistance is used, the threshold voltage of a transistor is lowered. .

[0352] The oxide semiconductor with the increased carrier density is slightly n-type. An oxide semiconductor with an increased carrier density may be called a "slightly-n" oxide semiconductor. stomach.

[0353] The carrier density of a substantially intrinsic oxide semiconductor is 1×10 5 cm -3 More than 1×10 18 c m -3 Less than 1×10 is preferable. 7 cm -3 More than 1×10 17 cm -3 The following is preferred: 1×10 9 cm -3 5×10 or more 16 cm -3 More preferably, 1×10 10 cm -3 More than 1×10 16 cm -3 More preferably, 1×10 11 cm -3 1 more ×10 15 cm -3 The following is even more preferred:

[0354] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0355] (Embodiment 6) The following describes a CAC (Cl This paper explains the configuration of the 3G-OS (3G-Aligned Composite).

[0356] CAC-OS is, for example, an oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region having the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixture of particles with sizes of 2 nm or more or less, or close to that size, in a mosaic or patch pattern It is also called.

[0357] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more of the following: tantalum, tungsten, or magnesium. It may be included.

[0358] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide is one of the CAC-OS) a-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0.) or indium zinc oxide compound (hereinafter referred to as In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0) . ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into a mosaic shape. Mosaic InO X1 , or In X2 Zinc Y2 O Z2 was distributed uniformly in the film. This is a cloud-like configuration.

[0359] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than in region 2.

[0360] IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of the crystalline compounds include those which are

[0361] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0362] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. In a material composition containing a, Zn, and O, some of the nanoparticles are observed to be mainly composed of Ga. The regions where the In nanoparticles are observed are the same as those where the In nanoparticles are observed as the main component. This refers to a structure in which the crystals are randomly distributed in a mosaic pattern. Structure is a secondary factor.

[0363] It should be noted that the CAC-OS does not include a laminated structure of two or more films having different compositions. For example, a structure consisting of two layers, a film mainly made of In and a film mainly made of Ga, is not included. do not have.

[0364] In addition, GaO X3 The region where In is the main component and X2 ZincY2 O Z2 , or InO X1 but In some cases, a clear boundary between the region of the main component and the region of the main component may not be observed.

[0365] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected types of sodium, etc. are included, CAC-OS will The region observed is a nanoparticle of the metal element as the main component, and the region observed is a nanoparticle of In as the main component. The nanoparticle-like regions are randomly distributed in a mosaic pattern. say.

[0366] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas and The gas to be used should be selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. In addition, the ratio of oxygen gas to the total flow rate of the deposition gas during deposition may be For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is preferable that the content be 0% or more and 10% or less.

[0367] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, no clear peaks are observed in the measurement region from the X-ray diffraction. It can be seen that no orientation in the ab plane direction or the c-axis direction is observed.

[0368] In addition, the CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nano-beam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample with electrons, a ring-shaped region of high brightness and the Therefore, the electron diffraction pattern indicates that the CAC-OS The crystal structure has no orientation in the planar and cross-sectional directions. It can be seen that it has a crystal structure.

[0369] For example, in the case of CAC-OS made of In-Ga-Zn oxide, energy dispersive X-ray Spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) The EDX mapping obtained using a GaO X3 The region where is the main component and , In X2 Zinc Y2 O Z2 , or InO X1 The areas where the main component is It can be confirmed that the compound has the structure shown in FIG.

[0370] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from ZO compounds. That is, CAC-OS is GaO X3 The main ingredients are In a certain area, X2 Zinc Y2 O Z2 , or InO X1 The region where is the main component and The phase is separated into two layers, and the regions each containing one element as a main component are arranged in a mosaic pattern.

[0371] Here, In X2 Zinc Y2 O Z2, or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y 2O Z2 , or InO X1 The carriers flow through the area where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zinc Y2 O Z2 , or InO X The region where 1 is the main component is distributed in a cloud-like shape in the oxide semiconductor, which results in a high electric field effect. Mobility (μ) can be achieved.

[0372] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching performance. Switching operation can be achieved.

[0373] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by In X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) can.

[0374] In addition, semiconductor devices using CAC-OS have high reliability. It is ideal for a variety of semiconductor devices, including displays.

[0375] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0376] (Embodiment 7) In this embodiment, a package containing an image sensor chip and a camera module An example will be described. The image sensor chip has a structure of an imaging device according to one embodiment of the present invention. The composition can be used.

[0377] FIG. 39(A) is a perspective view showing the appearance of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 810 for fixing an image sensor chip 850, a cover It has a bar glass 820 and an adhesive 830 for bonding the two together.

[0378] FIG. 39(B) is a perspective view of the bottom surface of the package. The structure of BGA (Ball grid array) with solder balls as bumps 840 is used. In addition to BGA, LGA (Land grid array) and PGA (P in Grid Array) etc.

[0379] FIG. 39(C) shows a package in which the cover glass 820 and part of the adhesive 830 are omitted. FIG. 39(D) is a cross-sectional view of the package. Package substrate An electrode pad 860 is formed on the substrate 810, and the electrode pad 860 and the bump 840 are The electrode pad 860 is electrically connected to the electrode pad 860 via a hole 880 and a land 885. is electrically connected to the electrodes of the image sensor chip 850 by wires 870. is.

[0380] FIG. 40(A) shows a camera in which an image sensor chip is housed in a lens-integrated package. FIG. 1 is a perspective view of the appearance of the upper surface side of a camera module. A package substrate 811 that fixes the cap 851, a lens cover 821, and a lens 835 In addition, between the package substrate 811 and the image sensor chip 851, An IC chip 890 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0381] FIG. 40B is a perspective view showing the appearance of the lower surface side of the camera module. The bottom surface and four side surfaces of the package 11 are provided with lands 841 for mounting. The structure is a lat no-lead package. Note that this structure is just an example. It can be QFP (Quad flat package) or the BGA mentioned above. stomach.

[0382] FIG. 40C shows a module with the lens cover 821 and a portion of the lens 835 omitted. FIG. 40(D) ​​is a cross-sectional view of the camera module. A part of the electrode pad 861 is used as the image sensor chip. The electrodes of the chip 851 and the IC chip 890 are electrically connected by wires 871. is.

[0383] By housing the image sensor chip in a package of the above type, mounting becomes easy. Therefore, the present invention can be incorporated into various semiconductor devices and electronic devices.

[0384] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0385] (Embodiment 8) The imaging device, the display device, and the semiconductor device including both of the imaging device and the display device according to one embodiment of the present invention can be used. Examples of electronic devices that can be used include display devices, personal computers, and image storage devices equipped with recording media. image reproduction devices, mobile phones, portable game consoles, portable data terminals, e-book terminals Cameras such as video cameras and digital still cameras, goggle-type displays (head Mounted displays), navigation systems, audio playback devices (car audio, digital digital audio players, copiers, fax machines, printers, printer-combined machines, These include automated teller machines (ATMs) and vending machines. An example is shown in Figure 41.

[0386] FIG. 41(A) shows a surveillance camera having a housing 951, a lens 952, a support portion 953, etc. As one of the components for acquiring images in the surveillance camera, an imaging device according to one aspect of the present invention is used. The term "surveillance camera" is a common name and does not limit its use. For example, a device that has a function as a surveillance camera is a camera or a video camera. Also called La.

[0387] FIG. 41B shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring an image in the video camera, one aspect of the present invention is The imaging device may include:

[0388] FIG. 41C shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 63, a light emitting unit 967, a lens 965, etc. Acquire an image with the digital camera The imaging device according to one embodiment of the present invention can be provided as one of the components for performing the imaging.

[0389] FIG. 41D shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 has a time signal, ... A part for acquiring an image in the information terminal. The imaging device according to one embodiment of the present invention can be provided as an imaging device.

[0390] FIG. 41(E) shows a portable game machine, which includes a housing 901, a display unit 903, a microphone 905, and a speaker. The device includes a camera 906, operation keys 907, a stylus 908, and a camera 909. The portable game machine shown in 41(E) has only one display unit, The number of display units that the portable game machine has is not limited to this. The imaging device according to one embodiment of the present invention can be provided as one of the components for performing the imaging.

[0391] FIG. 41(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display portion 912 has a touch panel function through which data can be input and output. As one of the components for acquiring images in the portable data terminal, the imaging device according to one aspect of the present invention is The imaging device may be provided.

[0392] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0393] 11 Image sensor 12 A / D Converter 20 pixels 20a pixels 20b pixels 20c pixels 20h pixels 20i pixels 20j pixels 20k pixels 21 Pixel Array 23 Row Driver 24 Line Driver 25 Analog Switch 26 Current source circuit 28 Comparator 29 Counter Circuit 30 Terminals 31 Terminal 41 Transistor 42 Transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 47 Transistor 61 Wiring 61h Wiring 61i Wiring 61j Wiring 61k wiring 62 Wiring 63 Wiring 64 Conductive Layer 65 Wiring 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 81a Insulating layer 81b Insulating layer 81c Insulating layer 81d Insulating layer 81e Insulating layer 81f Insulating layer 81g Insulation layer 81h Insulation layer 81j Insulation layer 82 Conductors 83 Conductors 84 Conductive Layer 91 Wiring 92 Wiring 93 Wiring 94 Conductive Layer 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 114 Transistor 115 Transistor 116 Transistor 117 Transistor 119 Board 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 130d Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive Layer 143 areas 150 Conductive layer 151 Conductive layer 152 Conductive layer 153 areas 160 Insulating layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 191 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 500 Single crystal silicon substrate 510 areas 520 areas 530 areas 540 areas 545 areas 550 Conductive layer 560 Conductive Layer 600 Single crystal silicon substrate 660 Channel Formation Region 700 Shift Register 701 Wiring 702 Wiring 703 Wiring 704 Wiring 705 Wiring 710 Pulse output circuit 710_i Pulse output circuit 710_i-1 Pulse output circuit 710_n Pulse output circuit 710_1 Pulse output circuit 710_2 Pulse output circuit 711 Terminal 712 Terminal 713 Terminal 713_1 Terminal 714 Terminal 715 Terminal 715_n terminal 716 Terminals 721 Transistor 722 Transistor 724 Transistor 725 Transistors 726 Transistor 727 Transistor 728 Transistor 729 Transistor 731 Transistor 732 Transistor 733 Capacitive element 734 Capacitive element 741 Wiring 746 Wiring 761 nodes 762 nodes 763 nodes 810 Package Substrate 811 Package Substrate 820 Cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 rand 850 Image Sensor Chip 851 Image sensor chip 860 Electrode Pads 861 Electrode Pads 870 Wire 871 Wire 880 through hole 885 rand 890 IC chips 901 Case 903 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1300 layers 1400 layers 1530 Light blocking layer 1540 Microlens Array 1550a Optical conversion layer 1550b Optical conversion layer 1550c Optical conversion layer

Claims

1. a first layer having a first transistor; a second layer having a region disposed above the first layer and having a second transistor; a conductor penetrating the second layer and penetrating the interface between the first layer and the second layer; a first photodiode and a second photodiode having an area disposed above the second layer; an insulating layer having a region disposed above the first photodiode and having a region disposed above the second photodiode; a color filter having a region disposed above the insulating layer; a microlens array having an area disposed above the color filter; the first transistor, the first photodiode, and the second photodiode are included in a pixel array; the second transistor is included in a circuit that controls the pixel array; The conductor is electrically connected to the circuit, the conductor is disposed in an area that does not overlap with the microlens array, the insulating layer has a region disposed between the conductor and a single crystal silicon substrate on which the first photodiode and the second photodiode are formed; the insulating layer has a region disposed in a groove between the first photodiode and the second photodiode; The insulating layer comprises oxygen and hafnium. Imaging device.

2. a first layer having a first transistor; a second layer having a region disposed above the first layer and having a second transistor; a conductor penetrating the second layer and penetrating the interface between the first layer and the second layer; a first photodiode and a second photodiode having an area disposed above the second layer; an insulating layer having a region disposed above the first photodiode and having a region disposed above the second photodiode; a color filter and a light-shielding layer having an area disposed above the insulating layer; a microlens array having a region disposed above the color filter and a region disposed above the light-shielding layer; the first transistor, the first photodiode, and the second photodiode are included in a pixel array; the second transistor is included in a circuit that controls the pixel array; The conductor is electrically connected to the circuit, the conductor is disposed in an area that does not overlap with the microlens array, the insulating layer has a region disposed between the conductor and a single crystal silicon substrate on which the first photodiode and the second photodiode are formed; the insulating layer has a region disposed in a groove between the first photodiode and the second photodiode; The insulating layer comprises oxygen and hafnium. Imaging device.

3. a first layer having a first transistor; a second layer having a region disposed above the first layer and having a second transistor; a conductor penetrating the second layer and penetrating the interface between the first layer and the second layer; a first photodiode and a second photodiode having an area disposed above the second layer; an insulating layer having a region disposed above the first photodiode and having a region disposed above the second photodiode; a color filter having a region disposed above the insulating layer; a microlens array having an area disposed above the color filter; the first transistor, the first photodiode, and the second photodiode are included in a pixel array; the second transistor is included in a circuit that controls the pixel array; The conductor is electrically connected to the circuit, the conductor is disposed in an area that does not overlap with the microlens array, the insulating layer has a region disposed between the conductor and a single crystal silicon substrate on which the first photodiode and the second photodiode are formed; the insulating layer has a region disposed in a groove between the first photodiode and the second photodiode; the insulating layer includes a first insulating film and a second insulating film that are stacked together; the first insulating film contains oxygen and silicon; the second insulating film contains oxygen and hafnium; Imaging device.

4. a first layer having a first transistor; a second layer having a region disposed above the first layer and having a second transistor; a conductor penetrating the second layer and penetrating the interface between the first layer and the second layer; a first photodiode and a second photodiode having an area disposed above the second layer; an insulating layer having a region disposed above the first photodiode and having a region disposed above the second photodiode; a color filter and a light-shielding layer having an area disposed above the insulating layer; a microlens array having a region disposed above the color filter and a region disposed above the light-shielding layer; the first transistor, the first photodiode, and the second photodiode are included in a pixel array; the second transistor is included in a circuit that controls the pixel array; The conductor is electrically connected to the circuit, the conductor is disposed in an area that does not overlap with the microlens array, the insulating layer has a region disposed between the conductor and a single crystal silicon substrate on which the first photodiode and the second photodiode are formed; the insulating layer has a region disposed in a groove between the first photodiode and the second photodiode; the insulating layer includes a first insulating film and a second insulating film that are stacked together; the first insulating film contains oxygen and silicon; the second insulating film contains oxygen and hafnium; Imaging device.

Images