Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics, and a semiconductor device with stable electric characteristics.SOLUTION: A semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided on the semiconductor layer. The first conductive layer is provided on the first insulating layer. The semiconductor layer includes a first region overlapping with the first conductive layer and the first insulating layer, a second region not overlapping with the first conductive layer but overlapping with the first insulating layer, and a third region overlapping neither the first conductive layer nor the first insulating layer. The semiconductor layer contains metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium. The first element exists in a state of being bound with oxygen.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and a , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof A semiconductor device functions by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used for transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the proportion of indium compared to the proportion of gallium, the field effect mobility (simply called the mobility A semiconductor device having improved mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. The company plans to improve some of its production facilities for transistors using polycrystalline silicon and amorphous silicon. This allows the use of metal oxide transistors, which reduces capital investment. The field effect mobility of the transistor is higher than that of amorphous silicon, so the driver circuit It is possible to realize a high-performance display device having the above-mentioned structure.

[0005] In addition, Patent Document 2 discloses that aluminum, boron, and gallium are added to the source and drain regions. The group consisting of lithium, indium, titanium, silicon, germanium, tin, and lead. An oxide semiconductor film having a low-resistance region containing at least one of these as a dopant is used. A thin film transistor having the same structure is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2011-228622 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a semiconductor device having stable electrical characteristics. Another object of the present invention is to provide a semiconductor device with high reliability. One of our goals is to provide

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from descriptions in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided on the semiconductor layer. The first conductive layer is provided on the first insulating layer. The semiconductor layer includes a first region overlapping the first conductive layer and the first insulating layer, and a first a second region that does not overlap the first conductive layer and overlaps the first insulating layer; and a third region that does not overlap either of the edge layers. The semiconductor layer includes a metal oxide. The first region and the third region include a first element. The first element is boron, phosphorus, aluminum, or the like. The first element is one or more elements selected from the group consisting of zinc, zinc, and magnesium. The first element is bonded to oxygen. It exists in this state.

[0010] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, and a first The semiconductor device has a first insulating layer provided on the semiconductor layer. The conductive layer is provided on the first insulating layer. The second insulating layer is a semiconductor layer, a first insulating layer, and the first conductive layer. The semiconductor layer overlaps the first conductive layer and the first insulating layer. a first region, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer; The second insulating layer has a third region in contact with the insulating layer. The semiconductor layer includes a metal oxide. The second region and the third region contain more hydrogen than the first insulating layer. The first element is selected from boron, phosphorus, aluminum, and magnesium. It is one or more elements. The first element is present in a state bonded to oxygen.

[0011] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, and The semiconductor device has a first insulating layer provided on the semiconductor layer. The second insulating layer is disposed on the first insulating layer. The second insulating layer is disposed between the semiconductor layer, the first insulating layer, and the first The semiconductor layer is provided on the first conductive layer. The semiconductor layer is provided on the first conductive layer and the first insulating layer in a first region that overlaps the first conductive layer and the first insulating layer. a second region that does not overlap the first conductive layer and overlaps the first insulating layer; and a second insulating layer. and a third region in contact with the semiconductor layer. The semiconductor layer includes a metal oxide. The second insulating layer includes Selected from aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. The second region and the third region include the first element, and nitrogen. The first element is one or more selected from boron, phosphorus, aluminum, and magnesium. The first element is also present in a state bonded to oxygen.

[0012] In the above, the first insulating layer has a fourth region overlapping the first conductive layer and the first region. It is preferable that the first region has a first area and a fifth area overlapping the second area. Preferably, the fifth region contains a first element. In this case, the first element in the fifth region is It is preferable that it exists in a state bound to oxygen.

[0013] In the above, the first insulating layer contains an oxide, and the second insulating layer contains a nitride. It is preferable.

[0014] In the above, the first insulating layer has a portion protruding beyond a side surface of the first conductive layer. In plan view, an end of the first conductive layer is located inside an end of the first insulating layer. is preferred.

[0015] In the above, the second insulating layer is formed on the upper and side surfaces of the first conductive layer and the first insulating layer. It is preferable that it contacts the upper surface and the side surface, and the upper surface and the side surface of the third region.

[0016] In the above, it is preferable that the device further comprises a second conductive layer and a third insulating layer. At this time, the third insulating layer is provided to cover the second conductive layer, and the semiconductor layer is The second conductive layer is provided on the edge layer, and is connected to the semiconductor layer, the first insulating layer, and the third insulating layer through the semiconductor layer, the first insulating layer, and the third insulating layer. It is preferable that the second conductive layer has a portion overlapping with the first conductive layer.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: A first step of forming a dielectric layer, a first insulating film including an oxide on the semiconductor layer, and a first conductive layer a second step of forming a first conductive film and a first insulating film by etching the first conductive film and the first insulating film; forming a conductive layer and a first insulating layer having a portion protruding beyond a side surface of the first conductive layer; a third step of forming a portion of the semiconductor layer that is not covered by the first insulating layer; A fourth step of supplying a first element into the first insulating layer and the semiconductor layer using the conductive layer as a mask. and a fifth step of supplying hydrogen to a portion of the semiconductor layer that is not covered by the first insulating layer. The first element is boron, phosphorus, aluminum, or magnesium. It is preferable that

[0018] In the fourth step, the first element is doped by plasma ion doping or It is preferably delivered using the on-implant method.

[0019] In the fifth step, a portion of the semiconductor layer that is not covered with the first insulating layer is contacted. Then, a second insulating layer containing hydrogen is formed by plasma CVD, and then a heat treatment is performed. It is preferable to supply hydrogen to the semiconductor layer by this.

[0020] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: A first step of forming a dielectric layer, a first insulating film including an oxide on the semiconductor layer, and a first conductive layer a second step of forming a first conductive film and a first insulating film by etching the first conductive film and the first insulating film; forming a conductive layer and a first insulating layer having a portion protruding beyond a side surface of the first conductive layer; a third step of forming a portion of the semiconductor layer that is not covered by the first insulating layer; A fourth step of supplying a first element into the first insulating layer and the semiconductor layer using the conductive layer as a mask. and forming a first layer in contact with a portion of the semiconductor layer that is not covered with the first insulating layer, and then applying heat. and a fifth step of performing a heat treatment. The first element is boron, phosphorus, aluminum, etc. The first layer is preferably aluminum, titanium, or magnesium. One or more elements selected from tantalum, tungsten, chromium, or ruthenium, and nitrogen It is preferable that the composition further comprises

[0021] In the fourth step, the first element is doped by plasma ion doping or It is preferably delivered using the on-implant method.

[0022] In the above, the heat treatment is performed in a nitrogen-containing atmosphere at a temperature of 200° C. or higher and 450° C. or higher. It is preferable to carry out the reaction at a temperature of 0.1 °C or less. Effect of the Invention

[0023] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. It is possible to provide a semiconductor device having stable characteristics, or a highly reliable semiconductor device. Alternatively, a highly reliable display device can be provided.

[0024] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief description of the drawings]

[0025] [Figure 1] 1 shows a configuration example of a semiconductor device. [Diagram 2] 1 shows a configuration example of a semiconductor device. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] 1A and 1B are a block diagram and a circuit diagram of a display device. [Figure 15] 1A and 1B are a circuit diagram and a timing chart of a display device. [Figure 16] 1 shows an example of a display module configuration. [Figure 17] Example of electronic device configuration. [Figure 18] Example of electronic device configuration. [Figure 19] Example of electronic device configuration. [Figure 20] Example of electronic device configuration. [Figure 21] Sheet resistance of metal oxide films. [Figure 22] Sheet resistance of metal oxide films. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0027] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component may be different. may be exaggerated for clarity.

[0028] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the This is added to avoid confusion and is not intended to limit the number.

[0029] In addition, in this specification, words indicating arrangement such as "above" and "below" refer to elements relative to each other. The positional relationship between the components is used for convenience in describing the drawings. The positional relationship of the elements changes depending on the direction in which each element is depicted. The terms are not limited to those described in the detailed description, but may be rephrased appropriately depending on the situation.

[0030] In this specification, the functions of the source and drain of a transistor are different. When using polarity transistors, or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are often used interchangeably. It is possible to do so.

[0031] In this specification, the channel length direction of a transistor is the direction between the source region and the drain region. This refers to one of the directions parallel to the line that connects the two gate regions at the shortest distance. That is, the channel length The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0032] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0033] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and The term "insulating film" may sometimes be used interchangeably.

[0034] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state of being.

[0035] In this specification, a display panel, which is one aspect of a display device, displays (outputs) images on a display surface. Therefore, the display panel is one aspect of an output device.

[0036] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). inted Circuit) or TCP (Tape Carrier Packa ge) or COG (Chip On Gauge) connectors attached to the board. Display module is a device that has ICs mounted using a method such as display glass. It may be called a display panel, a display unit, or simply a display panel.

[0037] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images, etc. on a display surface. The function of displaying information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. The touch panel also functions as a touch sensor that detects the touch of the touch panel. A card is one form of input / output device.

[0038] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with touch function. A display panel and a touch sensor panel may be used. It may also be configured to have a touch sensor function inside or on the surface.

[0039] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. It may be called a touch panel module, a display module, or simply a touch panel. be.

[0040] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to one embodiment of the present invention will be described. I will explain it below.

[0041] One embodiment of the present invention is a semiconductor layer in which a channel is formed on a formation surface, and a gate insulating film on the semiconductor layer. A gate insulating layer (also called a first insulating layer) and a conductive layer that functions as a gate electrode on the gate insulating layer. The semiconductor layer is a semiconductor specific conductive layer. It is preferable that the semiconductor layer is made of a metal oxide (hereinafter, also referred to as an oxide semiconductor) exhibiting a high conductivity type. .

[0042] The gate insulating layer is preferably provided so as to cover a part of the upper surface of the semiconductor layer. The gate electrode is provided so that its end is located inside the end of the gate insulating layer. In other words, the gate insulating layer is preferably a gate insulating layer at least on the semiconductor layer. It is preferable that the electrode has a portion that protrudes outward beyond the end of the electrode.

[0043] The semiconductor layer has a first region overlapping the gate electrode and the gate insulating layer, and a second region overlapping the gate insulating layer. a second region that overlaps both the gate electrode and the gate insulating layer and a second region that does not overlap the gate electrode; The first region functions as a channel formation region. The third region is a region having a lower resistance than the first region, and is a source region or a drain region. The second region has a lower resistance than the first region, and the third region functions as a It is preferable that the region has a higher resistance than the region.

[0044] The second region is a first region in which a carrier supply source included in the third region is a channel forming region. The second region can function as a buffer region to prevent diffusion of the second region. By providing a region, the carrier concentration in the first region, which is the channel formation region, can be made extremely low. The second region can be a lightly doped transistor (LDD). ain) area.

[0045] Here, in the second region and the third region, oxygen is bonded to the metal oxide, and the metal oxide is It is preferable that an element capable of generating oxygen deficiency (also referred to as the first element) is contained in the above. Suitable elements include, for example, boron, phosphorus, aluminum, magnesium, silicon, etc. The element is present in the semiconductor layer in a state of being bonded to oxygen. It is more preferable to do so.

[0046] The element in the second and third regions combines with oxygen in the metal oxide, forming a metal oxide. Oxygen vacancies occur in the oxide. These oxygen vacancies combine with hydrogen contained in the film, Since the second region and the third region serve as a carrier supply source, the second region and the third region have a lower resistance than the first region. Furthermore, the third region preferably has a higher concentration of the element than the second region. This makes it possible to make the third region have a lower resistance than the second region. .

[0047] In addition, the gate insulating layer is provided with a portion that contacts the second region, i.e., a portion that overlaps with the gate electrode. It is preferable that the first element is contained even in the portion where the first element is not present. The portion in contact with the channel forming region, i.e., the portion overlapping with the gate electrode, is doped with the first element. It is preferred that no is added.

[0048] A heat treatment is performed in a state where a gate insulating layer containing an oxide is provided in contact with the upper surface of the semiconductor layer. By this, oxygen released from the gate insulating layer can be supplied to the semiconductor layer. This makes it possible to compensate for oxygen vacancies in the semiconductor layer, resulting in highly reliable transistors. It is possible.

[0049] On the other hand, when oxygen is supplied to the second region, the carrier density decreases and the electrical resistance increases. However, in one embodiment of the present invention, the second region of the gate insulating layer is The first element is added to the portion where the oxide film is formed. In addition, by adding the first element described above, the amount of oxygen released can be reduced. As a result, the supply of oxygen from the gate insulating layer to the second region is suppressed, and the second region The region can maintain a low electrical resistance.

[0050] By adopting such a structure, oxygen vacancies are sufficiently reduced, and the carrier density is extremely low. A channel forming region, a source region and a drain region having an extremely low electrical resistance, and and an LDD region, and thus a semiconductor device having excellent electrical characteristics and high reliability can be realized. can.

[0051] Such a transistor is formed by, for example, forming a gate insulating layer and a semiconductor layer using a gate electrode as a mask. The conductor layer is subjected to a process of supplying the first element and then a heat treatment. It can be made.

[0052] At this time, the first element is supplied by a plasma ion doping method or an ion implantation method. These methods are preferred because they make it easier to adjust the depth to which ions are added. This makes it easier to target the region including the gate insulating layer and the semiconductor layer with ions.

[0053] In addition, when the first element is added, the semiconductor layer is doped in a region on the gate insulating layer side or in a region on the semiconductor layer side. The ion supply conditions are adjusted so that the concentration of the first element near the interface between the gate insulating layer and the semiconductor substrate is the highest. It is preferable to set the above conditions. This allows both the semiconductor layer and the gate insulating layer to be formed in a single process. The first element can be added to the second region of the gate insulating layer at an appropriate concentration. By forming a region with a high concentration of the first element in the vicinity of the substrate, the oxygen diffusion in this region is improved. This effectively reduces the diffusion of oxygen in the gate insulating layer to the second region. Furthermore, since the gate insulating layer is not provided on the third region, The first element is added in high concentration to the region 3, making it more resistive, and the low resistance region and the source region are separated. It is possible to further reduce the contact resistance with the source electrode or the drain electrode.

[0054] In addition, as described above, when an element that easily bonds with oxygen is used as the first element, the first The element exists in a state of being bonded to oxygen in the semiconductor layer. That is, the first element exists in the semiconductor layer. By taking away oxygen from the semiconductor layer, oxygen vacancies are generated in the semiconductor layer, and the oxygen vacancies are combined with hydrogen in the film. Furthermore, the first element in the semiconductor layer is stable in an oxidized state. Therefore, the low resistance region can be stably realized without being desorbed by heat during the manufacturing process. For example, temperatures of 400°C or more, 600°C or more, or 800°C or more may occur during the manufacturing process. Even if the temperature rises, a stable low resistance region can be maintained.

[0055] It is also preferable to use an insulating film containing an oxide as the gate insulating layer. It is preferable that the insulating layer contains oxygen (also called excess oxygen) that is desorbed by heating. At this time, the first element in the gate insulating layer is in a state of being bonded to the excess oxygen in the gate insulating layer. The excess oxygen and the first element are bonded and stabilized, and the first element is added. In the region, almost no oxygen is desorbed even when heated, or oxygen is diffused. This causes oxygen to be supplied from the gate insulating layer to the second region, While preventing the increase in resistance due to the increase in the temperature, oxygen is supplied to the channel formation region (first region) to This reduces oxygen vacancies, resulting in the creation of highly reliable transistors with good electrical characteristics. It can be achieved.

[0056] The first element is an element that bonds with oxygen in the semiconductor layer and the gate insulating layer to stabilize it. For example, it is preferable to use an element whose oxide can exist in a solid state under standard conditions. Particularly preferred elements are rare gases, typical nonmetallic elements other than hydrogen, typical metal elements, and the like. In particular, boron, phosphorus, aluminum, It is preferable to use aluminum, magnesium, silicon, etc.

[0057] By the way, dopants can be added to a thin film or bulk of silicon to make the silicon n-type. There is a technology to convert the semiconductor into a p-type semiconductor or a p-type semiconductor. This is a method to control the carrier density by substituting dopants into silicon atom sites. For example, phosphorus and arsenic in silicon act as donors, giving them n-type conductivity. The boron and aluminum in silicon act as acceptors, so In this way, the conductivity of silicon can be increased depending on the type of dopant. In this way, the polarity of the conductivity can also be controlled.

[0058] On the other hand, in one embodiment of the present invention, the first element is introduced into the film by extracting oxygen from the metal oxide. It acts to create oxygen vacancies, and the oxygen vacancies combine with hydrogen in the film to form carriers. Therefore, the first element itself acts as a donor or acceptor in the metal oxide. For example, boron and aluminum are not required to act as accesses in silicon. Even if an element functions as a valence atom, it is difficult to give n-type conductivity to a metal oxide, as is the case with phosphorus. In this respect, the function required for the first element is to The function required for the dopant in the semiconductor device is completely different from that required for the semiconductor device.

[0059] Moreover, it is preferable that the third region contains more hydrogen than the first region and the second region. This allows the third region to have a lower resistance than the second region. In addition, even if the third region contains a large amount of hydrogen, the first region can be prevented from being affected by the presence of the second region. This effectively prevents hydrogen from diffusing into the region. The channel formation region has an extremely low carrier density, and the source and drain regions have an extremely low resistance. Since the transistor is in a stable state, it is possible to realize a transistor with excellent electrical characteristics.

[0060] As a method for supplying hydrogen to the third region, for example, a film containing hydrogen (also called the second insulating layer) may be used. It is preferable to provide the second region on the third region in contact with the second region and perform the heat treatment in this state. At this time, a first insulating layer is provided in contact with the upper surface of the second region, and the second region and the second insulating layer Since the first and second regions are not in contact with each other, the hydrogen concentration in the second region can be made lower than that in the third region. can.

[0061] Alternatively, the gate electrode is used as a mask to perform ion doping, ion implantation, or hydrogen-containing Hydrogen may be supplied to the semiconductor layer by a method such as a heat treatment under an atmosphere. Even in this case, the first insulating layer is provided on the second region, so that the The concentration of hydrogen in the second region can be made lower than that in the third region.

[0062] That is, the second region is a region in which the concentration of the first element is lower than that of the third region, and Since the amount of oxygen vacancies is small and the concentration of hydrogen is low, the second region The first region has a lower carrier concentration than the third region, and can be considered a high-resistance region.

[0063] Alternatively, the third region is subjected to a heat treatment in a state in which the first layer is formed to cover the third region. It is preferable that the resistance of the region is reduced by performing the above-mentioned process.

[0064] The first layer may be made of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. A film containing at least one metal element such as aluminum or arsenic can be used. It is preferable that the metal contains at least one of aluminum, titanium, tantalum, and tungsten. is a nitride containing at least one of these metal elements, or An oxide containing the following can be suitably used.

[0065] For example, nitrides such as aluminum nitride film, aluminum titanium nitride film, and titanium nitride film A film or an oxide film such as an aluminum titanium oxide film can be preferably used. Alternatively, a metal film such as a tungsten film or a titanium film may be used.

[0066] For example, when an aluminum titanium nitride film is used, the composition formula is AlTiN x (x is greater than 0 (real number less than 3) or the composition formula is AlTi x N y (x is a real number greater than 0 and less than or equal to 2, It is more preferable to use a film that satisfies the following condition: y is a real number greater than 0 and less than or equal to 4.

[0067] In addition, the higher the temperature of the heat treatment, the more the resistance of the third region is reduced, which is preferable. The temperature of the heat treatment may be determined in consideration of the heat resistance of the gate electrode. For example, 150° C. 500°C or higher, preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher The temperature can be 450° C. or less, and more preferably 300° C. or more and 400° C. or less. For example, by setting the heat treatment temperature at around 350°C, production equipment using large glass substrates can be used. Therefore, semiconductor devices can be produced with a high yield.

[0068] By performing a heat treatment in a state where the first layer is provided in contact with the third region, Oxygen is attracted to the first layer, and oxygen vacancies can be formed in the third region. By this, a third region with extremely low resistance can be formed. Since the first layer and the second region are not in direct contact with each other, oxygen is not directly absorbed in the first layer. As a result, a third region is formed that has a much lower resistance than the second region. It is possible.

[0069] The third region thus formed has the characteristic that it is difficult for the resistance to increase during subsequent processing. For example, heat treatment in an atmosphere containing oxygen, film formation in an atmosphere containing oxygen, etc. Even if the above-mentioned step is performed, there is no risk of impairing the conductivity of the third region, so that the electrical characteristics are good, and A highly reliable transistor can be realized.

[0070] In addition, in the case where the first layer after the heat treatment has electrical conductivity, the first layer after the heat treatment On the other hand, if the first layer has insulating properties, it is preferable to leave it. By doing so, the first layer can function as a protective insulating film (second insulating layer).

[0071] In particular, the aluminum nitride film or the aluminum titanium nitride film has excellent insulating properties. Since it is a film that has been removed, it is preferable to leave it as it is.

[0072] A more specific example will be described below with reference to the drawings.

[0073] [Configuration example 1] FIG. 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1C is a cross-sectional view taken along the dashed line A1-A2 shown in FIG. It corresponds to a cross-sectional view taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as a protective insulating layer) are omitted in the figure. The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction. In addition, the top views of the transistors in the following drawings are the same as those in FIG. In this regard, some of the components will be omitted in the illustration.

[0074] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating The insulating layer 116 is a dielectric layer 118. The insulating layer 118 is a dielectric layer 116. The insulating layer 118 is a dielectric layer 118. The insulating layer 116 is a dielectric layer. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is The metal oxide layer 103 is provided to cover a part of the top surface of the semiconductor layer 108. The semiconductor layer 108 and the conductive layer 112 are stacked in this order on the insulating layer 110. In addition, the metal oxide layer 114 and the conductive layer 112 have a portion overlapping with each other in a plan view. The insulating layer 116 is disposed so as to be located inside the end of the insulating layer 110. The top and side surfaces of the metal oxide layer 112, the side surfaces of the metal oxide layer 114, the top and side surfaces of the insulating layer 110, The insulating layer 103 is provided so as to cover the upper and side surfaces of the conductor layer 108 and the upper surface of the insulating layer 103. A layer 118 is provided over insulating layer 116 .

[0075] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 includes a gate electrode provided on the semiconductor layer 108. This is a so-called top-gate transistor.

[0076] As shown in FIGS. 1A and 1B, the transistor 100 is formed on an insulating layer 118. The conductive layer 120a and the conductive layer 120b may be included. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. are the openings 141a and 141b provided in the insulating layer 118 and the insulating layer 116, respectively. It is electrically connected to a region 108N, which will be described later, via 41b.

[0077] The semiconductor layer 108 preferably comprises a metal oxide.

[0078] For example, the semiconductor layer 108 may be made of indium and M (where M is gallium, aluminum, or silicon). Boron, Yttrium, Tin, Copper, Vanadium, Beryllium, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, and magnesium; and zinc. In particular, M is aluminum, gallium, yttrium, or It is preferable to use one or more elements selected from tin.

[0079] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferable.

[0080] The semiconductor layer 108 may be a layer having different compositions, different crystallinity, or different impurity concentrations. Alternatively, the layer may be a laminated structure having such layers laminated thereon.

[0081] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes are roughly the same as each other. It has been done.

[0082] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The contours do not overlap, and the contour of the upper layer is located inside the contour of the lower layer, or the contour of the upper layer is located inside the contour of the lower layer. In this case, it is also said that the top surface shape roughly matches.

[0083] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing into the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, A material that is less permeable to oxygen and hydrogen than 0 can be used.

[0084] The metal oxide layer 114 makes it easier for the conductive layer 112 to absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 can be prevented from Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0085] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0086] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a gate film or the like since the driving voltage can be reduced.

[0087] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). Conductive oxides such as silicon-doped indium tin oxide (ITSO) In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0088] The metal oxide layer 114 is made of an oxide material containing at least one of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable that the metal oxide layer 114 is formed by the same sputtering method as the semiconductor layer 108. By applying a metal oxide film formed using a ring target, the equipment can be standardized. Therefore, it is preferable.

[0089] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. In the case of using a metal oxide material containing gallium, the composition (content) of gallium is higher than that of the semiconductor layer 108. It is preferable to use a material having a high oxygen blocking property. At this time, the semiconductor layer 108 contains a material having a higher indium content than the metal oxide layer 114. By using such a material, the field-effect mobility of the transistor 100 can be increased.

[0090] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0091] The semiconductor layer 108 has a channel forming region that overlaps with the conductive layer 112 via the insulating layer 110. The semiconductor layer 108 has a pair of regions 108L sandwiching the channel formation region therebetween, The region 108L is an insulating region of the semiconductor layer 108. This is a region that overlaps with the edge layer 110 and does not overlap with the conductive layer 112. is a region of the semiconductor layer 108 that does not overlap with either the conductive layer 112 or the insulating layer 110. and this is the area in contact with the insulating layer 116.

[0092] The regions 108L and 108N are regions having a lower resistance and a higher carrier concentration than the channel formation region. Regions with high oxygen vacancy density, high impurity concentration, or n-type Also, the region 108N is a region having a lower resistance than the region 108L. The regions are those with high impurity concentration, high oxygen vacancy density, high impurity concentration, or n-type. It can also be said to be an area where

[0093] The region 108L and the region 108N are regions that contain an impurity element (first element). The impurity elements include, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and a Examples of rare gases include aluminum, magnesium, and rare gases. The elements include helium, neon, argon, krypton, and xenon. In particular, boron, It is preferable that the material contains phosphorus, magnesium, or aluminum. The above may be included.

[0094] The region 108N may have a region having a higher concentration of the above impurities than the region 108L. Moreover, the region 108N has a peak of impurity concentration at a position deeper than the region 108L. It's fine.

[0095] The insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are formed of an oxide. It is preferable to use a film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An oxide film such as a tungsten film can be used. Oxygen released from the insulating layer 103 or the insulating layer 110 during heat treatment in the process is transported to the semiconductor layer 1 The oxygen vacancies in the semiconductor layer 108 can be reduced by supplying the oxygen to the channel formation region of the semiconductor layer 108. .

[0096] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. A region overlapping with the conductive layer 112 and functioning as a gate insulating layer and a region not overlapping with the conductive layer 112 are formed. 108L).

[0097] The insulating layer 110 has a region 1 containing the above-mentioned impurity element in a region not overlapping with the conductive layer 112. Region 110d is located at least near the interface with region 108L. 1B and 1C, the region 110d is a channel region of the semiconductor layer 108. It is preferable that the insulating layer is not provided in a portion adjacent to the formation region.

[0098] In addition, the insulating layer 103 has a boundary with the insulating layer 110 in a region that does not overlap with the conductive layer 112. The region 103d containing the above-mentioned impurity element is provided near the surface and near the interface with the insulating layer 116. Although not shown, the region 103d is located near the interface with the region 108N and the region 108L. In this case, the area overlapping with the area 108N or the area 108L may be provided adjacent to the area 108N. The impurity concentration is lower than that in the portion in contact with the insulating layer 110 or the insulating layer 116 .

[0099] Here, the impurity concentration in the region 108L becomes higher as it approaches the insulating layer 110. It is preferable that the concentration gradient be such that the uniform concentration is uniform throughout the region 108L. Since the total amount of impurity elements in the region 108L can be reduced compared to the case where the concentration is set to 100%, The amount of impurities that can diffuse into the channel formation region due to the effects of heat during the process can be kept low. Cut.

[0100] The region 108N may also have a similar concentration gradient. Since the resistance becomes lower toward the upper portion, the contact resistance with the conductive layer 120a (or the conductive layer 120b) is further reduced. This can be effectively reduced.

[0101] Moreover, the impurity concentration in the region 110d becomes higher as it approaches the semiconductor layer 108. It is preferable to have such a concentration gradient. In the insulating layer 110, the region 110d to which the above-mentioned impurity element is added is different from the other regions. Therefore, the region 108L of the insulating layer 110 can be prevented from releasing oxygen. The region 110d located near the interface functions as a blocking layer against oxygen, and the region 1 It can effectively reduce the oxygen supplied to 08L.

[0102] As described later, impurity elements are added to the regions 108L, 108N, and 110d. The process can be performed by using the conductive layer 112 as a mask. The region 108N and the region 110d can be formed in a self-aligned manner. Since an insulating layer 110 is provided on the region 108L, the region 108N and the region 108L In some cases, the profile of the impurity concentration gradient in the depth direction may differ.

[0103] In addition, in Fig. 1(B) and (C), etc., the insulating layer is used to exaggerate the areas with high impurity concentrations. The layer 110 and the insulating layer 103 are partially covered with a hatching layer as a region 110d or a region 103d. In reality, the insulating layer 110 and the insulating layer 103 are not aligned in the thickness direction. The above impurity elements may be contained throughout the entirety.

[0104] The regions 108N, 108L, and 110d each have an impurity concentration of 1×10 1 9 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 More preferably, 1 ×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 The region where In addition, the region 108L preferably contains less impurities than the region 110d of the insulating layer 110. When the region 108L has a high concentration of impurities, the electrical resistance of the region 108L can be reduced more effectively. In addition, the region 108N has a portion with a higher impurity concentration than the region 108L. It is more preferable that

[0105] The concentrations of impurities contained in the regions 108L, 108N, and 110d are, for example, Secondary Ion Mass Spectrometry (SIMS) X-ray photoelectron spectroscopy (XPS) and It can be analyzed by analytical methods such as XPS analysis. In cases where the sample is in a state where the surface is not uniform, ion sputtering from the front or back side and XPS analysis are combined. By doing so, it is possible to know the concentration distribution in the depth direction.

[0106] In the regions 108L and 108N, the impurity elements are present in an oxidized state. For example, boron, phosphorus, magnesium, aluminum, etc. are used as impurity elements. It is preferable to use elements that are easily oxidized, such as aluminum and silicon. Since the element can exist stably in an oxidized state by bonding with oxygen in the semiconductor layer 108, The process was subject to high temperatures (e.g., 400°C or higher, 600°C or higher, or 800°C or higher). Even in such a case, the impurity element is prevented from being desorbed from the oxide in the semiconductor layer 108. By removing oxygen, many oxygen vacancies are generated in the regions 108L and 108N. The oxygen vacancies and hydrogen in the film combine to become a carrier supply source. The region 108N is in an extremely low resistance state.

[0107] In addition, when performing a process at high temperatures in a later step, the outside, region 108L and region 10 If a large amount of oxygen is supplied to the regions 108L and 108N from the film near the region 8N, Therefore, when performing high-temperature processing, it is recommended to use an acid. The semiconductor layer 108 is covered with the insulating layer 116, which has a high barrier property against oxygen. preferable.

[0108] Also in the region 110d, the impurity element is preferably present in an oxidized state. Such easily oxidizable elements are bonded to oxygen in the insulating layer 110 and remain in an oxidized state. Because it can exist stably, it is prevented from being desorbed even when exposed to high temperatures in later processes. In particular, the insulating layer 110 contains oxygen (also called excess oxygen) that can be desorbed by heating. In this case, the excess oxygen and the impurity element are bonded and stabilized, so that the region 110d It is possible to suppress the supply of oxygen to the region 108L. Since the region 110d containing the pure element is in a state in which oxygen is difficult to diffuse, the region 110d It is also possible to prevent oxygen from being supplied to the region 108L from above the region 110d. This can be done.

[0109] For example, when boron is used as an impurity element, the regions 108L, 108N, and 108L are The boron contained in the region 110d may exist in a state of being bonded to oxygen. This can be confirmed by observing the spectral peaks due to B2O3 bonds in the analysis. In addition, in the XPS analysis, the spectral peak due to the existence of the element boron alone was The peak is not observed or is buried in the background noise at the lower limit of measurement. The crack strength becomes extremely small.

[0110] The insulating layer 116 is provided in contact with a region 108N of the semiconductor layer 108.

[0111] The insulating layer 116 serves as a source of hydrogen for the region 108N. For example, the insulating layer It is preferable that the insulating layer 116 is a film that releases hydrogen when heated. is provided in contact with the region 108N, and a heat treatment is performed after the formation of the insulating layer 116. Hydrogen can be supplied to the 08N to reduce its resistance.

[0112] The insulating layer 116 is formed by using a gas containing hydrogen as a deposition gas. This prevents water from entering the region 108N during the formation of the insulating layer 116. The material can be supplied effectively.

[0113] The insulating layer 116 may be made of, for example, silicon nitride, silicon nitride oxide, or silicon oxide nitride. An insulating film such as aluminum nitride or aluminum nitride oxide can be used.

[0114] The region 108N contains many oxygen vacancies due to the addition of impurity elements as described above. Therefore, in addition to the hydrogen contained in the semiconductor layer 108, the hydrogen is further absorbed from the insulating layer 116. By supplying hydrogen to the semiconductor, the carrier density can be further increased.

[0115] On the other hand, the region 108L is not in contact with the insulating layer 116 because the insulating layer 110 is present therebetween. Therefore, less hydrogen is supplied to the region 108 than to the region 108N. Since the resistance of region 108L is lower than that of region 108N, region 108L can be made to have a higher resistance than region 108N.

[0116] Alternatively, an insulating film containing a nitride may be used as the insulating layer 116 in contact with the region 108N. By providing an insulating layer 116 containing nitride in contact with the region 108N, In addition, the insulating layer 116 is in contact with the region 108N. It is preferable to perform the heat treatment in this state, since this promotes a further reduction in resistance.

[0117] Examples of nitrides that can be used for the insulating layer 116 include silicon nitride and gallium nitride. It is particularly preferred to use nitrides of semiconductor materials or metal nitrides such as aluminum nitride. For example, silicon nitride has a blocking effect against hydrogen and oxygen, so it is difficult to This prevents both the diffusion of hydrogen from the semiconductor layer to the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside. This makes it possible to realize a highly reliable transistor.

[0118] In addition, when metal nitrides are used, aluminum, titanium, tantalum, tungsten, quartz, etc. It is preferable to use nitrides of chromium or ruthenium. In particular, nitrides of aluminum or titanium are used. For example, aluminum is used as a sputtering target. The nitride alumina was formed by reactive sputtering using a nitrogen-containing gas as the deposition gas. The aluminum film is extremely thin, and can be formed by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas. The film has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen. Therefore, an insulating film containing such a metal nitride is provided in contact with a semiconductor layer. By doing so, not only can the resistance of the semiconductor layer be reduced, but oxygen can also be prevented from diffusing from the semiconductor layer to the outside. In addition, hydrogen can be prevented from diffusing into the semiconductor layer.

[0119] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the thickness of the layer is 5 nm or more. Even with such a thin film, hydrogen and oxygen This allows the compound to have both high blocking properties against elements and a function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be any thickness, but in consideration of productivity, it is preferably 500 nm or less. It is preferable that the thickness is 200 nm or less, and more preferably 50 nm or less.

[0120] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0 A membrane is used that satisfies the following: x is a real number less than or equal to 2, preferably, x is a real number greater than 0.5 and less than or equal to 1.5. This makes it possible to obtain a film having excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the dissipation of heat generated when the transistor 100 is driven. do.

[0121] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like is used as the insulating layer 116. It is possible.

[0122] By providing such an insulating layer 116 in contact with the region 108N, the insulating layer 116 The oxygen in the region 108N can be absorbed, and oxygen vacancies can be formed in the region 108N. In this case, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 and the region 108N Between the insulating layer 116 and the insulating layer 116, a layer containing an oxide of a metal element (for example, aluminum) is provided. It may be formed.

[0123] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, the region 1 In the vicinity of the interface of the insulating layer 116 of the 08N, there is a region where indium oxide is precipitated or In some cases, regions with high ion concentration are formed. The presence of such regions can be attributed to, for example, X X-ray Photoelectron Spectros (XPS) This may be possible using analytical methods such as copy number analysis.

[0124] In this way, the region 108N is made to have more oxygen vacancies than the region 108L. Therefore, the resistance of the region 108B can be lower than that of the region 108L. By using an insulating film containing a metal oxide as the edge layer 116, the insulating layer 116 in the region 108N A region where highly conductive indium oxide is precipitated is formed near the interface on the side of the It can be an area.

[0125] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon nitride, silicon nitride oxide, silicon oxynitride, and aluminum oxide. Hafnium, Aluminum Oxide Nitride, Aluminum Nitride, Hafnium Oxide, Hafnium Aluminum The insulating layer 118 can be formed of an inorganic insulating material such as polycarbonate. In this case, an organic resin material can be used as the insulating layer 118. .

[0126] In this example, a laminated structure of an insulating layer 116 and an insulating layer 118 is used as the protective layer. However, if the insulating layer 118 is unnecessary, it may not be provided. A laminated structure may also be used.

[0127] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. I will explain it below.

[0128] The oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, the oxygen Hydrogen bonds to the vacancies and can become a carrier source. When this occurs, the electrical characteristics of the transistor 100 change, typically resulting in a shift in the threshold voltage. Therefore, in the channel formation region, the fewer oxygen vacancies the better. .

[0129] Therefore, in one embodiment of the present invention, the insulating film in the vicinity of the channel formation region of the semiconductor layer 108 is Specifically, the insulating layer 110 located above the channel formation region and the insulating layer 111 located below the channel formation region The insulating layer 103 and the insulating film 104 are formed by the heat during the manufacturing process. By transferring oxygen from the insulating layer 110 to the channel formation region, the oxygen in the channel formation region is It is possible to reduce the element deficiency.

[0130] In addition, the semiconductor layer 108 preferably has a region in which the atomic ratio of In to M is greater than 1. It is preferable that the In content is high. The field effect mobility of the transistor can be improved. can.

[0131] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is greater than that between Ga and oxygen. Since the bonding strength is weaker than that of the element, when the In content is high, oxygen vacancies occur in the metal oxide film. In addition, the same phenomenon occurs when the metal element M is used instead of Ga. When there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor tend to deteriorate. This can result in poor performance and reduced reliability.

[0132] However, in one embodiment of the present invention, the channel formation region of the semiconductor layer 108 containing a metal oxide Since a large amount of oxygen can be supplied to the region, metal oxide materials with a high In content are used. This makes it possible to achieve extremely high field effect mobility, stable electrical characteristics, and It is possible to realize a transistor that also has high reliability.

[0133] For example, the atomic ratio of In to M is 1.5 or more, or 2 or more, or 3 or more, Metal oxides having a .DELTA. of 3.5 or more, or 4 or more can be suitably used.

[0134] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=4:2. It is preferable that the ratio of the numbers of In, M, and Zn atoms is 3 or about 3. It is preferable that the composition ratio of In:M:Zn is 5:1:6 or in the vicinity thereof. As for the composition, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 may be approximately equal. That is, the ratio of the numbers of In, M, and Zn atoms is In:M:Zn=1:1:1 or It may also include nearby materials.

[0135] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this in a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-mentioned high field effect mobility transistor is used as a source driver (especially the source It can be used for a demultiplexer connected to the output terminal of a shift register of a driver. As a result, it is possible to provide a display device having a small number of wires connected to the display device.

[0136] The semiconductor layer 108 has a region in which the atomic ratio of In to M is greater than 1. However, when the crystallinity of the semiconductor layer 108 is high, the field effect mobility may be reduced. The crystallinity of the layer 108 can be determined, for example, by X-ray diffraction (XRD). ion) or transmission electron microscope (TEM) It can be analyzed by using a ion electron microscope. .

[0137] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect level density. By reducing the oxygen vacancies, the carrier density in the film can be reduced. A transistor using such a metal oxide film in a channel formation region of a semiconductor layer has a threshold The electrical characteristics where the voltage is negative (also called normally on) are rare. In addition, a transistor using such a metal oxide film has a characteristic of having a significantly small off-state current. It is possible.

[0138] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, the semiconductor layer 108 is easily processed. Damage caused during the formation of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with a relatively low crystallinity for the semiconductor layer 108, This improves the electrical conductivity and enables the realization of a transistor with high field effect mobility.

[0139] The semiconductor layer 108 is a c-axis aligned cryostat (CAAC) layer. Metal oxide film with stal structure, nc (nano crystal) structure Metal oxide films or metal oxide films with a mixture of CAAC and nc structures can be used. preferable.

[0140] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0141] For example, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different compositions. For example, when an In-M-Zn oxide is used, the number of atoms of In, M, and Zn is The ratio is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1 :1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn =1:3:2 or a film formed using a sputtering target with a ratio of approximately It is preferable to use two or more of them in a laminate.

[0142] In addition, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different crystallinity. In this case, the same oxide target can be used, but the deposition conditions can be changed to reduce the exposure to air. It is preferable that they are formed continuously and without touching.

[0143] At this time, the semiconductor layer 108 is made of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, a metal oxide film having an nc structure may be formed. The semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure. The function or material structure of metal oxides that can be suitably used for the semiconductor layer 108a and the semiconductor layer 108b The composition of the CAC (Cloud-Aligned Composite) is described later. The description can be cited.

[0144] For example, the oxygen flow rate during deposition of the first metal oxide film is set to be equal to or lower than the oxygen flow rate during deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during deposition of the first metal oxide film. During the film formation, oxygen is not allowed to flow. This prevents oxygen from being introduced during the formation of the second metal oxide film. In addition, the first metal oxide film is more effective in supplying the element than the second metal oxide film. The film has lower crystallinity and higher electrical conductivity than the first film. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, so that the semiconductor layer 1 Damage during processing of 08 and during deposition of the insulating layer 110 can be suppressed.

[0145] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably, it is 0% or more and 20% or less, typically, it is 10%. The oxygen flow rate during the formation of the second metal oxide film is set to 50% or more and 100% or less. Preferably, the ratio is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably, The ratio is preferably 90% or more and 100% or less, and typically 100%. The first and second metal oxide films may be formed under different conditions such as pressure, temperature, and power. By keeping all other conditions the same except for the oxygen flow rate, the time required for the film formation process can be shortened. This is preferable.

[0146] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0147] [Configuration example 2] Hereinafter, a configuration example of a transistor having a partly different configuration from the above configuration example 1 will be described. In the following, explanations of parts that overlap with the above-mentioned configuration example 1 may be omitted. In the drawings shown below, parts having the same functions as those in the above configuration example 1 are indicated by hatching. In some cases, the turns are the same and no code is assigned.

[0148] FIG. 2A is a top view of a transistor 100A, and FIG. 2B is a top view of a transistor 100B. FIG. 2(C) is a cross-sectional view of the channel length direction of transistor 100A, and FIG. 2(D) is a cross-sectional view of the channel width direction of transistor 100A. 1 is a cross-sectional view in the direction.

[0149] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 is a region in which a channel is formed in the semiconductor layer 108 and a region in which a gate insulating film is formed in the semiconductor layer 108. and a region overlapping with the conductive layer 112.

[0150] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode). The conductive layer 112 functions as a second gate electrode (also called a top gate electrode). A part of the insulating layer 103 functions as a first gate insulating layer. and a portion of the insulating layer 110 functions as a second gate insulating layer.

[0151] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 In the following description, for ease of explanation, the semiconductor layer 10 The portion of the conductive layer 112 of the conductive layer 8 is sometimes called a channel formation region. The portion that does not overlap with the layer 112 and overlaps with the conductive layer 106 (including the region 108L and the region 108N) Channels can also form in the junctions (parts including the junction).

[0152] As shown in FIGS. 2A and 2C, the conductive layer 106 is made of a metal oxide layer 114 and an insulating layer. The conductive layer 112 is electrically connected to the insulating layer 103 through an opening 142 provided in the insulating layer 103 and the conductive layer 112 . In this way, the conductive layer 106 and the conductive layer 112 can be given the same potential. It is possible to do so.

[0153] The conductive layer 106 may be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. In addition, the conductive layer 106 is preferably made of a high melting point metal such as tungsten or molybdenum. By using a material containing this, processing at a higher temperature can be carried out in a subsequent step.

[0154] As shown in FIGS. 2A and 2C, the conductive layer 112 and the It is preferable that the conductive layer 106 protrudes outward beyond the end of the semiconductor layer 108. At this time, as shown in FIG. 2C, the entire semiconductor layer 108 in the channel width direction is covered with the insulating layer 11. 0 and the insulating layer 103, the conductive layer 112 and the conductive layer 106 cover the conductive layer 106.

[0155] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by a pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108 in order to induce a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0156] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. In this case, the transistor 100A may be turned on by applying a potential to one electrode. It is also possible to control the threshold voltage when driving the device with one electrode.

[0157] This concludes the description of configuration example 2.

[0158] [Example of manufacturing method] A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100A illustrated in the above configuration example will be taken as an example for explanation.

[0159] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device are formed by sputtering. Chemical Vapor Deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method The CVD method can be a plasma chemical vapor deposition (PE CVD (Plasma Enhanced CVD) method and thermal CVD method. One of the thermal CVD methods is metal-organic chemical vapor deposition (MOCVD). There is a method called CVD.

[0160] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife method, slit coating, roll coating, curtain coating, knife coating The insulating layer can be formed by a method such as a method for forming a thin film.

[0161] In addition, when processing the thin films that constitute the semiconductor device, photolithography and other methods are used. In addition, nanoimprinting, sandblasting, lift-off, The thin film may be processed by a method such as a masking method using a metal mask. The island-shaped thin film may be directly formed by the film method.

[0162] There are two typical photolithography methods. A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the mask after forming a photosensitive thin film. Then, development is performed to process the thin film into a desired shape.

[0163] In the photolithography method, the light used for exposure is, for example, i-line (wavelength 365 nm), Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may be performed by immersion lithography. Using extreme ultraviolet (EUV) light and X-rays, Also, instead of light for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferable because it allows extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is not necessary.

[0164] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as the above can be used.

[0165] 3 to 6 show the channel of the transistor 100A at various stages in the manufacturing process. The cross sections in the longitudinal direction and the channel width direction are shown side by side.

[0166] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a first gate electrode. A conductive layer 106 is formed to function as a conductive layer.

[0167] [Formation of insulating layer 103] Next, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 3(A)). The insulating layer 103 may be formed by using a PECVD method, an ALD method, a sputtering method, or the like. can be done.

[0168] After the insulating layer 103 is formed, a process of supplying oxygen to the insulating layer 103 may be performed. For example, a plasma treatment or a heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be introduced into the insulating layer 103 by plasma ion doping or ion implantation. may be supplied.

[0169] [Formation of Semiconductor Layer 108] Next, a metal oxide film is formed on the insulating layer 103 and processed to form island-shaped semiconductor layers. The conductor layer 108 is formed (FIG. 3(B)).

[0170] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0171] In addition, when forming a metal oxide film, oxygen gas, inert gas (e.g., helium gas, In addition, the metal oxide film may be formed by mixing the gas (argon gas, xenon gas, etc.) with the gas. The higher the ratio of oxygen gas in the total deposition gas during deposition (hereinafter, also referred to as the oxygen flow ratio), the greater the amount of oxygen in the deposition gas. This can improve the crystallinity of the metal oxide film, resulting in a highly reliable transistor. The lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor can be used.

[0172] When the semiconductor layer 108 has a laminated structure, the same sputtering target is used to produce the same composition. By continuously forming the films in the film chamber, it is possible to obtain a good interface, which is preferable. The deposition conditions for each metal oxide film were varied under different pressures, temperatures, power, etc. However, by keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened. In addition, when metal oxide films having different compositions are laminated, the air is preferably It is preferable to form the films successively without exposing them to heat.

[0173] The metal oxide film is classified into two types: a metal oxide film having a CAAC structure and a metal oxide film having an nc structure. The deposition conditions are set so that the metal oxide film has a mixture of CAAC structure and nc structure. It is preferable to set the film forming conditions so that the metal oxide film to be formed has the CAAC structure. The deposition conditions for the nc structure depend on the composition of the sputtering target used. Since the composition of the material varies, the substrate temperature, oxygen flow rate, pressure, power, etc. are adjusted appropriately according to the composition. Just set it.

[0174] The deposition conditions for the metal oxide film are as follows: the substrate temperature is from room temperature to 450° C. The substrate temperature is preferably from room temperature to 300° C., more preferably from room temperature to 200° C., and even more preferably For example, the substrate 102 may be a large glass substrate or a resin substrate. When using a plastic substrate, productivity is increased if the substrate temperature is set to room temperature or higher but less than 140°C. In addition, the substrate temperature is set to room temperature or is not intentionally heated. By forming a film, the crystallinity can be reduced.

[0175] In addition, before the metal oxide film is formed, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a treatment for removing the above-mentioned elements and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C to 200°C in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. When plasma treatment is performed in an atmosphere containing nitrogen gas, organic matter on the surface of the insulating layer 103 is removed. After such a treatment, the surface of the insulating layer 103 is exposed to the atmosphere. It is preferable to form the metal oxide film continuously without performing the above-mentioned process.

[0176] Metal oxide films are processed using either wet etching or dry etching. In this case, the part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be used. The part may be etched and thinned.

[0177] After the metal oxide film is formed or processed into the semiconductor layer 108, the metal oxide film or Alternatively, heat treatment may be performed in order to remove hydrogen or water from the semiconductor layer 108. The temperature is typically 150° C. or higher but lower than the strain point of the substrate, or 250° C. or higher but lower than 450° C. or 300° C. or higher and 450° C. or lower.

[0178] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in air, the substrate may be heated in an atmosphere containing oxygen. It is preferable that the mixture does not contain hydrogen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment time can be shortened.

[0179] [Formation of insulating film 110f and metal oxide film 114f] Next, the insulating film 110f and the metal oxide film 110f are formed on the insulating layer 103 and the semiconductor layer 108. Form 14f.

[0180] The insulating film 110f is a film that will later become the insulating layer 110. For example, the insulating film 110f may be For example, an oxide film such as a silicon oxide film or a silicon oxynitride film is deposited by a plasma enhanced chemical vapor deposition apparatus. It is preferable to form the layer by using a plasma enhanced CVD (PECVD) apparatus or simply a plasma enhanced CVD (plasma enhanced chemical vapor deposition) apparatus. It is also preferable to form the insulating film by using a PECVD method using microwaves.

[0181] The metal oxide film 114f is a film that will later become the metal oxide layer 114. It is preferable that 4f is formed by, for example, a sputtering method in an atmosphere containing oxygen. This makes it possible to supply oxygen to the insulating film 110f when the metal oxide film 114f is formed. Cut.

[0182] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming the film by a sputtering method using a target, the above method is used. can be done.

[0183] The metal oxide film 114f is formed by reactive spat deposition using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, An aluminum oxide film can be formed.

[0184] When the metal oxide film 114f is formed, the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating film thickness. The oxygen supplied during 10f can be increased. The oxygen flow ratio or oxygen partial pressure can be increased, for example, by 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or more, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure at 100% and to make the oxygen partial pressure as close to 100% as possible.

[0185] In this manner, the metal oxide film 114f is formed by the sputtering method in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating film 110f during the formation of the metal oxide film 114f. At the same time, oxygen can be prevented from being released from the insulating film 110f. It is possible to trap a large amount of oxygen in the film 110f. As a result, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, and the Oxygen vacancies can be reduced, and highly reliable transistors can be realized.

[0186] In addition, by performing a heat treatment after the formation of the metal oxide film 114f, the insulating film 110f is Oxygen may be supplied to the semiconductor layer 108. The heat treatment may be performed using one or more of nitrogen, oxygen, and a rare gas. The reaction can be carried out at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing

[0187] Next, the metal oxide film 114f, the insulating film 110f, and a part of the insulating layer 103 are etched. By this, an opening reaching the conductive layer 106 is formed. 112 and the conductive layer 106 can be electrically connected through the opening.

[0188] [Formation of Conductive Film 112f] Next, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f ( FIG. 3(C). The conductive film 112f is formed by sputtering a metal or alloy target. It is preferable to form the film by a sputtering method.

[0189] [Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112] Then, a resist mask 115 is formed over the conductive film 112f. In the area not covered by the mask 115, the conductive film 112f is removed by anisotropic etching. Then, the metal oxide film 114f and the insulating film 110f are etched (FIG. 4(A)).

[0190] The conductive film 112f, the metal oxide film 114f, and the insulating film 110f are etched by the same etching. The etching conditions may be different, or the etching conditions or techniques may be different. For example, the conductive film 112f and the metal The oxide film 114f is etched first, and then the insulating film 110f is etched under different etching conditions. By etching, damage to the semiconductor layer 108 due to etching can be reduced. do.

[0191] Here, the resist mask 115 is preferably formed on a region that will become the insulating layer 110. It is nice.

[0192] Next, the conductive film 112f and the metal oxide film 114f are etched by an isotropic etching method. The surface is etched to set back the end face (also called side etching). A conductive layer 112 whose end is located inside the end of the insulating layer 110 in plan view and a metal oxide A nitride layer 114 can then be formed (FIG. 4(B)).

[0193] Here, the conductive film 112f and the metal oxide film 114f are etched using the semiconductor layer 108 and It is preferable to select conditions or a method that etch the insulating layer 103 as little as possible. Here, when the conductive film 112f and the metal oxide film 114f are side-etched, the resist This may be performed with the mask 115 removed, but it is preferable to leave the resist mask 115. Therefore, only the side surface of the conductive layer 112 can be etched without thinning the conductive layer 112. preferable.

[0194] Here, the metal oxide film 114f is side-etched in the same manner as the conductive film 112f. However, only the conductive film 112f may be side-etched. Like the insulating layer 110, the metal oxide layer 114 has a region that does not overlap with the conductive layer 112. The configuration is as follows.

[0195] After the conductive layer 112 and the metal oxide layer 114 are formed, the resist mask 115 is removed.

[0196] [Supplying process of impurity elements (formation of region 108L)] Next, impurity elements are implanted into the insulating layer 110 and the semiconductor layer 108 using the conductive layer 112 as a mask. 140 is supplied (also called added or injected) to the region 108L and the region 11 At this time, the semiconductor layer 108 and the insulating layer 103 are formed. In the region of 110 that overlaps with the conductive layer 112, the conductive layer 112 serves as a mask and the impurity source is The element 140 is not provided.

[0197] The impurity element 140 is preferably supplied by a plasma ion doping method or an ion implantation method. These methods can be used to measure the concentration profile in the depth direction by ion acceleration. It is possible to control the voltage and dose with high precision. Plasma ion doping By using this method, productivity can be increased. In addition, ion implantation using mass separation is also used. By using this, the purity of the impurity element supplied can be increased.

[0198] In the supplying process of the impurity element 140, the interface between the semiconductor layer 108 and the insulating layer 110, is a portion close to the interface in the semiconductor layer 108, or a portion close to the interface in the insulating layer 110. It is preferable to control the treatment conditions so that the highest concentration is obtained. In this way, the semiconductor layer 108 and the insulating layer 110 are both supplied with the impurity element 140 at an optimal concentration. It is possible.

[0199] The impurity elements 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples of the material include aluminum, magnesium, silicon, and rare gases. Representative examples include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon. It is.

[0200] As a source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically B2H6 gas or BF3 gas can be used. In addition, when supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas may be used.

[0201] Other raw gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. In addition, the ion source is not limited to gas, and a solid or liquid vaporized by heating can also be used. good.

[0202] The addition of the impurity element 140 affects the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108. This can be controlled by setting conditions such as acceleration voltage and dose amount taking into consideration the above.

[0203] For example, when boron is added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV to 100 kV, preferably 7 kV to 70 kV, more preferably The voltage can be preferably in the range of 10 kV to 50 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 ×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 More preferably, 1 ×10 15 ions / cm 2 More than 3×10 16 ions / cm 2 The following range should be set: can.

[0204] In addition, when phosphorus is added by ion implantation or plasma ion doping, the acceleration The voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, more preferably More preferably, the voltage can be in the range of 40 kV to 80 kV. For example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm2 Hereinafter, preferably 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 More preferably, 1×10 15 ions / cm 2 More than 3×10 16 ions / cm 2 The following range should be met: can be done.

[0205] The method of supplying the impurity element 140 is not limited to this. For example, plasma processing, A treatment utilizing thermal diffusion by heating may be used. In the case of plasma treatment, the impurities to be added are By generating plasma in a gas atmosphere containing a pure element and performing plasma processing, As a device for generating the plasma, a dry Etching equipment, ashing equipment, plasma CVD equipment, high density plasma CVD equipment, etc. It can be used.

[0206] Here, the impurity element 140 is added to the region 108L through the insulating layer 110, and at the same time, The impurity element 140 is also introduced into the region not covered by the insulating layer 110 (the region that will later become the region 108N). In this region, the concentration of the impurity element 140 is higher than that in the region 108L. In addition, the concentration gradient profile of the impurity element 140 in the depth direction is May differ from 08L.

[0207] [Formation of insulating layer 116 and region 108N] Next, a process of supplying hydrogen to the exposed region of the semiconductor layer 108 is performed. The insulating layer 116 containing hydrogen is formed in contact with the exposed region of the semiconductor layer 108. (Figure 5(B)).

[0208] The insulating layer 116 may be formed by a plasma CVD method using a deposition gas containing hydrogen. For example, silicon nitride is formed by using a deposition gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen is contained in the film. Also, during the deposition process, the exposed portion of the semiconductor layer 108 may contain It becomes possible to supply hydrogen.

[0209] After the insulating layer 116 is formed, a heat treatment is performed to release hydrogen from the insulating layer 116. It is preferable that a part of the nitrogen, oxygen, In an atmosphere containing one or more of the rare gases, the temperature is 150° C. or higher and 450° C. or lower, preferably 200° C. It is preferable to carry out the treatment at a temperature of 0.degree. C. or higher and 400.degree. C. or lower.

[0210] By supplying hydrogen in this manner, a region 108N having extremely low resistance is formed in the semiconductor layer 108. The region 108N has a higher carrier concentration than the region 108L. These are also called regions with high oxygen vacancies, regions with high hydrogen concentrations, or regions with high impurity concentrations. This can be done.

[0211] Alternatively, the insulating layer 116 and the region 108N may be formed by the following method.

[0212] First, the insulating layer 116 is formed in contact with the exposed region of the semiconductor layer 108 .

[0213] The insulating layer 116 may be made of aluminum, titanium, tantalum, tungsten, chromium, or A film containing at least one metal element such as ruthenium is formed. It is preferable that the material contains at least one of tungsten, tantalum, and tungsten. A nitride containing at least one of these metal elements, or a compound containing at least one of these metal elements The insulating layer 116 can be formed of an aluminum titanium nitride film or an oxide film. Nitride films such as titanium nitride film and aluminum nitride film, and oxide films such as titanium aluminum oxide film A nitride film or the like can be suitably used.

[0214] Here, the insulating layer 116 is formed by sputtering using nitrogen gas or oxygen gas as a deposition gas. It is preferable to form the film by the method described above. By controlling the flow rate of the film forming gas, The film quality can be easily controlled.

[0215] Next, a heat treatment is performed. By the heat treatment, the area of ​​the semiconductor layer 108 in contact with the insulating layer 116 is The resistance of the region is reduced, and a low-resistance region 108N is formed in the semiconductor layer 108.

[0216] The heat treatment is preferably carried out in an inert gas atmosphere such as nitrogen or a rare gas. The higher the processing temperature, the more preferable. However, the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, etc. For example, the temperature can be set to 120° C. or higher and 500° C. or lower, preferably 15 0°C or higher and 450°C or lower, more preferably 200°C or higher and 400°C or lower, and even more preferably 2 The temperature can be 50°C or higher and 400°C or lower. For example, the heat treatment temperature can be about 350°C. By achieving this, it is possible to produce semiconductor devices with a high yield rate using production equipment that uses large glass substrates. It is possible.

[0217] In this case, the insulating layer 116 is not removed, so the heat treatment can be performed after the insulating layer 116 is formed. The heat treatment may be carried out at any stage. The heat treatment may be carried out simultaneously with other heat treatments or heat-related processes. You can sleep.

[0218] By the heat treatment, oxygen in the semiconductor layer 108 is extracted into the insulating layer 116. The oxygen vacancies are generated. The oxygen vacancies are bonded to hydrogen in the semiconductor layer 108, The carrier concentration increases, and the resistance of the region 108N in contact with the insulating layer 116 decreases.

[0219] Alternatively, the metal elements contained in the insulating layer 116 may be diffused into the semiconductor layer 108 by the heat treatment. By doing so, a part of the semiconductor layer 108 may be alloyed, resulting in a lower resistance.

[0220] Alternatively, nitrogen or hydrogen contained in the insulating layer 116, or nitrogen contained in the atmosphere of the heat treatment, The silicon or the like diffuses into the semiconductor layer 108 by heat treatment, and the area in contact with the insulating layer 116 There may also be a case where the resistance of the region 108N becomes low.

[0221] The region 108N of the semiconductor layer 108, which has a low resistance due to such a complex action, is extremely The region 108N thus formed is a stable low-resistance region. Even if a process in which oxygen is supplied is performed, the resistance is not easily increased.

[0222] In this embodiment, the insulating layer 11 having insulating properties is used as the layer for forming the region 108N. 6 is used in the example described above, but a conductive film is used in contact with the region that will become the region 108N. In this case, after the formation of the region 108N, The conductive film can be oxidized or nitrided to be insulated, to form the insulating layer 116. Alternatively, the film may be removed after the region 108N is formed, and the insulating layer 116 may not be provided. It may also be composed of.

[0223] In this manner, the region 108N can be formed.

[0224] In addition, by carrying out the above-mentioned heat treatment, the regions 108L and 108N can be more stably For example, by performing a heat treatment at the above temperature, The impurity element 140 is appropriately diffused and locally homogenized, and an ideal concentration gradient of the impurity element is formed. In addition, the region 108L, the region 108N, and the region 110d having the above structure can be formed by the heat treatment. If the processing temperature is too high (for example, 500° C. or higher), the impurity elements 140 will be removed from the region 108L. This may lead to a deterioration in the electrical characteristics and reliability of the transistor. do.

[0225] In addition, when the impurity element 140 is supplied to the region 108L and the region 108N, the semiconductor layer 1 In some cases, defects in the insulating layer 08 or the insulating layer 110 can be repaired by a heat treatment.

[0226] In addition, oxygen is introduced from the insulating layer 110 to the channel formation region of the semiconductor layer 108 by the heat treatment. At this time, the protruding portion of the insulating layer 110 is provided with a layer near the interface with the region 108L. Since a region 110d to which the impurity element 140 is supplied is formed adjacent to the insulating layer 110, The oxygen released from the region 108 is prevented from diffusing into the region 108L. In addition, the insulating layer 11 can be effectively prevented from becoming highly resistive. A region 110d is formed in a portion overlapping with the channel forming region of the semiconductor layer 108 of FIG. Therefore, oxygen released from the insulating layer 110 is selectively supplied to the channel forming region. It is possible.

[0227] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed on the insulating layer 116 (FIG. 6(A)).

[0228] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, the region 1 Depending on the impurities contained in the regions 108N and 108L, the impurities may be There is a risk of diffusion to the surrounding area including the channel formation region. As a result, the channel formation region is The electrical resistance of the region 108N or the region 108L may increase. The temperature for forming the insulating layer 116 or the insulating layer 118 is, for example, 150° C. or higher. 400°C or less, preferably 180°C to 360°C, more preferably 200°C to 25 The insulating layer 118 is preferably formed at a low temperature of 0° C. or less. Even a transistor with a short length can have good electrical characteristics.

[0229] After the insulating layer 118 is formed, heat treatment may be performed.

[0230] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118 and a part of the insulating layer 116 are etched to form an opening 114 reaching the region 108N. 41a and an opening 141b are formed.

[0231] [Formation of Conductive Layer 120a and Conductive Layer 120b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 6(B)).

[0232] Through the above steps, the transistor 100A can be manufactured.

[0233] [Modification of the Example of the Manufacturing Method] Hereinafter, a manufacturing method example that is partially different from the above manufacturing method example will be described. Explanation of overlapping parts will be omitted, and only differences will be explained.

[0234] [Variation 1] First, the conductive layer 106, the insulating layer 103, and the semiconductor layer 108 are formed in the same manner as described above. Then, an insulating film 110f, a metal oxide film 114f, and a conductive film 112f are formed. A resist mask 115 is formed on 2f.

[0235] Next, the metal oxide film 114f and the conductive film 112f are etched to remove the metal oxide layer 11 4 and a conductive layer 112 are formed (FIG. 7(A)).

[0236] At this time, the metal oxide layer 114 and the conductive layer 112 are formed to be etched away from the contour of the resist mask 115. For example, the metal oxide film 114f and the conductive film 114c are first processed so that the end portion is located on the inside. After etching 12f by anisotropic etching, the size is removed by isotropic etching. The metal oxide layer 114 and the conductive layer 112 are formed by etching.

[0237] Next, the insulating film 110f is anisotropically etched using the resist mask 115. As a result, the outer periphery of the conductive layer 112 is The insulating layer 110 having a protruding portion on the side can be formed. Remove Q115.

[0238] By using this method, when etching the metal oxide film 114f and the conductive film 112f, Since the semiconductor layer 108 is not exposed, these components are scattered on the surface of the semiconductor layer 108, This prevents adhesion of the metal to the substrate, which makes it possible to realize highly reliable transistors. Cut.

[0239] The above description can be applied to the subsequent steps.

[0240] [Modification 2] First, the conductive layer 106, the insulating layer 103, and the semiconductor layer 108 are formed in the same manner as described above. Then, an insulating film 110f, a metal oxide film 114f, and a conductive film 112f are formed. A resist mask is formed over the conductive film 112f, and the conductive film 112f and the metal oxide film 114f are By etching, the metal oxide layer 114 and the conductive layer 112 are formed. The resist mask may have the same pattern as the resist mask 115, but It is preferable that the resist mask 11 is a pattern that covers the region that will become the conductive layer 112. When the same pattern as in the modification 5 is used, the metal oxide film 114f and the conductive The film 112f is side-etched, and then the resist mask is removed.

[0241] Next, the conductive layer 112 is used as a mask to perform a masking process on the insulating film 110f and the semiconductor layer 108. The impurity element 140 is added to the conductive layer of the semiconductor layer 108 (FIG. 8A). A region 108L doped with an impurity element can be formed in a portion not overlapping with 112. At the same time, the region 110d in which the impurity element is added in the insulating film 110f and the insulating layer 110c are In the semiconductor substrate 03, a region 103d is formed in which an impurity element is added.

[0242] Next, a resist mask is applied to cover the upper and side surfaces of the conductive layer 112 and the metal oxide layer 114. The resist mask 115 is a pattern that covers the area that will become the insulating layer 110. Thereafter, the insulating film 110f is etched to form a portion protruding beyond the conductive layer 112. The insulating layer 110 having the portion is formed, and a portion of the semiconductor layer 108 (region 108N and (Fig. 8(B)).

[0243] At this stage, hydrogen may be added to the exposed part of the semiconductor layer . For example, the resist mask 115 is used as a mask to perform ion doping or ion Hydrogen may be added by a method such as injection. Alternatively, the hydrogen may be added by heating in an atmosphere containing hydrogen. When a heat treatment is performed, the resist mask 115 may be altered. Therefore, it is preferable to remove the conductive layer 112 before the heat treatment. In this state, a heat treatment is performed in an atmosphere containing hydrogen to remove oxide on the surface of the conductive layer 112. It is also expected to have the secondary effect of reducing and removing

[0244] Next, the insulating layer 11 is formed in contact with the exposed portion of the semiconductor layer 108 by the same method as above. 6 is formed and then a heat treatment is performed to form a region 108N (FIG. 8C).

[0245] In this manner, when the impurity element 140 is added, the region 1 of the semiconductor layer 108 is The region that will become region 108L and the region that will become region 108N are both covered with an insulating film 110f. Since the impurity concentration profiles in the depth direction are the same, In addition, when etching the insulating film 110f, the conductive layer Since the conductive layer 112 and the metal oxide layer 114 are covered with the resist mask 115 and are not exposed, A part of the components of the metal oxide layer 112 and the metal oxide layer 114 may adhere to the surface of the semiconductor layer 108. This can be prevented.

[0246] The above description can be applied to the subsequent steps.

[0247] The above is a description of the modified example of the manufacturing method.

[0248] [Components of Semiconductor Devices] Next, components included in the semiconductor device of this embodiment will be described in detail.

[0249] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates A plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. are used as the substrate 102. In addition, the substrate 102 may be a substrate on which a semiconductor element is provided. It may be used.

[0250] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100, etc. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 10 can be separated from the semiconductor device 10 and transferred to another substrate. 0 etc. can be transferred to substrates with poor heat resistance or flexible substrates.

[0251] [Insulating layer 103] The insulating layer 103 is formed by sputtering, CVD, evaporation, pulsed laser deposition (PLD), or the like. The insulating layer 103 can be formed by, for example, an oxide film. The semiconductor layer may be a single layer or a multilayer structure of a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, the insulating layer 103 is The region in contact with the insulating layer 103 is preferably formed using an oxide insulating film. It is preferable to use a membrane which releases oxygen by

[0252] The insulating layer 103 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a multilayer.

[0253] In addition, the insulating layer 103 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the above-mentioned film is used, a pretreatment such as an oxygen plasma treatment is performed on the surface in contact with the semiconductor layer 108. and oxidizing the surface or the vicinity of the surface.

[0254] [Conductive Film] The conductive layer 112 and the conductive layer 106 function as a gate electrode, and a source electrode or drain electrode. A conductive layer 120a functions as one of the drain electrodes, and a conductive layer 120b functions as the other drain electrode. b: chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium tungsten, manganese, nickel, iron, cobalt, or any of the above. The alloys are made of the above metal elements or alloys combining the above metal elements. Each of them can be formed.

[0255] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. Alternatively, an oxide conductor or a metal oxide film may be used.

[0256] Here, we will explain about oxide conductors (OC). For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. Then, a donor level is formed near the conduction band. As a result, the metal oxide has high electrical conductivity. The metal oxide that has been made conductive can be called an oxide conductor.

[0257] In addition, as the conductive layer 112, etc., a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating film that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0258] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is preferable to use one or more of the above. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and has the following properties with respect to copper, oxygen, and hydrogen: Since the barrier layer 104 has a high barrier property and releases little hydrogen from itself, it is preferable that the barrier layer 104 is in contact with the semiconductor layer 108. It can be suitably used as a conductive film or a conductive film in the vicinity of the semiconductor layer 108 .

[0259] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. Silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film tungsten oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, Magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film, or more The insulating layer 110 may have a laminated structure of two layers or three or more layers. The above laminated structure may also be used.

[0260] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above-mentioned method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film is formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film therein.

[0261] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. It is possible to suppress leakage current caused by tunnel current. In particular, hafnium oxide, which has crystallinity, is It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0262] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in this study must have an atomic ratio of In to M of 1 or more. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2: 4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn= 5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. .

[0263] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 having crystallinity can be easily formed. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering used for the semiconductor layer 108 may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], the film is formed. The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. There may be cases where this occurs.

[0264] In addition, when the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, When Ga is 4, this includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when describing that the atomic ratio is In:Ga:Zn=5:1:6 or close to that, When n is 5, Ga is greater than 0.1 and is equal to or less than 2, and Zn is equal to or greater than 5 and is equal to or less than 7. Also, the atomic ratio is In:Ga:Zn=1:1:1 or in the vicinity. When mounting, when In is 1, Ga is greater than 0.1 and less than 2, and Zn is 0. Includes cases greater than 1 and less than or equal to 2.

[0265] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0266] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure described below. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0267] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0268] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystal structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which the film is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0269] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. The crystallinity can be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). The physical properties of an oxide semiconductor having an OS are stable. The oxide semiconductor used is heat resistant and highly reliable.

[0270] In crystallography, the three axes that make up a unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the lattice. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis that intersects the layers is the Generally, the c-axis is taken as the c-axis. A typical example of a crystal with such a layered structure is Graphite is classified as a hexagonal crystal, and the a- and b-axes of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The InGaZnO4 crystal can be classified as a hexagonal system, and the a-axis and The a- and b-axes are parallel to the plane of the layer, and the c-axis is perpendicular to the layers (i.e., the a- and b-axes).

[0271] An oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film) is shown in the TEM image. In some cases, it may not be possible to clearly identify the crystal parts in the microcrystalline oxide semiconductor film. The crystal part has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, microcrystals with sizes between 1 nm and 10 nm or between 1 nm and 3 nm are often An oxide semiconductor film having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) film In addition, the grain boundaries of the nc-OS film can be clearly seen in the TEM images. There may be cases where this is not possible.

[0272] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that in the crystalline region. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam of 50 nm or more (for example) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using the electron beam shown below, a circle is drawn. A bright area is observed (ring-shaped) and multiple spots are observed within that area. This may be the case.

[0273] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S-film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to OS films, the carrier density and electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0274] The nc-OS film is formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a low temperature compared to the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is relatively low (for example, below 130°C) or the board is not heated. Since it can form films even on large glass substrates, it is suitable for use with large glass substrates or resin substrates. This allows for increased productivity.

[0275] An example of the crystal structure of a metal oxide will be described. In the following, In-Ga-Zn oxide Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). A metal oxide film formed by the ring method will be described as an example. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either the nc (nano crystal) structure or the CAAC structure. On the other hand, the substrate temperature is set to room temperature (RT). Metal oxides formed by sputtering tend to have an nc crystal structure. Room temperature (RT) as used herein includes the temperature at which the substrate is not intentionally heated.

[0276] [Metal oxide composition] The following describes a CAC (C This paper explains the configuration of the Multicloud Aligned Composite Operating System (MSO).

[0277] In this specification, CAAC (c-axis aligned crystal l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Shows an example.

[0278] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has a function of insulating in part and a function of semiconductor in the whole material. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a layer, the conductive function is to allow the flow of electrons (or holes) that serve as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the function of the material and the function of the material complement each other, the material can be switched (On / Off). The function of ff can be given to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the functions are separated. By combining them, the functions of both can be maximized.

[0279] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0280] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than one millimeter.

[0281] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide gap component due to the insulating region and a conductive region. In this configuration, when the carrier flows, In addition, carriers mainly flow in the narrow gap component. The component with a gap acts complementary to the component with a wide gap to produce a narrow gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field effect mobility can be obtained.

[0282] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0283] The above is a description of the components.

[0284] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0285] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain about this.

[0286] [Configuration example] FIG. 9A is a top view of a display device 700. The display device 700 is provided with a sealant 712. The first substrate 701 and the second substrate 705 are bonded together. In the region sealed by the second substrate 705 and the sealant 712, the first substrate 701 A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided on the substrate. The pixel portion 702 is provided with a plurality of display elements.

[0287] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. Through the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 Various signals are supplied to each of these.

[0288] A plurality of gate driver circuit sections 706 may be provided. The path portion 706 and the source driver circuit portion 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is mounted on the first substrate 70. 1, or can be mounted on FPC716.

[0289] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0290] Examples of a display element provided in the pixel portion 702 include a liquid crystal element and a light emitting element. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, etc. are used. The light emitting element can be LED (Light Emitting Diode). Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs and semiconductor lasers. MEMS (Micro Electro Mechanical Systems) using the optical interferometry or optical interference method l Systems) elements, microcapsule type, electrophoretic type, electrowet type Display elements using the electronic powder method or the like can be used. It is also possible.

[0291] A display device 700A shown in FIG. 9B is a display device having a flexible resin instead of the first substrate 701. A display device having an adhesive layer 743 and capable of being used as a flexible display. Here is an example.

[0292] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in a region P1 in FIG. 9B, the pixel section 702 and a part of the resin layer 743 The pair of gate driver circuit sections 706 are connected to the pixel section 70. The gate driver circuit section 706 is provided on both sides of the pixel section 702. , the recess is provided along a circular arc-shaped contour.

[0293] The resin layer 743 has a protruding shape at the portion where the FPC terminal portion 708 is provided. Also, a part of the resin layer 743 including the FPC terminal portion 708 is disposed on the back side in the region P2 in FIG. By folding back a part of the resin layer 743, the FPC 716 can be attached to the pixel section 7 The display device 700A can be mounted on the back of the display device 02 in such a state that the display device 700A is mounted on the back of the display device 02. This makes it possible to reduce the space required for electronic devices.

[0294] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. The source driver circuit section 704 in 00A includes a protection circuit, a buffer circuit, a demultiplexer, The configuration may include at least one of a crosstalk circuit, etc.

[0295] The display device 700B shown in FIG. 9C can be suitably used in electronic devices having a large screen. The display device 700B is, for example, a television device, a monitor device, , personal computers (including notebook and desktop computers), tablet devices, It can be suitably used for digital signage and the like.

[0296] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuits. The sensor 722 has a first section 722.

[0297] The source driver ICs 721 are each attached to an FPC 723. In addition, the plurality of FPCs 723 are arranged such that one terminal is connected to the first board 701 and the other terminal is connected to the printed board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things.

[0298] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0299] With this configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It is possible to realize a display device with a resolution of 4K2K or 8K4K. It is possible to realize a display device with extremely high resolution.

[0300] [Cross-section example] The following describes a configuration in which a liquid crystal element is used as a display element, and a configuration in which an EL element is used. 10 to 13. Note that FIGS. 10 to 12 are respectively the same as FIG. 9(A). FIG. 13 is a cross-sectional view taken along the dashed line QR shown in FIG. 9(B). 10 and 11 are cross-sectional views of the display element 700A taken along dashed line ST. 12 and 13 show a configuration using an EL element.

[0301] [Description of common parts of the display device] The display device shown in FIG. 10 to FIG. 13 includes a wiring portion 711, a pixel portion 702, and a The wiring section 711 includes a driver circuit section 704 and an FPC terminal section 708. 7 and a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. The absence of element 790 is shown.

[0302] The transistor 750 and the transistor 752 are the transistors exemplified in the first embodiment. can be applied.

[0303] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The retention time of the image signal can be extended, and the interval between writing the image signal can be set to be longer. Since the frequency of refresh operations can be reduced, this has the effect of reducing power consumption.

[0304] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in a device, the switching transistor in the pixel section and the driver circuit section In other words, the transistors can be formed on the same substrate, such as a silicon wafer. It is also possible to adopt a configuration that does not use a driving circuit formed by the above-mentioned method, and the number of parts of the display device can be reduced. In addition, by using a transistor capable of high speed operation in the pixel portion, It is possible to provide high quality images.

[0305] The capacitor 790 shown in FIG. 10, FIG. 12, and FIG. 13 is a third capacitor included in the transistor 750. The lower electrode is formed by processing the same film as the gate electrode in 1, and the same metal oxide as the semiconductor layer is and an upper electrode formed by processing a material. The upper electrode is a source electrode of the transistor 750. The resistance of the gate electrode is reduced in the same manner as the source and drain regions. A part of an insulating film that functions as a first gate insulating layer of the transistor 750 is provided on the That is, the capacitor 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. The upper electrode is a layered structure in which the source electrode and drain electrode of the transistor are formed. The electrodes are connected to wiring obtained by processing the same film as the electrodes.

[0306] In addition, a planarization insulating layer is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0307] A transistor 750 included in the pixel portion 702 and a transistor 751 included in the source driver circuit portion 704 A transistor having a different structure from the transistor 752 may be used. For example, A top-gate transistor is applied to one side and a bottom-gate transistor is applied to the other side. The gate driver circuit section 706 may also be configured using a source driver. This is similar to the driver circuit section 704.

[0308] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0309] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, and an anisotropic conductive film 78. The wiring 760 is connected to the FPC 710 via an anisotropic conductive film 780. In this example, the wiring 760 is electrically connected to a terminal of the transistor 750, The source electrode and drain electrode 752 are formed from the same conductive film.

[0310] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used as the first substrate 701. When using a substrate that can be used for the first substrate 701, water or water may be provided between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer having a barrier property against elements.

[0311] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and insulating films in contact with these are provided. A border membrane 734 is provided.

[0312] [Example of the configuration of a display device using a liquid crystal element] The display device 700 shown in FIG. 10 includes a liquid crystal element 775 and a spacer 778. The element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The electrode layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over the planarization insulating film 770 and functions as a pixel electrode. do.

[0313] The conductive layer 772 can be formed using a material that transmits or reflects visible light. The transparent material may be, for example, an oxide material containing indium, zinc, tin, etc. As the reflective material, for example, a material containing aluminum, silver, etc. is used. It is good.

[0314] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive type. In the case of a liquid crystal display device of the transmission type, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0315] The display device 700 shown in FIG. 11 includes a liquid crystal element 77 of a horizontal electric field type (for example, an FFS mode). 5 is formed on a conductive layer 772 with an insulating layer 773 interposed therebetween, the insulating layer 773 serving as a common electrode. A conductive layer 774 is provided. An electric field is generated between the conductive layer 772 and the conductive layer 774, The alignment state of the liquid crystal layer 776 can be controlled.

[0316] In FIG. 11, a holding container is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0317] Although not shown in FIGS. 10 and 11, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as a backlight and a sidelight can be provided as appropriate.

[0318] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, etc. Crystal (PDLC: Polymer Dispersed Liquid Crystal) , Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the lateral electric field mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0319] The liquid crystal element modes are Twisted Nematic (TN) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optically Compensated Biref ringence mode, ECB (Electrically Controlled Birefringence mode, guest host mode, etc. .

[0320] In addition, the liquid crystal layer 776 is made of a polymer dispersed liquid crystal or a polymer network liquid crystal. A scattering type liquid crystal element can also be used. In this case, the color film 736 is not provided, and black and white display is possible. Alternatively, a colored film 736 may be used to perform color display.

[0321] In addition, as a driving method for liquid crystal elements, a time-series additive color mixing method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the color film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors R (red), G (green), and B (blue). This has the advantage of improving the aperture ratio of pixels and increasing the definition.

[0322] [Display device using light-emitting element] The display device 700 shown in FIG. 12 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound, has inorganic compounds such as quantum dots.

[0323] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, etc.

[0324] In the display device 700 shown in FIG. 12, a conductive layer 772 is provided on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. Note that the light-emitting element 782 emits light toward the conductive layer 772. A bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788 can be used. It may also be a dual emission structure.

[0325] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light shielding film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting. In some cases, the colored film 736 may not be provided.

[0326] FIG. 13 shows a configuration of a display device that can be suitably applied to a flexible display. FIG. 13 is a cross-sectional view taken along dashed line ST in the display device 700A shown in FIG. It is.

[0327] A display device 700A shown in FIG. 13 includes a support substrate instead of the first substrate 701 shown in FIG. It has a laminated structure of a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744. The transistor 750, the capacitor 790, and the like are formed on an insulating layer 744 provided on a resin layer 743. It is provided in.

[0328] The support substrate 745 is a substrate that contains organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The resin layer 74 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferably thinner than the supporting substrate 745 .

[0329] 12. In addition, the display device 700A shown in FIG. 13 includes a protective layer 704 instead of the substrate 705 shown in FIG. 40. The protective layer 740 is attached to the sealing film 732. A glass substrate or a resin film can be used as the protective layer 740. , polarizing plates, scattering plates, and other optical components, input devices such as touch sensor panels, and the like. A configuration in which two or more of these are stacked may be applied.

[0330] In addition, the EL layer 786 of the light-emitting element 782 is an island on the insulating film 730 and the conductive layer 772. The EL layer 786 is formed so that each subpixel emits a different light. In this way, color display can be achieved without using the color film 736. A protective layer 741 is provided to cover the light emitting element 782. The protective layer 741 protects the light emitting element 782 from inclusions such as water. The protective layer 741 has a function of preventing diffusion of impurities. It is also preferable to use a laminated structure including at least one inorganic insulating film and at least one organic insulating film. preferable.

[0331] 13 shows a bendable region P2. In the region P2, the support substrate 7 45, in addition to the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. The bendable region P2 is provided with as little inorganic insulating film as possible, and is provided with a conductive material containing a metal or an alloy. By laminating only layers containing organic materials, cracks do not occur when the material is bent. In addition, by not providing the support substrate 745 in the region P2, A portion of the display device 700A can be bent with a small radius of curvature.

[0332] [Example of configuration in which an input device is provided on a display device] Moreover, an input device may be provided in the display device shown in FIG. An example of such a sensor is a touch sensor.

[0333] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, etc. Various methods can be used, such as a pressure-sensitive, optical, or pressure-sensitive method. Or, two or more of these can be used. may be used in combination.

[0334] The touch panel is of the so-called in-cell type, in which the input device is formed between a pair of substrates. The touch panel of the present invention is a so-called on-cell type touch panel in which an input device is formed on a display device. There are also so-called out-cell type touch panels, which are used by attaching them to a display device.

[0335] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0336] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0337] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0338] The display device shown in FIG. 14A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 505. 6 and a terminal portion 507. Note that the protection circuit 506 may be omitted. .

[0339] The transistors in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also use the transistor of one embodiment of the present invention. may be applied.

[0340] The pixel section 502 is a multi-layered pixel array arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The pixel circuit 501 includes a number of pixel circuits 501 for driving a number of display elements.

[0341] The driver circuit unit 504 includes a gate driver that outputs scanning signals to the scanning lines GL_1 to GL_X. 504a, a source driver 50 for supplying data signals to the data lines DL_1 to DL_Y. The gate driver 504a includes at least a shift register. The source driver 504b may be, for example, a plurality of analog switches. Also, the source driver 504b is configured using a shift register, etc. may be configured as follows.

[0342] The terminal unit 507 is a terminal for inputting power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals are provided for connecting the power supply to the power source.

[0343] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, Various wiring such as the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501, Connected.

[0344] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film) The circuit board is bonded to the board by COG or TAB (Tape Automated Bonding). It may also be configured to be mounted on a substrate.

[0345] In addition, the pixel circuits 501 shown in FIG. 14(A) may be, for example, The configuration shown in FIG.

[0346] The pixel circuit 501 shown in FIG. 14B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0347] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0348] The pixel circuit 501 shown in FIG. 14C includes transistors 552 and 554 and a capacitance element. The pixel circuit 501 includes a data line DL_n , the scanning line GL_m, the potential supply line VL_a, the power supply line VL_b, etc. are connected to the pixel electrodes GL_m, GL_m.

[0349] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. A low power supply potential VSS is applied to the gate of the transistor 554. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0350] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0351] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0352] (Embodiment 4) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0353] [Circuit configuration] FIG. 15A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0354] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, The other end is connected to one electrode of the capacitor C1. The gate of the transistor M2 is G2, one of the source and drain is the wiring S2, and the other is the other electrode of the capacitance C1, and 401 and 402, respectively.

[0355] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) ems) elements, etc. can be applied.

[0356] The node connecting the transistor M1 and the capacitor C1 is the node N1, and the transistor M2 is the The node connecting to the path 401 is node N2.

[0357] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via transistor M1, capacitive coupling via capacitor C1 This makes it possible to change the potential of the node N2 in response to a change in the potential of the node N1.

[0358] Here, in one or both of the transistors M1 and M2, The transistor using an oxide semiconductor, which is exemplified in 1, can be used. Therefore, the potentials of the nodes N1 and N2 can be maintained for a long period of time due to the extremely low off-current. In addition, when the period for which the potential of each node is held is short (specifically, when the frame In cases where the system frequency is 30 Hz or more, transistors using semiconductors such as silicon A meter may also be used.

[0359] [Driving method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. 4B is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, we have not included various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The effects of the transistor threshold voltage, etc. are not taken into account.

[0360] In the operation shown in FIG. 15B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0361] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the line S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supplies.

[0362] The node N1 is connected to a potential V ref is given. In addition, the node N2 is supplied with a first data potential V w is given. Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0363] [Period T2] In the next period T2, a potential is applied to the wiring G1 to turn on the transistor M1. A potential for turning off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. The state may be a locking state.

[0364] A second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N 2 changes by a potential dV. That is, the circuit 401 has a first data potential V w And electricity In FIG. 15B, the potential dV is a positive value. However, it may be a negative value. That is, the second data potential V dat a is the potential V ref It may be lower.

[0365] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes the second Data potential V data The potential becomes close to

[0366] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the line 401 can be generated, the gray scale correction can be performed within the pixel circuit 400. It will be possible to do so.

[0367] In addition, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when liquid crystal elements are used, overdriving is possible. It is possible to realize drive such as a spring.

[0368] [Example of application] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 15C includes a circuit 401LC. has a liquid crystal element LC and a capacitance C2.

[0369] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the Potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0370] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0371] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Achieving high-speed display through overdrive operation and using liquid crystal materials with high drive voltage In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0372] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 15D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0373] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the One of the rains is at potential V H The other is one electrode of the light-emitting element EL. The capacitor C2 is connected to the other electrode at potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0374] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0375] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value of can be changed appropriately.

[0376] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, the transistor It is also possible to correct the variations in the electrical characteristics of M3 and the light-emitting element EL.

[0377] In addition, the circuit is not limited to the circuits shown in FIG. 15(C) and (D), and may include other transistors, capacitors, etc. may be added.

[0378] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0379] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. I will explain this in more detail.

[0380] The display module 6000 shown in FIG. 16(A) includes an upper cover 6001 and a lower cover 6002. A display device 6006, a frame 6009, and a printer 6002 are connected to the FPC 6005. The semiconductor device has a support substrate 6010 and a battery 6011.

[0381] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0382] The upper cover 6001 and the lower cover 6002 are adapted to the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0383] The display device 6006 may have a function as a touch panel.

[0384] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0385] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0386] FIG. 16B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. It is.

[0387] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guiding portions (light guiding portion 6017a, light guiding portion 6017b).

[0388] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are disposed on top of the light guide unit 6011. 017a and fixed to light guiding portion 6017b.

[0389] Light 6018 emitted from the light emitting portion 6015 is guided to the display device 600 by the light guiding portion 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0390] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information on the position where the touch operation was performed.

[0391] The light emitting unit 6015 may be a light source such as an LED element, and in particular, may be a light source that emits infrared rays. It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that can receive light and convert it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0392] The light guiding portion 6017a and the light guiding portion 6017b transmit light 6018. The light receiving unit 6016 can be disposed under the display device 6006, and external light is received by the light receiving unit 601. 6, which prevents the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively prevented.

[0393] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0394] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Reveal.

[0395] The electronic device 6500 shown in FIG. 17(A) is a mobile device that can be used as a smartphone. It is a portable information terminal.

[0396] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, and a button 6 504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0397] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0398] FIG. 17B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0399] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. In the space surrounded by the protective member 6510, a display panel 6511, an optical member 6512, and a The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. There are.

[0400] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The panel 6513 is fixed by an adhesive layer (not shown).

[0401] In addition, in an area outside the display portion 6502, a part of the display panel 6511 is folded back. The folded part is connected to the FPC6515. The 6515 is equipped with IC 6516. The FPC 6515 is a printed circuit board 6 517.

[0402] A flexible display panel according to one embodiment of the present invention is applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. 1 is extremely thin, so it can accommodate a large-capacity battery 6518 while keeping the thickness of the electronic device to a minimum. Also, a part of the display panel 6511 can be folded back and an FPC can be attached to the back side of the pixel area. By arranging the connection part with 6515, it is possible to realize electronic devices with narrow bezels.

[0403] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0404] (Embodiment 7) In this embodiment, an electronic device including a display device manufactured according to one embodiment of the present invention will be described. I will explain this in more detail.

[0405] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and large screen It is possible to provide an electronic device that is compatible with both.

[0406] The display unit of the electronic device according to one embodiment of the present invention may be a display device that supports, for example, full high definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0407] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices that can be used for personal computers, digital cameras, digital video cameras, digital photo frames, mobile phones, etc. Examples of the portable electronic device include mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0408] An electronic device to which one aspect of the present invention is applied is installed on the inner or outer wall of a house or building, the interior of a car, etc. The sensor can be installed along a flat or curved surface of a housing or exterior.

[0409] FIG. 18A shows the appearance of a camera 8000 with a viewfinder 8100 attached. This is a diagram.

[0410] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0411] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0412] The camera 8000 can be operated by pressing the shutter button 8004 or by using a touch panel. By touching the display portion 8002, an image can be captured.

[0413] The housing 8001 has a mount having electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as a

[0414] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0415] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The Finder 8100 is attached to the Camera 8000. The information can be displayed on the display unit 8102 .

[0416] The button 8103 has a function such as a power button.

[0417] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied to a camera having a built-in viewfinder. It may be La 8000.

[0418] FIG. 18B is a diagram showing the external appearance of the head mounted display 8200.

[0419] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0420] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0421] In addition, the attachment part 8201 is provided with a flow sensor that flows in accordance with the movement of the user's eyeball at a position where the attachment part 8201 touches the user. A plurality of electrodes capable of detecting a current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse rate of the user by measuring the current flowing through the electrodes. In addition, the mounting part 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information on the display unit 8204. The display portion 8204 may have a function of changing an image displayed on the display portion 8204 in accordance with the user's movement.

[0422] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0423] 18(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, and a backlight. The optical element has a band-shaped fixture 8304 and a pair of lenses 8305.

[0424] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but may be configured in such a way that two display units 8302 are provided and one of the display units is One display unit may be arranged for each eye.

[0425] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0426] The electronic device shown in FIG. 19A to FIG. 19G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0427] The electronic devices shown in FIGS. 19A to 19G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by a wireless communication function, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data, etc. The electronic device may have a variety of functions, but is not limited to these. Also, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external It has the functions of storing the captured image on a memory card (built into the camera or the internal memory) and displaying the captured image on the display. It is okay to do so.

[0428] The electronic devices shown in FIGS. 19A to 19G will be described in detail below.

[0429] FIG. 19A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more or 100 inches or more It is possible to incorporate.

[0430] FIG. 19B is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. In the example shown in FIG. 9, three icons 9050 are displayed. 051 can be displayed on another surface of the display unit 9001. , notifications of incoming e-mails, SNS, phone calls, etc., subject of e-mails and SNS, sender Name, date, time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0431] FIG. 19C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example in which information 9053 and information 9054 are displayed on different sides is shown. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check information 9053 displayed in a position that can be observed from above 2. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0432] 19(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can communicate with, for example, a wireless headset. Therefore, a hands-free call is also possible. The device 9006 can transmit data to and from other information terminals and can also charge the device. The charging operation may be performed by wireless power supply.

[0433] 19(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 19(E) shows the portable information terminal 9201 in an unfolded state, and FIG. 19(G) shows the portable information terminal 9201 in a folded state. Figure 19(F) shows the state where the two are changing from Figure 19(E) to Figure 19(G). The portable information terminal 9201 is highly portable when folded and is unfolded and is in a perspective view. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. For example, the display unit 9001 is curved with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0434] FIG. 20A shows an example of a television device. A television device 7100 includes a housing 7 A display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0435] The television device 7100 shown in FIG. 20A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75 A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control operation device 7111 may have a display unit in addition to the operation buttons.

[0436] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0437] FIG. 20B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, The display unit 7500 is assembled in the housing 7211. It is embedded in the

[0438] Figure 20(C) and (D) show digital signage. An example of a sub-sign is shown below.

[0439] The digital signage 7300 shown in FIG. 20C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0440] FIG. 20(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0441] The larger the display 7500, the more information can be provided at once, and the closer it is to the human eye. Since it is easy to attach to the skin, it has the effect of increasing the effectiveness of advertising, for example.

[0442] It is preferable that a touch panel be applied to the display unit 7500 so that a user can operate it. This will enable the use of the information not only for advertising purposes, but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide users with information they are looking for.

[0443] Also, as shown in FIG. 20(C) and (D), the digital signage 7300 or the digital The signage 7400 is connected wirelessly to an information terminal 7311 such as a smartphone carried by a user. For example, the advertisement displayed on the display unit 7500 may be The information is displayed on the screen of the information terminal 7311, and the information terminal 7311 is operated. In this way, the display on the display unit 7500 can be switched.

[0444] In addition, the Digital Signage 7300 or Digital Signage 7400 can be equipped with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0445] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. It is possible.

[0446] Although the electronic device of the present embodiment has a display unit, the present invention can be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above-mentioned semiconductor device.

[0447] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. EXAMPLES

[0448] In this example, a sample (sample A1) in which an impurity element was added to a metal oxide film and a sample (sample B2) in which a metal oxide film was added to a metal oxide film were A sample (sample A2) was prepared by supplying hydrogen to the oxide film, and its sheet resistance was evaluated.

[0449] [Sample preparation] [Sample A1] The sample A1 is a silicon oxynitride film formed on a glass substrate, and an island-shaped metal oxide film is formed on the first silicon oxynitride film. The metal oxide film is doped with ions through a second silicon oxynitride film. The sample was doped with boron by the doping method. The second silicon oxynitride film was doped with boron. After the addition of the third silicon oxynitride film, the metal oxide film is covered with the third silicon oxynitride film. An opening was formed down to the oxide film, and a terminal was provided.

[0450] In the sample A1, the metal oxide film was an In-Ga-Zn oxide film with a thickness of about 40 nm. The boron doping conditions were as follows: This was the condition under which the concentration was highest.

[0451] [Sample A2] Sample A2 is a silicon oxynitride film formed on a glass substrate, on which island-shaped metal oxide films are formed. a silicon nitride film containing hydrogen and a fourth oxide film in contact with the metal oxide film; This is a sample in which a heat treatment was performed after forming a silicon nitride film. After forming the silicon film, an opening reaching the metal oxide film was formed, and a terminal was provided.

[0452] In sample A2, the metal oxide film was formed under the same conditions as sample A1. , Plasma C using a mixture of SiH4 gas, N2 gas, and NH3 gas as the deposition gas. The film was formed by the VD method. Heat treatment was performed in a nitrogen atmosphere at 350°C for 1 hour.

[0453] [Sheet resistance] FIG. 21 shows the results of measuring the sheet resistance of the prepared samples A1 and A2.

[0454] As shown in FIG. 21, the sheet resistance of sample A1 is about 380 Ω / □, and the sheet resistance of sample A2 is about The resistance of both is 240Ω / □, and it can be confirmed that the resistance is reduced. The sheet resistance of a metal oxide film in which the carrier concentration is sufficiently reduced without treatment is The resistance is above the device's detection limit (for example, 5MΩ / □ or higher).

[0455] In addition, sample A2, to which hydrogen was supplied, had a lower resistance than sample A1, to which an impurity element was added. This suggests that adding impurity elements to a metal oxide film and then supplying hydrogen to the film can It is suggested that the carrier density is further increased and the resistance is lowered compared to samples A1 and A2. can be.

[0456] From the above results, in the transistor of one embodiment of the present invention, The second region, which is sandwiched between the first and second regions, is made of metal oxide doped with impurity elements, which allows for a relatively high The third region is a region that is highly resistive to the LDD region, and is doped with impurity elements and then immersed in water. By supplying an element, it is possible to make the source region or drain region extremely low resistance. I found out that... EXAMPLES

[0457] In this embodiment, an aluminum nitride film was formed in contact with the metal oxide film to reduce the resistance. A sample (sample B1) was prepared and its sheet resistance was evaluated.

[0458] [Sample preparation] [Sample B1] Sample B1 is a silicon oxynitride film formed on a glass substrate, on which an island-shaped metal oxide film is formed. The metal oxide film is then subjected to a first heat treatment after forming an aluminum nitride film in contact with the metal oxide film. The sample was subjected to the heat treatment. After the first heat treatment, the aluminum oxide film and After forming the silicon oxynitride film 2 and performing a second heat treatment, the metal oxide film An opening was formed through which a terminal was provided.

[0459] In the sample B1, the metal oxide film was formed under the same conditions as the sample A1 illustrated in Example 1. The aluminum oxide film was formed using an aluminum target and N2 gas and Ar gas as the deposition gas. The first heat treatment and the second heat treatment were performed by reactive sputtering using a mixed gas of benzene and benzene. The heat treatment was carried out under nitrogen atmosphere at 350° C. for 1 hour.

[0460] [Sheet resistance] The sheet resistance of the sample A1 illustrated in Example 1 and the prepared sample B1 were measured. The results are shown in Figure 22.

[0461] As shown in FIG. 22, the sheet resistance of sample A1 is about 380 Ω / □, and that of sample B1 is about The resistance of both is 270Ω / □, and it can be confirmed that the resistance is reduced. The sheet resistance of a metal oxide film in which the carrier concentration is sufficiently reduced without treatment is The resistance is above the device's detection limit (for example, 5MΩ / □ or higher).

[0462] In addition, the sample B1, which has an aluminum nitride film formed in contact with a metal oxide film, does not contain impurity elements. This shows that the metal oxide film is not doped with impurity elements. In addition, a film that easily absorbs oxygen, such as an aluminum nitride film, is formed in contact with the above. It was shown that the carrier density was increased and the resistance was lowered more than in samples A1 and B1. To be tempted.

[0463] From the above results, in the transistor of one embodiment of the present invention, The second region, which is sandwiched between the first and second regions, is made of metal oxide doped with impurity elements, which allows for a relatively high The LDD region is a highly resistive region, and a film that easily absorbs oxygen is formed on the third region outside of the LDD region. By forming a film, it is possible to form a source region or drain region with extremely low resistance. I found out that... [Explanation of symbols]

[0464] 100, 100A: transistor, 102: substrate, 103: insulating layer, 103d: region, 1 06: conductive layer, 108, 108a, b: semiconductor layer, 108L, 108N: region, 110: Insulating layer, 110d: region, 110f: insulating film, 112: conductive layer, 112f: conductive film, 11 4: metal oxide layer, 114f: metal oxide film, 115: resist mask, 116, 118 : insulating layer, 120a, b: conductive layer, 140: impurity element, 141a, b, 142: opening

Claims

[Claim 1] A semiconductor layer, a first insulating layer, and a first conductive layer, the first insulating layer is provided on the semiconductor layer; the first conductive layer is provided on the first insulating layer; the semiconductor layer has a first region overlapping the first conductive layer and the first insulating layer, a second region not overlapping the first conductive layer and overlapping the first insulating layer, and a third region not overlapping both the first conductive layer and the first insulating layer; the semiconductor layer comprises a metal oxide; the second region and the third region contain a first element; the first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium; The first element is present in a state of being bonded to oxygen. Semiconductor device.

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