Semiconductor device

Abstract

To stabilize electrical characteristics of a transistor formed by using an oxide semiconductor to improve reliability.SOLUTION: In a semiconductor device, a region containing many crystalline components and a region containing many amorphous components are individually formed on one oxide semiconductor film. The region containing many crystalline components is formed to become a channel formation region and the other regions are formed to contain many amorphous components. Preferably, an oxide semiconductor film in which a region containing many crystalline components in a self-aligned manner and a region containing many amorphous components are mixed is formed. In order to individually form regions having different crystallinities in one oxide semiconductor film, an oxide semiconductor film containing many crystalline components is formed first, and subsequently a process of making a part of the oxide semiconductor film be amorphous is performed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a transistor and a manufacturing method thereof. The present invention also relates to a transistor formed in a semiconductor device and a method for manufacturing the same. The present invention relates to a semiconductor device having a

[0002] In addition, the invention disclosed in this specification uses silicon as a component of a semiconductor integrated circuit. In addition to semiconductors, this includes elements made of compound semiconductors, one example of which is the wide-gap Applications of top semiconductors are disclosed.

[0003] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0004] Electronic and optical devices are fabricated using silicon-based transistors. In recent years, in addition to transistors using silicon, transistors using oxide semiconductors have been developed. The technology of manufacturing such materials and applying it to electronic and optical devices is attracting attention.

[0005] In an active matrix liquid crystal display device, a transistor is provided for each pixel. Such transistors are constructed using amorphous silicon, polycrystalline silicon, etc. In addition, transistors made of amorphous silicon are often used. Although the field effect mobility of the capacitor is low, it can be used for liquid crystal display devices with a large area. In addition, transistors made of polycrystalline silicon have high field effect mobility. However, it is difficult to meet the demand for a larger area liquid crystal display device.

[0006] Oxide semiconductors have been attracting attention as a transistor material that can replace silicon-based materials. This is because a transistor made of an oxide semiconductor has a higher efficiency than an amorphous silicon transistor. The field effect mobility is higher than that of a transistor constructed using a capacitor, and the transistor is suitable for use in liquid crystal displays. For example, the oxide semiconductor, niobium oxide, A transistor was fabricated using lead and In-Ga-Zn-O oxide, and the pixel shift of a display device was Techniques for applying this to switching elements and the like are disclosed in Patent Documents 1 and 2.

[0007] Patent Document 3 discloses a semiconductor device having a stack of oxide semiconductor films in which an amorphous component remains at the interface with a substrate. A transistor is disclosed.

[0008] However, in a transistor including an oxide semiconductor, the threshold voltage Specifically, in an oxide semiconductor, some of the hydrogen acts as a donor. When the carrier concentration of the oxide semiconductor increases, the gate A channel is formed in the oxide semiconductor without applying a voltage between the port and the source. , the threshold voltage of the transistor is shifted in the negative direction.

[0009] Even if the field effect mobility is high, the threshold voltage is high or the threshold voltage is negative. If the threshold voltage is high, it is difficult to control the circuit that contains the transistor. In the case of a transistor with a large absolute value of the threshold voltage, the transistor It may not be able to perform its switching function as a transistor and may become a load. If the threshold voltage is negative, the source and drain electrodes In other words, the transistor tends to be normally on, i.e., a current flows between these two transistors.

[0010] In the case of an n-channel transistor, the channel is opened only when a positive voltage is applied to the gate electrode. It is desirable to have a transistor in which a drain current flows out. There are transistors in which a channel does not form even under negative voltage conditions, and transistors in which a channel forms even under negative voltage conditions A transistor through which an in-current flows is unsuitable for use in a circuit.

[0011] Note that it is difficult to completely remove hydrogen from an oxide semiconductor. Transistors made of semiconductors are generally made of silicon-based materials. In comparison with a transistor, it is difficult to control the threshold voltage. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-135066 A Summary of the Invention [Problem to be solved by the invention]

[0013] In view of the above-described problems, one embodiment of the present invention provides a transistor including an oxide semiconductor. Another object of the present invention is to reduce fluctuations in the electrical characteristics of a semiconductor device and stabilize the characteristics. One of the objectives is to improve the reliability of the system. [Means for solving the problem]

[0014] One embodiment of the present invention is a transistor including an oxide semiconductor layer having different crystallinity depending on the region. Specifically, the ratio of the crystalline region in the channel forming region is A transistor is formed by using an oxide semiconductor layer having a higher proportion of crystalline regions than the other regions. Configure.

[0015] For example, one embodiment of the present invention is a semiconductor device including a gate layer, a gate insulating layer provided over the gate layer, and The oxide semiconductor layer is provided over the gate insulating layer, and the oxide semiconductor layer is provided separately from the gate insulating layer. a source electrode layer and a drain electrode layer which are formed on the oxide semiconductor layer; an etching stop layer provided in a region between the source electrode layer and the drain electrode layer; The oxide semiconductor layer has a crystal structure in a first region overlapping an interface with the etching stop layer. The ratio of the region overlapping the interface with the source electrode layer or the drain electrode layer is The percentage of crystalline area is higher than that of the transistor.

[0016] In the transistor having the above structure, the crystalline region in the first region (channel formation region) is higher than the proportion of crystalline regions in the second region (other regions). The defect density in the first region is lower than the defect density in the second region. The defects in the oxide semiconductor layer are trap sites for impurities in the oxide semiconductor layer. Therefore, in the transistor of one embodiment of the present invention, The diffusion of impurities such as hydrogen into the first region is likely to occur, whereas the diffusion in the opposite direction (the second region) is likely to occur. The diffusion of impurities such as hydrogen from the first region to the second region is unlikely to occur. In the transistor, the concentration of impurities such as hydrogen in the channel formation region is reduced. As a result, it is possible to stabilize the electrical characteristics and improve the reliability.

[0017] Another aspect of the present invention is a semiconductor device including an oxide semiconductor layer and a gate insulating film on the oxide semiconductor layer. a gate electrode layer on a gate insulating film; and an oxide semiconductor layer having a first region and a second region. and a third region, the first region overlapping the gate electrode layer, the first region being in contact with the second region. The first region is located between the third region, the first region having a higher proportion of crystalline components than amorphous components, and the second region is located between the third region. The first region and the third region have a higher ratio of amorphous components than crystalline components, and the second region and the third region have a higher ratio of amorphous components than crystalline components. The semiconductor device is characterized in that the second region has a higher hydrogen concentration than the first region.

[0018] In the above structure, in one oxide semiconductor layer pattern, a region having a large crystal component and a region having a non-crystal component are formed. The region with a high crystalline content becomes the channel formation region. The other regions are preferably made to have a large amount of amorphous components. In the present invention, an oxide semiconductor film is formed in which a region having a large crystalline component and a region having a large amorphous component are mixed. do.

[0019] In the above structure, the second region or the third region is a source electrode layer or a drain electrode layer. The first region is electrically connected to the electrode layer and has a higher electrical conductivity than the first region which is a channel forming region.

[0020] The oxide semiconductor film in a region to be a channel formation region contains a large amount of crystalline components. It is preferable that the c-axis be aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor film is formed. When the oxide semiconductor film contains a large amount of crystalline components, metal atoms in the region that becomes the channel formation region The bonding state between the oxygen atoms and the silicon dioxide is ordered, and the occurrence of oxygen vacancies can be suppressed.

[0021] In addition to oxygen vacancies, the oxide semiconductor film has a function of generating electrons, which serve as carriers, by hydrogen. Therefore, hydrogen in the oxide semiconductor film in the region that becomes the channel formation region is also low. It is preferable to reduce it.

[0022] A region having a large amount of amorphous components is formed in at least a part of an oxide semiconductor film having a crystalline component, Hydrogen is attracted to and captured by the amorphous region (also called intrinsic gettering). The hydrogen concentration in the region that will become the channel formation region is compared to the hydrogen concentration in the region with a large amount of amorphous components. Hydrogen diffuses into the region with a high amorphous content and is captured in the region with a high amorphous content. This stabilizes the system.

[0023] The minority carrier density is extremely small, and carrier generation sources such as oxygen vacancies and hydrogen are reduced. A transistor using an oxide semiconductor film including a channel formation region has an extremely small off-state current. It's easy to make.

[0024] In this specification, "hydrogen" refers to a hydrogen atom, and for example, when it is described as "containing hydrogen", In this case, hydrogen derived from hydrogen molecules, hydrocarbons, hydroxyl groups, water, etc. is also included.

[0025] In addition, when hydrogen is added to an oxide semiconductor film, the electrical conductivity is increased, and therefore the amorphous component The regions with a high amorphous content contain more hydrogen than the regions with a high crystalline content, so the The dielectric constant is higher than in regions with a higher crystalline content.

[0026] A region having a large crystalline component and a region having a large amorphous component are formed in one oxide semiconductor film. In order to achieve this, first, an oxide semiconductor film containing a large amount of crystalline components is formed, and then, a part of the oxide semiconductor film is A process is carried out to make the portion amorphous.

[0027] The oxide semiconductor film containing a large amount of crystalline components can be formed by adjusting the film formation conditions, for example, the temperature of the film formation substrate to 200° C. or higher. In addition, even if the temperature of the substrate to be deposited is less than 200°C, the acid If a heat treatment at 200°C or higher is performed after the deposition of the oxide semiconductor film, an oxide film containing a large amount of crystalline components is formed. Note that the oxide semiconductor film has a stoichiometric composition immediately after the film formation. Since it is preferable to make the sputtering gas in a supersaturated state with more oxygen than the composition, It is preferable to form the film under conditions where the ratio is high, and the film is formed in an oxygen atmosphere (100% oxygen gas). It is more preferable to do so.

[0028] In addition, the formation of an oxide semiconductor film with a high crystalline content is affected by impurities such as copper, aluminum, and chlorine. It is preferable to appropriately select a process that does not cause contamination or adhesion to the surface of the oxide semiconductor film. When such impurities are attached to the surface of the oxide semiconductor film, the film is exposed to oxalic acid, dilute hydrofluoric acid, etc. Alternatively, a plasma treatment (such as N2O plasma treatment) may be performed to form an oxide semiconductor film. It is preferable to remove surface impurities.

[0029] The present invention also provides a method for manufacturing a semiconductor device, the method including: forming an oxide semiconductor layer including a crystal component having a c-axis approximately perpendicular to the oxide semiconductor layer; A gate insulating film is formed on the gate electrode layer, and a gate electrode layer is formed on the gate insulating film. A part of the oxide semiconductor layer is made amorphous as a mask, and a source electrode layer is in contact with the amorphous region. Alternatively, a method for manufacturing a semiconductor device in which a drain electrode layer is formed.

[0030] As one of the processes for making a part of the oxide semiconductor film amorphous, an ion implantation apparatus or In this study, an ion plasma device was used to add elements, specifically rare gases such as argon, oxygen, and dopant. If an ion implantation device or an ion plasma device is used, Even if the oxide semiconductor film is covered with an insulating layer, argon may reach the oxide semiconductor film through the insulating layer. Further, oxygen or a dopant can be added to the oxide semiconductor film, so that part of the oxide semiconductor film can be made amorphous.

[0031] In addition, as one of the processes for making a part of the oxide semiconductor film amorphous, argon plasma is used. The oxide semiconductor layer may be exposed to a plasma or oxygen plasma. and forming an oxide semiconductor layer including a crystal component having a c-axis approximately perpendicular to the surface of the oxide semiconductor layer. A gate insulating film is formed, a gate electrode layer is formed on the gate insulating film, and a gate insulating film is formed on the oxide semiconductor layer. a region overlapping with the oxide semiconductor insulating film is partially exposed, and the exposed region of the oxide semiconductor layer is made amorphous; A method for fabricating a semiconductor device in which a source electrode layer or a drain electrode layer is formed in contact with an amorphous region This is the manufacturing method.

[0032] The case where part of the oxide semiconductor film is made amorphous by exposure to argon plasma or oxygen plasma In the case of the oxide semiconductor film, only the exposed surface and vicinity of the oxide semiconductor film become amorphous, and When the oxide semiconductor film is thin, the exposed region is amorphous. However, the region to be made amorphous is thin, and the thickness of the oxide semiconductor film is large. In the absence of such a crystal structure, only the surface layer will be amorphous, and the other regions will be regions with a high crystal content. The region exposed to the plasma is different from the region not exposed to the plasma (e.g., the channel formation region). The ratio of amorphous components is higher and the ratio of crystalline components is lower than the source region. The second region can function as a drain region.

[0033] In addition, when heat treatment is performed after the process for making part of the oxide semiconductor film amorphous, the recrystallization The recrystallized region has a lower crystallinity than the channel formation region. This feature is also one of the features of the present invention, and the structure of the present invention is an oxide semiconductor layer and an oxide semiconductor a gate insulating film over the oxide semiconductor layer and a gate electrode layer over the gate insulating film; The gate electrode layer includes a first region, a second region, and a third region, the first region overlapping the gate electrode layer, and the first The first region is located between the second region and the third region, and the first region is located between the second region and the third region. The semiconductor device is characterized by having higher crystallinity than the conventional semiconductor region.

[0034] In the above structure, the second region or the third region is a source electrode layer or a drain electrode layer. and a second region or a third region in contact with the source electrode layer or the drain electrode layer. The vicinity of the interface of the first region is amorphous, and the hydrogen concentration in the vicinity of the interface is One of its features is that it is higher than

[0035] In addition, one of the processes for making a part of the oxide semiconductor film amorphous is a process using a high power For example, a sputtering may be performed using a metal oxide film. When forming a conductive film for forming wiring, a part of the oxide semiconductor film is formed by sputtering. In this case, a part of the oxide semiconductor film is made amorphous depending on the film formation conditions of the conductive film. Therefore, a part of the oxide semiconductor film can be made amorphous without increasing the number of steps. It is possible.

[0036] In addition, a process for making a part of the oxide semiconductor film amorphous is performed, so that the crystal formation The oxygen vacancies in the amorphous region are greater than those in the amorphous region. An insulating layer containing excess oxygen is provided above or below the oxide semiconductor film, and oxygen is removed by heat treatment or the like. The amount of oxygen is reduced by diffusing the oxygen into the oxide semiconductor film.

[0037] The density of the region with a large crystal content in the oxide semiconductor film is 6.0 g / cm 3 twist High 6.375g / cm 3 If the film density is low, the amount of oxygen and hydrogen that diffuses is large. become.

[0038] In addition, 6.375 g / cm 3 The density value is In2O3:Ga2O3:ZnO=1:1: In-Ga, which has a composition of 2 [molar ratio] (In:Ga:Zn=1:1:1 [atomic ratio]), The theoretical density value of the a-Zn-O compound. The composition of the oxide semiconductor film was also determined by X-ray photoelectron spectroscopy. Optical method (XPS:X-ray Photoelectron Spectroscopy) It can be measured using:

[0039] The film density of the oxide semiconductor film was measured by Rutherford backscattering spectroscopy (RBS). rd Backscattering Spectrometry and X-ray reflectivity measurement It can be measured by X-Ray Reflection (XRR).

[0040] In addition, the material used for the oxide semiconductor film is indium oxide, tin oxide, zinc oxide, tin oxide, or tin oxide. In-Zn oxides, Sn-Zn oxides, and Al-Zn oxides, which are oxides of elemental metals , Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide , In-Ga-Zn oxide (also written as IGZO), which is an oxide of a ternary metal, I n-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al -Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In- La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-N d-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd -Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho- Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Z n-type oxides, In-Lu-Zn-type oxides, and oxides of quaternary metals, In-Sn-Ga- Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al- Zn-based oxides and the like can be used.

[0041] In this case, for example, In-Ga-Zn oxide refers to an oxide having In, Ga, and Zn. It means oxide, and the ratio of In, Ga, and Zn does not matter. Metal elements other than n may be included.

[0042] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn system with an atomic ratio of Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide with a molecular ratio of 0.1% or an oxide with a composition close to that. However, the present invention is not limited to the above.

[0043] In addition, as a structure of a transistor in which a region with a large amount of crystalline components is used as a channel formation region, For example, a top-gate transistor or a bottom-gate transistor may be used. In addition, a back gate electrode may be provided. By applying a voltage to the can be done.

[0044] One embodiment of the present invention includes a transistor or a circuit including a transistor. The present invention relates to a semiconductor device, for example, a transistor in which a channel formation region is formed using an oxide semiconductor film. The present invention relates to a semiconductor device having a circuit including a transistor. For example, LSIs, CPUs, power devices mounted on power circuits, memories, thyristors, etc. , converters, image sensors, and other semiconductor integrated circuits, and liquid crystal display panels. The present invention relates to electronic equipment that incorporates, as a component, a light-emitting display device having an electro-optical device or a light-emitting element. Effect of the Invention

[0045] Hydrogen is attracted from the channel formation region of the oxide semiconductor film to the region with a high amorphous content and immobilized. By removing as much hydrogen as possible from the channel formation region, a highly purified I-type (intrinsic semiconductor) was obtained. By making it an I-type, the threshold of the transistor can be The voltage value can be made positive, and a so-called normally-off switching element can be realized. do.

[0046] If a normally-off switching element can be realized, it can be used to develop low-power semiconductor devices. Locations can be provided. [Brief description of the drawings]

[0047] [Figure 1] 1A and 1B are a top view and a cross-sectional view, respectively, illustrating a structural example of a transistor. [Diagram 2] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process for a transistor. [Diagram 3] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process for a transistor. [Figure 4] 1A to 1C are diagrams showing an example of a display device. [Diagram 5] 1A and 1B are diagrams showing an example of a display device. [Figure 6] 1A and 1B are diagrams showing an example of a display device. [Figure 7] 1A and 1B are diagrams showing an example of an image sensor. [Figure 8] 1A and 1B are diagrams showing an example of a storage device. [Figure 9] Model diagram used to calculate the transfer of excess oxygen. [Figure 10] Calculation results for the model diagram in Figure 9. [Figure 11] A model used to calculate the movement of oxygen vacancies. [Figure 12] Calculation results for the model diagram in Figure 11. [Figure 13] 1A and 1B are cross-sectional views and a top view illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 16]FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 17] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 18] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 19] FIG. 1 is a perspective view illustrating one embodiment of a semiconductor device. [Figure 20] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 21] 1A and 1B are a block diagram illustrating one embodiment of a semiconductor device and a partial circuit diagram thereof. [Figure 22] 1A to 1C are diagrams illustrating electronic devices. [Diagram 23] 1A to 1C are diagrams illustrating electronic devices. [Figure 24] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] The present invention is not limited to the following description, and various modifications in form and details are possible. It will be easily understood by those skilled in the art. Furthermore, the present invention is not limited to the description of the embodiments shown below. The above definitions are not to be construed as construed in any manner that would violate the principles of international law.

[0049] (Embodiment 1) One aspect of the present invention will be described in detail below.

[0050] <1. Transistor> FIG. 1 to FIG. 3 show examples of a structure and a manufacturing process of a transistor according to one embodiment of the present invention. and explain.

[0051] <1-1. Example of transistor structure> FIG. 1 illustrates a structural example of a transistor according to one embodiment of the present invention. FIG. 1(A) is a top view of the transistor, and FIG. 1(B) is a cross-sectional view of the AB transistor shown in FIG. 2 is a cross-sectional view of the transistor taken along a line.

[0052] The transistor shown in FIGS. 1A and 1B includes a gate layer 1 provided on a substrate 100. A gate insulating layer 2 is provided on the gate layer 1, and a gate insulating layer 3 is provided on the gate insulating layer 2. The oxide semiconductor layer 3 is provided on the oxide semiconductor layer 3 in a separated state. and a region on the oxide semiconductor layer 3, which is a region between the source electrode layer 4 and the drain electrode layer 5. and an etching stop layer 6 provided in the region between the electrode layers 5. The transistor shown in FIGS. 1(A) and 1(B) is provided with an etching stop layer 6. The transistor is an inverted staggered type (etching stop type, channel stop type).

[0053] In the transistors shown in FIGS. 1(A) and 1(B), the etching stop layer 6 is an oxide. The region on the semiconductor layer 3 is not only the region between the source electrode layer 4 and the drain electrode layer 5 but also The insulating layer 14 is also provided between the end of the oxide semiconductor layer 3 and the source electrode layer 4 and the drain electrode layer 5 . In other words, the source electrode layer 4 and the drain electrode layer 5 are provided on the etching stop layer 6. The insulating film 1 is in contact with the oxide semiconductor layer 3 through the opening.

[0054] Furthermore, in the oxide semiconductor layer 3 of the transistor illustrated in FIGS. A region 7 overlapping the interface with the gate stop layer 6 and the source electrode layer 4 or the drain electrode layer 5 The crystallinity is different between the interface with the region 7 and the region 8 that overlaps it. The proportion of crystalline regions in region 7 is higher than the proportion of crystalline regions in region 8. The region includes all or most of the region in which a channel is formed in response to the voltage between the first electrode layer 4 and the second electrode layer 5. do.

[0055] That is, in the transistors shown in FIGS. 1(A) and 1(B), the entire or a large part of the channel The defect density in the region 7 where the portion is to be formed is lower than the defect density in the region 8. The defects in the oxide semiconductor layer 3 are due to impurities such as hydrogen contained in the oxide semiconductor layer 3. Therefore, in the transistors shown in Fig. 1(A) and (B), In the case of the Cr-Si ... Therefore, the diffusion of the impurity into the region 8 is difficult to occur. As a result, the transistors shown in FIGS. In the transistor, the concentration of impurities such as hydrogen in the region 7 is reduced, and the electrical characteristics are improved. It is possible to improve stability and reliability.

[0056] In addition, in the transistors shown in Figures 1(A) and 1(B), the switching characteristics are improved. This is possible. The details are explained below.

[0057] A transistor in which a channel is formed in an oxide semiconductor has a low-temperature property depending on processing conditions or heat treatment conditions. The electrical characteristics of the oxide semiconductor may change due to the presence of impurities during the formation process of the oxide semiconductor. The oxide semiconductor is contaminated with substances (such as chlorine, fluorine, boron, or hydrogen) or oxygen is released from the oxide semiconductor. Such contamination or desorption occurs at the edge of the oxide semiconductor. That is, in a transistor in which a channel is formed in an oxide semiconductor, In the case of the low-resistance oxide semiconductor, an end portion of the oxide semiconductor becomes a low-resistance region, and a transistor is formed in the low-resistance region. In this transistor, a parasitic channel is easily formed. The oxide semiconductor in the region where the gate and source voltage is applied The channel formed on the shortest path (also called the former channel) and the parasitic channel (the latter In other words, two types of channels can be formed:

[0058] In transistors in which two types of channels can be formed, in most cases, The threshold voltage between the gate and source where the channel is formed is different. The threshold voltage at which the hole is formed is higher than the threshold voltage at which the channel is formed. The current driving capability of the former channel is higher than that of the latter channel. Therefore, the voltage between the gate and source of the transistor in the off state is increased. In this case, the current between the source and drain changes in two stages. The first step change (between the source and drain) occurs near the threshold voltage at which the channel is formed. The current increase was confirmed, and the former channel was formed near the threshold voltage. A second-stage change (an increase in the current between the source and drain) is observed.

[0059] In the transistor shown in FIGS. 1(A) and 1(B), the etching stop layer 6 are provided between the end of the oxide semiconductor layer 3 and the source electrode layer 4 and the drain electrode layer 5 . Therefore, even if the end regions of the oxide semiconductor layer 3 become low resistance regions, as shown in FIG. In the transistors shown in 1(A) and 1(B), no parasitic channel is formed. That is, in the transistors shown in FIGS. 1(A) and 1(B), the switching characteristics are improved. It is possible to achieve this.

[0060] The structure that can improve the switching characteristics is shown in Figures 1(A) and (B). The reason why a parasitic channel is formed at the edge of an oxide semiconductor is that This is because there is a source and a drain of a transistor electrically connected to the end. Therefore, at least one of the source electrode layer 4 and the drain electrode layer 5 is located at the end of the oxide semiconductor layer 3. If the transistor is not electrically connected to the For example, at least one of the source electrode layer 4 and the drain electrode layer 5 may be an oxide semiconductor. If the transistor has a structure that does not contact the side surface of the conductor layer 3, the switching characteristics can be improved. It is possible.

[0061] <1-1-1. Specific examples of the substrate 100> The substrate 100 is made of a material having a heat resistance sufficient to withstand the heat treatment in the manufacturing process of the transistor. Any substrate may be used as long as it has the desired properties. For example, a glass substrate, a ceramic substrate, The substrate may be a crystalline silicon substrate, a quartz substrate, a sapphire substrate, or the like. A flexible substrate may be used as the substrate 100. Note that impurities contained in the substrate 100 may be later formed. In order to prevent the inclusion of foreign matter in the oxide semiconductor layer to be formed, an insulating layer is formed on the substrate 100. is also possible.

[0062] <1-1-2. Specific examples of gate layer 1> Gate layer 1 may be aluminum, copper, titanium, tantalum, tungsten, or molybdenum. , chromium, neodymium, scandium or alloys containing these elements Alternatively, a laminate of these films may be applied.

[0063] The gate layer 1 is made of a metal oxide containing nitrogen, specifically, an In-Ga -Zn-O film, In-Sn-O film containing nitrogen, In-Ga-O film containing nitrogen, In-Zn-O film, nitrogen-containing Sn-O film, nitrogen-containing In-O film, or metal nitride film (I nN, SnN, etc.) can also be applied. These films have an energy of 5 eV (electron volts) or more, Preferably, it has a work function of 5.5 eV (electron volts) or more, and when used as a gate, The threshold voltage of the transistor can be made positive, making it a so-called normally-off switch. It is possible to realize a switching element.

[0064] <1-1-3. Specific examples of gate insulating layer 2> The gate insulating layer 2 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a nitride film. Silicon oxide film, aluminum oxide film, aluminum oxynitride film, gallium oxide film, etc. Also, a laminate of these materials can be applied. Silicon oxynitride and aluminum oxynitride are compounds that contain more oxygen than nitrogen. Silicon nitride oxide is a material that contains more nitrogen than oxygen. This refers to substances with a high content.

[0065] In particular, it is preferable to use a layer containing an aluminum oxide film as the gate insulating layer 2. Aluminum oxide membranes are impermeable to both impurities such as hydrogen and oxygen. Therefore, the aluminum oxide film is used as the gate insulating layer 2. By applying the layer containing the oxide semiconductor layer, it is possible to prevent oxygen from being released from the oxide semiconductor layer 3 and to prevent the oxide semiconductor layer from being oxidized. This can prevent impurities such as hydrogen from being mixed into the compound semiconductor layer 3.

[0066] The gate insulating layer 2 may be a hafnium oxide film, an yttrium oxide film, or a hafnium silicon film. HfSi x O y (x>0, y>0) film, nitrogen-doped hafnium silicate film, hafnium aluminate (HfAl x O y (x>0, y>0) film, or oxide film It is also possible to apply a film containing titanium (a film made of a so-called high-k material). The use of such a film makes it possible to reduce gate leakage current.

[0067] <1-1-4. Specific examples of oxide semiconductor layer 3> <(1) Materials> As the oxide semiconductor layer 3, a film containing at least indium can be used. It is preferable to use a film containing indium and zinc for the electric characteristics of the transistor. In addition, the films have gallium as a stabilizer to reduce the variation in thermal stability. It is preferred to apply

[0068] The oxide semiconductor layer 3 is made of tin, hafnium, aluminum, or zirconium. or the lanthanides, lanthanum, cerium, praseodymium, neodymium, , europium, gadolinium, terbium, dysprosium, holmium, erbium One or more of sulphur, thulium, ytterbium, or lutetium are added. It is also possible to apply a membrane containing it as a ballast.

[0069] For example, the oxide semiconductor layer 3 may be an indium oxide film or an In -Zn-based oxide film, In-Mg-based oxide film, In-Ga-based oxide film, oxide of ternary metals In-Ga-Zn oxide film, In-Al-Zn oxide film, In-Sn-Zn oxide film Oxide film, In-Hf-Zn oxide film, In-La-Zn oxide film, In-Ce-Z n-based oxide film, In-Pr-Zn-based oxide film, In-Nd-Zn-based oxide film, In-Sm -Zn-based oxide film, In-Eu-Zn-based oxide film, In-Gd-Zn-based oxide film, In- Tb-Zn oxide film, In-Dy-Zn oxide film, In-Ho-Zn oxide film, I n-Er-Zn oxide film, In-Tm-Zn oxide film, In-Yb-Zn oxide film , In-Lu-Zn ​​oxide film, In-Sn-Ga-Zn oxide film, which is an oxide of a quaternary metal oxide film, In-Hf-Ga-Zn oxide film, In-Al-Ga-Zn oxide film, In -Sn-Al-Zn oxide film, In-Sn-Hf-Zn oxide film, In-Hf-Al -Zn-based oxide film can be applied.

[0070] Here, for example, In-Ga-Zn oxide is a material having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than Zn may be included.

[0071] Note that part of the oxygen constituting the oxide semiconductor layer 3 may be replaced with nitrogen.

[0072] <(2) Crystal structure> As described above, the oxide semiconductor layer 3 is a film in which the proportion of crystalline regions varies depending on the region. For example, For example, the oxide semiconductor film includes amorphous regions and crystalline regions. The crystal structure of the oxide semiconductor is not limited to a specific structure.

[0073] The oxide semiconductor film has, for example, CAAC (C Axis Aligned Crystalline) in the crystalline region. The microcrystalline type has a higher defect level density than CAAC. Note that an oxide semiconductor having CAAC is called CAAC-OS (C Axis Alignment d Crystalline Oxide Semiconductor).

[0074] The crystalline region of the oxide semiconductor film may have, for example, a CAAC-OS. For example, the c-axis is oriented, and the a-axis and / or b-axis are not macroscopically aligned.

[0075] The oxide semiconductor film may have, for example, microcrystals in a crystalline region. The oxide semiconductor film having a microcrystalline oxide semiconductor is In the crystalline region, for example, microcrystals (also called nanocrystals) with a size of 1 nm or more and less than 10 nm are present. Alternatively, the oxide semiconductor film having a microcrystalline oxide semiconductor has a crystalline region, for example, For example, an oxide semiconductor having a crystalline-amorphous mixed phase structure with a crystalline portion of 1 nm or more and less than 10 nm is is doing.

[0076] The oxide semiconductor film has at least an amorphous portion in the amorphous region. The oxide semiconductor having an amorphous portion may be called an amorphous oxide semiconductor. The amorphous part has a higher defect level density than the microcrystalline and CAAC. Amorphous oxide semiconductor In the oxide semiconductor film having the above structure, the amorphous region has, for example, a disordered atomic arrangement and contains no crystalline components. Alternatively, in the oxide semiconductor film including an amorphous oxide semiconductor, the amorphous region is, for example, It is completely amorphous and has no crystalline parts.

[0077] Note that the oxide semiconductor film may be a CAAC-OS film, a microcrystalline oxide semiconductor film, or an amorphous oxide semiconductor film. The mixed film may be a film having, for example, an amorphous oxide semiconductor region and a microcrystalline oxide semiconductor region. It has a semiconductor region and a CAAC-OS region.

[0078] Note that the oxide semiconductor film may have, for example, a single crystal in a crystalline region.

[0079] The oxide semiconductor film has a plurality of crystal parts, and the c-axes of the crystal parts are aligned along a normal vector of a surface on which the crystal parts are formed. It is preferable that the crystal orientation of the crystals is parallel to the normal vector of the surface. The directions of the a-axis and the b-axis may be different between the oxide semiconductor films. One example is the CAAC-OS film. The CAAC-OS film is described in detail below.

[0080] The CAAC-OS film is not completely amorphous. For example, the CAAC-OS film has crystalline and The oxide semiconductor has a crystalline-amorphous mixed phase structure having an amorphous portion and an amorphous portion. The size of the part is often such that it fits within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by pe), the boundary between the amorphous part and the crystalline part in the CAAC-OS film, the crystalline part, The boundary between the crystal and crystalline regions is not clear. The grain boundaries cannot be confirmed. In this case, the decrease in electron mobility caused by grain boundaries is suppressed.

[0081] The crystal parts included in the CAAC-OS film have, for example, a c-axis that is perpendicular to the normal to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the line vector or the surface normal vector and perpendicular to the ab plane When viewed from the normal direction, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from the direction perpendicular to the c-axis, Metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. The directions of the a-axis and the b-axis may be different between the two. When describing it as straight, it is also in the range of 80° to 100°, preferably 85° to 95°. In addition, when simply describing it as parallel, it is -10° or more and 10° or less, and preferably This also includes the range of -5° to 5°.

[0082] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface.

[0083] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film is Depending on the shape (cross-sectional shape of the surface to be formed or cross-sectional shape of the surface), In addition, the crystallization process such as heat treatment is performed when or after the film is formed. Therefore, the c-axis of the crystal part is The direction is aligned so as to be parallel to the normal vector of the surface on which the light is formed or the normal vector of the surface.

[0084] Transistors using CAAC-OS films show changes in electrical characteristics when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0085] In addition, oxygen desorption from the CAAC-OS film tends to occur from the side surface (end surface) of the film. (For more information on this point, see the following Supplement: Regarding oxygen elimination from the oxide semiconductor layer.) (This will be described in detail later.) Therefore, when a CAAC-OS film is used as the oxide semiconductor layer 3, As shown in FIGS. 1(A) and 1(B), the etching stop layer 6 is formed at the edge of the oxide semiconductor layer 3. A transistor having a configuration in which the insulating layer is provided between the source electrode layer 4 and the drain electrode layer 5 is preferably used. This is because it is possible to prevent the formation of a parasitic channel in the transistor. be.

[0086] <(3) Layer structure> The oxide semiconductor layer 3 may be a single-layer oxide semiconductor film or a multi-layer oxide semiconductor film. For example, a stack of conductive films may be used. A layer including at least two of a conductive film and a CAAC-OS film is used as the oxide semiconductor layer 3. It is possible.

[0087] In addition, a layer consisting of a stack of oxide semiconductor films having different compositions may be used as the oxide semiconductor layer 3. Specifically, the first oxide semiconductor film (hereinafter, the lower oxide semiconductor film) in contact with the gate insulating layer 2 may be The source electrode layer 4, the drain electrode layer 5, and the etching stop layer 6 are connected to the A second oxide semiconductor film (hereinafter also referred to as an upper layer) having a composition different from that of the first oxide semiconductor film is formed. A layer containing the above-mentioned compound may also be used as the oxide semiconductor layer 3.

[0088] For example, when the lower and upper layers are both composed of indium, gallium, and zinc, In order to achieve this, the indium concentration in the lower layer is made higher than the indium concentration in the upper layer. and / or The indium concentration in the lower layer is made higher than the gallium concentration in the lower layer, and It is preferred that the gallium concentration in the upper layer be greater than the indium concentration in the upper layer.

[0089] This improves the mobility of the transistor having the oxide semiconductor layer 3 and reduces the parasitic channel Specifically, by increasing the indium concentration in the lower layer, This can improve the mobility of the transistor. In conductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the increase in the In content This is due to the fact that the gallium concentration in the upper layer increases as the s-orbitals overlap. By increasing the temperature, oxygen desorption is suppressed, and the formation of parasitic channels in the upper layer is suppressed. This is because the formation energy of oxygen vacancies in Ga is larger than that in In. This is because oxygen deficiency is unlikely to occur.

[0090] <1-1-4. Specific examples of source electrode layer 4 and drain electrode layer 5> The source electrode layer 4 and the drain electrode layer 5 are made of aluminum, copper, titanium, tantalum, Elements selected from tungsten, molybdenum, chromium, neodymium, and scandium, The film can be made of an alloy containing these elements or a nitride containing these elements. Also, a laminate of these films can be applied.

[0091] In addition, a light-transmitting conductive film is used as the source electrode layer 4 and the drain electrode layer 5. For example, indium oxide tin oxide (In2O3-SnO2) film, in oxide The film is made of In2O3-ZnO or a film containing silicon oxide. It can be used.

[0092] <1-1-5. Specific examples of the etching stop layer 6> The etching stop layer 6 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. film, silicon nitride oxide film, aluminum oxide film, aluminum oxynitride film, or gallium oxide film A laminate of these materials can also be used. .

[0093] In particular, a layer containing an aluminum oxide film can be used as the etching stop layer 6. It is preferable to use a layer containing an aluminum oxide film as the etching stop layer 6. In addition, the desorption of oxygen from the oxide semiconductor layer 3 is prevented, and hydrogen and the like are prevented from entering the oxide semiconductor layer 3. This is because it is possible to prevent the inclusion of impurities.

[0094] <1-2. Example of transistor manufacturing process> 2 and 3 are diagrams illustrating an example of a manufacturing process of the transistor shown in FIG. 3A to 3C are cross-sectional views showing a manufacturing process of the transistor. do.

[0095] <(1) Formation of gate layer 1 (Figure 2(A))> First, a conductive film is formed on the substrate 100. Then, a photolithography is performed on the conductive film. A mask is formed by using a method. Then, the conductive film in the portion not covered by the mask is etched. As a result, the gate layer 1 is formed.

[0096] The conductive film can be formed by a sputtering method or the like. A heat treatment may be performed before or after the film is formed or after the gate layer 1 is formed. GRTA (Gas Rapid Thermal Annealing) is a method of heat treatment using hot gas. Heat treatment may be performed at 650°C for 1 to 5 minutes using a GRTA The high-temperature gas used in the process is a rare gas such as argon or an inert gas such as nitrogen. Alternatively, heat treatment may be performed in an electric furnace at 500° C. for 30 minutes to 1 hour.

[0097] <(2) Formation of gate insulating layer 2 (FIG. 2(B))> Next, the gate insulating layer 2 is deposited on the substrate 100 and the gate layer 1 .

[0098] The gate insulating layer 2 can be formed by using a plasma CVD method, a sputtering method, or the like. After the gate insulating layer 2 is formed, a heat treatment is performed to reduce the content of water or hydrogen. For example, a heating process may be performed at 300°C to 700°C under reduced pressure or in an inert atmosphere. The heat treatment may be performed for one hour or less. As a result, the oxide semiconductor layer 3 to be formed later is This can suppress the incorporation of hydrogen into the fuel cell.

[0099] When the gate insulating layer 2 includes an aluminum oxide film, a sputtering method or the like is used. The aluminum film is directly formed on the aluminum substrate, or the aluminum film is formed and then oxidized to form the oxide film. In addition, the oxidation treatment may be performed by using oxygen plasma. treatment or oxygen doping treatment.

[0100] In addition, the aluminum oxide film has a high blocking function. When the gate insulating layer 2 containing It is preferable to perform the treatment before the formation of the aluminum oxide film. After the formation of an insulating film other than the aluminum oxide film constituting the layer 2, the aluminum oxide Before forming the aluminum film or after forming the aluminum film, the aluminum film is subjected to an oxidation treatment. It is preferable to carry out the heat treatment before the gate insulating film is formed. The water or hydrogen content in the layer 2 can be effectively reduced.

[0101] <(3) Formation of oxide semiconductor layer 3 (FIG. 2(C))> Next, an oxide semiconductor film is formed on the gate insulating layer 2. Next, the oxide semiconductor film A mask is formed on the substrate by photolithography. The oxide semiconductor film in the unetched portion is removed by etching. A layer 3 is formed.

[0102] The oxide semiconductor film can be formed by a sputtering method or the like. The oxide semiconductor film is grown under conditions in which a large amount of oxygen is contained in the oxide semiconductor film (for example, under an atmosphere of 100% oxygen). It is preferable to form the film by sputtering at 1000 K. The amount of oxygen contained in the oxide semiconductor film is increased (preferably when the oxide semiconductor is in a crystalline state). In addition, the oxygen content may be in excess of the stoichiometric composition. In order to enhance the crystallinity of the semiconductor film, the film may be formed while the substrate 100 is heated. .

[0103] In addition, after the formation of the oxide semiconductor film or the oxide semiconductor layer 3, a water- or hydrogen-containing For example, a heat treatment may be performed under reduced pressure or in an inert atmosphere to reduce the amount of fluorine. In this case, the heat treatment should be performed at 300°C to 700°C for 1 hour or less. When the layer 2 is an insulating layer containing oxygen, the oxygen contained in the gate insulating layer 2 is removed by this heat treatment. can be supplied to the oxide semiconductor film or the oxide semiconductor layer 3. Therefore, even if oxygen vacancies occur in the oxide semiconductor film or the oxide semiconductor layer 3, The oxygen deficiency can be compensated for by oxygen supply from the gate insulating layer 2.

[0104] <(4) Formation of Etching Stop Layer 6 (FIG. 3(A))> Next, an insulating film is formed on the gate insulating layer 2 and the oxide semiconductor layer 3. A mask is formed on the insulating film by photolithography. The uncovered portions of the insulating film are removed by etching. A top layer 6 is formed.

[0105] The insulating film can be formed by using a plasma CVD method, a sputtering method, or the like. After the formation of the etching stop layer 6, the water or hydrogen content is reduced. Heat treatment may be performed. For example, the heat treatment may be performed at 300° C. or higher and 70° C. or higher under reduced pressure or in an inert atmosphere. The heat treatment may be performed at 0° C. or less for 1 hour or less. Contamination can be suppressed.

[0106] In addition, when the etching stop layer 6 includes an aluminum oxide film, it is possible to form the aluminum oxide film by a method such as sputtering. The aluminum film is directly formed using a SiO2 film or is oxidized after the aluminum film is formed. The aluminum oxide film can be formed by the oxidation treatment. Examples of the treatment include a plasma treatment and an oxygen doping treatment.

[0107] In addition, the aluminum oxide film has a high blocking function. In the case where an etching stop layer 6 containing It is preferable to carry out the heat treatment before forming the aluminum oxide film. After the formation of an insulating film other than the aluminum oxide film constituting the etching stop layer 6, Before forming an aluminum oxide film, or after forming an aluminum film, It is preferable to carry out the heat treatment before carrying out the oxidation treatment on the film. Therefore, the water or hydrogen content in the etching stop layer 6 can be effectively reduced. can.

[0108] <(5) Crystallinity Control of Oxide Semiconductor Layer 3 (FIG. 3(B))> Next, a plasma treatment is performed. In the plasma treatment, the gas species is Al. Inert gas such as argon or nitrogen, or oxygen gas, etc., is used. Specifically, the crystals contained in the specific region of the etching stop layer 6 become amorphous. The crystals in the unetched region 8 become amorphous. As a result, the etching stop layer 6 The proportion of crystalline regions in region 7 covered by the crystalline layer is greater than the proportion of crystalline regions in region 8. It will become more expensive.

[0109] <(6) Formation of source electrode layer 4 and drain electrode layer 5 (FIG. 3(C))> Next, a conductive film is formed on the oxide semiconductor layer 3 and the etching stop layer 6. A mask is formed on the conductive film by photolithography. The conductive film in the portion not covered by the source electrode layer is removed by etching. 4 and drain electrode layer 5 are formed.

[0110] The conductive film can be formed by a sputtering method or the like. When the conductive film is formed by the ring method, the oxide semiconductor layer 3 can be formed by setting the conditions. It is possible to make the crystals contained in the region 8 amorphous. For example, By increasing the thickness of the upper layer, it is possible to promote the amorphization of the region 8. It is also possible to omit the step (5) of controlling the crystallinity of the oxide semiconductor layer 3.

[0111] <2. Semiconductor Devices> A specific example of a semiconductor device including the above-described transistor will be described below with reference to FIG. The following description will be given with reference to FIG.

[0112] <2-1.Display device> FIG. 4 is a diagram showing an example of a display device configured using the above-mentioned transistor. Specifically, the display device shown in FIG. 4 has all or part of the driver circuit and a pixel section provided on the same substrate. This is a display device that is used in a variety of applications (a so-called system-on-panel display device). The above-mentioned transistor is provided in the driver circuit and the pixel portion. It is possible to apply.

[0113] In FIG. 4A, a pixel portion 4002 is provided on a substrate 4001. A sealant 4005 is provided, and the device is sealed with a substrate 4006. In this case, the sealing material 4005 is disposed on the substrate 4001 in a region other than the region surrounded by the sealing material 4005. A single crystal semiconductor film or a polycrystalline semiconductor film is formed on an IC chip or a separately prepared substrate. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are also mounted. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 4002 are connected to the signal line driver circuit 4003 and the scanning line driver circuit 4004 or the pixel portion 4002. Various signals and potentials are transmitted via FPC (Flexible printed circuit). Powered by 4018a and 4018b.

[0114] In FIG. 4B and FIG. 4C, a pixel portion 4002 is provided on a substrate 4001. A sealant 4005 is provided so as to surround the scanning line driver circuit 4004. A substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. The pixel portion 4002 and the scanning line driver circuit 4004 are formed by a substrate 4001 and a sealant 4005. The display element is sealed with a substrate 4006. In the embodiment, a region other than the region surrounded by the sealant 4005 on the substrate 4001 is A single crystal semiconductor film or a polycrystalline semiconductor film is formed on an IC chip or a separately prepared substrate. A signal line driver circuit 4003 is mounted on the substrate 4001. In FIG. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 400 Various signals and potentials are supplied to 2 from an FPC4018.

[0115] In addition, in FIG. 4B and FIG. 4C, a signal line driver circuit 4003 is separately formed. Although an example in which the scanning line driving circuit is mounted on a substrate 4001 is shown, the present invention is not limited to this configuration. Alternatively, a circuit may be formed separately and mounted, or a part of a signal line driver circuit or a part of a scanning line driver circuit may be mounted. Alternatively, the circuit board may be formed separately and mounted.

[0116] The method of connecting the separately formed drive circuit is not particularly limited, and may be any method such as COG ( hip on glass method, wire bonding method, or TAB (Tape The Automated Bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are mounted by the COG method. FIG. 4B shows an example of mounting a signal line driver circuit 4003 by the COG method. C) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0117] The display device includes a panel in which a display element is sealed, and a controller for the panel. This includes modules in which ICs, etc., including lasers, are mounted.

[0118] In this specification, the term "display device" refers to an image display device, a display device, or It also refers to a light source (including lighting equipment). It also refers to a connector, such as FPC or TCP, that is attached. A module with a printed wiring board at the end of the TCP, or a display element All modules with ICs (integrated circuits) directly mounted on the chip using the COG method are included in the display device. This shall be done.

[0119] In addition, the pixel portion and the scanning line driver circuit provided on the substrate each have a plurality of transistors. Therefore, the transistor described in Embodiment 1 can be used.

[0120] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, and the like. A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element emits light when a current or voltage is applied. This category includes elements whose intensity can be controlled, specifically inorganic EL (Electro L uminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium in which the contrast changes depending on the light can also be applied.

[0121] Another embodiment of a display device will be described with reference to FIGS. 4 and 6. FIG. 6A shows a display device according to the present invention. This corresponds to the cross-sectional view at MN in FIG. 4(B).

[0122] As shown in FIG. 4 and FIG. 6, the display device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are terminals of the FPC 4018. and electrically connected to the anisotropic conductive layer 4019 .

[0123] The connection terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. 4016 is the same as the source electrode layer and drain electrode layer of the transistors 4010 and 4011. It is formed of a conductive layer.

[0124] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 provided on a substrate 4001 are In FIG. 4 and FIG. 6, the transistor included in the pixel portion 4002 4010 and a transistor 4011 included in the scanning line driver circuit 4004. In FIG. 6A, an insulating layer 4020 is provided over the transistors 4010 and 4011. In FIG. 6B, an insulating layer 4021 is further provided.

[0125] The transistors 4010 and 4011 may be any of the transistors described above. In addition, in FIG. 6(A) and (B), the oxide semiconductor layer is a source electrode layer and a drain electrode layer. The transistor shown in FIG. 1 has a structure in which the gate electrode layer extends outward beyond the end of the gate electrode layer. In a transistor having such a structure, the etching stop layer is disposed at an end of the oxide semiconductor layer. The parasitic channel in the transistor is not necessarily provided between the source electrode layer and the drain electrode layer. It is possible to suppress the formation of holes.

[0126] In addition, a conductive layer is further provided at a position overlapping with the oxide semiconductor layer of the transistor 4011 for the driver circuit. Note that the conductive layer may have the same potential as the gate electrode layer of the transistor 4011. The second gate electrode layer may be the same or different and may function as the second gate electrode layer. The potential of the conductive layer may be GND, 0V, or may be in a floating state. The layer shields the external electric field, i.e. prevents the external electric field from reaching the inside (the circuitry including the transistors). It has a function to prevent the action of the conductive layer (especially the electrostatic shielding function against static electricity). This function prevents the electrical characteristics of transistors from fluctuating due to the influence of external electric fields such as static electricity. This can prevent the above from happening.

[0127] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display a picture, and various display elements can be used. Children can be used.

[0128] <2-1-1. Liquid crystal display device> FIG. 6(A) shows an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 serving as a display element includes a first electrode layer 4030 and a second electrode layer 40 31, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between the alignment films 31 and 32. The second electrode layer 4031 is provided with functional insulating layers 4032, 4033. 406 side, and the first electrode layer 4030 and the second electrode layer 4031 are disposed between the liquid crystal layer 4008 and the The structure is such that the electrodes are stacked with an intermediate layer interposed therebetween.

[0129] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. It is a pixel which is provided to control the thickness (cell gap) of the liquid crystal layer 4008 . A spherical spacer may also be used.

[0130] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials (liquid crystal compositions) can be in a cholesteric phase, a smectic phase, or a cubic phase depending on the conditions. It shows phases such as chiral nematic, isotropic, etc.

[0131] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4030, and the second electrode layer 4031 The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric liquid crystal is increased, The blue phase is the phase that appears just before the transition from the cholesteric phase to the isotropic phase. It can be expressed by using a liquid crystal composition in which a blue crystal and a chiral agent are mixed. In order to expand the temperature range in which the blue phase appears, a polymerizable monomer is added to the liquid crystal composition that exhibits the blue phase. Alternatively, a liquid crystal layer can be formed by adding a polymerization initiator and carrying out a polymer stabilization treatment. The liquid crystal composition exhibiting the blue phase has a short response time and is optically isotropic, so that it can be easily aligned. Since no alignment film is required, rubbing treatment is not required and viewing angle dependency is small. This eliminates the need for rubbing treatment, and therefore prevents electrostatic damage caused by rubbing treatment. Therefore, defects and damages of the liquid crystal display device during the manufacturing process can be reduced. The productivity of the device can be improved. There is a risk that the electrical characteristics of a transistor may change significantly due to electrical influences, resulting in deviation from the design range. Therefore, a blue phase can be obtained in a liquid crystal display device having a transistor using an oxide semiconductor layer. It is more effective to use a liquid crystal composition which exhibits a high polarization.

[0132] The specific resistance of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 1 1 Ω cm or more, and more preferably 1×10 12 Ω·cm or more. The specific resistance values ​​specified in the specification are those measured at 20°C.

[0133] The size of the storage capacitor provided in the liquid crystal display device is determined by the capacitance of the transistor arranged in the pixel portion. The capacitance is set so that the charge can be held for a predetermined period of time, taking into account the current flow and other factors. The size may be set in consideration of the off-state current of the transistor. By using a transistor having a nitride semiconductor layer, the liquid crystal capacitance in each pixel is It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the be.

[0134] A transistor including an oxide semiconductor layer disclosed in this specification has a current value in an off state of Therefore, the retention time of electric signals such as image signals can be reduced. The write interval can be set longer when the power is on. Since the frequency of the refresh operation can be reduced, this has the effect of reducing power consumption.

[0135] In addition, the transistor including the oxide semiconductor layer disclosed in this specification has a relatively high field effect. Since the high mobility can be obtained, high-speed operation is possible. By using the transistor in a liquid crystal display device, The driver transistors used in the driving circuit section can be formed on the same substrate. In other words, it is necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driving circuit. Since there is no need for a semiconductor device, the number of components can be reduced. By using a transistor capable of high speed operation, a high-quality image can be provided.

[0136] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, ASM(Axially Symmetric aligned) Micro-cell) mode, OCB(Optical Compensated) Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal mode etc. can be used.

[0137] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV (Advanced Super View) mode, etc. It can also be applied to VA type liquid crystal display devices. What is a VA type liquid crystal display device? VA type LCD is a type of LCD that controls the alignment of liquid crystal molecules in a LCD panel. In this type, the liquid crystal molecules are oriented vertically relative to the panel surface when no voltage is applied. In addition, a pixel is divided into several regions (subpixels), each of which is processed in a different way. This is called multi-domain or multi-domain design, which is designed to knock down molecules in the opposite direction. Any method that can be used.

[0138] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. For example, a polarizing substrate and a retardation Circular polarization by the substrate may be used. Also, backlight, sidelight, etc. may be used as the light source. It may be used.

[0139] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (RGB=RGB). The color is not limited to the three colors RGBW (W stands for white). ), or RGB plus one or more colors such as yellow, cyan, or magenta. The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may be applied to monochrome display devices. It is also possible.

[0140] <2-1-2.EL display device> As a display element included in the display device, a light-emitting element that utilizes electroluminescence is used. A light-emitting element that utilizes electroluminescence can be applied to a light-emitting device that uses an active light-emitting material. They are generally classified according to whether they are organic compounds or inorganic compounds. the latter is called an inorganic EL element.

[0141] In an organic EL element, electrons and positive electrodes are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0142] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements are classified into two types: The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized light emission that utilizes organic EL elements. do.

[0143] In order to extract light emitted from the light emitting element, at least one of a pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. Top emission, bottom emission, and both the substrate side and the opposite side of the substrate. There are light emitting devices with a double-sided emission structure that emits light from both sides, and light emitting devices with any emission structure can be used. It is possible.

[0144] 5(A), (B) and (B) show examples of light-emitting devices using light-emitting elements as display elements. show.

[0145] FIG. 5(A) is a plan view of the light emitting device, and dashed lines S1-T1 and S2-T 2 and the cross section taken along S3-T3 corresponds to FIG. 5(B). 2, the electroluminescent layer 542 and the second electrode layer 543 are omitted and are not shown.

[0146] The light-emitting device shown in FIG. 5 includes a transistor 510, a capacitor 520, and wiring 512 disposed on a substrate 500. The transistor 510 has a layer intersection 530 and is electrically connected to the light emitting element 540. 5 shows a bottom emission type in which light from the light emitting element 540 is extracted through the substrate 500. This is a light emitting device having a mold structure.

[0147] The transistor 510 can be any of the transistors described above.

[0148] The transistor 510 includes a gate layer 511, a gate insulating layer 502, an oxide semiconductor layer 512, The conductive layers 513a and 513b function as source and drain electrode layers.

[0149] The capacitor 520 includes a conductive layer 521, a gate insulating layer 502, an oxide semiconductor layer 522, and a conductive The conductive layer 521 and the conductive layer 523 form a gate insulating layer 502 and an oxide semiconductor A capacitance is formed by sandwiching the dielectric layer 522 therebetween.

[0150] The wiring layer intersection 530 is an intersection between the gate layer 511 and the conductive layer 533. The gate insulating layer 502 intersects with the conductive layer 533 and the gate insulating layer 511 .

[0151] An interlayer insulating layer 50 is disposed on the transistor 510, the capacitor element 520, and the wiring layer intersection 530. 4 is formed on the interlayer insulating layer 504, and a color filter is formed in the area overlapping the light emitting element 540. A flat insulating film is provided on the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 is provided which functions as a planar insulating layer.

[0152] A first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are formed in this order on an insulating layer 506. A light emitting element 540 including a stacked laminate structure is provided. The junction 510 is formed in the insulating layer 506 and the interlayer insulating layer 504, and reaches the conductive layer 513a. In the opening, the first electrode layer 541 and the conductive layer 513a are in contact with each other, thereby forming an electrical connection. A partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. It is being done.

[0153] The insulating layer 506 is a photosensitive acrylic film having a thickness of 1500 nm, and the partition wall 507 is a A 0 nm photosensitive polyimide film can be used.

[0154] The color filter layer 505 may be made of, for example, a chromatic light-transmitting resin. As the chromatic light-transmitting resin, a photosensitive or non-photosensitive organic resin can be used. By using a photosensitive organic resin layer, the number of resist masks can be reduced, simplifying the process. It is preferable.

[0155] The chromatic colors are colors other than achromatic colors such as black, gray, and white. The color filter layer is a colored It is made of a material that transmits only chromatic light. Chromatic colors include red, green, and blue. Also, cyan, magenta, yellow, etc. may be used. The color filter layer transmits only the colored light. The color filter layer has a peak at the wavelength of light of the color. It is advisable to appropriately control the optimum film thickness, taking into consideration the relationship between the material concentration and the light transmittance. The thickness of the color filter layer 505 may be set to 1500 nm or more and 2000 nm or less.

[0156] In the light-emitting device shown in FIG. 6B, a light-emitting element 4513 which is a display element is a pixel portion 4 The light-emitting element 45 is electrically connected to the transistor 4010 provided in the light-emitting element 45. The structure of the 13th embodiment is a stack of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031. The layer structure is not limited to the configuration shown in FIG. The structure of the light-emitting element 4513 can be changed appropriately depending on the type of light-emitting element.

[0157] The partition wall 4510 (FIG. 6B) and the partition wall 507 (FIG. 5B) are made of an organic insulating material or an inorganic insulating material. The first electrode layer 4030 (FIG. 6) is formed using an insulating material. (B)), an opening is formed on the first electrode layer 541 (FIG. 5(B)), and the side wall of the opening is It is preferable to form the inclined surface so as to have a continuous curvature.

[0158] The electroluminescent layer 4511 (FIG. 6B) and the electroluminescent layer 542 (FIG. 5B) are single layers. The film may be constructed in such a manner that a plurality of layers are laminated.

[0159] The light-emitting element 4513 (FIG. 6B) and the light-emitting element 540 (FIG. 5B) are configured to emit oxygen, hydrogen, water, In order to prevent the intrusion of carbon dioxide and the like, the second electrode layer 4031 (FIG. 6(B)) and the second electrode layer 543 (FIG. 5B), partition wall 4510 (FIG. 6B), partition wall 507 (FIG. 5B) A protective film may be formed. The protective film may be a silicon nitride film, a silicon oxynitride film, a die A DLC film or the like can be formed.

[0160] In addition, oxygen and hydrogen are added to the light-emitting element 4513 (FIG. 6B) and the light-emitting element 540 (FIG. 5B). In order to prevent water, carbon dioxide, etc. from entering, the light emitting element 4513 (FIG. 6B) and the light emitting element 5 A layer containing an organic compound that covers 40 (FIG. 5(B)) may be formed by a vapor deposition method.

[0161] In addition, in the space sealed by the substrate 4001, the substrate 4006, and the sealant 4005, The filling material 4514 is provided and sealed. In this way, the airtight structure is formed so that the filling material 4514 is not exposed to the outside air. Protective films with high heat resistance and low degassing (laminated films, UV curable resin films, etc.) It is preferable to package (enclose) the container in a container-type container or a cover material.

[0162] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, etc. Midi, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Ethylene For example, nitrogen may be used as a filler. .

[0163] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0164] <2-1-3. Electrophoretic display device> It is also possible to provide electronic paper as a display device, which drives electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. It is easy to read, consumes less power than other display devices, and can be made thin and light. It has advantages.

[0165] The electrophoretic display device may have various configurations, but the first particles have a positive charge. and a second particle having a negative charge are immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. The color of the first particles and the color of the second particles are different (including colorless). Let us assume that.

[0166] In this way, electrophoretic displays are devices in which materials with high dielectric constants move to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0167] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. In addition, a color display is possible by using a color filter or particles having a pigment.

[0168] The first particles and the second particles in the microcapsules are made of a conductive material and an insulating material. , semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of a magnetochromic material, a magnetophoretic material, and a composite material thereof. Just use it.

[0169] In addition, display devices using the twist ball display method can also be used as electronic paper. The twist ball display method uses spherical particles painted in black and white to and the first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. A display method in which a potential difference is generated between the electrode layers in order to control the orientation of the spherical particles. It is.

[0170] <2-2.Image sensor> FIG. 7(A) shows an example of an image sensor. FIG. 7(A) shows an equivalent circuit of a photosensor. FIG. 7B is a cross-sectional view showing a part of the photosensor.

[0171] The photodiode 602 has one electrode connected to a photodiode reset signal line 658. The other electrode is electrically connected to the gate of transistor 640. 0 indicates that either the source or the drain is connected to the photosensor reference signal line 672, The other end of the input terminal is electrically connected to one of the source and drain of the transistor 656 . The transistor 656 has a gate connected to a gate signal line 659 and the other of the source and drain connected to a floating gate. It is electrically connected to the photo sensor output signal line 671 .

[0172] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor layer is not clearly shown. In order to make it easier to understand, the symbol for a transistor using an oxide semiconductor layer is written as “OS.” In FIG. 7A, a transistor 640 and a transistor 656 are the same as those described above. Note that in FIG. 7B, the oxide semiconductor layer is a semiconductor A transistor having a structure in which the source electrode layer and the drain electrode layer are extended outward beyond the ends of the source electrode layer and the drain electrode layer. In a transistor with such a structure, the etching stop layer is made of an oxide. The transistor can be formed without being provided between the end of the oxide semiconductor layer and the source electrode layer and the drain electrode layer. It is possible to suppress the formation of parasitic channels in the capacitor.

[0173] FIG. 7B shows a photodiode 602 and a transistor 640 in the photosensor. 6 is a cross-sectional view of the substrate 601 (element substrate) having an insulating surface. A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on the board 602 and the transistor 640 using an adhesive layer 608. do.

[0174] An insulating layer 631, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided on the transistor 640. The photodiode 602 is formed on an electrode layer 641 on an interlayer insulating layer 633. b, and a first semiconductor film 606a and a second semiconductor film 606b stacked in this order on the electrode layer 641b. , and the third semiconductor film 606c, and the first to third semiconductor films An electrode layer 642 electrically connected to the electrode layer 641b via a film, and a layer the same as the electrode layer 641b and an electrode layer 641 a electrically connected to the electrode layer 642.

[0175] The electrode layer 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating layer 634. The electrode layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641a. 5 is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 6 02 is electrically connected to a transistor 640 .

[0176] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor The film 606b is a high resistance semiconductor film (I-type semiconductor film), and the third semiconductor film 606c is an n-type 1 shows a pin-type photodiode in which semiconductor films having the above conductivity types are stacked.

[0177] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed of a fast silicon film. Using semiconductor material gas containing impurity elements (e.g. boron (B)), plasma CVD method Silane (SiH4) may be used as the semiconductor material gas. Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, An impurity element may be introduced into the amorphous silicon film by using an ion implantation method. After the impurity element is introduced by the method, the impurity element may be diffused by heating or the like. In this case, the method for forming the amorphous silicon film includes the LPCVD method and the vapor phase growth method. The first semiconductor film 606a may be formed by a deposition method such as a deposition method or a sputtering method. It is preferable to form it so that the thickness is 50 nm or less.

[0178] The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by using a semiconductor material gas. The rufus silicon film is formed by the plasma CVD method. Alternatively, Si2H6, SiH2Cl2, SiHCl3, The second semiconductor film 606b may be formed by the LPCVD method. Alternatively, the second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 200 nm or more and 1000 nm or less.

[0179] The third semiconductor film 606c is an n-type semiconductor film, and is made of an alumina containing an impurity element that imparts n-type conductivity. The third semiconductor film 606c is formed of a ruthenium silicon film. Formed by plasma CVD using semiconductor material gas containing elements (e.g. phosphorus (P)) Silane (SiH4) can be used as the semiconductor material gas. Alternatively, Si2H6 , SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain any organic elements, the film is then implanted using diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by ion implantation or the like. After the impurity element is introduced, heating or the like is preferably performed to diffuse the impurity element. The method for forming the amorphous silicon film includes the LPCVD method, the vapor phase growth method, and the spa The thickness of the third semiconductor film 606c is 20 nm to 200 nm. It is preferable to form it as follows.

[0180] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, a polycrystalline semiconductor may be used. Amorphous Semiconductor (SA S)) may be used.

[0181] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin type The photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the pin-type photodiode is formed, the photodiode 60 This shows an example of converting the light received by the semiconductor film 2 into an electrical signal. Since light from the semiconductor film side having a conductive type becomes disturbance light, the electrode layer is made of a conductive layer having a light blocking property. In addition, the n-type semiconductor film side can be used as the light receiving surface.

[0182] The insulating layer 631, the interlayer insulating layer 633, and the interlayer insulating layer 634 are made of an insulating material. Depending on the material, sputtering, plasma CVD, spin coating, dip coating, and Using spray coating, droplet ejection method (inkjet method), screen printing, offset printing, etc. It can be formed by

[0183] The insulating layer 631 may be made of an inorganic insulating material such as a silicon oxynitride layer or an oxide layer. A single layer such as a silicon nitride layer or an aluminum oxide layer, or a stacked layer can be used.

[0184] The interlayer insulating layers 633 and 634 function as planarizing insulating layers to reduce surface irregularities. The interlayer insulating layers 633 and 634 are preferably made of, for example, polyimide, acrylic, or the like. Heat-resistant organic resins such as benzocyclobutene resins, polyamides, and epoxy resins In addition to the above organic insulating materials, low-dielectric materials can be used. k materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. A single layer or a laminate of these can be used.

[0185] By detecting light 622 incident on the photodiode 602, information on the detected object is obtained. When reading the information of the detected object, a light source such as a backlight is used. can be used.

[0186] <2-3. Storage device> In the following, the transistors shown in this specification are used to maintain the internal memory even when power is not supplied. An example of a storage device that can hold data and has no limit on the number of times it can be written to is shown below with the aid of a drawing. explain.

[0187] FIG. 8 shows an example of the configuration of a storage device. FIG. 8(A) shows a cross-sectional view of the storage device, and FIG. ) shows a circuit diagram of the memory device.

[0188] The memory device illustrated in FIG. 8A and FIG. 8B includes a semiconductor material other than an oxide semiconductor in the lower portion. A transistor 3200 using an oxide semiconductor is provided in the upper portion of the transistor 3202. and a capacitor element 3204. The transistor 3202 is This is an example in which the structure of a transistor 420 shown in FIG.

[0189] Here, examples of semiconductor materials other than oxide semiconductors include polycrystalline silicon and single crystal silicon. By applying the above, the transistor 3200 can be made to operate at high speed. On the other hand, the transistor 3200 can store charge for a long time by using an oxide semiconductor. It is possible to provide a transistor capable of sustaining a constant current.

[0190] Note that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. The transistor 3202 is made of the same material as that used in memory devices. There is no need to limit the specific configuration of the storage device, such as the material and structure of the storage device, to those shown here. stomach.

[0191] The transistor 3200 in FIG. 8A is made of a semiconductor material (e.g., silicon). A channel forming region is provided on a substrate 3000 including a channel forming region and a The impurity region is provided on the channel forming region, and the intermetallic compound region is provided on the channel forming region. The gate insulating film is formed on the gate electrode layer, and the gate insulating film is formed on the gate electrode layer. In the drawings, the source electrode layer and the drain electrode layer may not be explicitly shown. In this case, the transistor may be called a transistor. In order to explain the connection relationship of the source and drain regions, In other words, in this specification, the term "source electrode layer" is used. may include a source region.

[0192] An element isolation insulating layer 3106 is provided on the substrate 3000 so as to surround the transistor 3200. An insulating layer 3220 is provided to cover the transistor 3200. The element isolation insulating layer 3106 is formed by LOCOS (Local Oxidation of Silicon). silicon) and STI (shallow trench isolation), etc. The element isolation technique can be used.

[0193] By using a single crystal semiconductor substrate as the substrate 3000, the transistor 3200 can operate at high speed. Therefore, the transistor can be used as a readout transistor. In this way, data can be read at high speed. As a process before forming the transistor 3204, the insulating layer 3220 covering the transistor 3200 is subjected to CMP. The insulating layer 3220 is planarized by a process, and the gate electrode layer of the transistor 3200 is also planarized. Expose the top surface.

[0194] Since the off-state current of the transistor 3202 is small, the use of this transistor allows In other words, no refresh operation is required, or the memory contents can be retained. In other words, it is possible to make a storage device that requires an extremely low frequency of refresh operations, thereby reducing power consumption. Power consumption can be significantly reduced.

[0195] One of the source electrode layer and the drain electrode layer of the transistor 3202 is a gate insulating layer and The electrode 3208 is electrically connected to the oxide semiconductor layer through an opening provided in the oxide semiconductor layer. The electrode 32 is electrically connected to the gate electrode layer of the transistor 3200 via the gate electrode 3208. 08 can be formed at the same time as the gate electrode layer of the transistor 3202.

[0196] In addition, an insulating layer 3222 is provided over the transistor 3202 as a single layer or a stacked layer. Then, the source electrode layer or the drain electrode layer of the transistor 3202 is connected through the insulating layer 3222. A conductive layer 3210a is provided in a region overlapping one of the electrode layers, and the transistor 32 One of the source electrode layer or the drain electrode layer of 02, the insulating layer 3222, and the conductive layer 3210a In other words, the source voltage of the transistor 3202 is One of the electrode layer and the drain electrode layer functions as one electrode of the capacitor 3204, and the conductive layer The electrode 3210a functions as the other electrode of the capacitor 3204. Alternatively, the capacitor 3204 may not be provided. , may be provided separately above the transistor 3202.

[0197] An insulating layer 3224 is provided over the capacitor 3204. A wiring 3216 is provided on the transistor 3202 and the other transistors. The wiring 3216 is provided to connect the stator to an opening formed in the insulating layer 3224. An electrode 3214 provided in the mouth, a conductive layer 3210b provided in the same layer as the conductive layer 3210a , and the transistor is connected to the insulating layer 3222 via an electrode 3212 provided in an opening formed in the insulating layer 3222. The source electrode layer or the drain electrode layer of the transistor 3202 is electrically connected to the other of the source electrode layer or the drain electrode layer of the transistor 3202 .

[0198] In FIG. 8A, a transistor 3200 and a transistor 3202 are at least The source region or drain of the transistor 3200 is also provided so as to overlap with the The in-situ region is designed to overlap with part of an oxide semiconductor layer included in the transistor 3202. In addition, the transistor 3202 and the capacitor 3204 are preferably For example, the capacitance element The conductive layer 3210a of the transistor 3204 is at least partially connected to the gate electrode layer of the transistor 3200. By adopting such a planar layout, Since the area occupied by the semiconductor device can be reduced, high integration can be achieved.

[0199] Next, an example of a circuit configuration corresponding to FIG. 8(A) is shown in FIG. 8(B).

[0200] In FIG. 8B, the first wiring (1st Line) and the source of the transistor 3200 The second line and the transistor 32 are electrically connected to each other. The drain electrode layer of the first wiring layer 100 is electrically connected to the drain electrode layer of the second wiring layer 100. ne) and one of the source electrode layer and the drain electrode layer of the transistor 3202 are electrically , and a fourth wiring (4th Line) and a gate electrode layer of a transistor 3202 The gate electrode layer of the transistor 3200 and the The other of the source electrode layer and the drain electrode layer of the transistor 3202 is a potential of the capacitor 3204. The fifth line and the capacitor element 3204 are electrically connected to one of the electrodes. The other electrode is electrically connected.

[0201] In the memory device illustrated in FIG. 8B, the potential of the gate electrode layer of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0202] The writing and retention of information will be explained. First, the potential of the fourth wiring is This sets the potential at which the transistor 3202 is turned on, turning the transistor 3202 on. As a result, the potential of the third wiring is applied to the gate electrode layer of the transistor 3200 and the capacitor 3 That is, a predetermined charge is applied to the gate electrode layer of the transistor 3200. is given (write). Here, the charges that give two different potential levels (Lo Then, either the w-level charge or the high-level charge is given. The potential of the fourth wiring is set to a potential at which the transistor 3202 is turned off. By turning off the transistor 3202, a voltage applied to the gate electrode layer of the transistor 3200 is applied to the gate electrode layer of the transistor 3200. The charge that is applied is retained (retention).

[0203] Since the off-state current of the transistor 3202 is extremely small, the gate The charge on the electrode layer is retained for an extended period of time.

[0204] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the first wiring, In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 3200 Depending on the amount of charge held in the gate electrode layer, the second wiring has a different potential. If the transistor 3200 is an n-channel type, then the gate electrode layer of the transistor 3200 is Apparent threshold V for a given gh level charge th_H Transistor 3 The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer of 200 t h_LHere, the apparent threshold voltage is the voltage at which the transistor 32 00” is defined as the potential of the fifth wiring required to make the “ON state.” Therefore, , the potential of the fifth wire is V th_H and V th_L By setting the potential between the The charge applied to the gate electrode layer of the transistor 3200 can be determined. For example, When a high-level charge is applied, the potential of the fifth wire is V0 (>V th _H ), the transistor 3200 is in the "on state." If the potential of the fifth wire is V0( <V th_L ) even if the transistor Therefore, by determining the potential of the second wiring, , the stored information can be read out.

[0205] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if information is not read out, the state of the gate electrode layer is The potential at which transistor 3200 is in the “off state” regardless of the state of the transistor, i.e., V th _H Alternatively, a potential smaller than the potential of the gate electrode layer may be applied to the fifth wiring. The potential at which transistor 3200 is "on" regardless of the th_L Greater than A threshold potential can be applied to the fifth wiring.

[0206] In the above-described memory device, a transistor including an oxide semiconductor is used, so that It is possible to retain memory contents for a long period of time. In other words, no refresh operation is required. Or, the frequency of refresh operations can be made extremely low, resulting in reduced power consumption. The power consumption can be reduced sufficiently. Also, when there is no power supply (but the potential is fixed), Even if the data is stored in a hard disk, it is possible to retain the contents for a long period of time. It is.

[0207] In addition, the above-mentioned memory device does not require a high voltage to write information, and the deterioration of the elements is prevented. There is no problem. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate is not possible. No gate insulation is required since there is no need to inject or extract electrons from the floating gate. In other words, the above-mentioned memory device does not have the problem of deterioration of the film. There is no limit to the number of times that data can be rewritten, which is an issue with static memory, and reliability is dramatically improved. In addition, information is written depending on the on and off states of the transistors. Therefore, high speed operation can be easily achieved.

[0208] A memory device including the transistors described in this specification may be a memory device including the transistors described in FIG. For example, the transistors in the memory cells of DRAMs may be , the transistor may be applied.

[0209] <Supplementary Note: Regarding oxygen desorption from the oxide semiconductor layer> The fact that oxygen is easily desorbed from the side surfaces (end faces) of the CAAC-OS film will be described in detail below.

[0210] Here, as an example of the oxide semiconductor film, a ternary metal oxide, In-Ga-Zn In the IGZO film, excess oxygen (excessive oxygen exceeding the stoichiometric ratio) The mobility of oxygen atoms and oxygen vacancies is explained with reference to the results of scientific and technological calculations. do.

[0211] The calculation was performed for one In IGZO with an atomic ratio of In:Ga:Zn=3:1:2. A model with one excess oxygen or oxygen vacancy on the -O plane was created by structural optimization (Figure 9 (A) to (C) and Fig. 11 (A) to (C)), and NEB (Nudged El The energy estimation for intermediate structures along the minimum energy path was performed using the energy-stable band method. The ghee was calculated for each.

[0212] The calculations were performed using the density functional theory (DFT)-based calculation program "OpenMX". The parameters are explained below.

[0213] The basis set used is the pseudo-atomic localized basis set. This basis set is the polarized basis set STO(S It is classified as a later Type Orbital.

[0214] The functionals include GGA / PBE (Generalized-Gradient-Appr oximation / Perdew-Burke-Ernzerhof) was used.

[0215] The cutoff energy was set to 200 Ry.

[0216] The sampling k points were set to 5 × 5 × 3.

[0217] In the calculation of the mobility of excess oxygen, the number of atoms in the calculation model was set to 85. In the calculation of the mobility of oxygen vacancies, the number of atoms in the calculation model is set to 8. I decided to make it three.

[0218] The mobility of excess oxygen or oxygen vacancies is determined by the rate at which excess oxygen or oxygen vacancies move to each site. The height of the energy barrier Eb that must be overcome to move the In other words, if the energy barrier Eb that must be overcome during the transfer is high, the transfer becomes difficult. If the energy barrier height Eb is low, it is easier to move.

[0219] First, the movement of excess oxygen will be explained. The model used to calculate the movement of excess oxygen is shown in Figure 9. The calculation was performed for the following two transition forms. The calculation results are shown in Figure 10. In 10, the horizontal axis represents the path length (of the movement of excess oxygen) and the vertical axis represents the state of model A in Figure 9(A). This is the energy required for movement relative to the energy of the object.

[0220] Regarding the transfer of excess oxygen, of the two transition forms mentioned above, the first transition is from model A to The first transition is from model A to model B. The second transition is from model A to model C.

[0221] The oxygen atom indicated as "1" in FIGS. 9(A) to 9(C) corresponds to the first oxygen atom of model A. The oxygen atom marked as “2” in Figure 9(A) to (C) is model A. The oxygen atom marked "3" in Figures 9(A) to 9(C) is called the second oxygen atom. This is called the third oxygen atom of Model A.

[0222] As is clear from FIG. 10, the maximum value of the energy barrier height Eb of the first transition (Eb max ) is 0.53 eV, and the maximum value of the energy barrier height Eb of the second transition ( Eb max ) is 2.38 eV. Therefore, the first transition has more energy than the second transition. Maximum height of energy barrier Eb (Eb max ) is low. Therefore, the time required for the first transition is The energy required for the first transition is less than that required for the second transition, so the first transition is more efficient than the second transition. It can be said that this is more likely to occur than

[0223] That is, the movement of the first oxygen atom of model A pushes out the third oxygen atom of model A. It can be said that the second oxygen atom of model A tends to move in the pushing direction rather than in the pushing direction. , oxygen atoms move along the layer of indium atoms rather than across it. It can be said to be easy to move around.

[0224] Next, the movement of oxygen vacancies will be explained. The model used to calculate the movement of oxygen vacancies is shown in Figure 1. The calculations were performed for the following two transition forms. The calculation results are shown in Figure 12. In FIG. 12, the horizontal axis represents the path length (of the movement of oxygen vacancies), and the vertical axis represents the path length of model A in FIG. This is the energy required (to move) relative to the energy of the state.

[0225] Regarding the transfer of oxygen vacancies, of the two transition forms mentioned above, the first transition is from model A to The first transition is from model A to model B. The second transition is from model A to model C.

[0226] In addition, the circles drawn with dotted lines in FIGS. 11(A) to (C) represent oxygen vacancies.

[0227] As is clear from FIG. 12, the maximum value of the energy barrier height Eb of the first transition (Eb max ) is 1.81 eV, and the maximum value of the energy barrier height Eb of the second transition ( Eb max ) is 4.10 eV. Therefore, the first transition has more energy than the second transition. Maximum height of energy barrier Eb (Eb max ) is low. Therefore, the time required for the first transition is The energy required for the first transition is less than that required for the second transition, so the first transition is more efficient than the second transition. It can be said that this is more likely to occur than

[0228] That is, the oxygen vacancies in model A are closer to the oxygen vacancies in model B than those in model C. Therefore, the oxygen vacancies also cross the indium atom layer. It can be said that the indium atoms tend to move along the layer of indium atoms rather than along the indium atom layer.

[0229] Next, to compare the likelihood of the four transition forms mentioned above from a different perspective, The temperature dependence of the transitions is explained below. The four transition modes mentioned above are: (1) the first transition mode with excess oxygen (2) Second transition with excess oxygen (3) First transition with oxygen deficiency (4) Second transition with oxygen deficiency There are four transitions:

[0230] The temperature dependence of these transitions is compared based on the transition frequency per unit time. The migration frequency Z ( / sec) at the temperature T (K) is the number of oxygen atoms at chemically stable positions. Using the vibration frequency Zo ( / sec), it can be expressed by the following equation (1).

[0231]

number

[0232] In addition, in formula (1), Eb max is the height of the energy barrier Eb for each transition is the maximum value, and k is the Boltzmann constant. Zo=1.0×10 13 ( / sec) Used in calculations.

[0233] The maximum energy barrier height Eb is reached when excess oxygen or oxygen deficiency occurs once per second. Value(Eb max) (when Z = 1 ( / sec)), T is calculated using Eq. (1) Solving this gives us the following: (1) First transition of excess oxygen: T = 206 K (-67 °C) at Z = 1 (2) Second transition of excess oxygen: T = 923 K (650 °C) at Z = 1 (3) First transition of oxygen vacancy: T=701K (428℃) at Z=1 (4) Second transition of oxygen vacancy: T=1590K (1317℃) at Z=1

[0234] On the other hand, when T = 300K (27°C), Z is as follows: (1) First transition of excess oxygen: Z=1.2×10 at T=300K 4 ( / sec) (2) The second transition of excess oxygen: Z = 1.0 × 10 at T = 300 K -27 ( / sec) (3) First transition of oxygen vacancy: Z=4.3×10 at T=300K -18 ( / sec) (4) Second transition of oxygen vacancy: Z=1.4×10 at T=300K -56 ( / sec)

[0235] Furthermore, Z when T = 723K (450°C) is as follows: (1) First transition of excess oxygen: Z=2.0×10 at T=723K 9 ( / sec) (2) The second transition of excess oxygen: Z=2.5×10 at T=723K -4 ( / sec) (3) First transition of oxygen vacancy: Z=2.5( / sec) at T=723K (4) Second transition of oxygen vacancy: Z=2.5×10 at T=723K -16 ( / sec)

[0236] Considering the calculation results, the excess oxygen is It is easier for indium atoms to move along a layer of indium atoms than across it. In addition, the oxygen vacancy was not observed at T = 300 K or T = 723 K. It is easier for indium atoms to move along the layer of indium atoms than across the layer of indium atoms. do.

[0237] Also, at T = 300 K, the migration of excess oxygen along the layer of indium atoms occurs very rapidly. At T = 723 K, the indium atom Not only does the excess oxygen move along the indium layer, but oxygen vacancies also move along the indium atom layer. However, the cross-layer migration of indium atoms is difficult for both excess oxygen and oxygen vacancies. is difficult.

[0238] Therefore, for example, in the CAAC-OS film, a layer of indium atoms is formed on the surface of the film. When the oxygen vacancies are present on the surface of the film, the excess oxygen and the oxygen vacancies are both on the surface of the film. It can be said that it tends to move along the forming surface or surface.

[0239] As described above, in the CAAC-OS film, excess oxygen and oxygen vacancies are generated in the film formation. Therefore, oxygen escape from the side of the film becomes a problem. When oxygen loss occurs, the amount of excess oxygen decreases, making it difficult to fill the oxygen vacancies. If oxygen vacancies exist, the oxide becomes unsuitable for use in switching elements. The electrical conductivity of the CAAC-OS film may be increased.

[0240] In the above explanation, when excess oxygen or oxygen vacancy crosses the layer of indium atoms, However, the same applies to metals other than indium contained in the oxide semiconductor film. do.

[0241] (Embodiment 2) In this embodiment, one mode of a manufacturing method of a semiconductor device will be described with reference to FIGS. One embodiment of a semiconductor device will be described with reference to FIGS. 13(C), 13(D), and 13(E). I will use this to explain.

[0242] FIG. 13C, FIG. 13D, and FIG. 13E show an example of a semiconductor device. 13A and 13B are a plan view and a cross-sectional view of the transistor 410. FIG. 13E is a plan view of the transistor 410. FIG. 13C is a cross-sectional view taken along line X1-X2 of FIG. 13E. FIG. 13D is 13(E) is a cross-sectional view taken along line Y1-Y2 of FIG.

[0243] The transistor 410 shown in FIG. 13(C), FIG. 13(D), and FIG. 13(E) is a transistor having a substrate 40 A base insulating layer 436 is formed on the insulating film 436, and an oxide semiconductor film 403 is formed on the base insulating layer 436. A gate insulating film 402 is provided on the semiconductor film 403, and an oxide semiconductor is formed on the gate insulating film 402. A gate electrode layer 401 provided on the conductive film 403 and a The insulating film 406, the gate insulating film 402, and the oxide semiconductor A source electrode layer 405a or a drain electrode layer 405b electrically connected to the film 403, and an insulating film 407 provided on the source electrode layer 405a and the drain electrode layer 405b. It is composed of:

[0244] In the transistor 410, the oxide semiconductor film 403 overlaps with the gate electrode layer 401. A channel forming region 409 overlaps the channel forming region 409, and a channel forming region 4 09, and low resistance regions 404a and 404b containing dopants are formed. The dopant is an element that changes the electrical conductivity of the oxide semiconductor film. The group 15 elements (representatively nitrogen (N), phosphorus (P), arsenic (As), and antimony (Ant)) Sb), Boron (B), Aluminum (Al), Tungsten (W), Molybdenum (Mo), indium (In), gallium (Ga), fluorine (F), chlorine (Cl), titanium The metal is at least one selected from titanium (Ti) and zinc (Zn).

[0245] The oxide semiconductor film 403 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. In this embodiment, the low resistance region 404a and the low resistance region 404b are doped with a dopant. The resistive region 404b is almost entirely amorphous, or the ratio of the amorphous component is higher than the crystalline component. This area is considered to be

[0246] FIG. 13A shows a cross-sectional view of a process before an impurity element that serves as a dopant is introduced. The oxide semiconductor film 403 before the introduction of the impurity element serving as a dopant is a single crystal film or a polycrystalline film. The membrane is called a polycrystal membrane or a CAAC-OS membrane.

[0247] The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). m or less) and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Dep In addition, the oxide semiconductor film 403 can be formed by a spa Film deposition is performed on multiple substrate surfaces set approximately perpendicular to the target surface. Alternatively, the film may be formed by using a sputtering apparatus which performs the above steps.

[0248] For single crystal films, polycrystalline films, or CAAC-OS films, the deposition conditions of the deposition method or the deposition This can be achieved by increasing the substrate temperature during deposition or by appropriately performing a heat treatment after deposition.

[0249] As shown in FIG. 13B, the low resistance region 404a and the low resistance region 404b are After forming the gate electrode layer 401, an impurity element is introduced using the gate electrode layer 401 as a mask. The method of doping the impurity element is as follows: In this case, an ion implantation method or an ion doping method is used. The gate insulating layer 10 may function as a source or drain region.

[0250] By providing the low resistance region 404a and the low resistance region 404b, the pair of low resistance regions The electric field applied to the channel forming region 409 provided between the regions can be reduced. The source electrode layer 405a and the drain electrode layer 405b are formed in the low resistance region 404a and the low resistance region 404b, respectively. 404b, the oxide semiconductor layer 403 and the source electrode layer 405a and The contact resistance with the drain electrode layer 405b can be reduced.

[0251] In this embodiment, the channel formation region 409 is formed by the low resistance region 404a and the low resistance In comparison with the resistive region 404b, the proportion of crystalline components is higher than that of amorphous components. Hydrogen is attracted in the direction indicated by the dotted arrow in the figure, and the low resistance region 404a and the low resistance region 4 The hydrogen concentration in the channel formation region 409 is lower than that in 04b.

[0252] In addition, impurities such as hydrogen are sufficiently removed from the oxide semiconductor film 403. , Highly purified by supplying sufficient oxygen to make it supersaturated with oxygen. Specifically, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 atom s / cm 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5x 10 17 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer is as follows: Secondary Ion Mass Spectrometry (SIMS) Also, if sufficient oxygen is supplied, oxygen supersaturation occurs. In order to achieve this state, an insulating layer (Si Ox, etc.) is placed in contact with the

[0253] The insulating layer containing excess oxygen is the base insulating layer 436 and the gate insulating film 402. The insulating base layer 436 and the gate insulating film 403 are provided so as to be in contact with each other and to enclose the insulating base layer 436 and the gate insulating film 403. 2) By appropriately setting the film formation conditions in the PCVD method or sputtering method, the film contains a large amount of oxygen. In addition, a large amount of excess oxygen is included in the insulating layer. In this case, oxygen doping by ion implantation, ion doping, or plasma treatment is used. Oxygen is added by

[0254] The above "oxygen doping" refers to the doping with oxygen (at least oxygen radicals, oxygen atoms, oxygen molecules, etc.) ions, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions The term "bulk" refers to the addition of oxygen to a thin film. The term "oxygen dopant" is used to clarify that the dopant is added not only to the surface but also to the inside of the thin film. "Oxygen plasma doping" includes "oxygen plasma doping," which adds oxygen plasma to the bulk. .

[0255] The oxygen doping treatment can be carried out using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen doping treatment, a rare gas may be contained in the oxygen-containing gas.

[0256] By the above-described oxygen doping treatment, the interface between the insulating layer and the oxide semiconductor film or the bulk of the insulating layer In the above, at least one portion of the film has oxygen in an amount exceeding the stoichiometric ratio. A region can be provided.

[0257] In addition, an insulating film 40 is formed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. The insulating film 406 is planarized to reduce surface irregularities caused by the transistor. The planarizing insulating film may be made of polyimide resin, acrylic resin, or benzene. In addition to the above organic materials, organic materials such as cyclobutene-based resins can be used. Low dielectric constant materials (low-k materials) can be used. A planarizing insulating film may be formed by stacking a plurality of insulating films.

[0258] In addition, the insulating layer may be formed so as to surround the oxide semiconductor film and to be disposed outside the insulating layer containing excess oxygen. It is preferable to provide a blocking layer (such as AlOx) that suppresses oxygen release from the oxide semiconductor film. stomach.

[0259] The insulating film 407 corresponds to the blocking layer. An aluminum film is laminated, and oxygen is doped on the insulating layer and aluminum film from above the aluminum film. By carrying out the above steps, a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer. In both cases, it is preferable to oxidize the aluminum film to form an aluminum oxide film. The aluminum oxide film is covered with a titanium oxide film, a tungsten oxide film, a nickel oxide film, and an oxide film. A molybdenum film or a magnesium oxide film is laminated, and the titanium oxide film and the tungsten oxide film are laminated. , the resistivity of nickel oxide film, molybdenum oxide film, or magnesium oxide film is 1×10 10 Ωm or more 1×10 19 Ωm or less (preferably 1×10 10 Ωm or more 1×10 18 Ωm or more or less, more preferably 1×10 11 Ωm or more 1×10 15 It is preferable to set the resistance to Ωm or less. By providing a film having the above resistivity, electrostatic damage to a semiconductor device can be prevented. .

[0260] By wrapping the oxide semiconductor film with an insulating layer or a blocking layer containing excess oxygen, A state in which the composition of a semiconductor layer is nearly equal to the stoichiometric composition or is less than the stoichiometric composition. It is possible to make the oxide semiconductor film in a supersaturated state with a large amount of oxygen. For example, when the oxide semiconductor film is IGZO, An example of the stoichiometric composition is In:Ga:Zn:O=1:1:1:4 [atomic ratio]. Therefore, the atomic ratio of oxygen in the oxide semiconductor film is more than 4.

[0261] Note that, although an example of stacking the insulating films 406 and 407 is shown in this embodiment mode, the present invention is not limited to this. The insulating film 406 may be omitted.

[0262] The transistor 410 is formed by self-aligning a region having a large crystal component (i.e., a channel forming region 409 ) and a region with a large amount of amorphous components (i.e., low resistance region 404a and low resistance region 404b). The hydrogen concentration in the channel formation region 409 is controlled to be The hydrogen concentration in the channel of transistor 410 is reduced compared to that in the region with more hydrogen. By removing hydrogen as much as possible from the pore formation region and supplying oxygen, highly purified I-type or By making it an I-type, the threshold voltage of the transistor can be This can be a positive switching element, and a so-called normally-off switching element can be realized. The channel formation region of the transistor 410 has an extremely low minority carrier density and is oxygen Carrier generation sources such as defects and hydrogen are reduced, making it possible to make the off-current extremely small.

[0263] (Embodiment 3) In this embodiment, referring to FIG. 14, a semiconductor device having a sidewall on the side wall of a gate electrode layer is An example of a method for manufacturing the device will be described.

[0264] First, a base insulating layer 436 is formed over a substrate 400 having an insulating surface.

[0265] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. In addition, a silicon substrate, a silicon carbide substrate, etc. can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A semiconductor device having a semiconductor element on a substrate such as a silicon-on-insulator (SOI) substrate can also be used. may be used as the substrate 400.

[0266] A semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture such a semiconductor device, a transistor including an oxide semiconductor film 403 is formed on a flexible substrate. Alternatively, the transistor 440a including the oxide semiconductor film 403 may be formed on another substrate. The resistor 440a may be fabricated, and then peeled off and transferred to a flexible substrate. In order to peel and transfer the oxide semiconductor film 403 from the formation substrate to a flexible substrate, A release layer may be provided between the resistor 440a and the substrate 440b.

[0267] The base insulating layer 436 is formed of a silicon oxide film by a plasma CVD method, a sputtering method, or the like. Con, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, hafnium oxide, It can be formed using gallium oxide or a mixture of these materials.

[0268] The base insulating layer 436 may be a single layer or a stacked layer. For example, The In-Hf-Zn oxide film and the oxide semiconductor film 403 may be laminated in this order. 0, silicon oxide film, In-Zr-Zn system with atomic ratio of In:Zr:Zn=1:1:1 The oxide film and the oxide semiconductor film 403 may be stacked in this order. film, In-Gd-Zn oxide film with an atomic ratio of In:Gd:Zn=1:1:1, oxide semiconductor The conductive films 403 may be laminated in order.

[0269] In this embodiment mode, the base insulating layer 436 is formed of silicon oxide by a sputtering method. A membrane is used.

[0270] In addition, a nitride insulating film may be provided between the base insulating layer 436 and the substrate 400. The film is made of silicon nitride or silicon oxide nitride by plasma CVD or sputtering. The insulating layer is formed using aluminum nitride, aluminum oxide nitride, or a mixture of these materials. It is possible.

[0271] Since the base insulating layer 436 is in contact with the oxide semiconductor film 403, at least For example, the amount of oxygen in the base insulating layer 436 is preferably greater than the stoichiometric ratio. When a silicon oxide film is used, SiO 2+α (However, α>0). This By using such a base insulating layer 436, oxygen can be supplied to the oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, This makes it possible to compensate for oxygen vacancies in the film.

[0272] For example, the base insulating layer 436 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, may be formed using an oxide semiconductor By providing the base insulating layer 436 in contact with the oxide semiconductor film 403, the oxide semiconductor film 403 can be easily formed without being affected by an acid. The oxide semiconductor film 403 and the base insulating layer 436 can be heated to 1000° C. By performing heat treatment with the oxide semiconductor film 403 in contact with the oxide semiconductor film 403, oxygen is supplied to the oxide semiconductor film 403. It is also possible.

[0273] A region of the base insulating layer 436 in contact with the oxide semiconductor film 403 is subjected to planarization treatment. The planarization treatment may be, but is not limited to, a polishing treatment (e.g., chemical Chemical Mechanical Polishing (CMP) ), dry etching treatment, or plasma treatment can be used.

[0274] The plasma treatment may be, for example, a reverse sputtering treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the cleaning is performed, powdery substances (particles, dust, etc.) adhering to the surface of the base insulating layer 436 are removed. (also called) can be removed.

[0275] As the planarization process, the polishing process, the dry etching process, and the plasma process may be performed multiple times. In addition, when performing the steps in combination, the order of the steps is not particularly limited. It is not limited to a specific value and may be appropriately set depending on the unevenness of the surface of the base insulating layer 436.

[0276] The planarization process is, for example, a chemical mechanical treatment on the surface of a silicon oxide film used as the base insulating layer 436. Polishing treatment by polishing method (polishing conditions: polyurethane-based polishing cloth, silica-based slurry, slurry Temperature: Room temperature, polishing pressure: 0.001MPa, polishing speed (table / spindle): 60rpm / 56 rpm, polishing time 0.5 min) was performed, and the average surface roughness (R a) may be set to approximately 0.15 nm.

[0277] Next, the oxide semiconductor film 403 is formed over the base insulating layer 436 .

[0278] In the process of forming the oxide semiconductor film 403, hydrogen or water is added to the oxide semiconductor film 403. In order to prevent the inclusion of the oxide semiconductor film 403, a sputtering process was performed as a pretreatment for the formation of the oxide semiconductor film 403. The substrate on which the insulating base layer 436 is formed is preheated in a preheating chamber of the deposition apparatus. It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed in the base insulating layer 436. The exhaust means provided in the preheating chamber is preferably a cryopump.

[0279] In addition, impurities such as hydrogen (including water and a hydroxyl group) are reduced in the base insulating layer 436, and oxygen is prevented from being generated. In order to obtain an excess state, hydrogen (including water and a hydroxyl group) is removed (dehydrated) from the base insulating layer 436. Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen doping The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed multiple times. Well, you can do both repeatedly.

[0280] The oxide semiconductor film 403 is in a supersaturated state immediately after deposition, in which oxygen is more than the stoichiometric composition. For example, the oxide semiconductor film 403 is formed by a sputtering method. In this case, it is preferable to form the film under conditions in which the proportion of oxygen in the film forming gas is high. It is preferable to perform film formation in an atmosphere (100% oxygen gas). When deposition is performed under conditions with a high oxygen content, especially in an atmosphere of 100% oxygen gas, the deposition temperature is increased to 300°C or higher. As a result, the release of Zn from the film can be suppressed.

[0281] In addition, in order to supply sufficient oxygen to the oxide semiconductor film 403 and to make the oxide semiconductor film 403 supersaturated with oxygen, The insulating films in contact with the oxide semiconductor film 403 (the insulating films provided to surround the oxide semiconductor film 403) are It is preferable that the insulating film contains excess oxygen.

[0282] Note that in this embodiment, the oxide semiconductor film 403 is formed by a sputtering method. The target for this purpose has a composition of In:Ga:Zn=3:1:2 [atomic percentage]. An In-Ga-Zn oxide film (IGZO film) is formed using an oxide target.

[0283] The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The relative density is 95% or more and 99.9% or less. Use a metal oxide target with high relative density. As a result, the formed oxide semiconductor film can be a dense film.

[0284] The oxide semiconductor film 403 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or an arsenic compound. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0285] The substrate is held in a film-forming chamber that is kept in a reduced pressure state. Then, the remaining moisture in the film-forming chamber is removed. A sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the above target. In order to remove residual moisture in the deposition chamber, an oxide semiconductor film 403 is formed on the substrate. type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps It is preferable to use a turbo molecular pump with a cold trap as the exhaust means. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen atoms, water (H2O) and other compounds that contain hydrogen atoms (preferably compounds that contain carbon atoms) Since gases such as impurities and impurities are exhausted from the deposition chamber, the oxide semiconductor film 403 formed in the deposition chamber is The concentration of substances can be reduced.

[0286] In addition, the base insulating layer 436 and the oxide semiconductor film 403 are successively formed without exposure to the air. It is preferable that the base insulating layer 436 and the oxide semiconductor film 403 be formed in succession without being exposed to air. By forming the insulating layer 436 in this manner, it is possible to prevent impurities such as hydrogen and moisture from being adsorbed on the surface of the base insulating layer 436. It is possible.

[0287] The oxide semiconductor film 403 is formed by forming an island-like oxide semiconductor film into a film-like oxide semiconductor film by a photolithography process. The insulating film can be formed by processing the oxide semiconductor film.

[0288] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0289] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. For example, an etchant used for wet etching of an oxide semiconductor film may be used. The cleaning solution can be a mixture of phosphoric acid, acetic acid, and nitric acid. O-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Dry etching using the Inductively Coupled Plasma (ICP) etching method For example, the IGZO film can be etched by ICP etching. Then, etching was performed (etching conditions: etching gas (BCl3:Cl2 = 60 sccm: 20sccm), power supply power 450W, bias power 100W, pressure 1.9Pa), and It can be processed into.

[0290] The oxide semiconductor film 403 contains almost no impurities such as copper, aluminum, or chlorine. In the manufacturing process of the transistor 440a, In this way, a process is performed in which there is no risk of these impurities being mixed in or attached to the surface of the oxide semiconductor film 403. It is preferable to select an appropriate one. When the oxide semiconductor film 403 is attached to the surface of the oxide semiconductor film 403, the oxide semiconductor film 403 is preferably made of oxalic acid. or dilute hydrofluoric acid, or by plasma treatment (such as N2O plasma treatment). It is preferable to remove impurities on the surface of the oxide semiconductor film 403 by using a fluorine-containing oxide The copper concentration of the semiconductor film 403 is 1×10 18 atoms / cm 3 Less than or equal to 1×10 1 7 atoms / cm 3 The aluminum concentration in the oxide semiconductor film 403 is 1 ×10 18 atoms / cm 3 The chlorine concentration in the oxide semiconductor film 403 is 2 ×10 18 atoms / cm 3 The following applies.

[0291] In addition, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300° C. or higher and 700° C. or lower. The temperature should be below ℃ or below the distortion point of the substrate. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor The film 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0292] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0293] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0294] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not included. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than ppm.

[0295] After the oxide semiconductor film 403 is heated by heat treatment, high-purity oxygen gas, high-purity 100°C nitrous oxide gas or ultra dry air (CRDS (Cavity Ring Down Laser Dispersion) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). (air having a concentration of 1 ppm or less, preferably 10 ppb or less) may be introduced. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, Preferably, the concentration is 0.1 ppm or less. The action of dehydration or dehydrogenation reduces the amount of impurities present in the process. By supplying oxygen, which is the main component of oxide semiconductors, The semiconductor film 403 can be highly purified and made electrically I-type (intrinsic).

[0296] Note that the timing of the heat treatment for dehydration or dehydrogenation is determined based on the time when the oxide semiconductor film is heated to 1000° C. The step may be performed after the formation of the oxide semiconductor film 403 or after the formation of the island-shaped oxide semiconductor film 403.

[0297] The heat treatment for dehydration or dehydrogenation may be carried out multiple times or may be carried out in combination with other heat treatments. You can sleep.

[0298] The heat treatment for dehydration or dehydrogenation is performed to form the oxide semiconductor film 403 into an island shape. When the oxide semiconductor film 403 covers the base insulating layer 436, the oxide semiconductor film 403 is heated to 3000.degree. This is preferred because it can prevent the oxygen contained in 436 from being released by heat treatment. It is nice.

[0299] Next, a gate insulating film 442 covering the oxide semiconductor film 403 is formed.

[0300] In order to improve coverage of the gate insulating film 442, a film of The above-mentioned planarization process may be performed. In that case, it is preferable that the oxide semiconductor film 403 have a surface with good flatness.

[0301] The thickness of the gate insulating film 442 is set to 1 nm or more and 20 nm or less. A method such as a deposition method, a CVD method, a pulsed laser deposition method, or an ALD method can be used as appropriate.

[0302] The material of the gate insulating film 442 is a silicon oxide film, a gallium oxide film, an aluminum oxide film, or the like. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a nitride oxide film. The gate insulating film 442 can be formed using a silicon film. It is preferable that the gate insulating film 442 contains oxygen in the portion in contact with the gate insulating film 442. It is preferred that there is at least a stoichiometric amount of oxygen present (in the bulk), e.g. For example, when a silicon oxide film is used as the gate insulating film 442, SiO 2+α (just In this embodiment, the gate insulating film 442 is made of SiO 2+α (Ta The silicon oxide film is used as the gate insulating film 44. By using the oxide semiconductor film 403 as the second oxide semiconductor film, oxygen can be supplied to the oxide semiconductor film 403, and the characteristics of the oxide semiconductor film 403 can be improved. In addition, the gate insulating film 442 can be formed in a thickness appropriate for the size and thickness of a transistor to be manufactured. It is preferable to form the gate insulating film 442 taking into consideration its step coverage.

[0303] The material of the gate insulating film 442 is hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate Hafnium aluminate (HfAl x O y(x>0, y>0)), lanthanum oxide By using high-k materials, the gate leakage current can be reduced. The insulating film 442 may have a single layer structure or a multilayer structure.

[0304] In addition, the gate insulating film 442 is made of a material that reduces impurities such as hydrogen (including water and hydroxyl groups) and is made of an acid. In order to obtain a hydrogen-rich state, hydrogen (including water and hydroxyl groups) is removed (desorbed) from the gate insulating film 442. Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen Doping treatment may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed multiple times. Alternatively, both may be performed repeatedly.

[0305] In this embodiment, the gate insulating film 442 is subjected to a thermal treatment at a temperature of 200° C. to 400° C. The gate insulating film 442 is then subjected to an oxygen plasma treatment using microwaves. The gate insulating film 442 is dehydrated or dehydrogenated, and oxygen doped. can.

[0306] Next, a conductive film and an insulating film are stacked on the gate insulating film 442. Etching is performed to form a stack of the gate electrode layer 401 and the insulating film 413.

[0307] The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, aluminum, etc. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as their main components The gate electrode layer 401 can be formed using a gold material. Semiconductor films such as element-doped polycrystalline silicon films, nickel silicide, etc. The gate electrode layer 401 may have a single layer structure or a stacked layer structure. The structure may also be used.

[0308] The material of the gate electrode layer 401 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, oxide Conductive materials such as silicon doped indium tin oxide can also be used. A laminated structure of the conductive material and the metal material may also be used.

[0309] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 442 is made of a metal oxide film containing nitrogen. In-Ga-Zn-O films containing nitrogen and In-Sn-O films containing nitrogen , In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn- O film, nitrogen-containing In-O film, and metal nitride film (InN, SnN, etc.) can be used. These films have a valence of 5 eV (electron volts) or more, preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of a transistor is increased by 1000 V. Therefore, a so-called normally-off switching element can be realized.

[0310] The insulating film 413 is typically a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. , aluminum oxide nitride film, silicon oxide film, silicon oxynitride film, aluminum oxide film An inorganic insulating film such as an aluminum oxynitride film can be used as the insulating film 413. The insulating film 11 can be formed by using a plasma CVD method, a sputtering method, or the like.

[0311] Next, the oxide semiconductor film 403 is doped with the gate electrode layer 401 and the insulating film 413 as masks. A punt is introduced to form low resistance regions 404a and 404b (see FIG. 14(A)).

[0312] The dopant introduction process is carried out by adjusting the injection conditions such as the acceleration voltage and the dose amount, as well as the thickness of the film through which the dopant passes. In this embodiment, phosphorus is used as the dopant, and indium is used as the dopant. Phosphorus ions are implanted using the ion implantation method. The dopant dose is 1×10 13 io ns / cm 2 5×10 or more 16 ions / cm 2 The following would suffice.

[0313] The dopant concentration in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0314] The dopant may be introduced while the substrate 400 is being heated.

[0315] Note that the treatment of introducing a dopant into the oxide semiconductor film 403 may be performed multiple times. A plurality of types of punts may be used.

[0316] After the dopant introduction process, a heat treatment may be performed. The heating conditions are a temperature of 30 At 0°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heat treatment under a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air). You may go.

[0317] In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The phosphorus (P) ion implantation conditions were an acceleration voltage of 30 kV and a dose of 1.0×1. 0 15 ions / cm 2 Let us assume that.

[0318] The oxide semiconductor film 403 is a CAAC-OS film, a polycrystalline film, or a single crystal film. The semiconductor film 403 is doped with dopant depending on the conditions of the dopant introduction process and the type of dopant. The introduction of dopants may cause some of the material to become amorphous. Therefore, in the oxide semiconductor film that does not overlap with the gate electrode layer 401, the upper layer becomes amorphous. However, the lower layer may not be doped and may retain its crystalline components. In the case where a part of the film is made amorphous in this way, the above-mentioned heat treatment is performed to remove the amorphous region. It is preferable to recrystallize the oxide semiconductor film 403 to increase the crystallinity of the oxide semiconductor film 403.

[0319] Through the above steps, low resistance regions 404a and 404b are formed on either side of a channel forming region 409. 4b is provided, and an oxide semiconductor film 403 having high crystallinity is formed.

[0320] Next, in order to form a sidewall insulating layer (hereinafter also referred to as a sidewall), an insulating film 448 is formed. (See FIG. 14(B)).

[0321] The insulating film 448 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. , aluminum oxynitride film, silicon nitride film, aluminum nitride film, silicon nitride oxide film An inorganic insulating film such as an aluminum nitride oxide film can be used, and it may be a single layer or a laminated layer. The insulating film 448 is formed by plasma CVD, sputtering, or CV deposition using a deposition gas. The CVD method can be the LPCVD method, the plasma CVD method, etc. Alternatively, a coating method or the like can be used.

[0322] Then, the insulating film 448 is anisotropically etched to form sidewall insulating layers 414a and 414b. do.

[0323] Furthermore, the gate electrode layer 401, the insulating film 413, and the sidewall insulating layers 414a and 414b are used as a mask. Then, the gate insulating film 442 is etched to form the gate insulating film 402 (FIG. 14(C) )). Also, the gate insulating film 442 is etched to form low resistance regions 404a and 404b. Expose a part of b.

[0324] Next, a process is performed to make a part of the exposed low resistance regions 404a and 404b amorphous. One of the treatments for improving the quality of the material is exposure to argon plasma or oxygen plasma. Alternatively, the substrate may be exposed to a plasma containing a dopant. The plasma may be oxygen, argon, or When the oxide semiconductor film 403 is thicker than the depth from the surface to which the dopant is added, By exposing the exposed low-resistance regions 404a and 404b to plasma, only the surface layers become amorphous. The crystal components are maintained in the other regions. By providing the amorphous regions 445a and 445b, the structure shown in FIG. Hydrogen is attracted in the direction indicated by the dotted arrow in (D), forming amorphous regions 445a and 445b. This attracts and immobilizes hydrogen to the surface, thereby removing as much hydrogen as possible from the channel formation region.

[0325] In addition, when a part of the exposed low-resistance regions 404a and 404b is amorphous, the insulating film The gate electrode layer 401 is protected from plasma by the sidewall insulating layers 413 and 414a and 414b. This is important in

[0326] In addition, other methods of processing to make a part of the exposed low resistance regions 404a, 404b amorphous may be used. One method is to use an ion implantation device or an ion plasma device to implant argon, oxygen, or dopant. Addition of ethylene glycol may also be performed.

[0327] Next, a protective insulating film is formed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. As a highly dense inorganic insulating film (typically an aluminum oxide film), the insulating film 407 Form.

[0328] The insulating film 407 may be a single layer or a multilayer, and preferably includes at least an aluminum oxide film. I wish.

[0329] The aluminum oxide film is applied at a high density (film density 3.2 g / cm 3 More than 3.6 g / cm, preferably 3.6 g / cm 3 By using the above-mentioned, it is possible to provide the transistor 440a with stable electrical characteristics. The film density can be measured by Rutherford backscattering spectroscopy or X-ray reflectometry. In addition, the aluminum oxide film has a stoichiometric ratio exceeding that of the bulk. For example, when an aluminum oxide film is used, AlO x (where x>1.5).

[0330] The aluminum oxide film used as the insulating film 407 is a film that can remove impurities such as hydrogen and moisture and oxygen. It has a high blocking effect that prevents both from passing through the membrane.

[0331] Therefore, the insulating film 407 is resistant to hydrogen, moisture, and other factors that may cause fluctuations during and after the manufacturing process. What impurities are mixed into the oxide semiconductor film 403 and what is the main component material of the oxide semiconductor? The oxide semiconductor film 403 functions as a protective film for preventing release of oxygen from the oxide semiconductor film 403. The aluminum oxide film can also supply oxygen to the oxide semiconductor film 403 provided in contact therewith. can.

[0332] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. The insulating film 407 may be a metal film obtained by oxidizing the metal film. In this embodiment, an aluminum film is doped with oxygen. An aluminum oxide film obtained by the above process is used.

[0333] Besides the aluminum oxide film, the insulating film 407 can be typically a silicon oxide film or a nitride film. Inorganic insulating films such as silicon oxide film, aluminum oxide nitride film, and gallium oxide film are used. Also, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, , lanthanum oxide film, barium oxide film, or metal nitride film (e.g., aluminum nitride film) can also be used.

[0334] An interlayer insulating film 415 is formed on the insulating film 407. The interlayer insulating film 415 has the same structure as the insulating film 407. The interlayer insulating film 415 can be formed by using the above-mentioned materials and methods. The interlayer insulating film 4 is formed to a thickness that can flatten the unevenness caused by the transistor 440a. The 15 is a silicon oxynitride film formed by a CVD method or a silicon oxide film formed by a sputtering method. A silicon oxide film formed by the above process can be used.

[0335] In addition, the interlayer insulating film 415 is a planarizing insulating film for reducing surface irregularities caused by transistors. The planarizing insulating film may be formed of polyimide resin, acrylic resin, or vinyl resin. In addition to the above organic materials, organic materials such as benzocyclobutene resins can be used. , low dielectric constant materials (low-k materials), etc. can be used.

[0336] An opening reaching the oxide semiconductor film 403 is formed in the interlayer insulating film 415 and the insulating film 407. A source electrode layer 405a and a drain electrode layer 405b are formed on the source electrode layer 405a. The drain electrode layer 405b is used to connect to other transistors or elements, and various circuits can be constructed. It can be achieved.

[0337] Examples of the conductive film used for the source electrode layer 405a and the drain electrode layer 405b include A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned Metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) In addition, the lower or upper side of a metal film such as Al or Cu may be used. Both are made of high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film A laminated structure of a silicon nitride film, a molybdenum nitride film, and a tungsten nitride film may also be used. The conductive film used for the source electrode layer and the drain electrode layer is formed of a conductive metal oxide. Conductive metal oxides include indium oxide (In2O3) and tin oxide (SnO 2), zinc oxide (ZnO), indium oxide tin oxide (In2O3-SnO2), indium oxide Indium zinc oxide (In2O3-ZnO) or silicon oxide on these metal oxide materials can be used.

[0338] For example, the source electrode layer 405a and the drain electrode layer 405b may be formed of a single molybdenum film. layer, a laminate of a tantalum nitride film and a copper film, or a laminate of a tantalum nitride film and a tungsten film, etc. can be used.

[0339] In order to reduce the number of steps, a part of the exposed low resistance regions 404a and 404b is made amorphous. As another method of the treatment, the source electrode layer 405a and the drain electrode layer 405 When forming the conductive film used in b, sputtering is performed with high power. In this case, a conductive process may be used to partially remove the exposed low resistance regions 404a and 404b. Since the film can be made amorphous by adjusting the film formation conditions, the oxide can be formed without increasing the number of processes. A portion of the semiconductor film can be made amorphous.

[0340] Through the above steps, a semiconductor device including the transistor 440a of this embodiment can be manufactured. (See FIG. 14(E)).

[0341] 15A to 15D, 16A, and 16B, a transistor 440a and are transistors 440b, 440c, 440d, 440e, 440f, Shows 440g.

[0342] In the transistors 440b, 440c, 440d, and 440e, the source electrode layer 405a , and the drain electrode layer 405b are formed on the exposed top surface of the oxide semiconductor film 403 and the sidewall insulating layer Therefore, the source electrode layer 405a or the drain electrode layer 414b is provided in contact with the source electrode layer 405a or the drain electrode layer 414b. amorphous regions 445a and 445b in which the oxide electrode layer 405b and the oxide semiconductor film 403 are in contact with each other; The distance from the gate electrode layer 401 is the width of the sidewall insulating layer in the channel length direction, which allows for further miniaturization. In addition to being achievable, more consistent control over the manufacturing process is possible.

[0343] In this manner, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 The distance between the gate electrode layer 401 and the amorphous regions 445a and 445b, which are in contact with each other, is shortened. Therefore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 40 3 (amorphous regions 445a and 445b) and the resistance between the gate electrode layer 401 The resistance is reduced, improving the on-characteristics of the transistors 440b, 440c, 440d, and 440e. It is possible to do so.

[0344] 15(A) and 15(B), the insulating film 407 is an interlayer insulating film 415, a source electrode layer 405a, the drain electrode layer 405b, the sidewall insulating layers 414a and 414b, and the insulating film 413. It is set up as such.

[0345] In the manufacturing process of the transistors 440b and 440c, a gate electrode layer 401 and an insulating film 41 3, and the conductive film provided on the sidewall insulating layers 414a and 414b is cut (grinded, polished). The conductive film is divided by removing the source electrode layer 405a and the drain electrode layer 405b. The electrode layer 405b is formed. The cutting (grinding, polishing) method is chemical mechanical polishing (Chem The CMP (chemical mechanical polishing) method is preferably used. can be done.

[0346] In the manufacturing process of the transistor 440d, the gate electrode layer 401, the insulating film 413, and the side The conductive film provided on the wall insulating layers 414a and 414b is patterned using a photolithography process. The source electrode layer 405a and the drain electrode layer 405b are formed by etching using a resist mask. This is an example in which the pole layer 405b is formed.

[0347] In the manufacturing process of the transistor 440e, the gate electrode layer 401, the insulating film 413, and the side The conductive film provided on the wall insulating layers 414a and 414b is formed by a photolithography process. The resist mask is gradually etched away to form a source electrode layer 405 4 is an example in which the drain electrode layer 405a and the drain electrode layer 405b are formed.

[0348] In the transistor 440f, a source electrode layer and a drain electrode layer are formed on the gate of the oxide semiconductor film 403. In this example, the insulating film 403 is provided in a region that does not overlap with the oxide semiconductor film 402. Sputtering is performed with high power to form a metal film (aluminum film, titanium film, etc.) The oxide semiconductor film 403 is made amorphous and a metal element is diffused into the oxide semiconductor film 403 by heat treatment. The amorphous region 445a is turned into a resist and functions as a source electrode layer, and the amorphous region 445b is turned into a drain electrode layer. After the amorphous regions 445a and 445b are formed, the gold The metallic membrane is removed.

[0349] The transistor 440g has a structure in which the sidewall insulating layer also includes a barrier film. In this example, an insulating film that is a barrier film is formed so as to cover the insulating film 414b. After that, the insulating film 448 is anisotropically etched to form sidewall insulating layers 414a and 414b. After that, an insulating film is formed as a barrier film, and anisotropic etching is performed on the barrier film to form an insulating film 417. For example, an aluminum film is formed as the barrier film, and the aluminum The insulating film 448 may be doped with oxygen to form an aluminum oxide film. The first layer is anisotropically etched, and the second layer is anisotropically etched to form a transistor. As shown in FIG. 440g, the insulating film 417a is made up of sidewall insulating layers 414a and 414b, and insulating films 417a and 417b. A sidewall insulating layer can be formed.

[0350] As described above, the channel formation region contains crystalline components, and the amorphous region contains a large amount of amorphous components. A semiconductor device including transistors 440a to 440g each including an oxide semiconductor film having a region In the device, stable electrical characteristics can be imparted and high reliability can be achieved.

[0351] To realize high-speed response and high-speed operation of a semiconductor device having a transistor including an oxide semiconductor film A configuration and a method for making the same can be provided.

[0352] (Embodiment 4) In this embodiment, a transistor and a capacitor are manufactured on the same substrate without increasing the number of steps. An example of this will be described below with reference to FIG. 17(A) and FIG. 17(B).

[0353] A transistor can have either a single-gate structure in which one channel formation region is formed or a structure in which two are formed. The gate structure may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. The semiconductor device has two gate electrode layers arranged above and below the channel forming region with a gate insulating film interposed therebetween. A dual gate type may also be used.

[0354] The transistor 420 shown in FIG. 17B is a planar transistor having a top gate structure. This is an example of a transistor.

[0355] The transistor 420 in FIG. 17B has an insulating surface on which a base insulating layer 436 is provided. A channel forming region 409, low resistance regions 404a and 404b, and an amorphous The oxide semiconductor film 403 including the regions 445a and 445b, the source electrode layer 405a, the drain The transistor 42 includes an electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. Insulating films 406 and 407 are formed on the gate electrode layer 401. In the material, the capacitance wiring 450 overlaps with the source electrode layer 405a via the gate insulating film 402, A capacitor 451 is formed with the gate insulating film 402 as a dielectric.

[0356] An example of a method for manufacturing a semiconductor device will be described with reference to FIG. The insulating layer 436 and the oxide semiconductor film 403 having a crystalline component are formed by the same process. A detailed explanation will be omitted.

[0357] After the oxide semiconductor film 403 containing a crystalline component is formed, a source electrode A conductive film is formed to become a drain electrode layer (including a wiring formed in the same layer). The conductive film is a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Or a metal nitride film containing the above-mentioned elements (titanium nitride film, molybdenum nitride film, titanium nitride film, etc.) For example, a tin film or the like can be used.

[0358] Next, a resist mask is formed on the conductive film by a photolithography process, and selectively etched. After etching to form the source electrode layer 405a and the drain electrode layer 405b, The mask is removed.

[0359] Note that when the conductive film is formed by sputtering, the source electrode layer 405a and the drain electrode layer When plasma is used for etching to form 405b, the oxide semiconductor film 403 There is a risk that the surface will become amorphous or that impurities will adhere to it. In that case, The surface is exposed to oxalic acid or dilute hydrofluoric acid, or plasma treatment (such as N2O plasma treatment) is performed. ) to remove the amorphized surface and expose the crystalline components, or to oxidize It is preferable to remove impurities from the surface of the semiconductor film. If exposed to hydrofluoric acid or plasma treatment (such as N2O plasma treatment), The oxide semiconductor film 403 is thinned by the addition of the oxide semiconductor film 403. stomach.

[0360] Next, the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b were A covering gate insulating film 402 is formed.

[0361] Then, the gate electrode layer 401 is formed by plasma CVD or sputtering. The gate insulating film 402 is formed to a thickness of 100 nm (see FIG. 17A). In the case of using such a thin insulating film, planarization treatment may be performed before the gate insulating film 402 is formed. In this embodiment, the capacitance wiring 450 is also made of the same material as the gate electrode layer 401. The gate insulating film 402 is sandwiched between the source electrode layer 405a and the capacitance wiring 450. A capacitor 451 is formed by using a part of the film 402 as a dielectric.

[0362] Next, the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b are formed on a mask. A rare gas or a dopant is introduced into the oxide semiconductor film 403 as a gate insulating film to make the film amorphous. Crystalline regions 445a and 445b are formed.

[0363] The thicknesses of the source electrode layer 405a and the drain electrode layer 405b, the amount of a rare gas or a dopant, Depending on the introduction conditions, the oxide under the source electrode layer 405a and the drain electrode layer 405b may be When a rare gas or a dopant is introduced into the semiconductor film 403, the region where the rare gas or the dopant is introduced becomes amorphous. In some cases, this may be the case.

[0364] By providing the amorphous regions 445a and 445b, water is absorbed in the amorphous regions 445a and 445b. This attracts and fixes the hydrogen in the channel formation region 409, and can remove the hydrogen as much as possible. .

[0365] In this embodiment, the region reaching the interface between the oxide semiconductor film 403 and the base insulating layer 436 is The regions are illustrated as amorphous regions 445a and 445b, but may be formed by introducing a rare gas or a dopant. Depending on the conditions for introducing and amorphizing the rare gas or dopant, it is possible to introduce the rare gas or dopant only near the surface. In some cases, only the upper layer becomes an amorphous region by adding water. This attracts and fixes the hydrogen in the channel formation region 409, and can remove the hydrogen as much as possible. .

[0366] Next, an insulating film 40 is formed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. Form 6.

[0367] Next, a highly dense inorganic insulating film (typically aluminum oxide) is formed on the insulating film 406 as a protective insulating film. An insulating film 407 is formed as a SiO 2 film (see FIG. 17B). In the embodiment, an example in which the insulating films 406 and 407 are stacked is shown, but the present invention is not particularly limited, and the insulating film 406 may be omitted. It may be omitted.

[0368] In order to efficiently introduce the rare gas or dopant, the gate electrode layer 4 is The gate insulating film 402 is etched using the SiO 2 film and the capacitance wiring 450 as a mask to form an oxide semiconductor. A part of the conductive film 403 may be exposed. Then, argon plasma treatment or oxygen plasma treatment is performed to remove the oxide semiconductor film 403 from the exposed portion. may be made amorphous.

[0369] In FIG. 17B, the source electrode layer 405a and the drain electrode layer 405b are The overlapping regions are shown as low resistance regions 404a and 404b, and the channel forming region 40 An amorphous region 445a is provided between the low resistance region 404a and the semiconductor layer 409. An amorphous region 445b is provided between the region 409 and the low resistance region 404b. The hydrogen concentration in the channel formation region 409 and the low resistance region 404 a, the concentration is higher than that of 404b.

[0370] As described above, the channel formation region 409 containing crystalline components and the channel formation region 409 containing a large amount of amorphous components are The transistor 420 includes an oxide semiconductor film having amorphous regions 445a and 445b. In the semiconductor device, stable electrical characteristics can be imparted and high reliability can be achieved. .

[0371] In addition, this embodiment mode can be freely combined with the embodiment mode 2 or 3. For example, in combination with the third embodiment, a sidewall insulating layer may be provided in contact with the side surface of the gate electrode layer. In this case, a sidewall insulating layer is provided in contact with the side surface of the capacitance line 450 .

[0372] (Embodiment 5) In this embodiment, an example of a semiconductor device (memory device) different from that in the first embodiment will be described with reference to the drawings. I will explain this in more detail.

[0373] FIG. 18 shows an example of a configuration of a semiconductor device. FIG. 18A shows a cross-sectional view of the semiconductor device. FIG. 18B shows a plan view of the semiconductor device, and FIG. 18C shows a circuit diagram of the semiconductor device. Here, FIG. 18(A) is a cross-sectional view taken along lines C1-C2 and D1-D2 in FIG. 18(B). Equivalent.

[0374] The semiconductor device shown in FIG. 18(A) and FIG. 18(B) has a transistor using a first semiconductor material in the lower part. A transistor 160 is formed on the upper surface of the semiconductor substrate 10 and a transistor 162 is formed on the upper surface of the semiconductor substrate 10 using a second semiconductor material. The transistor 162 has the same structure as the transistor 420 described in Embodiment 3. Here is an example of its use.

[0375] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0376] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. In the embodiment 1, 2, or 3, an oxide semiconductor is used to hold the In addition to using transistors such as those shown in FIG. It is not necessary to limit the specific configuration of the semiconductor device, such as the structure, to that shown here.

[0377] The transistor 160 in FIG. 18A includes a semiconductor material (e.g., silicon). The channel forming region 116 is provided on the substrate 185 and the channel forming region 116 is sandwiched between the substrate 185 and the The impurity region 120 and the intermetallic compound region 124 in contact with the impurity region 120 are formed as shown in FIG. a gate insulating film 108 provided on the channel forming region 116; and a gate electrode 110 provided on the gate electrode. In some cases, the transistor does not have a gate electrode or drain electrode. In this case, the source is sometimes used to explain the connection relationship of the transistor. The source and drain regions are sometimes referred to as the source electrode and drain electrode. In this specification, the term "source electrode" may include a source region.

[0378] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. Insulating layers 128 and 130 are provided over the transistor 160 .

[0379] The transistor 160 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a read transistor, data can be read at high speed. As a process before forming the transistor 162 and the capacitor 164, The insulating layer covering the transistor 160 is subjected to a CMP process to planarize the insulating layers 128 and 130. At the same time, the upper surface of the gate electrode layer of the transistor 160 is exposed.

[0380] A transistor 162 illustrated in FIG. 18A has a channel formation region formed using an oxide semiconductor. The transistor 162 is a top-gate transistor. The film has a channel forming region where crystalline components are retained, and an amorphous region. The present invention uses an oxide semiconductor in which the hydrogen concentration in the channel formation region is reduced by attracting hydrogen. As a result, the transistor 162 has excellent off-state characteristics.

[0381] Since the off-state current of the transistor 162 is small, the use of the transistor 162 enables long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or Therefore, it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0382] An insulating layer 150 is provided over the transistor 162 as a single layer or a stacked layer. A conductive layer 1 is provided in a region overlapping with the electrode layer 142a of the transistor 162 via the layer 150. 48b, which is formed by the electrode layer 142a, the insulating layer 150, and the conductive layer 148b. That is, the electrode layer 142a of the transistor 162 is The conductive layer 148b functions as one electrode of the capacitor 164. When capacitance is not required, the capacitor 164 is not provided. The capacitor 164 may be provided above the transistor 162. The conductive layer 148b may be formed in the same process as the gate electrode 148a of the transistor 162. It may be formed.

[0383] An insulating layer 152 is provided over the transistor 162 and the capacitor 164. A wiring 156 is provided on the insulating layer 152, and the wiring 156 is connected to a transistor 162. It is provided to connect other transistors. The line 156 is formed through an opening formed in the insulating layer 150, the insulating layer 152, the gate insulating film 146, etc. The electrode is electrically connected to the electrode layer 142b via an electrode formed on the The oxide semiconductor layer 144 of the transistor 162 is provided so as to overlap with at least part of the oxide semiconductor layer 144 of the transistor 162. It is preferred.

[0384] In FIG. 18(A) and FIG. 18(B), a transistor 160 and a transistor 162 are provided so as to overlap at least partially, and the source region of the transistor 160 Alternatively, the drain region and the oxide semiconductor layer 144 are preferably provided so as to partly overlap each other. In addition, the transistor 162 and the capacitor 164 are preferably For example, the conductive layer 148b of the capacitor 164 is , at least a portion of which overlaps with the gate electrode 110 of the transistor 160 . By adopting such a planar layout, it is possible to reduce the area occupied by the semiconductor device. This allows for high integration.

[0385] Next, an example of a circuit configuration corresponding to FIG. 18(A) and FIG. 18(B) is shown in FIG. 18(C).

[0386] In FIG. 18C, the first wiring (1st Line) and the source of the transistor 160 The electrodes are electrically connected to the second wiring (2nd Line) and the transistor 160. The drain electrode is electrically connected. Also, the third wiring (3rd Line) The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode of the fourth transistor 162. The wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected. The gate electrode of the transistor 160 and the source voltage of the transistor 162 are The other of the electrode and drain electrode is electrically connected to one of the electrodes of the capacitor 164. The wiring (5th Line) and the other electrode of the capacitor 164 are electrically connected to each other.

[0387] In the semiconductor device shown in FIG. 18C, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0388] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (write Here, the charges that give two different potential levels (hereafter, low-level charges, H Then, the voltage of the fourth wire is The transistor 162 is turned off by setting the potential at which the transistor 162 is turned off. By this, the charge applied to the gate electrode of the transistor 160 is held (retained). Hold).

[0389] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0390] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the electrode, the second wire takes on a different potential. If the transistor 160 is an n-channel type, a high level voltage is applied to the gate electrode of the transistor 160. Apparent threshold V when a load is applied th_H is the gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the electrode th_L Lower Here, the apparent threshold voltage is the voltage at which transistor 160 is turned on. This refers to the potential of the fifth wiring required to achieve this. Therefore, the potential of the fifth wiring V th_H and V th_L By setting the potential V0 between For example, in writing, a high level charge is given, the potential of the fifth wire is V0 (> V th_H ) Then, Tran When a low level charge is applied, the fifth resistor 160 is in the "ON state." The potential of the wiring is V0( <V th_L ) transistor 160 is in the "off state" Therefore, the stored data can be read by checking the potential of the second wiring. It is possible.

[0391] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential at which transistor 160 is in the “off state,” i.e., V th_H Yo Alternatively, a potential smaller than the potential of the gate electrode may be applied to the fifth wiring. The potential at which the resistor 160 is in the "on" state, i.e., V th_L The larger potential is Just give it to wiring number 5.

[0392] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. This makes it possible to reduce the frequency of the power consumption significantly. In addition, even if there is no power supply (although it is preferable that the potential is fixed), Even if the memory is changed, the stored contents can be retained for a long period of time.

[0393] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0394] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0395] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0396] (Embodiment 6) In this embodiment mode, one mode of a structure of a memory device different from that in Embodiment 5 will be described.

[0397] FIG. 19 is a perspective view of a storage device. The storage device shown in FIG. A memory cell array (memory cell array 3400a to memory cell array 3400b) including a plurality of recells. The memory cell array 3400a is disposed at the bottom of the memory cell array 3400n. It has logic circuits 3004 required for operating the memory cell array 3400n.

[0398] In FIG. 19, a logic circuit 3004, a memory cell array 3400a, and a memory cell array 34 00b is illustrated, and the memory cell array 3400a or the memory cell array 3400b is illustrated. Among the multiple memory cells included, the memory cell 3170a and the memory cell 3170b are replaced. The table shows the memory cells 3170a and 3170b. Alternatively, the circuit configuration may be the same as that described in the previous embodiment.

[0399] In addition, in FIG. 20, a transistor 3171a included in a memory cell 3170a is shown as a representative. The transistor 3171b included in the memory cell 3170b is shown as a representative. The transistor 3171a and the transistor 3171b each have a channel formation region in an oxide semiconductor film. The structure of a transistor in which a channel formation region is formed in an oxide semiconductor film is as described below. Since the configuration is the same as that described in any one of the first to third embodiments, the description thereof will be omitted.

[0400] The electrode 3501a formed in the same layer as the gate electrode layer of the transistor 3171a is The transistor 3171b is electrically connected to the electrode 3003a via 502a. The electrode 3501c formed in the same layer as the gate electrode layer is connected to the electrode 3502c. It is electrically connected to 3003c.

[0401] In addition, the logic circuit 3004 uses a semiconductor material other than an oxide semiconductor for a channel formation region. The transistor 3001 is made of a semiconductor material (e.g., An element isolation insulating layer 3106 is provided on a substrate 3000 including silicon, and the element isolation insulating layer 31 The transistor obtained by forming a region to be a channel formation region in the region surrounded by 06. The transistor 3001 can be formed on an insulating surface. A channel formation region is formed in a semiconductor film such as a polycrystalline silicon film or a silicon film of an SOI substrate. The transistor 3001 may be a known transistor. can be used, so the explanation will be omitted.

[0402] Between a layer in which the transistor 3171a is formed and a layer in which the transistor 3001 is formed The wiring 3100a and the wiring 3100b are formed on the transistor. An insulating film 3140a is provided between the layer on which the sta 3001 is formed, and the wiring 3100a An insulating film 3141a is provided between the wiring 3100b and the transistor. An insulating film 3142a is provided between the layer on which the stanchion 3171a is formed.

[0403] Similarly, a layer in which the transistor 3171b is formed and a layer in which the transistor 3171a is formed Between the layers, a wiring 3100c and a wiring 3100d are formed. An insulating film 3140b is provided between the layer in which the transistor 3171a is formed and the An insulating film 3141b is provided between the line 3100c and the wiring 3100d. An insulating film 3142b is provided between the layer in which the transistor 3171b is formed and the layer in which the transistor 3171b is formed. There are.

[0404] Insulating film 3140a, insulating film 3141a, insulating film 3142a, insulating film 3140b, insulating film 3 The insulating film 3142b functions as an interlayer insulating film and has a flattened surface. It can be said that:

[0405] The wiring 3100a, the wiring 3100b, the wiring 3100c, and the wiring 3100d form a memory cell. The electrical connection between the logic circuit 3004 and the memory cell can be performed. do.

[0406] The electrode 3303 included in the logic circuit 3004 is electrically connected to the circuit provided above. It is possible.

[0407] For example, as shown in FIG. 20, the electrode 3505 connects the electrode 3303 to the wiring 3100a. The wiring 3100a can be electrically connected to the transistor by the electrode 3503a. The gate electrode layer of the electrode 3171a is electrically connected to the electrode 3501b formed in the same layer. In this manner, the wiring 3100a and the electrode 3303 are connected to the The electrode 3501b can be electrically connected to the source or drain. The source or drain of the transistor 3171a and the electrode 3502b form a Electrode 3003b can be electrically connected to electrode 3503b. 3100c.

[0408] In FIG. 20, the electrode 3303 and the transistor 3171a are electrically connected to each other through the wiring 3100a. However, this is not limited to the above example. The electrical connection with the wiring 3100a may be made via the wiring 3100b, or the wiring 3100a and the wiring 3100b may be made via the wiring 3100c. Alternatively, the signal may be transmitted through both the wiring 3100a and the wiring 3100b. Alternatively, the measurement may be performed using other electrodes without using any electrodes.

[0409] In addition, in FIG. 20, a layer in which the transistor 3171a is formed and a layer in which the transistor 3001 is formed are Between the layers, a wiring layer in which a wiring 3100a is formed and a wiring 3100b are formed. In the above embodiment, two wiring layers are provided, but the present invention is not limited to this. Between the layer in which the transistor 3171a is formed and the layer in which the transistor 3001 is formed, One wiring layer may be provided, or three or more wiring layers may be provided.

[0410] In addition, in FIG. 20, a layer in which the transistor 3171b is formed and a layer in which the transistor 3171a is formed are Between the layer in which the wiring 3100c is formed and the layer in which the wiring 3100d is formed, The present invention is not limited to a configuration in which two wiring layers are provided, but the present invention is not limited to this. Between the layer in which the transistor 3171b is formed and the layer in which the transistor 3171a is formed In the above embodiment, one wiring layer may be provided, or three or more wiring layers may be provided. .

[0411] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0412] (Embodiment 7) In this embodiment, as an example of a semiconductor device, a semiconductor device according to any one of the second to fourth embodiments will be described. A CPU (Central Processor) that uses at least one of the transistors shown This article explains the "Input Unit".

[0413] FIG. 21(A) is a block diagram showing a specific configuration of a CPU. The PU is provided on a substrate 1190 with an ALU 1191 (ALU: Arithmetic logic c unit, arithmetic logic unit), ALU controller 1192, instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, A register 1196, a register controller 1197, and a bus interface (Bus I / F)1198, rewritable ROM1199, and ROM interface (ROM The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 are provided on separate chips. Of course, the CPU shown in FIG. 21(A) is an example showing a simplified configuration. However, actual CPUs have a wide variety of configurations depending on their applications.

[0414] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0415] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0416] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by the internal clock generator 100. Supply to the seed circuit.

[0417] In the CPU shown in FIG. 21A, a register 1196 is provided with a memory cell. The memory cell of the register 1196 may be the memory cell disclosed in the fifth embodiment. can be done.

[0418] In the CPU shown in FIG. 21A, the register controller 1197 controls the ALU 1191. The holding operation in the register 1196 is selected according to the instruction from the register. In the memory cell of the data storage device 1196, a logic element that inverts the logic holds data. The logic element that inverts the logic is selected to hold the data by the capacitance element. If the data retention by the register is selected, the memory cell in the register 1196 is When data retention is selected in the capacitive element, the capacitive element is supplied with a power supply voltage. The data in the register 1196 is rewritten, and the power supply voltage is supplied to the memory cell in the register 1196. can be stopped.

[0419] Regarding the power supply shutdown, as shown in FIG. 21(B) or FIG. 21(C), A switching element is connected between the nodes to which the power supply potential VDD or VSS is applied. The circuit shown in FIG. 21(B) and FIG. 21(C) will be described below. Do the following.

[0420] In FIG. 21B and FIG. 21C, a switch for controlling the supply of a power supply potential to a memory cell The switching element includes a memory circuit including a transistor disclosed in any one of the second to fourth embodiments. 1 shows an example of a path configuration.

[0421] The memory device shown in FIG. 21B includes a switching element 1141 and a memory cell 1142. Specifically, each memory cell 1142 has: The memory cells described in the fifth embodiment can be used. A high level is applied to each memory cell 1142 via a switching element 1141. A power supply potential VDD is supplied to the memory cell group 1143. The potential of the signal IN and the potential of the low-level power supply potential VSS are applied to 1142. .

[0422] In FIG. 21B, the switching element 1141 is a semiconductor device having a structure similar to that described in any one of the above-described embodiments 2 to 4. The transistor disclosed in the above publication has a gate electrode provided with The switching is controlled by the signal SigA.

[0423] In FIG. 21B, the switching element 1141 has only one transistor. However, there is no particular limitation and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0424] In FIG. 21B, a memory cell group 1143 is enabled by a switching element 1141. The supply of a high-level power supply potential VDD to each memory cell 1142 is controlled. The supply of the low-level power supply potential VSS is controlled by the switching element 1141. This is also fine.

[0425] In addition, in FIG. 21C, each memory cell 1142 included in the memory cell group 1143 is A low-level power supply potential VSS is supplied to the memory device through a switching element 1141. The switching element 1141 switches each memory cell in the memory cell group 1143. The supply of a low-level power supply potential VSS to the memory cell 1142 can be controlled.

[0426] A switch is provided between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied. When a switching element is installed to temporarily stop the CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer inputs information to an input device such as a keyboard. You can stop the CPU from operating while you are no longer entering information, which reduces power consumption. Power consumption can be reduced.

[0427] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor). processor), custom LSI, FPGA (Field Programmable Gauge It can also be applied to LSIs such as MOSFET's (MOSFET gate arrays).

[0428] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0429] (Embodiment 8) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic devices include televisions, monitors and other display devices, lighting devices, desktop Or notebook type personal computer, word processor, DVD (Digital Playing still or moving images stored on a recording medium such as a Versatile Disc image reproducing devices, portable CD players, radios, tape recorders, headphone stereos Audio, stereos, cordless telephone handsets, transceivers, portable radios, mobile phones, car phones , portable game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translators, voice input devices appliances, video cameras, digital still cameras, electric shavers, microwave ovens and other high-frequency heating equipment Electric rice cookers, electric washing machines, vacuum cleaners, air conditioners and other air conditioning equipment, tableware Washing machines, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerators These include medical equipment such as refrigerators, freezers for storing DNA, smoke detectors, radiation detectors, and dialysis machines. In addition, it is used in emergency exit lights, traffic lights, conveyor belts, elevators, escalators, industrial Examples include industrial equipment such as robots and power storage systems. In addition, oil-based engines and Vehicles propelled by electric motors using power from non-aqueous secondary batteries are also included in the category of electrical equipment. The above-mentioned moving body includes, for example, an electric vehicle (EV), an internal combustion engine, and Hybrid electric vehicles (HEV) and plug-in hybrid electric vehicles (PHEV) These tires and wheels are converted into tracks, and motorized vehicles including electric-assisted bicycles Bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters Examples of spacecraft include microcomputers, aircraft, rockets, satellites, space probes, interplanetary rovers, and spacecraft. Specific examples of these electronic devices are shown in FIG.

[0430] FIG. 22A shows a table 9000 having a display section. The table 9000 includes: A display unit 9003 is incorporated in a housing 9001, and an image is displayed on the display unit 9003. In addition, the configuration in which the housing 9001 is supported by four legs 9002 is shown. The housing 9001 also includes a power cord 9005 for power supply.

[0431] The transistor described in any of Embodiments 1 to 3 can be used in the display portion 9003. This makes it possible to provide high reliability to electronic devices.

[0432] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, making the screen It may also be used as a control device to control other home appliances by operation. For example, an image sensor If a semiconductor device having a sensor function is used, the display portion 9003 can have a touch input function. This can be done.

[0433] In addition, the screen of the display unit 9003 can be vertically supported on the floor by a hinge provided on the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrowed, but if you put it on a table, If the display unit is built in, the space in the room can be used more effectively.

[0434] FIG. 22(B) shows a portable music player. The main body 3021 has a display unit 3023 and an earphone. A fixing part 3022 for mounting, a speaker, an operation button 3024, and an external memory slot 3025 and the like are provided. The transistors according to the second to fourth embodiments or the The memory shown in form 5 is applied to the memory or CPU built into the main body 3021. This makes it possible to provide a portable music player with even lower power consumption.

[0435] Furthermore, the portable music player shown in FIG. 22(B) has an antenna, a microphone function, and a wireless function. In addition, by linking it with a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversation by telephone is also possible.

[0436] FIG. 22C shows a computer, which includes a main body 9201 including a CPU, a housing 9202, a display unit 9203, keyboard 9204, external connection port 9205, pointing device 92 The computer can generate a transistor manufactured using one embodiment of the present invention. The display unit 9203 is manufactured by using the CPU shown in the seventh embodiment. This makes it possible to realize a computer with reduced power consumption.

[0437] Figures 23(A) and 23(B) show tablet terminals that can be folded in half. 9 shows the tablet terminal in an open state. The tablet terminal includes a housing 9630, a display unit 9631a, and a display unit 9631b, display mode switch 9034, power switch 9035, power saving mode It has a mode changeover switch 9036, a fastener 9033, and an operation switch 9038.

[0438] In the portable devices shown in FIG. 23(A) and FIG. 23(B), image data is temporarily stored. For example, in the fifth embodiment, SRAM or DRAM is used as a memory. Alternatively, the semiconductor device described in the sixth embodiment can be used as a memory. By adopting the semiconductor device described in the embodiment as a memory, writing and It has high-speed readout, long-term memory retention, and low power consumption. Cut.

[0439] In addition, a part of the display unit 9631a can be used as a touch panel area 9632a. Data can be input by touching the indicated operation keys 9638. The transistor described in any one of the above to 3 can be used for the display portion 9631a and the display portion 9631b. In the display unit 9631a, for example, half of the area is only for display. The other half of the area has a touch panel function. The present invention is not limited to this configuration. The entire area of ​​the display unit 9631a may have a touch panel function. For example, a keyboard may be displayed on the entire surface of the display portion 9631a, and the keyboard may be touched. The display portion 9631b can be used as a display screen.

[0440] In addition, in the display unit 9631b, as in the display unit 9631a, The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard button can be displayed on the display portion 9631b.

[0441] In addition, the touch panel area 9632a and the touch panel area 9632b can be touched simultaneously. You can also input the character.

[0442] A display mode changeover switch 9034 is used to change the display orientation between portrait and landscape. You can switch between black and white and color display. The 9036 tablet device is equipped with a light sensor that detects external light during use. The display brightness can be optimized according to the amount of light. In addition, it also incorporates other detection devices such as gyros, acceleration sensors, and other sensors that detect tilt. It may be stored.

[0443] FIG. 23A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. For example, one display panel may have a higher resolution than the other. It is also possible to use the following.

[0444] FIG. 23B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 96 33, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636 In addition, in FIG. 23B, a battery 9635 is used as an example of the charge / discharge control circuit 9634. , a configuration having a DC-DC converter 9636 is shown.

[0445] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the durability can be improved. This makes it possible to provide a tablet terminal that is highly durable and reliable even for long-term use.

[0446] In addition, the tablet terminals shown in Figs. 23(A) and 23(B) can store various information. Functions for displaying information (still images, videos, text images, etc.), calendars, dates, or times, etc. A function to display information on the display unit, and a function to operate or edit the information displayed on the display unit by touch input. It has the function of inputting information, the function of controlling processing by various software (programs), etc. This can be done.

[0447] The solar cell 9633 attached to the surface of the tablet device supplies power to the touch panel, The solar cell 9633 can be provided to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by providing a light emitting diode (LED) on one or both sides of the body 9630. The battery 9635 may be a lithium-ion battery. The use of such a structure has the advantage of enabling miniaturization.

[0448] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. ) shows a block diagram and explains the device. In FIG. 23(C), a solar cell 9633, a battery 96 35, DC-DC converter 9636, converter 9637, switches SW1 to SW3, The figure shows a display unit 9631, a battery 9635, and a DC-DC converter 9636. The converter 9637 and the switches SW1 to SW3 constitute a charge / discharge control circuit shown in FIG. This corresponds to route 9634.

[0449] First, an example of operation in which power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is converted to a DCD voltage to charge the Battery 9635. The voltage is increased or decreased by the C converter 9636. When power is being used from the battery 9633, the switch SW1 is turned on and the converter 96 37 increases or decreases the voltage to a voltage required for the display unit 9631. When not displaying the 31, turn SW1 off and SW2 on to charge the battery 96 The configuration may be such that charging is performed at 35.

[0450] The solar cell 9633 is shown as an example of a power generating means, but is not limited thereto. Batteries using other power generation methods such as piezoelectric elements and thermoelectric conversion elements For example, the device may be configured to transmit and receive power wirelessly (contactlessly). A non-contact power transmission module that charges by connecting the battery to the power source, or a combination of other charging methods. It is also possible to use the following.

[0451] In FIG. 24A, a television device 8000 includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs audio from a speaker unit 8003. The transistor described in any one of Embodiments 1 to 4 can be used to output a signal. It can be used for the display portion 8002 .

[0452] The display unit 8002 is a light-emitting device having light-emitting elements such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Device e) and PDP (Plasma Display Panel), It can be used.

[0453] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver and also has a modem. By connecting to a wired or wireless communication network via to communicate information to a single person (i.e., a single person), or two-way (i.e., between a sender and a receiver, or between receivers themselves) It is also possible.

[0454] The television device 8000 also includes a CPU and a memory for performing information communication. The television device 8000 may include the memory or the like described in any one of the fifth to seventh embodiments. It is possible to use a CPU.

[0455] In FIG. 24A, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is shown. The indoor unit 8200 is an example of an electronic device using the CPU of the seventh embodiment. The electronic device includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. In the illustrated example, the CPU 8203 is provided in the indoor unit 8200. 203 may be provided in the outdoor unit 8204. Alternatively, the indoor unit 8200 and the outdoor unit 82 The CPU 8203 may be provided in both the CPU 8204 and the CPU 8205. Because the CPU uses oxide semiconductors, it has excellent heat resistance and is a highly reliable air conditioner. A conditioner can be realized.

[0456] In FIG. 24A, an electric refrigerator-freezer 8300 includes a CPU using an oxide semiconductor. Specifically, an electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator compartment, 24(A), C The PU 8304 is provided inside the housing 8301. By using it for the CPU 8304 of an electric refrigerator-freezer 8300, power saving can be achieved.

[0457] FIG. 24B shows an example of an electric vehicle, which is an example of an electronic device. The power of the secondary battery 9701 is supplied to the control circuit 97 The output is adjusted by the control circuit 9702 and supplied to the driving device 9703. It is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). By using the CPU shown in the seventh embodiment as the CPU of the electric vehicle 9700, power saving can be achieved. It can be planned.

[0458] The driving device 9703 is a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 is configured in combination with the electric vehicle 9700. (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., load on the drive wheels) Based on input information (such as shipment information), the control circuit 9702 outputs a control signal. 702 is a secondary battery 9701 supplied with electric energy by a control signal from a processing device 9704. It adjusts the energy and controls the output of the drive unit 9703. Although not shown, an inverter for converting direct current to alternating current is also built in.

[0459] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0460] 1 Gate Layer 2 Gate insulation layer 3. Oxide semiconductor layer 4. Source electrode layer 5. Drain electrode layer 6 Etch stop layer 7 areas 8 areas 100 Substrates 106 Element isolation insulating layer 108 Gate insulating film 110 Gate electrode 116 Channel formation region 120 Impurity region 124 Intermetallic compound area 128 Insulating Layer 130 Insulating layer 142a Electrode layer 142b Electrode layer 144 Oxide semiconductor layer 146 Gate insulating film 148a Gate electrode 148b Conductive layer 150 Insulating layer 152 Insulating layer 156 Wiring 160 Transistors 162 Transistor 164 Capacitive element 185 Substrate 400 Substrates 401 Gate electrode layer 402 Gate insulating film 403 Oxide Semiconductor Film 404a Low resistance area 404b Low resistance region 405a Source electrode layer 405b Drain electrode layer 406 Insulating film 407 Insulating Film 409 Channel formation region 410 Transistor 413 Insulating film 414a Sidewall insulating layer 414b Sidewall insulating layer 415 Interlayer insulating film 417a Insulating film 417b Insulating film 420 Transistor 436 Undercoat insulation layer 440a transistor 440b transistor 440c transistor 440d transistor 440e transistor 440f transistor 440g transistor 442 Gate insulating film 445a Amorphous region 445b Amorphous region 448 Insulating Film 450 capacitance wiring 451 capacity 500 boards 502 Gate insulation layer 504 Interlayer insulation layer 505 Color filter layer 506 Insulating layer 507 Bulkhead 510 Transistor 511 Gate Layer 512 Oxide semiconductor layer 513a conductive layer 513b Conductive layer 520 Capacitive element 521 Conductive Layer 522 Oxide semiconductor layer 523 Conductive Layer 530 Wiring layer intersection 533 Conductive Layer 540 Light emitting element 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 622 light 631 Insulating layer 633 Interlayer Insulation Layer 634 Interlayer insulation layer 640 Transistor 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photosensor reference signal line 1141 Switching element 1142 Memory Cell 1143 Memory Cell Group 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 3000 boards 3001 Transistor 3003a electrode 3003b electrode 3003c electrode 3004 Logic Circuit 3021 Main unit 3022 Fixed part 3023 Display section 3024 Operation button 3025 External Memory Slot 3100a Wiring 3100b Wiring 3100c Wiring 3100d wiring 3106 Element isolation insulating layer 3140a Insulating film 3140b Insulating film 3141a Insulating film 3141b Insulating film 3142a Insulating film 3142b Insulating film 3170a Memory Cell 3170b memory cell 3171a Transistor 3171b Transistor 3200 Transistors 3202 Transistor 3204 Capacitive element 3208 Electrode 3210a conductive layer 3210b conductive layer 3212 Electrode 3214 Electrode 3216 Wiring 3220 Insulating layer 3222 Insulating layer 3224 Insulating layer 3303 Electrode 3400a Memory Cell Array 3400b memory cell array 3400n memory cell array 3501a electrode 3501b electrode 3501c electrode 3502a electrode 3502b electrode 3502c electrode 3503a electrode 3503b electrode 3505 Electrode 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4018a FPC(Flexible printed circuit) 4018b FPC(Flexible printed circuit) 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Insulation layer 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light emitting element 4514 Filling material 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9000 Table 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fastener 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9201 Main unit 9202 Case 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing Device 9630 Case 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / discharge control circuit 9635 Battery 9636 DC-DC Converter 9637 Converter 9638 Operation key 9639 Button 9700 Electric Vehicle 9701 Secondary battery 9702 Control circuit 9703 Drive unit 9704 Processing Equipment

Claims

[Claim 1] A gate layer; a gate insulating layer provided on the gate layer; an oxide semiconductor layer provided on the gate insulating layer; a source electrode layer and a drain electrode layer provided in regions isolated from each other over the oxide semiconductor layer; an etching stop layer provided in a region on the oxide semiconductor layer and between the source electrode layer and the drain electrode layer; a first region of the oxide semiconductor layer overlapping with an interface with the etching stop layer has a higher ratio of a crystalline region than a second region of the oxide semiconductor layer overlapping with an interface with the source electrode layer or the drain electrode layer.

Images