Semiconductor device

Abstract

To suppress deterioration of transistors.SOLUTION: An embodiment of the invention includes a first period and a second period. In the first period, a first transistor and a second transistor are alternately and repeatedly turned on and off, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off and the third transistor and the fourth transistor are alternately and repeatedly turned on and off. Thus, since the period during which the transistors are turned on can be shortened, characteristics degradation of the transistors is suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device and a display device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a liquid crystal display device, a driving method thereof, or the semiconductor device and the display device. or an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on a substrate is expected to contribute greatly to reducing costs and improving reliability. Development is underway actively to contribute significantly to the

[0003] A transistor formed of a non-single crystal semiconductor has an increased threshold voltage or a decreased mobility. As this transistor degradation progresses, the driver circuit becomes less operable. Therefore, there is a problem that the image cannot be displayed. Patent Document 1 discloses a shift register that can suppress deterioration of transistors. In these documents, in order to suppress the deterioration of the transistor characteristics, These two transistors are connected to the output terminal of the flip-flop and to VSS (hereinafter referred to as a negative power supply) is connected between the first transistor and the second transistor. The other transistor is turned on alternately. This allows the transistor to be turned on Since the time during which the transistor becomes in this state is shortened, deterioration of the transistor characteristics can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-50502 A [Patent Document 2] JP 2006-24350 A [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, p.333-336 Summary of the Invention [Problem to be solved by the invention]

[0006] In conventional technology, the time that a transistor is on is approximately half of one frame period. Alternatively, the transistors may be degraded so that the shift register can still function. The channel width of the transistor needs to be increased. When this happens, the gate of the transistor and the source or drain may easily short out. Alternatively, if the channel width of the transistor becomes larger, each of the transistors constituting the shift register The parasitic capacitance of the transistor increases. When the parasitic capacitance of the shift register increases, the circuit that supplies signals or voltages to the shift register Therefore, it is necessary to use a circuit having a large current capability.

[0007] In view of the above problems, an object of one embodiment of the present invention is to shorten the time during which a transistor is on. Another object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. Another object of one embodiment of the present invention is to reduce the channel width of a transistor. Another object of one embodiment of the present invention is to reduce the layout area. Another object of one embodiment of the present invention is to narrow the frame of a display device. Another object of one embodiment of the present invention is to provide a display device with high resolution. Another object of the present invention is to reduce costs. Another object of one embodiment of the present invention is to reduce distortion or delay of a signal. Another object of one embodiment of the present invention is to reduce power consumption. An object of one embodiment of the present invention is to reduce the current capacity of an external circuit. An embodiment is to reduce the size of an external circuit or the size of a display device having the external circuit. The objectives of the present invention are to provide a method for solving the above problems. Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not necessarily solve all of the above problems. [Means for solving the problem]

[0008] One aspect of the present invention is a first switch electrically connected between a first wiring and a second wiring. a second switch electrically connected between the first wiring and the second wiring; a third switch electrically connected between the first wiring and the second wiring; a fourth switch electrically connected between the first and second electrodes; and a pixel including a liquid crystal element. A method for driving a liquid crystal display device having a first switch and a second switch that are turned off a first period in which the third switch and the fourth switch are in a non-conducting state; and a driving method for a liquid crystal display device having the period.

[0009] In one embodiment of the present invention, the first period and the second period are repeated in sequence. It is also possible.

[0010] In one embodiment of the present invention, the first period and the second period may be approximately equal in length. good.

[0011] One aspect of the present invention is a first switch electrically connected between a first wiring and a second wiring. a second switch electrically connected between the first wiring and the second wiring; a third switch electrically connected between the first wiring and the second wiring; a fourth switch electrically connected between the first and second electrodes; and a pixel including a liquid crystal element. A method for driving a liquid crystal display device having a first switch, a second switch, a third switch, a first sub-period in which the first switch is in a conductive state, and a fourth switch is in a non-conductive state; a second switch that is in a non-conducting state, and a third switch that is in a non-conducting state, In the sub-period, the second switch is in a conductive state, and the first switch, the third switch, and a first sub-period in which the first switch is turned on and a fourth switch is turned off; a fourth switch that makes the first switch, the second switch, the third switch, and the fourth switch non-conductive; During the sub-period, the third switch is in a conductive state, and the first switch, the second switch, and In the fifth subperiod, the fourth switch is in a non-conducting state, the fourth switch is in a conducting state, and the first a sixth sub-period in which the first switch, the second switch, and the third switch are in a non-conducting state; and a second period having a first period.

[0012] In one embodiment of the present invention, the first period and the second period are repeated in sequence. It is also possible.

[0013] In one embodiment of the invention, the first period and the second period are approximately equal in length. Good too.

[0014] In one embodiment of the present invention, the first sub-period and the second sub-period are repeated in sequence. The fourth sub-period and the fifth sub-period may be repeated in sequence.

[0015] In one embodiment of the present invention, a first sub-period, a second sub-period, a third sub-period, and a third sub-period are included. The fourth sub-period, the fifth sub-period, and the sixth sub-period are approximately equal in length. Good too.

[0016] The switch may be of various types. For example, an electrical switch may be used. In other words, anything that can control the flow of electric current is acceptable. For example, a transistor (e.g., a bipolar transistor) may be used as a switch. transistors, MOS transistors, etc.), diodes (e.g. PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal diode, MIS (Metal Insulator Semiconductor) conductor diodes, diode-connected transistors, etc. Alternatively, a logic circuit that combines these can be used as a switch.

[0017] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode causes Thus, the device operates by controlling conduction and non-conduction.

[0018] In addition, both N-channel and P-channel transistors are used to realize a CMO An S-type switch may be used as the switch.

[0019] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits, etc.). Therefore, a given connection relationship is For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be modified in any manner without departing from the spirit or scope of the present invention. This also includes things other than relationships.

[0020] For example, if A and B are electrically connected, the following can be considered: The elements that function as One or more diodes (e.g., anode, diode, etc.) may be connected between A and B. Alternatively, When A and B are functionally connected, a circuit (e.g. For example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits , step-down circuits, level shifter circuits that change the potential level of signals, voltage sources, current sources , switching circuits, amplification circuits (circuits that can increase the signal amplitude or current, etc., operational amplifiers , differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, One or more control circuits may be connected between A and B. For example, If the signal output from A is transmitted to B, even if there is another circuit between them, then A and B are considered to be are considered to be functionally connected.

[0021] In addition, when it is explicitly stated that A and B are electrically connected, it means that A and B are electrically When A and B are electrically connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is no connection between A and B) and B is functionally connected (i.e., there is no connection between A and B). When A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when it is explicitly stated that something is electrically connected, it should simply be " is the same as if it were expressly stated only that the

[0022] In addition, a display element, a display device which is a device having a display element, a light-emitting element, The light-emitting device can have a variety of configurations and elements. For example, the display element, display device, light-emitting element, or light-emitting device may be an EL (electroluminescent EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, graphene Rating light bulbs (GLV), plasma displays (PDP), digital microphones Chroma mirror device (DMD), piezoelectric ceramic display, carbon nanotube, Displays whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects. The display device using the EL element may be an EL display. As a display device using electron emission elements, a field emission display (FED) ) and SED type flat panel displays (SED: Surface-conduction Display devices using liquid crystal elements such as LCDs and LCD displays (transmissive LCDs, semi-transmissive LCDs, reflective LCDs) LCDs, direct-view LCDs, projection LCDs), electronic inks, An example of a display device using an electrophoretic element is electronic paper.

[0023] The liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. It is an element that consists of a pair of electrodes and liquid crystal. The optical modulation action of liquid crystal is as follows: Controlled by the electric field applied to the liquid crystal (including the horizontal electric field, vertical electric field, or diagonal electric field) The liquid crystal element is a nematic liquid crystal, a cholesteric liquid crystal, a smectic liquid crystal, Liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal , polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal Side-chain polymer liquid crystals, plasma-addressed liquid crystals (PALC), banana-shaped liquid crystals, etc. The liquid crystal driving method is Twisted Nematic (TN) mode. mode, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, MVA (Multi-domain Vertical Ali gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) mode, ECB (Electrically Controlled Birefring ngence) mode, FLC (Ferroelectric Liquid Crys tal) mode, AFLC(AntiFerroelectric Liquid Cr ystal) mode, PDLC (Polymer Dispersed Liquid Crystal mode, guest host mode, Blue Phase mode However, the present invention is not limited to this, and the liquid crystal element and its driving method can be used. A variety of different types of filters can be used.

[0024] Note that various types of transistors can be used. There is no limitation on the type of transistor to be used. For example, amorphous silicon, polycrystalline silicon, Microcrystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) silicon The use of thin film transistors (TFTs) having non-single crystal semiconductor films, such as is possible.

[0025] In addition, by using a catalyst (such as nickel) when producing polycrystalline silicon, It is possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. When manufacturing microcrystalline silicon, a catalyst (such as nickel) is used to make the crystals This will further improve the properties of the material, making it possible to manufacture transistors with excellent electrical properties. It is not possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel). It is possible.

[0026] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline can improve the overall panel quality. It is preferable to perform the process on the whole body, but it is not limited to this. The crystallinity of the polymer may be improved.

[0027] Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like.

[0028] Or ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO , TiO, AlZnSnO (AZTO), or other compound semiconductors or oxide semiconductors Transistors and thin-film transistors made of these compound semiconductors or oxide semiconductors In addition, these compound semiconductors or oxide semiconductors can be used. It can be used not only for the channel part of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistor elements, pixel electrodes, transparent Furthermore, they can be formed simultaneously with the transistor or can be formed, thereby reducing costs.

[0029] Alternatively, transistors formed by inkjet or printing methods can be used. come.

[0030] Alternatively, transistors having organic semiconductors or carbon nanotubes can be used. This makes it possible to form transistors on a flexible substrate. A semiconductor device using such a substrate can be made resistant to shocks.

[0031] Furthermore, transistors of various structures can be used. For example, MOS transistors Transistors such as junction transistors and bipolar transistors can be used as transistors. It is possible to do this.

[0032] In addition, MOS transistors, bipolar transistors, etc. can be mixed on one substrate. It may be formed.

[0033] In addition, various other transistors can be used.

[0034] Note that the transistor can be formed using various substrates. The substrate is not limited to a specific one. For example, the substrate may be a single crystal substrate (e.g., silicon substrate), SOI substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless less steel substrate, substrate with stainless steel foil, tungsten substrate, tungsten A substrate having a stainless steel foil, a flexible substrate, etc. can be used. Examples include barium borosilicate glass, aluminoborosilicate glass, etc. Examples of the substrate include polyethylene terephthalate (PET) and polyethylene naphthalate. Plastics such as polyethersulfone (PEN) and polyethersulfone (PES), or acrylics Other examples include laminated films (polypropylene, etc.) Polyethylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), including fibrous materials Paper, base film (polyester, polyamide, polyimide, inorganic deposition film, paper Or, a transistor is formed using one substrate, and then transferred to another substrate. The transistors may be transposed and placed on a different substrate. The substrates that can be placed on the device include single crystal substrates, SOI substrates, glass substrates, quartz substrates, and plastic substrates. Substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, hemp) , synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, Cupra, rayon, recycled polyester, etc.), leather substrate, rubber substrate, stainless steel A substrate made of stainless steel, a substrate made of stainless steel foil, etc. can be used. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of an animal, such as a human, may be used as the substrate. Alternatively, a substrate may be used to form the transistors, and the substrate may be polished to make it thinner. The substrates to be polished include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, etc. The substrates used are stainless steel substrates, stainless steel foil substrates, etc. By using these substrates, it is possible to form transistors with good characteristics and to Formation of low-power transistors, manufacture of durable devices, imparting heat resistance, weight reduction, It is possible to achieve a thinner design.

[0035] The structure of the transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes can be applied.

[0036] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. In addition, by arranging gate electrodes above and below the channel, multiple transistors can be formed. The configuration is like that of transistors connected in parallel.

[0037] A structure in which a gate electrode is disposed above a channel region, and a structure in which a gate electrode is disposed below a channel region The structure in which the channel region is divided into multiple regions is called the normal staggered structure. a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series In addition, a source electrode and a drain electrode are provided in the channel region (or a part of it). A structure in which the two are overlapped can also be applied.

[0038] Note that various types of transistors can be used and can be formed using various substrates. Therefore, all the circuits required to realize a given function can be implemented simultaneously. For example, the circuit required to realize a specific function may be formed on a single substrate. All of the circuits are mounted on various substrates such as glass, plastic, single crystal, or SOI. Alternatively, the substrate may be formed using a material necessary for realizing a desired function. A part of the circuitry required to realize a certain function is formed on a substrate. It is also possible that a part of the semiconductor device is formed on a separate substrate. All of the circuits required for the above-mentioned purpose do not necessarily have to be formed using the same substrate. Some of the circuits required to realize the above functions are formed by transistors on a glass substrate. Another part of the circuitry required to realize a predetermined function is formed on the single crystal substrate; An IC chip consisting of transistors formed on a single crystal substrate is called COG (Chip On Glass). On Glass) to connect to a glass substrate and place the IC chip on the glass substrate. Alternatively, the IC chip can be inserted into a TAB (Tape Automate) It is also possible to connect it to the glass substrate using a printed circuit board or a bonding method.

[0039] A transistor is defined as a transistor having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain region and the source region. A current can be passed through the drain region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is unclear which is the source and which is the drain. Therefore, it is difficult to determine whether the source or drain is the same. In some cases, the region that functions as a source or drain is not called a source or drain. In some cases, they are referred to as the first terminal and the second terminal. They may be referred to as the first electrode and the second electrode. Or, they may be referred to as the first region and the second region. There is a match.

[0040] A transistor has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector are connected to the first terminal and the second terminal. It may be written as 2 terminals, etc.

[0041] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed directly on A. This also includes cases where A and B are not in a state where the object is located between them, that is, where there is another object between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers , etc.).

[0042] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). In the cases listed, layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. In addition, other layers (such as layers C and D) may be formed as follows: It may be a single layer or a multi-layer.

[0043] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is no other object between A and B. This also includes cases where a layer is interposed between layers. For example, if a layer B is formed above a layer A, In this case, layer B is formed directly on layer A, and layer B is formed directly on layer A. Another layer (such as layer C or layer D) is formed on top of it, and layer B is formed directly on top of it. In addition, other layers (such as layers C and D) may be used as single layers. It may be a multi-layer structure.

[0044] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that B is formed, this also includes the case where B is formed diagonally above. .

[0045] The same applies to the case where B is below A, or B is below A.

[0046] In addition, where something is explicitly stated as singular, it is preferable that it be singular. However, it is not limited to this and plurals are also possible. It is preferable that the items described in the above are plural. However, this is not limited to this. It is also possible for the term to be singular.

[0047] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0048] Note that the diagram is a schematic representation of an ideal example, and is not limited to the shapes or values ​​shown in the diagram. For example, there are variations in shape due to manufacturing techniques, variations in shape due to errors, and noise. Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Or, it is possible to include current variation.

[0049] In addition, technical terms may be used for the purpose of describing a specific embodiment or example. Many, but not limited to:

[0050] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It is possible to use the term as meaning equivalent to the general meaning understood by a person skilled in the art. Any words defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0051] In addition, the terms first, second, third, etc., refer to various elements, members, regions, layers, or sections from one another. Therefore, the words first, second, third, etc. are used to distinguish between elements, parts, etc. The number of materials, regions, layers, areas, etc. is not limited. It is possible to replace "second" or "third" etc.

[0052] In addition, "up," "upward," "down," "downward," "sideways," "right," "left," Spatial location terms such as "diagonally," "in the back," or "in front" refer to an element or may be used to simply illustrate the relationship of a feature to other elements or features in a diagrammatic manner. However, this is not limited to the above, and the terms that indicate these spatial arrangements are added to the direction depicted in the figure. In addition, other orientations are possible. For example, if B is explicitly stated as above A, The device in the figure is not limited to B being above A. Since it is possible for B to be under A, it is possible for B to be under A. The phrase "on" can include an orientation of "under" in addition to an orientation of "on." However, the device in the figure can be rotated in various directions, so The word "above" refers to the directions "above" and "below," as well as "sideways," "right," and "left." The orientation may include other orientations such as "towards," "diagonally," "behind," or "forward." .

[0053] In one aspect of the present invention, a first terminal is connected to a first wiring, and a second terminal is connected to a second wiring. a first transistor having a gate connected to the third wiring and a first terminal connected to the first wiring; a second terminal connected to the second wiring, and a gate connected to the fourth wiring; A transistor having a first terminal connected to a first wiring and a second terminal connected to a second wiring. a third transistor having a gate connected to the fifth wiring; and a first terminal connected to the first wiring. a fourth transistor having a second terminal connected to the second wiring and a gate connected to the sixth wiring; and a transistor.

[0054] In one aspect of the present invention, a first terminal is connected to a first wiring, and a second terminal is connected to a second wiring. a first transistor having a gate connected to the third wiring and a first terminal connected to the first wiring; a second terminal connected to the second wiring, and a gate connected to the fourth wiring; A transistor having a first terminal connected to a first wiring and a second terminal connected to a second wiring. a third transistor having a gate connected to the fifth wiring; and a first terminal connected to the first wiring. a fourth transistor having a second terminal connected to the second wiring and a gate connected to the sixth wiring; A transistor having a first terminal connected to the seventh wiring and a second terminal connected to the second wiring. and a fifth transistor having a gate connected to the eighth wiring.

[0055] In one embodiment of the present invention, a first transistor and a second transistor are alternately turned on and off. a first period during which the third transistor and the fourth transistor are turned off; The first transistor and the second transistor are turned off, and the third transistor and the and a second period during which the first transistor and the second transistor are alternately turned on and off.

[0056] One aspect of the present invention is a first wiring in which a first wiring and a second wiring are in a conductive state via a first path. a second period during which the first wiring and the second wiring are in a conductive state via a second path; a third period in which the first wiring and the second wiring are in a conductive state via a third path; and a fourth period during which the wiring and the second wiring are in a conductive state via a fourth path. Effect of the Invention

[0057] According to one embodiment of the present invention, the time during which a transistor is turned on can be shortened. According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. According to one embodiment of the present invention, the channel width of a transistor can be reduced. In addition, the layout area of ​​the display device can be reduced. Alternatively, one embodiment of the present invention can provide a display device with high resolution. Alternatively, one embodiment of the present invention can increase the yield. One aspect of the present invention is to reduce costs. Alternatively, one embodiment of the present invention can reduce power consumption. Alternatively, in one embodiment of the present invention, the current capability of an external circuit can be reduced. Another embodiment of the present invention is a display device having an external circuit. The size can be reduced. [Brief description of the drawings]

[0058] [Figure 1] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Diagram 2] 1A and 1B are schematic diagrams for explaining the operation of the semiconductor device; [Diagram 3] 1A and 1B are a schematic diagram for explaining an operation of a semiconductor device and a circuit diagram of the semiconductor device; [Figure 4] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 8] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 9] 1A and 1B are schematic diagrams for explaining the operation of the semiconductor device; [Figure 10] 1A and 1B are schematic diagrams for explaining the operation of the semiconductor device; [Figure 11] 1A and 1B are schematic diagrams for explaining the operation of the semiconductor device; [Figure 12] 1A and 1B are schematic diagrams for explaining the operation of the semiconductor device; [Figure 13] 1A and 1B are schematic diagrams for explaining the operation of the semiconductor device; [Figure 14] 4 is a timing chart for explaining an operation of the semiconductor device. [Figure 15] 4 is a timing chart for explaining an operation of the semiconductor device. [Figure 16] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 17] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 18] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 19] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 20] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 21] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 22] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 23] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 24] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 25] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 26] FIG. 2 is a circuit diagram of a shift register. [Figure 27] 4 is a timing chart for explaining the operation of a shift register. [Figure 28] 4 is a timing chart for explaining the operation of a shift register. [Figure 29] FIG. 2 is a schematic diagram for explaining the operation of a shift register. [Diagram 30] FIG. 2 is a block diagram of a display device. [Diagram 31] FIG. 2 is a block diagram of a display device. [Diagram 32] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Diagram 33] 1 is a circuit diagram of a pixel and a timing chart for explaining the operation of the pixel. [Diagram 34] FIG. 2 is a circuit diagram of a pixel. [Diagram 35] 1A and 1B are a top view and a cross-sectional view of a display device. [Diagram 36] FIG. 2 is a cross-sectional view of a transistor. [Figure 37] FIG. 2 is a layout diagram of a shift register. [Figure 38] Layout diagram of a shift register [Figure 39] FIG. 1 is a diagram illustrating an electronic device. [Diagram 40] FIG. 1 is a diagram illustrating an electronic device. [Diagram 41] 1A and 1B are a circuit diagram and a schematic diagram for explaining the operation of a semiconductor device. [Diagram 42] 4 is a timing chart for explaining an operation of the semiconductor device. [Diagram 43] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 44] 4 is a timing chart for explaining an operation of the semiconductor device. [Diagram 45] 4 is a timing chart for explaining an operation of the semiconductor device. [Figure 46] 1A to 1C are cross-sectional views illustrating a manufacturing process of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention may be embodied in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. It should not be construed as being limited to the description of the embodiment. In the drawings, the same reference numerals are used to indicate the same objects, and the same parts or the same components are shown in different drawings. Detailed description of the parts having various functions will be omitted.

[0060] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment, and / or one or more other embodiments The application, combination, or replacement of the contents (or part of the contents) described in the form It is possible to do the following:

[0061] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0062] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part of it) described in another embodiment of the present invention , and many more diagrams can be constructed.

[0063] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. As an example, it is used in a shift register, a gate driver, a source driver, or a display device. Note that the semiconductor device of this embodiment mode can be represented as a driver circuit. be.

[0064] First, a basic circuit that can be used in the semiconductor device of this embodiment mode is shown in FIG. The circuit in FIG. 41A is a circuit including a plurality of circuits 101 and 102. The circuit 101 includes a switch 11_1 and a switch 11_2. The circuit 102 includes a plurality of switches, namely, a switch 12_1 and a switch 12_2. The switch 11_1, the switch 11_2, the switch 12_1, and the The switch 12_2 is connected between the wiring 111 and the wiring 112. The circuit in the above embodiment can be referred to as a semiconductor device or a driver circuit.

[0065] The switch 11_1, the switch 11_2, the switch 12_1, and the switch 12_2 are arranged The conductive state between the line 111 and the wiring 112 is controlled. As shown in FIG. 1, between the wiring 111 and the wiring 112, there are a path 121_1, a path 121_2, and a path There are multiple routes, such as route 122_1 and route 122_2. However, the present invention is not limited to these. When N (a natural number) switches are connected between the wire 111 and the wire 112, There can be N paths between 1 and the wire 112.

[0066] In addition, the path between the wiring A (for example, the wiring 111) and the wiring B (for example, the wiring 112) is described as In this case, the wire A can be connected to the wire B via a switch. In addition to the switch, various elements (e.g., transistors) can be connected between the wires A and B. transistors, diodes, resistors, or capacitors, or various circuits (e.g., A shift register circuit, an inverter circuit, a shift register circuit, etc.) can be connected. Therefore, for example, a resistor or a transistor may be connected in series or in parallel with the switch 11_1. Elements such as transistors can be connected.

[0067] As an example, a signal OUT is output from the wiring 111. The signal OUT is H It is often a digital signal with a low level and a high level, and functions as an output signal. Therefore, the wiring 111 can function as a signal line. The wiring 111 can be arranged to extend to the pixel portion. Alternatively, the wiring 111 may be connected to a transistor included in the pixel. The gate of the transistor (e.g., a selection transistor or a switching transistor) is connected to the Therefore, the signal OUT can be used as a selection signal, a transfer signal, a start signal, a reset signal, etc. The wiring 11 can function as a gate signal, a gate signal, or a scanning signal. The wiring 112 can function as a gate line, a scanning line, or an output signal line. As an example, a voltage V1 is supplied to the input terminal 11. The voltage V1 is a signal of L level. They are often roughly equal in value and can be used as ground voltage, power supply voltage, earth, reference voltage, or negative The wiring 112 can function as a power supply voltage, etc. However, the present invention is not limited to this. A signal may be input to the wiring 112. The wiring 112 can function as a signal line.

[0068] In addition, "generally" refers to errors due to noise, errors due to process variations, and errors due to the manufacturing process of the element. This includes various errors such as errors due to variations in manufacturing process and / or measurement errors.

[0069] As an example, the potential of the L level signal is V1, and the potential of the H level signal is V2. And V2>V1. Therefore, when describing voltage V2, voltage V2 is the signal The value is approximately equal to the H level of the The potential of the signal can be lower than V1 or higher than V1. Alternatively, the potential of the H-level signal can be lower than V2, or higher than V2. It is possible.

[0070] Voltage refers to the difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0071] Next, the operation of the circuit of FIG. 41(A) will be described with reference to the timing chart of FIG. The timing chart of FIG. 42 has multiple periods, and each period has multiple sub-periods. For example, the timing chart in FIG. (Hereinafter, the period is also referred to as a frame period). The period A includes a period A0, a period A1, and a period A2. A1, A2, and B3 (hereinafter, each sub-period is also referred to as one gate selection period). Period B has a number of sub-periods, Period B0, Period B1, and Period B2. do.

[0072] In the example of the timing chart in FIG. 42, the period A and the period B are arranged in that order. However, this is not limited to this, and Period A and Period B can be arranged in various orders. Alternatively, the timing chart may have a period other than period A and period B. Alternatively, one of period A and period B can be omitted.

[0073] In the period A, the period A1 and the period A2 are repeatedly arranged, and then the period A0 is arranged. After that, the period A1 and the period A2 are arranged repeatedly in the period A again. However, the present invention is not limited to this, and the periods A0, A1, and A2 may be arranged in various orders. Alternatively, the period A may include a period B0, a period B1, a period B2, and / or , other periods can be arranged. Or, period A0, period A1, and period It is possible to omit either period A0 or A2. Or, period A0 can be placed next to period A1. It is possible to place it next to period A2, or at the beginning of period A. It is possible to place the period after the first period or after other periods.

[0074] In addition, in the period B, the period B1 and the period B2 are repeatedly arranged, and then the period B0 is arranged. After that, the period B1 and the period B2 are arranged repeatedly in the period B. However, the present invention is not limited to this, and the periods B0, B1, and B2 may be arranged in various orders. Alternatively, the period B may include the period A0, the period A1, the period A2, and / or , other periods can be arranged. Or, period B0, period B1, and period It is possible to omit either period B0 or ​​period B2. Or, period B0 can be placed next to period B1. It is possible to place it next to period B2, or at the beginning of period B. It is possible to place the period after the first period or after other periods.

[0075] First, the operation during the period A will be described. During the period A, the switch 11_1 and the switch 12 Switch 11_1 is turned on and off repeatedly for each sub-period, and switch 11_2 and switch 12_2 are The on and off states of the switches 11_1 and 12_1 are inverted to each other. However, the present invention is not limited to this. The switches 11_1 and 12_1 are It can be turned off or it can be turned on. Or, switch 11_ 2 and / or switch 12_2 can be turned on.

[0076] In the period A1 of the period A, as shown in FIG. 41(C), the switch 11_1 is turned on. , the switch 11_2, the switch 12_1, and the switch 12_2 are turned off. As shown in FIG. 41(D), the path 121_1 is in a conductive state, and the paths 121_2 and 1 Then, the wiring 111 and the wiring 112 are in a non-conductive state. Since the switch 11_1 is turned on, the voltage (for example For example, a voltage V1 or a signal is supplied to the wiring 111 via the switch 11_1. Then, the wiring 111 and the wiring 112 are in a conductive state via the path 121_1. A voltage (for example, voltage V1) or signal supplied to 112 is input to wiring 1 via path 121_1. It will be supplied to 11.

[0077] In period A2 of period A, the switch 12_1 is turned on, and the switch 11_1 and the switch The switch 11_2 and the switch 12_2 are turned off. The path 122_1 is in a conductive state, and the paths 121_1, 121_2, and 122_2 are in a conductive state. Then, the wiring 111 and the wiring 112 are disconnected via the switch 12_1. Since the wiring 112 is in a conductive state, the voltage (for example, the voltage V1) or signal supplied to the wiring 112 is switched In other words, the signal is supplied to the wiring 111 via the switch 12_1. That is, since the path 122_1 is in a conductive state, the voltage (for example, For example, a voltage V1 or a signal is supplied to the wiring 111 via a path 122_1.

[0078] In period A0 of period A, the switch 11_1, the switch 11_2, the switch 12_1, And the switch 12_2 is turned off. Therefore, as shown in FIG. 1, the path 121_2, the path 122_1, and the path 122_2 are in a non-conductive state. Since the wiring 111 and the wiring 112 are in a non-conductive state, the voltage ( For example, no voltage (V1) or signal is supplied to the wiring 111.

[0079] Next, an operation in the period B will be described. In the period B, the switch 11_1 and the switch 12 Switch 11_1 is turned off, and switch 11_2 and switch 12_2 are turned on and off for each sub-period. However, this is not limited to the above, and the switches 11_2 and 12_3 may be repeated. _2 can be off and on. Or, switch Switch 11_1 and / or switch 12_1 can be turned on.

[0080] In the period B1 of the period B, the switch 11_2 is turned on, and the switch 11_1 and the switch The switch 12_1 and the switch 12_2 are turned off. Therefore, as shown in FIG. The path 121_2 is in a conductive state, and the paths 121_1, 122_1, and 122_ Then, the wiring 111 and the wiring 112 are disconnected via the switch 11_2. Since the line 112 is in a conductive state, the voltage (for example, voltage V1) or signal supplied to the line 112 is switched The signal is supplied to the wiring 111 via the switch 11_2. In other words, the signal is supplied to the wiring 111 via the switch 11_2. 2 is in a conductive state via the path 121_2, so that the voltage (e.g. For example, a voltage V1 or a signal is supplied to the wiring 111 via a path 121_2.

[0081] In a period B2 of the period B, the switch 12_2 is turned on, and the switch 11_1 and the switch The switch 11_2 and the switch 12_1 are turned off. Therefore, as shown in FIG. The path 122_2 is in a conductive state, and the paths 121_1, 121_2, and 122_ Then, the wiring 111 and the wiring 112 are connected to each other via the switch 12_2. Since the line 112 is in a conductive state, the voltage (for example, voltage V1) or signal supplied to the line 112 is switched In other words, the signal is supplied to the wiring 111 via the switch 12_2. 2 is in a conductive state via the path 122_2, so that the voltage (e.g. For example, a voltage V1) or a signal is supplied to the wiring 111 via a path 122_2.

[0082] In a period B0 of the period B, the switch 11_1, the switch 11_2, the switch 12_1, And the switch 12_2 is turned off. Therefore, as shown in FIG. 1, the path 121_2, the path 122_1, and the path 122_2 are in a non-conductive state. Since the wiring 111 and the wiring 112 are in a non-conductive state, the voltage ( For example, no voltage (V1) or signal is supplied to the wiring 111.

[0083] As described above, by changing the period during which each switch is on, Therefore, the time required for the switch to become It is possible to suppress deterioration such as the above.

[0084] Note that in the period A0 and the period B0, the wiring 111 is supplied with the voltage V2 or an H-level signal. (For example, a high-level clock signal) is often input. However, this is not limited to this. In other words, the wiring 111 can be in a floating state without receiving any voltage or signal. do.

[0085] Note that the time when period A0 starts in period A (or the time from the start of period A to the end of period A0) The time until the start time is the time when period B0 starts in period B (or the start In most cases, this is roughly equal to the time from the start of period B0 to the start of period B1. Not limited.

[0086] It is possible to replace a period with a step or an operation. For example, the first period, the second period, When the term "period 2" is mentioned, it can be interchangeably referred to as the first step or the second step. be.

[0087] If it is possible to operate as shown in Fig. 41(B) to (H), the switch configuration can be This is not limited to 41(A).

[0088] In addition, two or more of the switches 11_1 to 11_2 and the switches 12_1 to 12_2 It is possible for a number of switches (e.g., two, three, four) to be on at the same time. For example, It is possible for the switch 11_1 and the switch 12_1 to be on at the same time.

[0089] It should be noted that the circuit 101 and / or the circuit 102 may have three or more switches. For example, as shown in FIG. 43A, the circuit 101 includes switches 11_1 to 11_m. (m is a natural number), and the circuit 102 includes switches 12_1 to 12_ It is possible to have a plurality of switches, 11_1 to 11_m. Each of the switches corresponds to the switch 11_1 or the switch 11_2 and has the same function. Each of 2_1 to 12_m corresponds to the switch 12_1 or the switch 12_2 and has the same function. The switches 11_1 to 11_m and the switches 12_1 to 12_m are connected to the wiring 1. 43B, the wiring 111 is connected between the wiring 111 and the wiring 112. Between the wiring 112, a plurality of paths 121_1 to 121_m and a path 122 There are multiple paths, 121_1 to 121_m. However, this is not limited to this. , and / or the circuits 102 may each include one switch; or The number of switches included in the circuit 101 is different from the number of switches included in the circuit 102. It is possible.

[0090] FIG. 44 shows an example of a timing chart that can be used in the circuit of FIG. The timing chart of FIG. 44 is an example in which m=3. Therefore, the circuit 101: It is possible to have a plurality of switches 11_1 to 11_3, and the circuit 10 2 may have a plurality of switches 12_1 to 12_3. The timing chart of FIG. 4 has a plurality of periods, namely, a period A, a period B, and a period C. Period C, like Period A or Period B, is divided into multiple subperiods: Period C0, Period C1, and Period C2. In the example of the timing chart of FIG. 44, there are a period A, a period B, and Period A, Period B, and Period C are arranged in this order. However, this is not limited to this, and Period A, Period B, and Period C may be arranged in this order. can be arranged in various orders. In addition to period A, period B, and period C, various other periods may be included. It is possible to omit either period C1 or period C. Period C includes periods C1 and C2. After the period C2 and the period C1 are repeatedly arranged, the period C0 is arranged. Then, the period C1 is arranged again. In the period, the period C1 and the period C2 are arranged repeatedly. However, the present invention is not limited to this. C0, period C1, and period C2 can be arranged in various orders. Period C includes period A0, period A1, period A2, period B0, period B1, period B2, and / or Alternatively, the period C0, the period C1, and the period C2 may be arranged in a different manner. It is possible to omit either of the periods C0 and C2. Alternatively, the period C0 may be arranged next to the period C1. It can be placed next to period C2, or it can be placed next to other periods. It can be placed next to the

[0091] In the periods A and B, the switches 11_3 and 12_3 are turned off. As a result, the path 121_3 and the path 122_3 are in a non-conductive state. The switch 11_3 and / or the switch 12_3 can be turned on. do.

[0092] In the period C, the switch 11_3 and the switch 12_3 are turned on and off for each sub-period. Repeat switch 11_1, switch 11_2, switch 12_1, and switch 12 The on and off states of the switch 11_3 and the switch 12_3 are mutually In many cases, however, the switch 11_3 and the switch 11_4 are inverted. 12_3 can be on or off. switch 11_1, switch 11_2, switch 12_1, and / or switch 12_2 is capable of being turned on.

[0093] During period C1 of period C, switch 11_3 is turned on, and switches 11_1 and 1 Switch 1_2, switch 12_1, switch 12_2, and switch 12_3 are turned off. As a result, the path 121_3 is in a conductive state, and the paths 121_1, 121_2, and 122 are in a conductive state. _1, the path 122_2, and the path 122_3 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 11_3, so that the current supplied to the wiring 112 is A voltage (for example, voltage V1) or a signal to be output is supplied to the wiring 111 via the switch 11_3. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 121_3. Therefore, the voltage (for example, the voltage V1) or signal supplied to the wiring 112 passes through the path 121_3. The power is supplied to the wiring 111 via the power supply 112.

[0094] During period C2 of period C, switch 12_3 is turned on, and switches 11_1 and 1 Switch 1_2, switch 11_3, switch 12_1, and switch 12_2 are turned off. As a result, the path 122_3 is in a conductive state, and the paths 121_1, 121_2, and 121 _3, the path 122_1, and the path 122_2 are in a non-conductive state. Since the wiring 112 is in a conductive state via the switch 12_3, the current supplied to the wiring 112 is A voltage (for example, voltage V1) or a signal to be output is supplied to the wiring 111 via the switch 12_3. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 122_3. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 122_3. The power is supplied to the wiring 111 via the power supply 112.

[0095] In the period C0 of the period C, the switches 11_1, 11_2, 11_3, The switch 12_1, the switch 12_2, and the switch 12_3 are turned off. 21_1, Route 121_2, Route 121_3, Route 122_1, Route 122_2, Route 1 22_3 is in a non-conductive state. Then, the wiring 111 and the wiring 112 are in a non-conductive state. Therefore, a voltage (for example, voltage V1) or signal supplied to the wiring 112 is It will no longer be possible.

[0096] In FIG. 43(A), if m is large, the time when the switch is on can be shortened. Therefore, it is possible to suppress the deterioration of the elements or circuits used as switches. However, if m is too large, the circuit size becomes too large. Preferably, m≦6. More preferably, m≦4. Preferably, m=2 or m=3.

[0097] Note that the circuit in FIG. 41A includes a plurality of circuits corresponding to the circuit 101 or the circuit 102. FIG. 43C shows a circuit including a circuit 101, a circuit 102, and a circuit 103. The circuit 103 includes a switch 13_1 and a switch 13_2. The circuit 103 includes a plurality of switches, namely, the circuit 101 and the circuit 102. 2, the switch 13_1 corresponds to the switch 11_1 or the switch 12_1, The switch 13_2 corresponds to the switch 11_2 or the switch 12_2. 1 and the switch 13_2 are connected between the wiring 111 and the wiring 112. As shown in FIG. 3(D), a path 121_1 and a path 121_2 are provided between the wiring 111 and the wiring 112. In addition to the route 122_1 and the route 122_2, the route 123_1 and the route 123 However, the circuit is not limited to this, and the circuit may be a circuit 101 or One circuit corresponding to the circuit 102, or four or more circuits corresponding to the circuit 101 or the circuit 102 It is possible to have a circuit of

[0098] An example of a timing chart that can be used in the circuit of FIG. 43(C) is shown in FIG. In the timing chart of 45, period A has a plurality of sub-periods, periods A0 to A3. Period B has a number of sub-periods, periods B0 to B3. Period A has periods A1 to A3. After the period A0 is placed, the period A is again placed. Similarly, in period B, periods B1 to B3 are arranged repeatedly. After that, period B0 is placed. Then, in period B, periods B1 to B3 are placed. However, the present invention is not limited to this. In the period A, the periods A0 to A3 are arranged in a repeated manner. Alternatively, in the period B, the periods B0 to B3 can be arranged in various orders. Alternatively, the period A may be arranged in any order from the periods B0 to B3. Alternatively, period B may include period A0. Any of the periods A to A3 or other periods may be placed in the period A. In the period B, any one of the periods A0 to A3 can be omitted. Therefore, it is possible to omit any of the periods B0 to B3. The period A0 can be placed after any of the periods A1 to A3, and can be placed after any of the other periods. Alternatively, in period B, period B0 can be placed next to period B1 to It can be placed next to any of the periods in B3, and it can be placed next to any other period. It is possible.

[0099] In period A, the switch 11_1, the switch 12_1, and the switch 13_1 are turned on in sequence. The switches 11_2, 12_2, and 13_2 are turned off. However, the present invention is not limited to this, and the switches 11_1, 12_1, and 13_1 may be used. can be turned on in various orders. Switch 2_1 and switch 13_1 can be turned off and on. Alternatively, the switch 11_2, the switch 12_2, and / or the switch 13_ 2 can be turned on.

[0100] In the periods A0, A1, and A2 of the period A, the switch 13_1 and the switch 13 Therefore, the path 123_1 and the path 123_2 are in a non-conducting state. However, the present invention is not limited to this. The switch 13_1 and / or the switch 13_2 are turned on. It is possible to become.

[0101] In period A3 of period A, switch 13_1 is turned on, and switches 11_1 and 1 Switch 1_2, switch 12_1, switch 12_2, and switch 13_2 are turned off. As a result, the path 123_1 is in a conductive state, and the paths 121_1, 121_2, and 122 are in a conductive state. _1, the path 122_2, and the path 123_2 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 13_1, so that the current supplied to the wiring 112 is A voltage (for example, voltage V1) or a signal to be output is supplied to the wiring 111 via the switch 13_1. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 123_1. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 123_1. The power is supplied to the wiring 111 via the power supply 112.

[0102] In period B, the switch 11_2, the switch 12_2, and the switch 13_2 are turned on in sequence. Therefore, the switch 11_1, the switch 12_1, and the switch 13_1 are turned off. However, the present invention is not limited to this, and the switches 11_2, 12_2, and 13_2 may be used. can be turned on in various orders. Switch 2_2 and switch 13_2 can be turned off and on. Alternatively, the switch 11_1, the switch 12_1, and / or the switch 13_ 1 is allowed to be on.

[0103] In the periods B0, B1, and B2 of the period B, the switches 13_1 and 13_2 are Therefore, the path 123_1 and the path 123_2 are in a non-conducting state. However, the present invention is not limited to this. The switch 13_1 and / or the switch 13_2 are turned on. It is possible to become.

[0104] In period B3 of period B, switch 13_2 is turned on, and switches 11_1 and 1 Switch 1_2, switch 12_1, switch 12_2, and switch 13_1 are turned off. As a result, the path 123_2 is in a conductive state, and the paths 121_1, 121_2, and 122 _1, the path 122_2, and the path 123_1 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 13_2, so that the current supplied to the wiring 112 is A voltage (for example, voltage V1) or a signal to be output is supplied to the wiring 111 via the switch 13_2. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 123_2. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 123_2. The power is supplied to the wiring 111 via the power supply 112.

[0105] In FIG. 43C, the number of circuits corresponding to the circuit 101 or the circuit 102 is large. This shortens the time that the switch is on. However, the deterioration of the circuit 101 or the circuit can be suppressed. If the number of circuits corresponding to the circuit 102 is too large, the number of switches increases, and the circuit scale becomes large. Therefore, the number of circuits corresponding to the circuit 101 or the circuit 102 is It is preferably 6 or less, and more preferably 4 or less. Preferably, the number is three or two. However, the number is not limited to this. The number of circuits corresponding to the circuit 101 or the circuit 102 can be one or six or more. Something is possible.

[0106] In FIG. 43C, similarly to FIG. 43A, Each of the multiple circuits includes three or more switches connected between the wiring 111 and the wiring 112. It is possible to have a

[0107] It is possible to divide the wiring into a plurality of wirings. It is possible to input the same signal or voltage, or to input different signals or voltages. Alternatively, the multiple wirings may be connected to the same wiring or element. The multiple wirings can be connected to separate wirings or elements. In one example of FIG. 43(E), the wiring 112 is divided into a plurality of wirings 112A to 112D. The wiring 111 is divided into the wirings 112A to 112D and the wiring 111. , switch 11_1, switch 11_2, switch 12_1, and switch 12_2 are connected. The wirings 112A to 112D correspond to the wiring 112. A voltage V1 can be supplied to the wiring 112A to 112D. However, the present invention is not limited to this, and the wirings 112A to 112D can function as a It is possible to input different voltages or different signals to the wirings 112A to 112C. It is possible to share any one of the wirings 112A to 112D. Each of the lines can be shared with other lines.

[0108] As in FIG. 43E, the wiring 112 in FIG. 43A and FIG. 43C It is possible to divide the wiring 111 into a plurality of wirings. A switch can be connected between each of them.

[0109] Next, an example of a case where a transistor is used as a switch will be described with reference to FIG. FIG. 1A shows a switch 11_1, a switch 11_2, and a switch The switches 12_1 and 12_2 are transistors 101_1 and 101_2, respectively. A transistor 101_2, a transistor 102_1, and a transistor 102_2 are used. However, the present invention is not limited to this, and the contents described in Figs. In the combined configuration, transistors can be used as switches. For example, in FIG. 43(A), FIG. 43(C), and FIG. 43(E), A transistor can be used.

[0110] In addition, the transistor 101_1, the transistor 101_2, the transistor 102_1, and The transistor 102_1 and the transistor 102_2 are assumed to be N-channel transistors. A transistor is turned on when the voltage difference between the gate and source (Vgs) exceeds the threshold voltage (Vth). However, the present invention is not limited to this, and the transistor 101_1, the transistor The transistor 101_2, the transistor 102_1, and / or the transistor 102_2 are P A P-channel transistor can have a gate and a source. When the potential difference (Vgs) between them falls below the threshold voltage (Vth), the transistor turns on. As the switch, a CMOS switch can be used.

[0111] The connection relationship of the semiconductor device in FIG. The first terminals of the transistors 101_2, 102_1, and 102_2 The transistor 101_1, the transistor 101_2, and the transistor 101_3 are connected to the wiring 112. The second terminals of the transistors 102_1 and 102_2 are connected to the wiring 111. Then, the transistor 101_1, the transistor 101_2, and the transistor 102 The gate of the transistor 102_1 and the gate of the transistor 102_2 are connected to the wiring 113_1 and the wiring 113_2, respectively. , and the wiring 114_1 and the wiring 114_2. However, the present invention is not limited to this, and various other A variety of connection configurations are possible.

[0112] For example, the wiring 113_1 and the wiring 113_2 are connected to the signals S1_1 and S1 The signal S1_1 and the signal S1_2 are digital signals. In many cases, the wiring 114_1 and the wiring 114_2 can function as a clock signal. As an example, the signals S2_1 and S2_2 are input to the input terminals 114_2, respectively. The signal S2_1 is an inverted signal of the signal S1_1 or has a phase difference of 180° from the signal S1_1. It is often a shifted signal and can function as an inverted clock signal. The signal S2_2 is an inverted signal of the signal S1_2 or has a phase difference of 180° from the signal S1_2. It is often a shifted signal and can function as an inverted clock signal. However, the present invention is not limited to this, and includes the wiring 111, the wiring 112, the wiring 113_1, the wiring 113_2, Various other signals, currents, or voltages may be transmitted through the lines 114_1 and 114_2. It is possible to input pressure.

[0113] The signal S1_1 and the signal S1_2 are output every certain period (for example, every frame or every operation period). In many cases, the active state and the inactive state are repeated every time the signal S1 In the case of signals S1_1 and S1_2, the active and inactive states may be inverted. Similarly, the signal S2_1 and the signal S2_2 are generated every certain period (for example, every frame, In many cases, the active state and the inactive state are repeated every one operation period. In addition, the active and inactive states of the signals S2_1 and S2_2 are inverted. For example, in the kth frame (k is a natural number), the signals S1_1 and S2_2 are If the signal S1_1 and the signal S2_2 are in an active state, the signals S1_2 and S2_2 are in an inactive state. After that, in the k+1-th frame, the signal S1_1 and the signal S If signal S1_1 becomes inactive, signals S1_2 and S2_2 become active. However, the present invention is not limited to this, and both the signal S1_1 and the signal S1_2 may be in the same state. The signal can be in the same state (active or inactive). Both signal S2_1 and signal S2_2 are in the same state (active or inactive) Alternatively, the signals S1_1, S1_2, S2_1, and S3_2 may be the same. The number S2_2 is generated every several frames, every time the semiconductor device is powered on, or randomly. , it is possible for the active and inactive states to be cycled.

[0114] In addition, when a signal is in an active state, the signal can be at either H level or L level. On the other hand, a signal becomes inactive when it remains at a constant value (e.g. For example, the signal becomes an inactive state (H level or L level). When describing the state as "active," the signal is set to L level. For example, a signal is not guaranteed to remain at a constant value even when it goes active. is possible.

[0115] The wiring 113_1, the wiring 113_2, the wiring 114_1, and the wiring 114_2 are used for transmitting signals. It can function as a line, a clock signal line, or a clock signal line, but is not limited to this. A voltage is supplied to the wiring 113_1, the wiring 113_2, the wiring 114_1, and the wiring 114_2. When the wiring is connected to the power supply, these wirings can function as power supply lines.

[0116] It is possible to input a multi-phase clock signal to the semiconductor device. For example, n (n is It is possible to input a clock signal having n phases (a natural number) to a semiconductor device. A clock signal is a set of n clock signals that are out of phase with each other. For example, As an example, there are n clock signals whose periods are shifted by 1 / n. However, this is not limited to this.

[0117] In addition, the signals S1_1, S2_1, S1_2, and S2_2 are in the active state. In this case, in order to simplify the circuit that generates the signal, the time when it becomes L level and the time when it becomes H level are It is preferable that the time required for the L level to reach the threshold is approximately equal to the time required for the L level to reach the threshold. The time when the signal is at the H level can be longer than the time when the signal is at the L level. The time for which the output is turned on can be shorter than the time for which the output is turned on.

[0118] Balanced means that the duty ratio is approximately 50%, that is, the time between the H level and the L level is approximately 50%. Non-equilibrium means that the time of the H level is approximately equal to that of the This refers to the time between the peak and L levels being different.

[0119] Next, the operation of the semiconductor device in FIG. 1A will be described with reference to a timing chart in FIG. The timing chart in FIG. 1B corresponds to the timing chart in FIG. Note that a description of operations common to those in Fig. 41(A) will be omitted.

[0120] First, the operation in the period A will be described. In the period A, the signal S1_1 and the signal S2_1 are The signal S1_2 and the signal S2_2 are in an active state. Thus, the signal S1_1 and the signal S2_1 alternate between the H level and the L level in each sub-period. The signals S1_1 and S2_2 are at the L level. In the case of 1, the H level and the L level are often inverted. However, this is not limited to this. The signals S1_1 and S2_1 can be at the L level and at the H level. Alternatively, the signal S1_2 and / or the signal S2_2 may be at the H level. It is possible to become a Bell.

[0121] In the period A1 of the period A, the signal S1_1 becomes the H level, and the signals S1_2 and S2_ 1 and the signal S2_2 become L level. Therefore, as shown in FIG. The transistor 101_1 is turned on, and the transistor 101_2, the transistor 102_1, and the transistor 102_2 are turned on. The transistor 102_2 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through the line 101_1, the voltage V1 is transferred to the line 111 through the line 112. It is supplied via register 101_1.

[0122] In the period A2 of the period A, the signal S2_1 becomes the H level, and the signals S1_1 and S1_ 2, and the signal S2_2 become L level. Therefore, as shown in FIG. 2(B), The transistor 102_1 is turned on, and the transistors 101_1, 101_2, and The transistor 102_2 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through the line 102_1, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 102_1.

[0123] In period A0 of period A, signals S1_1, S1_2, S2_1, and S2 Therefore, as shown in FIG. 2C, the transistors 101_1 and 101_2 are turned on. The transistor 101_2, the transistor 102_1, and the transistor 102_2 are turned off. As a result, the wiring 111 and the wiring 112 are brought into a non-conductive state.

[0124] Next, the operation in the period B will be described. In the period B, the signals S1_2 and S2_2 are The signal S1_1 and the signal S2_1 are in an active state, and the signal S2_1 are in an inactive state. Thus, the signal S1_2 and the signal S2_2 alternate between the H level and the L level for each sub-period. The signals S1_1 and S2_1 go to the L level. In the case of 2, the H level and the L level are often inverted. However, this is not limited to this. The signals S1_2 and S2_2 can be at the L level and at the H level. Alternatively, the signal S1_1 and / or the signal S2_1 may be at the H level. It is possible to become a Bell.

[0125] In the period B1 of the period B, the signal S1_2 becomes H level, and the signals S1_1 and S2_ 1 and the signal S2_2 become L level. Therefore, as shown in FIG. The transistor 101_2 is turned on, and the transistors 101_1, 102_1, and The transistor 102_2 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through the line 101_2, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 101_2.

[0126] In the period B2 of the period B, the signal S2_2 becomes H level, and the signals S1_1 and S1_ 2 and the signal S2_1 become L level. Therefore, as shown in FIG. 3B, The transistor 102_2 is turned on, and the transistors 101_1, 101_2, and The transistor 102_1 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through the line 102_2, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 102_2.

[0127] In the period B0 of the period B, the signals S1_1, S1_2, S2_1, and S2 Therefore, as shown in FIG. 2C, the transistors 101_1 and 101_2 are turned on. The transistor 101_2, the transistor 102_1, and the transistor 102_2 are turned off. As a result, the wiring 111 and the wiring 112 are brought into a non-conductive state.

[0128] As described above, the semiconductor device of the present embodiment has a function of shortening the time during which a transistor is turned on. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment. By doing so, the life of these can be extended.

[0129] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to an N-channel type or It is possible to make it a P-channel type. Therefore, the number of steps is reduced compared to CMOS circuits. In particular, it is possible to reduce the number of defects, improve the yield, improve the reliability, or reduce the cost. If all transistors, including the elemental part, are N-channel type, the semiconductor layer of the transistor a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of the present embodiment is capable of suppressing the deterioration of the transistor. It is possible.

[0130] Alternatively, the transistor may be degraded so that the semiconductor device can operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of the present embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0131] In addition, the L level of the signal S1_1, the signal S1_2, the signal S2_1, and / or the signal S2_2 It is possible to make the potential of the resistor lower than V1. In this case, when the signal becomes L level, A reverse bias is applied to the transistor, which helps to reduce the degradation of the transistor. However, the present invention is not limited to this, and the signals S1_1, S1_2, S2_1, and / Or, the L level potential of the signal S2_2 can be higher than V1.

[0132] In addition, the H level of the signal S1_1, the signal S1_2, the signal S2_1, and / or the signal S2_2 It is possible to make the potential of the resistor lower than V2. In this case, the signal becomes H level, When the transistor is turned on, the Vgs of the transistor becomes smaller. However, the present invention is not limited to this, and the signal S1_1, the signal The potential of the H level of the signal S1_2, the signal S2_1, and / or the signal S2_2 is higher than V2. It is possible.

[0133] The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are Similarly, the channel width of the transistor 102_1 and It is preferable that the channel width of the transistor 102_1 is approximately equal to that of the transistor 102_2. By making the transistor sizes roughly equal, the current capabilities are roughly equal. Therefore, even if multiple transistors are used, the signal waveform The degree of degradation of the transistor characteristics can be made approximately equal. However, the present invention is not limited to this, and the channel of the transistor 101_1 may be equal to the channel of the transistor 101_2. The width of the gate of the transistor 101_1 and the channel width of the transistor 101_2 may be different. The channel width of the transistor 102_1 and the channel width of the transistor 102_2 are different. It is possible to make it happen.

[0134] When referring to the channel width of a transistor, this is expressed as the W / L (W: channel This can be expressed as the ratio of the channel width (L:channel length).

[0135] As shown in FIG. 4(A), similarly to FIG. 43(E), the wiring 112 is divided into wirings 112A to 112B. 12D. The first terminals of the transistors 101_2, 102_1, and 102_2 are connected to the wiring 112A, the wiring 112B, the wiring 112C, and the wiring 112D, respectively.

[0136] As shown in FIG. 3C, the transistor 101_1 and the transistor 101_2 The first terminals of the first and second terminals 113_1 and 113_2 can be connected to the wiring 113_2 and the wiring 113_1, respectively. Alternatively, as shown in FIG. 4B, the transistor 101_1 and the transistor 101_2 , the first terminal of the transistor 102_1, and the first terminal of the transistor 102_2 are connected to the wiring 1 13_2, wiring 113_1, wiring 114_2, and wiring 114_1. In this case, during the period when the transistor is turned off by the inactive signal, An active signal is input to the first terminal of the transistor. During this time, a low-level signal is input to the gate of the transistor, and a high-level signal is input to the gate of the transistor. This includes the period when the reverse bias is input to the first terminal of the transistor. This voltage is applied to the transistor, so the deterioration of the transistor can be suppressed. However, the transistors 101_1, 101_2, and 102 are not limited to the above. 114_1 and the first terminal of the transistor 102_2 are connected to a wiring 114_2 and a wiring 114_3, respectively. The same effect can be obtained when the wiring 113_1, wiring 113_2, and wiring 113_1 are connected. Alternatively, as shown in FIG. 4C, the transistor 101_1 and the transistor 101 The first terminals of the transistors 102_1 and 102_2 are connected to the It is possible to connect the line 114_1, the wiring 114_2, the wiring 113_1, and the wiring 113_2. It is Noh.

[0137] FIG. 5(A) shows a configuration in which a transistor is used as the switch in FIG. 43(C). The switches 13_1 and 13_2 are transistors 103_ The transistor 103_1 is a transistor 1. 01_1 or transistor 102_1, and transistor 103_2 corresponds to a transistor The transistors 103_1 and 103_2 correspond to the transistors 101_2 and 102_2. A first terminal of the transistor 103_2 is connected to the wiring 112, and The second terminal of the transistor 103_2 is connected to the wiring 111. The gate of the transistor 103_1 is connected to the wiring 115_1, and the gate of the transistor 103_2 is connected to the wiring 115_2. The wiring 115_1 and the wiring 115_2 are respectively connected to the wiring 115_1 and the wiring 115_2. Signals S3_1 and S3_2 are input. It is often a digital signal and can function as a clock signal.

[0138] It should be noted that the contents described with reference to FIG. 43(C) can be applied to FIG. 5(A).

[0139] As in FIG. 5(A), the semiconductor device in FIG. 3(C) and FIGS. 4(A) to 4(C) is , it is possible to have a plurality of circuits corresponding to the circuit 101 or the circuit 102.

[0140] FIG. 5B shows a configuration in which a transistor is used as the switch in FIG. 43A. The transistors 101_1 to 101_m serve as the switches 11_1 to 11_m. The switches 12_1 to 12_m are formed of transistors 102_1 to 102_m. The first terminals of the transistors 101_1 to 101_m are connected to the wiring 112. The second terminals of the transistors 101_1 to 101_m are connected to the wiring 111. The gates of the transistors 101_1 to 101_m are connected to the wirings 113_1 to 113_m, respectively. The first terminals of the transistors 102_1 to 102_m are connected to the wiring 112. In addition, second terminals of the transistors 102_1 to 102_m are connected to the wiring 111. The gates of the transistors 102_1 to 102_m are connected to the wirings 114_1 to 114_m, respectively. Signals S1_1 to S1_m are input to the wirings 113_1 to 113_m, respectively. Signals S2_1 to S2_m are input to the wirings 114_1 to 114_m, respectively. S1_1 to S1_m are sequentially set to the active state every certain period (for example, every frame). Similarly, the signals S2_1 to S2_m are activated in sequence every certain period (for example, every frame). This shortens the period that the signal is in the active state. This shortens the time that the transistor is on, which reduces the deterioration of the transistor. can be suppressed.

[0141] It should be noted that the contents described in FIG. 43(A) can be applied to FIG. 5(B).

[0142] As in FIG. 5B, the circuit 101, and circuit 102 may each include multiple transistors. In (A), the circuit corresponding to the circuit 101 or the circuit 102 also includes a plurality of transistors. It is possible to have a star.

[0143] As shown in FIG. 6A, the transistor 101_1 is connected to one terminal (hereinafter, also referred to as the positive terminal). The negative terminal of the positive terminal is connected to the wiring 111, and the negative terminal of the negative terminal is connected to the wiring 113_1. It is possible to replace the diode 101a_1 connected to the transistor. One terminal of the terminal 101_2 is connected to the wiring 111, and the other terminal is connected to the wiring 113_2. Alternatively, the transistor 1 may be replaced by a diode 101a_2. One terminal of 02_1 is connected to the wiring 111, and the other terminal is connected to the wiring 114_1. Alternatively, the transistor 102 may be replaced with a diode 102a_1. One terminal of the conductor 114_2 is connected to the wiring 111 and the other terminal is connected to the wiring 114_2. It is possible to replace the diode 102a_2.

[0144] As shown in FIG. 6B, the transistors 101_1, 101_2, The transistor 102_1 and the transistor 102_2 can be diode-connected. In this case, the transistor 101_1, the transistor 101_2, and the transistor 1 The first terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to the wiring 113_1 and the wiring 1 The transistor 101_1 is connected to the transistor 13_2, the wiring 114_1, and the wiring 114_2. The second transistors 101_2, 102_1, and 102_2 The terminal and the gate are connected to the wiring 111. 101_1, transistor 101_2, transistor 102_1, and transistor 10 The gates of the first and second gates 112_2 are connected to the wiring 113_1, the wiring 113_2, the wiring 114_1, and the wiring 11 It is possible to connect it to 4_2.

[0145] As in the case of Figs. 6(A)-(B), Figs. 3(C), 4(A)-(C), and 5(A) In the above (B), the transistors (for example, the transistor 101_1, the transistor 1 01_2, transistor 102_1, and transistor 102_2) are placed as diodes. Alternatively, the gate of the transistor and the first terminal or the second terminal may be replaced. It is possible to make the transistor diode-connected by connecting

[0146] As shown in FIG. 6(C), a P-channel transistor is used. It is possible to make the transistor 101p_1, the transistor 101p_2, the transistor The transistor 102p_1 and the transistor 102p_2 are the transistors 101_1 and 102p_2, respectively. corresponding to transistor 101_2, transistor 102_1, and transistor 102_2, If the polarity of the transistor is a P-channel type, the wiring 112 is supplied with a voltage V2, and the signals S1_1, S1_2, S2_1, and S2_2 are , in many cases, it is inverted compared to the timing chart of FIG. 1(B).

[0147] As with FIG. 6(C), FIG. 3(C), FIG. 4(A)-(C), FIG. 5(A)-(B), FIG. In 6(A)-(B), P-channel transistors are used as the transistors. It is possible.

[0148] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. It is possible to have the semiconductor device of the first embodiment. The semiconductor device of the present embodiment is Flip-flops, shift registers, gate drivers, source drivers, display devices, etc. Note that the semiconductor device of this embodiment mode can be used for a flip-flop or can be referred to as a driver circuit.

[0149] First, an example of a semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device in (A) includes a circuit 101, a circuit 102, and a transistor 201. The circuit 101 includes a plurality of transistors, namely, a transistor 101_1 and a transistor 101_2. The circuit 102 includes a transistor 102_1 and a transistor 102_2. The semiconductor device has a plurality of transistors.

[0150] The transistor 201 includes the transistor 101_1, the transistor 101_2, It is preferable that the polarity of the transistors 102_1 and 102_2 is the same as that of the transistors 102_2. However, the transistor 201 is not limited to a P-channel type. The optical fiber may be of the channel type.

[0151] Next, the connection relationship of the semiconductor device in FIG. The first terminal of the transistor 201 is connected to a wiring 211, and the second terminal of the transistor 201 is connected to a wiring 111. A first terminal of the transistor 101_1 is connected to a wiring 112. A second terminal of the transistor 101_1 is connected to the wiring 111. The first terminal of the transistor 101_2 is connected to a wiring 112, and the second terminal of the transistor 101_2 is connected to a wiring 111. A first terminal of the transistor 102_1 is connected to a wiring 112. A second terminal of the transistor 102_1 is connected to the wiring 111. The first terminal of the transistor 102_2 is connected to the wiring 114_1. A second terminal of the transistor 102_2 is connected to the wiring 111, and a second terminal of the transistor 102_3 is connected to the wiring 112. The gate of the transistor 102_2 is connected to the wiring 114_2. However, various other connection configurations are possible.

[0152] The gate of the transistor 201 is indicated as a node A. The gate of the transistor 101_2 is indicated as a node B1. The gate of the transistor 101_2 is indicated as a node B2. Node A, node B1, and node B2 can be referred to as wires.

[0153] Next, an example of a signal or voltage input to or output from each wiring will be described. A signal OUT is output from the wiring 211. A signal CK is input to the wiring 212. The signal CK corresponds to the signal S1 and can function as a clock signal. It is assumed that a voltage V1 is input to the wiring 112. However, this is not limited to this. These wires can also carry various other signals, voltages, or currents. It is.

[0154] Note that the wiring 211 can function as a signal line or a clock signal line. However, the wiring 211 is not limited to this, and can function as various other wirings. be.

[0155] Next, the function of the transistor 201 will be described. The timing for supplying the H-level signal CK to the wiring 111 is controlled according to the potential of the node A. This allows the OUT signal to be pulled up at a high level, and the OUT signal can be pulled up at a high level. The transistor can function as a backup transistor or a bootstrap transistor. For example, the transistor 201 is turned on during the period A0 described in the first embodiment. Then, a signal CK of H level is supplied to the wiring 111. However, this is not limited to this. Register 201 can have a variety of other functions.

[0156] Note that the semiconductor device can include a circuit 200 as shown in FIG. The circuit 200 may have a variety of configurations and may be implemented in one or more The polarity of these transistors is as follows: transistor 1 01_1, transistor 101_2, transistor 102_1, transistor 102_2 , and the same polarity as that of transistor 201, but is not limited to this. For example, the circuit 200 may include N-channel and P-channel transistors. That is, the circuit 200 may be a CMOS circuit. The circuit 200 has a plurality of terminals, 200a to 200k. 00b, terminal 200c, terminal 200d, terminal 200e, terminal 200f, terminal 200g, end The terminal 200h, the terminal 200i, the terminal 200j, and the terminal 200k are each connected to a wiring 211_1 , wiring 211_2, wiring 114_1, wiring 114_2, wiring 212, wiring 213, wiring 1 12, node A, wiring 111, node B1, and node B2 are connected. The terminals are not limited to the above, and the circuit 200 may have various other terminals. 200k may be omitted. Alternatively, each terminal of the circuit 200 may be omitted. Also, the electrodes can be connected to various wirings or nodes.

[0157] The wiring 211_1 and the wiring 211_2 are connected to a signal CK_1 and a signal CK_2, respectively. The signals CK_1 and CK_2 are respectively input to the signal S1_1 and the signal S1 The wiring 114_1 corresponds to the wiring 114_2 and can function as a clock signal. Signals CKB_1 and CKB_2 are input to 14_2, respectively. The signals KB_1 and CKB_2 correspond to the signals S2_1 and S2_2, respectively, and are inverted clocks. The wiring 212 is configured to receive a signal SP. The signal SP is often a digital signal and can function as a start signal. Alternatively, the signal SP may be a transfer signal, an output signal, or a The signal RE is input to the wiring 213. The signal RE is often a digital signal and functions as a reset signal. Alternatively, the signal RE may be a transfer signal of another stage (e.g., the next stage), an output signal However, it is not limited to this and can function as a selection signal, etc. Various other signals, voltages, or currents can be input to these wires. be.

[0158] The wiring 211_1 and the wiring 211_2 function as a signal line or a clock signal line. Alternatively, the wiring 212 and the wiring 213 may be a signal line, a gate line, or These wirings can function as scanning lines, etc. However, they are not limited to this. The lines can also function as various other wiring functions.

[0159] The circuit 200 includes signals CK_1, CK_2, CKB_1, CKB_2, Signal SP, signal RE, voltage V1, the potential of node A, signal OUT, the potential of node B1, and / or depending on the potential of node B2, the potential of node A, the signal OUT, the potential of node B1, And / or, the potential of the node B2 may be controlled, and the control circuit may function as a control circuit. However, the circuit 200 is not limited to this and may have various other functions. It is possible.

[0160] As shown in FIG. 8A, the semiconductor device includes a circuit 300 and a circuit 400. Various configurations can be used for the circuit 300 and the circuit 400. For example, the circuit 400 includes a transistor 101_1 for controlling the gate potential of the transistor 101_1. and a logic circuit for controlling the potential of the gate of the transistor 101_2. An example of such a logic circuit is a two-stage circuit shown in FIG. A logic circuit that combines AND and NOT of inputs, or a two-input However, the circuit 400 is not limited to this, and may be implemented in various other circuits. It is possible to use the path.

[0161] Note that the circuit 300 and the circuit 400 each include one or more transistors. The polarities of these transistors are: transistor 101_1, transistor 101_2, Same polarity as the transistor 102_1, the transistor 102_2, and the transistor 201 However, the present invention is not limited to this. For example, the circuit 300 and / or The circuit 400 may include N-channel and P-channel transistors. That is, the circuit 300 and / or the circuit 400 can be a CMOS circuit. It is possible.

[0162] The circuit 300 has a plurality of terminals 300a to 300i. The terminal 300a, the terminal 300b, the terminal 400f, Terminal 300c, terminal 300d, terminal 300e, terminal 300f, terminal 300g, terminal 300h , and the terminal 300i correspond to the wiring 211_1, the wiring 211_2, the wiring 114_1, the wiring 114_2, wiring 212, wiring 213, wiring 112, the gate of transistor 201, wiring 111. Terminal 400a, terminal 400b, terminal 400c, terminal 400d, terminal The terminals 400e and 400f correspond to the wiring 211_1, the wiring 211_2, and the transistor 201, the wiring 112, the gate of the transistor 101_1, the transistor 101_ 2. However, the present invention is not limited to this. 00 may have various other terminals, and any of the terminals 300a to 300i may be Alternatively, any one of the terminals 400a to 400f may be omitted. Each terminal of the circuit 300 and / or 400 is connected to various other wirings or nodes. It is possible.

[0163] The circuit 300 includes signals CK_1, CK_2, CKB_1, CKB_2, Depending on the signal SP, the signal RE, the voltage V1, the potential of the node A, and / or the signal OUT, The potential of the node A and / or the wiring 111 is controlled by the The circuit 400 receives the signals CK_1 and CK_2, the potential of the node A, and the voltage Depending on V1, the potential of node B1, and / or the potential of node B2, Alternatively, the potential of the node B2 may be controlled, and the potential of the node B2 may function as a control circuit. However, the circuit 300 and the circuit 400 are not limited to this, and may have various other functions. It is possible to do so.

[0164] Next, the operation of the semiconductor device of this embodiment will be described. The operation of the semiconductor device in (A) will be described with reference to Figs. 8(B), 9(A), 9(B), and 10(A). ), Fig. 10(B), Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13 The following description will be given with reference to FIG. 8(A) and FIG. 13(B). In FIG. 8(B), the signal CK, the signal CK_ 1, signal CK_2, signal CKB_1, signal CKB_2, signal SP, signal RE, node A potential (Va), the potential of node B1 (Vb1), the potential of node B2 (Vb2), and the signal O UT. One operation period (or one frame period) in the timing chart of FIG. 8(B) is , period T1, period T2, period T3, period T4, and period T5. 0(A), 11(A), 12(A), and 13(A) show the k-th frame. Schematic diagrams of the operation of the semiconductor device in periods T1, T2, T3, T4, and T5. 9(B), 10(B), 11(B), 12(B), and 13(B) are shown. are respectively in periods T1, T2, T3, T4, and T5 of the k+1th frame. 1A is a schematic diagram of the operation of the semiconductor device in FIG. The operation of the semiconductor device in FIG. 8(A) will be described with reference to FIG. It is possible to apply this to the operation of the semiconductor device of A) to (B).

[0165] First, in the period T1 of the kth frame, the signal CKB_1 becomes H level. Since the output of the transistor 102_2 becomes L level, the transistor 102_1 is turned on and the transistor 102 At the same time, the signals CK_1 and CK_2 become L level, so the circuit 400 reduces the potentials of nodes B1 and B2. The circuit 400 supplies a signal or voltage V1 of the same level to the nodes B1 and B2. The potentials of the nodes B1 and B2 are reduced by capacitive coupling. As a result, the transistor 101_1 and the transistor 101_2 are turned off. Similarly, the wiring 112 and the wiring 111 are brought into electrical conduction through the transistor 102_1. A voltage V1 is supplied from the wiring 112 to the wiring 111 via the transistor 102_1. At this time, the signal SP becomes H level, so the circuit 300 increases the potential of the node A. For example, the circuit 300 supplies a high-level signal or voltage V2 to node A. Then, The potential of the node A is equal to the L level potential (V1) of the signal CK and the threshold voltage of the transistor 201. When the voltage rises to the sum of V1 and Vth201, the transistor 201 Therefore, the wiring 211 and the wiring 111 are brought into electrical continuity through the transistor 201. Therefore, the L-level signal CK is supplied from the wiring 211 to the wiring 11 via the transistor 201. 1. After that, the potential of node A continues to rise. When the voltage Vth reaches at least V1+Vth201, the circuit 300 supplies a signal or Therefore, node A will maintain the potential at this time and will become a floating Thus, the signal OUT goes to the L level.

[0166] In addition, during the period T1 of the kth frame, the circuit 300 outputs a signal or voltage V1 of an L level. However, the present invention is not limited to this. It is possible that no signal, voltage, or the like is supplied to the wiring 111 .

[0167] On the other hand, in the period T1 of the (k+1)th frame, the signal CKB_1 becomes L level, and the signal CK Since B_2 is at the H level, the transistor 102_1 is turned off and the transistor 10 The operation differs from that in period T1 of the kth frame in that 2_2 is turned on.

[0168] Next, in the period T2 of the kth frame, the signal CKB_1 becomes L level, and the signal CKB Since _2 remains at the L level, the transistor 102_1 is turned off and the transistor 102_2 remains off. At the same time, the signal CK_1 goes to H level and the signal CK_2 The potential of the node A remains at a high value, but the potential of the node B remains at a low level. For example, the circuit 400 maintains the potentials of the nodes B1 and B2 at a low value. Alternatively, the circuit 400 may continue to provide a signal or voltage V1 to the nodes B1 and B2. The nodes B1 and B2 are connected to each other without supplying a signal or voltage to the nodes B1 and B2. This makes the transistor 101_1 and the transistor 101_2 in a floating state. As a result, the wiring 112 and the wiring 111 are not electrically connected to each other, as in FIG. At this time, the circuit 300 may not supply a signal or voltage to the node A. In other words, node A remains floating, so the potential (V1 + V th201 or more). Therefore, the transistor 201 remains on. Therefore, the wiring 211 and the wiring 111 remain in a conductive state. The potential of the wiring 111 starts to rise. Then, the potential of the node A Since the potential of the node A is kept floating, the potential of the gate and the second terminal of the transistor 201 is This is called bootstrap operation. The potential of node A rises to V2+Vth201+α (α is a positive number). Then, the potential of wire 1 The potential of the terminal 11 rises to the potential (V2) of the H-level signal CK. OUT becomes H level.

[0169] On the other hand, during the period T2 of the k+1th frame, the signal CK_1 remains at the L level, and the signal The difference from the operation in the kth frame period T2 is that CK_2 becomes H level. However, Even in this case, the potential of node A remains high, so the circuit 400 The potential of node B2 is kept low.

[0170] Next, during the period T3 of the kth frame, the signal CKB_1 becomes H level, and the signal CKB Since _2 remains at the L level, the transistor 102_1 is turned on, and the transistor 102_2 remains off. At the same time, the signal CK_1 goes to the L level and the signal CK_2 remains at the L level, the circuit 400 sets the potentials of the nodes B1 and B2 to a low value. For example, the circuit 400 may maintain a low level signal or voltage V1 at nodes B1 and Alternatively, the circuit 400 may continue to provide a signal, voltage, etc. to the nodes B1 and B2. Therefore, the transistor B1 and the node B2 are not supplied with the signal, and the node B1 and the node B2 are left floating. The transistor 102_1 and the transistor 102_2 remain off. As a result, Similarly, the wiring 112 and the wiring 111 are brought into electrical continuity through the transistor 102_1. Therefore, the voltage V1 is supplied from the wiring 112 to the wiring 111 via the transistor 102_1. At this time, the signal RE goes high, so the circuit 400 reduces the potential of the node A. For example, the circuit 400 supplies a signal or voltage V1 at an L level to the node A. As a result, the transistor 201 is turned off, and the wiring 211 and the wiring 111 are not electrically connected to each other. As a result, the signal OUT becomes L level.

[0171] In addition, during the period T3 of the kth frame, the circuit 300 outputs a signal or voltage V1 of an L level. It is possible to supply the same to the wiring 111.

[0172] On the other hand, during the period T3 of the (k+1)th frame, the signal CKB_1 remains at the L level. Since the signal CKB_2 goes high, the transistor 102_1 remains off. The operation differs from that in the k-th frame period T3 in that the transistor 102_2 is turned on.

[0173] Next, in the period T4 of the kth frame, the signal CKB_1 becomes L level, and the signal CKB Since _2 remains at the L level, the transistor 102_1 is turned off and the transistor 102_2 remains off. At the same time, the signal CK_1 goes to H level and the signal CK_2 Since the potential of the node B1 remains at the L level, the circuit 400 increases the potential of the node B1. For example, 00 provides a high level signal or voltage V2 to node B1. Alternatively, the circuit 400 The potential at node B1 is increased by capacitive coupling. For example, the circuit 400 maintains the potential at a low value by applying a signal or voltage V1 at a low level to a node Alternatively, the circuit 400 may provide a signal, voltage, etc., to node B2 without providing a signal, voltage, etc. This causes the node B2 to be in a floating state, so that the transistor 101_1 is turned on and the transistor As a result, the wiring 112 and the wiring 103 remain in the off state as in FIG. 111 is in a conductive state via the transistor 101_1, so that the voltage V1 is applied to the wiring 112 is supplied to the wiring 111 through the transistor 101_1. , the potential of the node A is maintained at V1. For example, the circuit 300 1 to node A. Alternatively, the circuit 300 may provide a signal, voltage, etc. to node A. This leaves node A floating. Therefore, transistor 201 is off. Therefore, the wiring 211 and the wiring 111 remain in a non-conductive state. The signal OUT remains at the L level.

[0174] In addition, during the k-th frame period T4, the circuit 300 outputs a signal or voltage V1 at an L level. The signal can be supplied to the wiring 111. However, this is not limited thereto. It is possible that no signal, voltage, etc. is supplied to the wiring 111.

[0175] On the other hand, during the period T4 of the (k+1)th frame, the signal CK_1 remains at the L level, and the signal The difference from the operation in the k-th frame period T4 is that CK_2 becomes H level. Since circuit 400 keeps node B1 low and raises node B2, The transistor 101_1 remains off and the transistor 101_2 turns on. , which is different from the operation in period T4 of the kth frame.

[0176] Next, in the period T5 of the kth frame, the signal CKB_1 becomes H level, and the signal CKB Since the output of transistor 102_2 remains at the L level, transistor 102_1 is turned on and transistor 10 2_2 remains off. At the same time, signal CK_1 goes to L level and signal CK_2 goes to L level. Since the potential at node B1 remains at the same level, the circuit 400 reduces the potential at node B1. 400 supplies a low level signal or voltage V1 to node B1. Alternatively, the circuit 400 , the potential at node B1 is decreased by capacitive coupling. For example, the circuit 400 maintains the potential of the node 2 at a low value. Alternatively, the circuit 400 may not provide a signal, voltage, etc. to node B2. Therefore, the node B2 is made floating. Therefore, the transistor 101_1 is turned off, and the transistor As a result, the wiring 111 and the transistor 101_2 remain in an off state, as in FIG. Since the line 112 is electrically connected via the transistor 102_1, the voltage V1 is applied to the line 1 12 to the wiring 111 through the transistor 102_1. For example, the circuit 300 outputs a signal or voltage at an L level. The circuit 300 may provide a voltage V1 to node A. Alternatively, the circuit 300 may provide a signal, voltage, etc. to node A. By not supplying a current to node A, node A is left floating. Therefore, transistor 201 Since the switch remains off, the wiring 211 and the wiring 111 remain in a non-conductive state. , the signal OUT remains at the L level.

[0177] In addition, during the period T5 of the kth frame, the circuit 300 outputs a signal or voltage V1 of an L level. The signal can be supplied to the wiring 111. However, this is not limited thereto. It is possible that no signal, voltage, etc. is supplied to the wiring 111.

[0178] On the other hand, during the period T5 of the (k+1)th frame, the signal CKB_1 remains at the L level. Since the signal CKB_2 becomes H level, the transistor 102_1 is turned off and the transistor This operation differs from that in the k-th frame period T5 in that the timer 102_2 is turned on.

[0179] As described above, the semiconductor device of this embodiment is capable of detecting the operation in the kth frame and the operation in the k+1th frame. By repeating this operation, the time that the transistor is on is shortened. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment. By doing so, the life of these can be extended.

[0180] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to an N-channel type or a P-channel type. Therefore, the number of steps can be reduced compared to CMOS circuits. In particular, it is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. When all transistors, including the junctions, are N-channel, the semiconductor layer of the transistor and Examples of the semiconductor include a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, and an oxide semiconductor. However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of the present embodiment is capable of suppressing the deterioration of the transistor. It is possible.

[0181] Alternatively, the transistor may be degraded so that the semiconductor device can operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of the present embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0182] In FIG. 8B, the period T2 is shown as a selection period, and the other periods (period T1, period The periods T3, T4, and T5 can be referred to as non-selection periods. The periods T1, T2, T3, T4, and T5 are respectively a set period, an output period, and It may be indicated as a reset period, a first non-select period, and a second non-select period.

[0183] As shown in FIG. 14A, the signals CK, CK_1, CK_2, and CKB In signal _1 and signal CKB_2, the time when it becomes H level is shorter than the time when it becomes L level. By doing so, it is possible to set the signal CK to the L level during the period T2. When this occurs, the potential of node A remains high, so that transistor 201 remains on. Therefore, the wiring 211 and the wiring 111 are kept in electrical continuity through the transistor 201. Therefore, the L-level signal CK is transmitted from the wiring 211 to the wiring 111 via the transistor 201. The channel width of the transistor 201 is often large, so the potential of the wiring 111 Therefore, the fall time of the signal OUT can be shortened. However, the present invention is not limited to this, and the signals CK, CK_1, CK_2, and CKB can be used. In the signals CKB_1 and CKB_2, the time when the signal is at the H level is longer than the time when the signal is at the L level. It is possible.

[0184] As shown in FIG. 14B, during the period T2, the voltage V1 or the L level signal is By supplying the signal OUT to the node A and the wiring 111, the signal OUT can be set to the L level. This allows the drive frequency to be slowed down, reducing power consumption. It is possible to reduce this.

[0185] Note that as shown in FIG. 5A, the semiconductor device may have multiple circuits corresponding to the circuit 101 or the circuit 102. In the case where the semiconductor device has multiple clock signals, it is possible to input multiple clock signals into the semiconductor device. A) is an example of a timing chart when a three-phase clock signal is input to a semiconductor device. However, this is not limited to the above.

[0186] Note that as shown in FIG. 5B, the circuit 101 or the circuit 102 includes a plurality of transistors. In FIG. 15B, the circuit 101 or the circuit 102 includes three transistors. 1 shows an example of a timing chart for a case in which the input / output terminal 14 is provided, but the present invention is not limited to this.

[0187] The channel width of the transistor 201 is the same as that of the transistors 101_1 and 10 1_2, which is larger than the channel width of the transistor 102_1 and the transistor 102_2. This reduces the on-resistance of the transistor 201. Therefore, the rise time or fall time of the signal OUT can be shortened. However, the channel width of the transistor 201 is not limited to this. Transistor 101_2, transistor 102_1, and / or transistor 102_ It is possible for the channel width to be smaller than 2.

[0188] In the transistor 201, the parasitic capacitance between the gate and the second terminal is It is preferable that the parasitic capacitance between the first terminal and the second terminal is larger than the parasitic capacitance between the first terminal and the second terminal. This is because the potential of node A tends to become high due to the bootstrap operation. Therefore, a conductive layer functioning as a gate and a conductive layer functioning as a source or drain are It is preferable that the overlapping area on the second terminal side is larger than that on the first terminal side. However, , but is not limited to this.

[0189] As described in the first embodiment, the wiring can be divided into multiple wirings. The same signal or voltage can be input to the multiple wirings, and the same signal or voltage can be input to the multiple wirings. Alternatively, the plurality of wirings may be connected to the same wiring. or elements, and the plurality of wirings can be connected to separate wirings or elements. In FIG. 16A, the wiring 112 is connected to the The configuration shown is when the wiring is divided into a plurality of wirings 112A to 112D.

[0190] As in FIG. 16(A), the wiring is divided into a plurality of wirings in FIG. 7(B) and FIG. 8(A). In addition to the wiring 112, the wiring 114_1, the wiring 114_2, the wiring 114_3, the wiring 114_4, the wiring 114_5, the wiring 114_6, the wiring 114_7, the wiring 114_8, the wiring 114_9, the wiring 114_10, the wiring 114_11, the wiring 114_12, the wiring 114 14_2, the wiring 211, the wiring 211_1, the wiring 211_2, the wiring 212, and / or the wiring It is possible to split line 213 into multiple wires.

[0191] As shown in FIG. 16B, the first terminal of the transistor 101_1 and the The first terminals of the first terminal 101_2 are connected to the wiring 211_1 and the wiring 211_2, respectively. The first terminal of the transistor 102_1 and the second terminal of the transistor 102_2 may be connected to each other. The first terminals can be connected to the wiring 114_2 and the wiring 114_1, respectively. By doing so, similarly to FIG. 4B, the transistors 101_1 to 101_2, In addition, a reverse bias can be applied to the transistors 102_1 and 102_2. However, the present invention is not limited to this, and the deterioration of the transistors can be suppressed. a first terminal of the transistor 101_1, a first terminal of the transistor 101_2, and a first terminal of the transistor 10 The first terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to various wirings or For example, the first terminal of the transistor 101_1 may be connected to various nodes. The first terminal of the transistor 101_1 is connected to a node B2, and the second terminal of the transistor 101_2 is connected to a node B1. It is possible to do so.

[0192] As in FIG. 16B, in FIG. 7B and FIG. 8A, the transistor 1 The first terminal of the transistor 101_1 and the first terminal of the transistor 101_2 are each connected to a wiring 211. The first transistor 102_1 can be connected to the wiring 211_2. The terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to a wiring 114_1 and a wiring 114 It is possible to connect with _2.

[0193] As shown in FIG. 17A, between the gate and the second terminal of the transistor 201, It is possible to newly connect the capacitive element 202. In this way, the boot in the period T2 During the strap operation, the potential of node A can be increased. As the Vgs of 01 increases, the fall time or rise time of the signal OUT However, the length of the capacitance element 202 is not limited to this. It is possible to use a transistor as a MOS capacitor. In order to increase the capacitance of the transistor, the gate of the transistor is connected to node A. The first terminal or the second terminal of the transistor is preferably connected to the wiring 111. I wish.

[0194] As in FIG. 17(A), in FIG. 7(B), FIG. 8(A), and FIG. 16(A) to (B), Even if the transistor 201 is turned on, a capacitor 202 is newly connected between the gate and the second terminal of the transistor 201. It is possible to continue.

[0195] It is also possible to split the output signal into two. For example, one output signal is fed to another stage. It can serve as a signal for forwarding to a flip-flop (e.g., the next stage). The other output signal can function as a signal output to a pixel. As shown in FIG. 17B, a transistor 203 can be newly added. The transistor 203 has a function similar to that of the transistor 201 and is an N-channel transistor. A first terminal of the transistor 203 is connected to a wiring 211. The second terminal of the transistor 203 is connected to the wiring 212. It is connected to the gate of register 201.

[0196] However, the transistor 203 can be a P-channel type, without being limited thereto. Alternatively, the first terminal of the transistor 203 and the first terminal of the transistor 201 are Alternatively, the gate of the transistor 203 and the gate of the transistor 204 may be connected to different wirings. The gate of the transistor 201 can be connected to a separate wiring.

[0197] As shown in FIG. 18, in addition to the transistor 203, the circuit 231 and the circuit 23 The circuit 231 has a function similar to that of the circuit 101. The circuit 232 has a function similar to that of the circuit 102. The circuit 231 includes a transistor 231_ The circuit 232 includes a plurality of transistors, namely, a transistor 231_1 and a transistor 231_2. The second transistor 232_1 and the second transistor 232_2 are included. The transistor 231_1, the transistor 231_2, the transistor 232_1, and the transistor The transistor 232_2 corresponds to the transistor 101_1, the transistor 101_2, and the transistor 232_3. The transistor 102_1 corresponds to the transistor 102_2, and is assumed to be an N-channel type. The transistor 231_1, the transistor 231_2, the transistor 232_1, and the transistor A first terminal of the transistor 232_2 is connected to the wiring 112. 1, the transistor 231_2, the transistor 232_1, and the transistor 232_2 The second terminal is connected to the wiring 212. The gates of the transistors 232_1 and 232_2 are connected to the nodes B2, node B3, wiring 114_1, and wiring 114_2. However, this is not limited to this. The transistors 231_1, 231_2, and 232_1, And / or, the transistor 232_2 can be a P-channel type. , transistor 231_1, transistor 231_2, transistor 232_1, and / or Alternatively, the first terminal or the second terminal of the transistor 232_2 is connected to separate wirings. It is possible.

[0198] In FIG. 17B and FIG. 18, an output signal from the wiring 111 is supplied to the pixel. When the output signal from the wiring 212 is a signal for transfer, the transistor 20 The channel width of transistor 3 is preferably smaller than the channel width of transistor 201. In this case, the wiring 111 is connected to a gate line or a pixel, and the load of the wiring 111 is This is because the load of the wiring 1 is often larger than that of the wiring 212. The signal output from the wiring 211 is a signal for transfer, and the signal output from the wiring 212 is a signal for the pixel. When the signal is to be output, the channel width of the transistor 203 is It can be larger than the channel width.

[0199] In FIG. 17B and FIG. 18, an output signal from the wiring 111 is supplied to the pixel. When the output signal from the wiring 212 is a signal for transfer, the transistor 23 1_1, transistor 231_2, transistor 232_1, and transistor 232_ The channel width of transistor 101_1, transistor 101_2, and transistor 1 02_1, it is preferable that the channel width of the transistor 102_2 is smaller than that of the transistor 102_2. Since the wiring 111 is connected to a gate line or a pixel, the load of the wiring 111 is the same as that of the wiring 2. This is because the load is often larger than that of 12. However, this is not limited to this. transistor 231_1, transistor 231_2, transistor 232_1, and transistor 2 The channel width of transistor 101_1, transistor 101_2, transistor The channel width of the transistor 102_1 can be larger than that of the transistor 102_2.

[0200] 17B and 18, the gate and the second terminal of the transistor 203 are A capacitive element can be connected between them.

[0201] As in the case of FIG. 17(B) and FIG. 18, FIG. 7(B), FIG. 8(A), FIG. 16(A) to FIG. 17B) and FIG. 17A, the transistor 203, the circuit 231, and / or the circuit It is possible to add a new path 232.

[0202] As shown in FIG. 19(A), a P-channel transistor is used as the transistor. It is possible to use the transistor 101p_1, the transistor 101p_2, The transistor 102p_1, the transistor 102p_2, and the transistor 201p are Transistor 101_1, transistor 101_2, transistor 102_1, transistor The transistor 102_2 corresponds to the transistor 201 and is a P-channel type. When the polarity of the transistor is P-channel type, as shown in FIG. 19(B), the wiring 112 is connected to a voltage V 2 are supplied, and signals CK, CK_1, CK_2, CKB_1, and CKB_ 2. The potential Va, the potential Vb1, the potential Vb2, and the signal OUT are in accordance with the timing chart of FIG. In many cases, the trend is inverted compared to the chart.

[0203] As in FIG. 19(A), FIG. 7(B), FIG. 8(A), FIG. 16(A)-(B), FIG. In (A) to (B) and FIG. 18, the transistor is a P-channel transistor. It is possible to use a

[0204] (Embodiment 3) In this embodiment, a specific example of the circuit 300 described in the second embodiment will be described. The circuit 300 can be referred to as a semiconductor device, a driver circuit, or a gate driver. The contents described in the first and second embodiments will not be described here. The contents described in the first to second embodiments may be freely combined with the contents described in this embodiment. can be done.

[0205] First, an example of the circuit 300 will be described with reference to FIG. Transistor 301, transistor 302, transistor 303, transistor 304_1 , transistor 304_2, transistor 305_1, and transistor 305_2. However, the circuit 300 is not limited to this and may include various other Alternatively, the circuit 300 can omit any of these transistors. It is.

[0206] In addition, transistor 301, transistor 302, transistor 303, and transistor 3 04_1, transistor 304_2, transistor 305_1, and transistor 305 _2 is preferably of the same polarity as the transistor 201 and is an N-channel type. However, the present invention is not limited to this, and the transistors 301, 302, Transistor 303, transistor 304_1, transistor 304_2, transistor 305 _1 and transistor 305_2 can be P-channel type.

[0207] Next, an example of the connection relationship of the circuit 300 will be described. is connected to the wiring 212, the second terminal of the transistor 301 is connected to the node A, The gate of the transistor 301 is connected to the wiring 212. The first terminal of the transistor 302 is connected to the wiring 112, and the second terminal of the transistor 302 is connected to the node A. The gate of the transistor 302 is connected to the wiring 213. A first terminal of the transistor 303 is connected to a wiring 112, and a second terminal of the transistor 303 is connected to a wiring 111. The gate of the transistor 303 is connected to the wiring 213. A first terminal of the transistor 304_1 and a first terminal of the transistor 304_2 are connected to the wiring 212. The second terminal of the transistor 304_1 and the second terminal of the transistor 304_2 are connected to the node A. The gates of the transistors 304_1 and 304_2 are connected to the wiring 114. The transistor 305_1 and the transistor 305_2 are connected to the wiring 114_2. A first terminal of the transistor 305_1 and a second terminal of the transistor 305_2 are connected to the node A. A second terminal of the transistor 305_2 is connected to the wiring 111. The gates of the transistors 305_2 are connected to the wirings 211_1 and 211_2, respectively. However, the present invention is not limited to this, and various other connection configurations are possible.

[0208] Next, an example of the function of each transistor will be described. By controlling the conduction state between the wiring 212 and the node A in response to the signal SP, This has the function of controlling the timing at which the signal is supplied to node A and functions as a diode. In response to a signal RE, the transistor 302 is connected between the wiring 112 and the node A By controlling the conduction state between the The transistor 303 has a function of controlling the input voltage Vpp and can function as a switch. By controlling the conduction state between the wiring 112 and the wiring 111 in response to the signal RE, a voltage It has a function of controlling the timing when V1 is supplied to the wiring 111 and functions as a switch. The transistor 304_1 can be connected to the wiring 212 in response to the signal CKB_1. By controlling the conductive state between node A and node B, the timing at which the signal SP is supplied to node A is The transistor has a function of controlling the switching of the transistor. 304_2 controls the conduction state between the wiring 212 and the node A in response to the signal CKB_2. By this, the timing at which the signal SP is supplied to the node A can be controlled. The transistor 305_1 can function as a latch in response to a signal CK_1. The transistor 111 has a function of controlling the electrical continuity between the node A and the wiring 111 and functions as a switch. The transistor 305_2 is connected to the node A in response to a signal CK_2. It has a function of controlling the electrical connection with 111 and can function as a switch. However, this is not a limitation and these transistors can have various other functions. It is Noh.

[0209] Next, the operation of the semiconductor device in FIG. 21A will be described with reference to a timing chart in FIG. This will be explained in light of the above.

[0210] First, in the period T1 of the kth frame, the signal SP becomes H level, so that the transistor 301 turns on. At the same time, the signal CKB_1 becomes H level and the signal CKB_2 becomes L level. This causes transistor 304_1 to turn on and transistor 304_2 to turn off. Therefore, the wiring 212 and the node A are brought into electrical continuity, and the signal SP is applied to the wiring 212. is supplied to node A. Then, the potential of node A starts to rise. At this time, the signal C Since the signal CK_1 and the signal CK_2 are at the L level, the transistors 305_1 and Therefore, the node A and the wiring 111 are not electrically connected to each other. Since the signal RE is at the L level, the transistor 302 and the transistor 303 are turned off. Therefore, the wiring 112 and the node A are not in electrical continuity, and the wiring 112 and the wiring 111 Then, the potential of node A drops from the potential of the H-level signal SP (V2) to The value obtained by subtracting the threshold voltage (Vth301) of the transistor 301 from the When the potential of the node A becomes H level, the transistor 301 is turned off. The potential (V2) of the signal CKB_1 is converted into the threshold voltage (Vth304 When the voltage of the transistor 304_ Here, when the potential of node A becomes V2-Vth301, transistor 1 is turned off. The transistors 301 and 304_1 are turned off. A is not conductive. Then, node A is in a floating state, so the potential is V2-Vt Maintain at h301.

[0211] On the other hand, in the period T1 of the (k+1)th frame, the signal CKB_1 becomes L level, and the signal CK Since B_2 is at the H level, the transistor 304_1 is turned off and the transistor 30 The operation differs from that in period T1 of the kth frame in that 4_2 is turned on.

[0212] Next, in the period T2 of the kth frame, the signal SP becomes L level, so that the transistor 301 remains off. Then, the signal CKB_1 goes to the L level and the signal CKB_2 Since the signal remains at the L level, the transistors 304_1 and 304_2 are off. Therefore, the wiring 212 and the node A remain in a non-conductive state. Signal CK_1 becomes H level and signal CK_2 remains L level. However, node A The potential of the transistor 305_1 and the transistor 305_2 is V2+Vth201+β (β is a positive number). The transistor 305_2 remains off. Since the signal RE remains at the L level, the transistor 302 Therefore, the wiring 112 and the node A are not electrically connected to each other. Therefore, the wiring 112 and the wiring 111 remain in a non-conducting state.

[0213] On the other hand, during the period T2 of the (k+1)th frame, the signal CKB_1 remains at the L level. The difference from the operation in the kth frame period T2 is that the signal CKB_2 becomes H level. However, even in this case, the potential of node A becomes V2+Vth201+β, so the transistor 305_1 and transistor 305_2 remain off.

[0214] Next, in the k-th frame period T3, the signal SP remains at the L level. The counter 301 remains off. Then, the signal CKB_1 goes to the H level, and the signal CKB_ 2 remains at the L level, so the transistor 304_1 is turned on and the transistor 3 04_2 remains off. Therefore, the wiring 212 and the node A are brought into electrical continuity. A signal SP of L level is supplied from the wiring 212 to the node A. At this time, the signal CK_1 Since the signal CK_2 remains at the L level, the transistors 305_1 and The transistor 305_2 remains off. Then, the signal RE goes to H level, so that the transistors 302 and Therefore, electrical continuity between the wiring 112 and the node A is established. Then, the wiring 112 and the wiring 111 are brought into a conductive state. Then, the voltage V1 is applied from the wiring 112 to the A voltage is supplied to the terminal A, and a voltage V1 is supplied from the wiring 112 to the wiring 111.

[0215] On the other hand, in the period T3 of the (k+1)th frame, the signal CKB_1 becomes L level, and the signal CK Since B_2 is at the H level, the transistor 304_1 is turned off and the transistor 30 The operation differs from that in period T3 of the kth frame in that 4_2 is turned on.

[0216] Next, in the k-th frame period T4, the signal SP remains at the L level. The counter 301 remains off. Then, the signal CKB_1 goes to the L level, and the signal CKB_ 2 remains at the L level, so the transistor 304_1 is turned off and the transistor 3 Therefore, the wiring 212 and the node A are kept in a non-conductive state. At this time, the signal CK_1 becomes H level and the signal CK_2 remains L level. , transistor 305_1 turns on and transistor 305_2 remains off. Therefore, the node A and the wiring 111 are brought into electrical continuity. Then, the signal RE becomes an L level. Therefore, the transistor 302 and the transistor 303 are turned off. 2 and the node A are brought out of conduction, and the wiring 112 and the wiring 111 are brought out of conduction.

[0217] On the other hand, during the period T4 of the (k+1)th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 goes high, transistor 305_1 remains off and transistor The operation differs from that in the k-th frame period T4 in that the starter 305_2 is turned on.

[0218] Next, in the k-th frame period T5, the signal SP remains at the L level. The counter 301 remains off. Then, the signal CKB_1 goes to the H level, and the signal CKB_ 2 remains at the L level, so the transistor 304_1 is turned on and the transistor 3 04_2 remains off. Therefore, the wiring 212 and the node A are brought into electrical continuity. A signal SP of L level is supplied to node A. At this time, the signal CK_1 becomes L level. Since the signal CK_2 remains at the L level, the transistor 305_1 is turned off and the transistor The transistor 305_2 remains off. Therefore, the node A and the wiring 111 are not electrically connected to each other. Since the signal RE remains at the L level, the transistor 302 and the transistor Therefore, the wiring 112 and the node A are not electrically connected to each other. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state.

[0219] On the other hand, during the period T5 of the (k+1)th frame, the signal CKB_1 remains at the L level. Since the signal CKB_2 goes high, the transistor 305_1 remains off. The operation differs from that in the k-th frame period T5 in that the transistor 305_2 is turned on.

[0220] As described above, the semiconductor device of this embodiment is capable of detecting the operation in the kth frame and the operation in the k+1th frame. By repeating this operation, the time that the transistor is on is shortened. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment. By doing so, the life of these can be extended.

[0221] In particular, the transistors 304_1, 304_2, 305_1, and The transistor 305_2 has a period in which it remains off and a period in which it alternates between on and off. Therefore, the transistor is turned on for a shorter period of time, The deterioration of characteristics can be suppressed.

[0222] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to an N-channel type or a P-channel type. Therefore, the number of steps can be reduced compared to CMOS circuits. In particular, it is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. When all transistors, including the junctions, are N-channel, the semiconductor layer of the transistor and Examples of the semiconductor include a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, and an oxide semiconductor. However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of the present embodiment is capable of suppressing the deterioration of the transistor. It is possible.

[0223] Alternatively, the transistor may be degraded so that the semiconductor device can operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of the present embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0224] The channel width of the transistor 304_1 and the channel width of the transistor 304_2 are It is preferable that the channel width of the transistor 305_1 and the channel width of the transistor 305_2 are approximately equal. It is preferable that the channel width of the transistor 305_1 is approximately equal to that of the transistor 305_2. The transistor 304_1 and the transistor 304_2 have the same function. This is because the transistor 5_1 and the transistor 305_2 have the same function. The channel width of the transistor 304_1 is not determined, and the channel width of the transistor 304_2 is It can be larger or smaller than the width of transistor 3. The channel width of transistor 305_1 can be larger than the channel width of transistor 305_2. And it is possible to make it small.

[0225] The channel width of the transistor 303 is larger than that of the transistor 302. This is because the load of the wiring 111 may be larger than the load of the node A. However, the channel width of the transistor 303 is not limited to this. It may be smaller than the channel width of the transistor 302 .

[0226] Note that some of the transistors included in the circuit 300 can be omitted. It is possible to omit either the transistor 305_1 or the transistor 305_2. In this case, the other gate of the transistor 305_1 and the transistor 305_2 is connected to a signal CK can be input. In FIG. 21B, the transistor 305_2 is omitted. However, the present invention is not limited to this, and various other transistors may be omitted. For example, both the transistor 305_1 and the transistor 305_2 can be Alternatively, the transistor 304_1 and the transistor 304_2 may be omitted. In this case, either the transistor 304_1 or the transistor A signal CKB can be input to the other gate of the input terminal 304_2. It is possible to omit both the transistor 304_1 and the transistor 304_2. Alternatively, the transistor 302 can be omitted. It is possible to omit 3.

[0227] As shown in FIG. 5B of the first embodiment, the circuit 101 and the circuit 102 are each configured with m transistors. In the case where the transistor 304 is a MOSFET, as shown in FIG. A number of transistors, 305_1 to 305_m, are connected to the It is possible to have a plurality of transistors. corresponds to the transistor 304_1 or the transistor 304_2, and the transistor 305 _1 to 305_m correspond to the transistor 305_1 or the transistor 305_2.

[0228] As in FIG. 22A, the circuit 300 in FIG. 21B also includes a transistor 3 Several transistors named 04_1 to 304_m and transistors 305_1 to 305_ It is possible to have a number of transistors, number m.

[0229] As shown in FIG. 22B, the transistor 305_1 and the transistor 305_ The first terminal of the transistor 2 is connected to the wiring 112, and the transistor 305_1 and the transistor The gates of 305_2 may be connected to nodes B1 and B2, respectively. However, the present invention is not limited to this, and the first transistor 305_1 and the first transistor 305_2 may be The first terminal can be connected to the wiring 114_2 and the wiring 114_1, respectively. Alternatively, the first terminals of the transistors 305_1 and 305_2 may be The line 211_2 can be connected to the wiring 211_1. Alternatively, the transistor 3 05_1, and the first terminal of the transistor 305_2 are connected to the node B2, the node B1, It is possible to connect with.

[0230] As in FIG. 22(B), the transistors in FIG. 21(B) and FIG. 22(A) are A first terminal of the transistor 305_1 and a first terminal of the transistor 305_2 are connected to the wiring 112. The gates of the transistors 305_1 and 305_2 are connected to nodes B1 and B2, respectively. It is possible to connect to board B2.

[0231] As shown in FIG. 23A, the first terminal of the transistor 301 is connected to the wiring 214. A voltage V2 is supplied to the wiring 214, and the wiring 214 is connected to a power supply However, the wiring 214 can function as a line. A signal that goes to H level at T1 can be input.

[0232] As in FIG. 23(A), in FIG. 21(B) and FIG. 22(A)-(B), A first terminal of the transistor 301 can be connected to the wiring 214 .

[0233] As shown in FIG. 23(B), a P-channel transistor is used as the transistor. It is possible that the transistor 301p, the transistor 302p, and the transistor 3 03p, transistor 304_1p, transistor 304_2p, transistor 305_ The transistors 301, 305_1p and 305_2p correspond to the transistors 301, 30 2, transistor 303, transistor 304_1, transistor 304_2, The transistors 305_1 and 305_2 are P-channel types. When the polarity of the transistor is a P-channel type, as shown in FIG. , a voltage V2 is supplied, and signals CK, CK_1, CK_2, CKB_1, and CKB_2, potential Va, and signal OUT are as follows, compared to the timing chart of FIG. Often it is inverted.

[0234] As in FIG. 23(B), FIG. 21(B), FIG. 22(A)-(B), and FIG. 23(A) In the above, it is possible to use a P-channel transistor as the transistor. .

[0235] (Embodiment 4) In this embodiment, a specific example of the circuit 400 described in the second embodiment will be described. The circuit 400 can be referred to as a semiconductor device, a driver circuit, or a gate driver. The contents described in the first and second embodiments will not be described here. The contents described in the first to third embodiments may be freely combined with the contents described in this embodiment. can be done.

[0236] First, an example of a circuit 400 will be described with reference to FIG. Transistor 401_1, transistor 401_2, transistor 402_1, The capacitor 402_2, the capacitor 403_1, and the capacitor 403_2 are provided. Without being limited thereto, the circuit 400 may have various other configurations. 400 may omit any of these transistors or capacitors.

[0237] In addition, the transistor 401_1, the transistor 401_2, the transistor 402_1, and and transistor 402_2 are preferably of the same polarity as transistor 201, However, the present invention is not limited to this, and the transistor 401_1, The transistor 401_2, the transistor 402_1, and the transistor 402_2 are P-channel The optical fiber may be of the channel type.

[0238] Next, an example of the connection relationship of the circuit 400 will be described. The first terminal of the transistor 401_1 is connected to the wiring 112, and the second terminal of the transistor 401_1 is connected to a node B1. The gate of the transistor 401_1 is connected to the node A. A first terminal of the transistor 401_2 is connected to the wiring 112, and a second terminal of the transistor 401_2 is connected to the wiring 112. is connected to node B2, and the gate of the transistor 401_2 is connected to node A. A first terminal of the transistor 402_1 is connected to the wiring 112. A second terminal of the transistor 402_1 is connected to a node B1. A gate of the transistor 402_1 is connected to a wiring A first terminal of the transistor 402_2 is connected to the wiring 112. The second terminal of the transistor 402_2 is connected to the node B2. A gate of the capacitor 403_2 is connected to the wiring 211_1. The other electrode of the capacitor 403_1 is connected to the wiring 211_1, and the other electrode of the capacitor 403_1 is connected to the node B1. One electrode of the capacitor 403_2 is connected to the wiring 211_2. The other electrode of the second electrode is connected to node B2. However, this is not limited to this, and various other A connection configuration is possible.

[0239] Next, an example of the functions of each transistor and each capacitor will be described. The transistor 401_1 controls the conduction state between the wiring 112 and the node B1 in response to the potential of the node A. By controlling the input of the MOSFET, the timing at which the voltage V1 is supplied to the node B1 can be controlled. The transistor 401_2 can be connected to the node A. By controlling the conduction state between the wiring 112 and the node B2 according to the potential, the voltage V1 The function of controlling the timing at which the signal is supplied to node B2 is to function as a switch. The transistor 402_1 is connected to the wiring 112 and the node 113 in response to a signal CK_2. By controlling the conduction state between the node B1 and the Transistor 4 has a function of controlling the switching of the transistor. 02_2 controls the conduction state between the wiring 112 and the node B2 in response to the signal CK_1. By this, the timing at which the voltage V1 is supplied to the node B2 is controlled. The capacitance element 403_1 can function as a latch in response to the signal CK_1. The capacitor 403_2 has a function of controlling the potential of the node B1. However, the present invention is not limited to this, and these transistors have a function of controlling the potential of the node B2. The transistors and capacitors can have a variety of other functions.

[0240] Next, the operation of the semiconductor device in FIG. 24A will be described with reference to a timing chart in FIG. This will be explained in light of the above.

[0241] First, in the period T1 of the kth frame, the potential of node A is set to a high value (for example, (V2-Vt h301), so the transistors 401_1 and 401_2 are turned on. At this time, the signal CK_1 becomes L level and the signal CK_2 becomes L level, so The transistor 402_1 and the transistor 402_2 are turned off. Electrical continuity is established between the wiring 112 and the node B2. The voltage V1 is supplied from the wiring 112 to the node B1, and the voltage V1 is supplied from the wiring 112 to the node B2. are supplied to.

[0242] Next, in the period T2 of the kth frame, the potential of node A becomes high (for example, (V2+Vt h201+α)), the transistor 401_1 and the transistor 401_2 are on. At this time, the signal CK_1 becomes H level and the signal CK_2 becomes L level. Therefore, transistor 402_1 remains off and transistor 402_2 remains off. Therefore, the wiring 112 and the node B1 remain in a conductive state, and the wiring 112 Then, the voltage V1 flows from the wiring 112 to the node B1. and a voltage V1 is supplied from a wiring 112 to a node B2.

[0243] On the other hand, during the period T2 of the (k+1)th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes H level, the transistor 402_1 is turned on and the transistor 4 The operation differs from that in period T2 of the kth frame in that 02_2 is turned off.

[0244] Next, in the k-th frame period T3, the potential of node A becomes V1, so that the transistor At this time, the signal CK_1 is at the L level. Since the signal CK_2 remains at the L level, the transistor 402_1 is turned off. Therefore, the wiring 112 and the node B1 are connected to each other. The wiring 112 and the node B2 are brought out of conduction. 403_1 receives an L-level signal CK_1 (the potential of the wiring 211_1) and V1 (the potential of the node B A potential difference between the potential of the capacitor 403_1 and the potential of the capacitor 403_2 is maintained. The potential difference between CK_2 (the potential of the wiring 211_2) and V1 (the potential of the node B2) is maintained. do.

[0245] Next, in the k-th frame period T4, the potential of node A remains at V1. At this time, the signal CK_1 remains off. becomes H level and the signal CK_2 remains L level, so that the transistor 402_1 Therefore, the wiring 112 and the node The wiring 112 and the node B2 are brought into a conductive state. A voltage V1 is supplied to the node B2 from the wiring 112. As a result, the node B1 is in a floating state. Therefore, when the signal CK_1 changes from the L level to the H level, the capacitance of the capacitive element 403_1 The coupling causes the potential at node B1 to rise.

[0246] On the other hand, during the period T4 of the (k+1)th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes H level, the transistor 402_1 is turned on and the transistor 4 The difference from the k-th frame period T4 is that 02_2 remains off. The wiring 112 and the node B1 are brought into electrical continuity, and the wiring 112 and the node B2 are brought into electrical continuity. Then, the voltage V1 is supplied to the node B1 from the wiring 112. As a result, the node B2 Therefore, when the signal CK_2 changes from the L level to the H level, the capacitance element 40 The potential of node B2 increases due to the capacitive coupling of 3_2.

[0247] Next, in the k-th frame period T5, the potential of node A remains at V1. At this time, the signal CK_1 remains off. becomes L level, and the signal CK_2 remains at L level, so that the transistor 402_1 Therefore, the wiring 112 and the node This brings the wiring 112 and the node B2 into a non-conductive state. Therefore, when the signal CK_1 goes from H level to L level, the nodes B1 and B2 go into a floating state. When the potential of the node B1 reaches the level, the potential of the node B1 decreases due to the capacitive coupling of the capacitor 403_1. However, since the signal CK_1 remains at the L level, the potential of the node B1 remains at V1. .

[0248] On the other hand, in the period T5 of the (k+1)th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes an L level, the potential of the node B2 is lowered by the capacitive coupling of the capacitor 403_2. The difference from the k-th frame period T5 is that the potential of the node B1 decreases by This differs from the period T5 of the k-th frame in that it remains at V1.

[0249] As described above, the semiconductor device of this embodiment is capable of detecting the operation in the kth frame and the operation in the k+1th frame. By repeating this operation, the time that the transistor is on is shortened. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment. By doing so, the life of these can be extended.

[0250] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to an N-channel type or a P-channel type. Therefore, the number of steps can be reduced compared to CMOS circuits. In particular, it is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. When all transistors, including the junctions, are N-channel, the semiconductor layer of the transistor and Examples of the semiconductor include a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, and an oxide semiconductor. However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of the present embodiment is capable of suppressing the deterioration of the transistor. It is possible.

[0251] Alternatively, the transistor may be degraded so that the semiconductor device can operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of the present embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0252] The channel width of the transistor 401_1 and the channel width of the transistor 401_2 are are preferably approximately equal to the channel width of the transistor 402_1. The channel width of the transistor 402_1 is preferably approximately equal to that of the transistor 402_2. The capacitance value of the capacitance element 403_1 or the area where one electrode and the other electrode overlap, and the capacitance element 4 The capacitance of 03_2 or the area where one electrode overlaps with the other electrode is approximately equal. It is preferable that the transistor 401_1 and the transistor 401_2 have the same The transistor 402_1 and the transistor 402_2 have the same function. This is because the capacitor 403_1 and the capacitor 403_2 have the same function.

[0253] The channel width of the transistor 401_1 is smaller than that of the transistor 402_1. Alternatively, the channel width of the transistor 401_2 is preferably larger than that of the transistor 401_1. It is preferable that the channel width of the first sigma-based ... The channel width of the transistor 401_1 is smaller than the channel width of the transistor 402_1. Alternatively, the channel width of the transistor 401_2 can be It is possible that the channel width of 402_2 is smaller.

[0254] As shown in FIG. 24B, the wiring 112 may be divided into a plurality of wirings 112G to 112J. It is possible to divide the transistor 401_1, the transistor 401_2, The first terminals of the transistors 402_1 and 402_2 are connected to the wiring 112G and The wiring 112H, the wiring 112I, and the wiring 112J are connected. It corresponds to the wiring 112. Therefore, the voltage V1 can be supplied to the wirings 112G to 112J. It is possible, and the wirings 112G to 112J can function as power supply lines. However, the present invention is not limited to this, and signals can be input to the wirings 112G to 112J. In this case, the wirings 112G to 112J can function as signal lines. In other words, it is possible to supply different signals or different voltages to the wirings 112G to 112J. be.

[0255] As shown in FIG. 24C, the transistor 401_1 and the transistor 402_ A first terminal of the transistor 401_1 is connected to a wiring 211_2, and a second terminal of the transistor 401_2 is connected to a wiring 211_3. A first terminal of the stator 402_2 can be connected to the wiring 211_1. When the transistor is turned off, the first terminal of the transistor is connected to the A clock signal is input to the transistor. Therefore, a reverse bias can be applied to the transistor. Therefore, deterioration of the characteristics of the transistor can be suppressed. The first terminals of the transistors 401_1 and 402_1 are connected to the wiring 1. 14_2, and the first terminals of the transistors 401_2 and 402_2 are connected to The terminal can be connected to the wiring 114_1. Even in this case, the reverse bias Since the voltage is applied to the transistor, deterioration of the transistor characteristics can be suppressed. The first terminals of the transistor 401_1 and the transistor 401_2 are connected to the wiring 112. It is possible to continue.

[0256] As shown in FIG. 25A, the transistor 402_1 and the transistor 402_ It is possible to omit 2.

[0257] As in FIG. 25(A), in FIGS. 24(B) to 24(C), the transistor 402 1, and the transistor 402_2 can be omitted.

[0258] As shown in FIG. 25B, a MOS capacitor can be used as the capacitance element. The transistor 403a_1 and the transistor 403a_2 are N-channel transistors. In many cases, the first terminal of the transistor 403a_1 and the second terminal of the transistor 403a_2 function as a MOS capacitor. The second terminal of the transistor 403a_1 is connected to the node B1, and the gate of the transistor 403a_1 is connected to the wiring 211. The first and second terminals of the transistor 403a_2 are connected to a node B 2, and the gate of the transistor 403a_2 is connected to the wiring 211_2. By doing so, the transistor 403a_1 and the transistor 403a_2 are charged. This makes it easier for a channel region to form, allowing the capacitance value to be increased.

[0259] As in FIG. 25(B), the capacity is also shown in FIGS. 24(B) to 24(C) and FIG. 25(A). As the capacitance element, a MOS capacitor can be used.

[0260] As shown in FIG. 5B of the first embodiment, the circuit 101 and the circuit 102 are each configured with m transistors. In the case where the transistor 401_1 is provided, as shown in FIG. A plurality of transistors 402_1 to 402_m; The semiconductor device includes a plurality of transistors and a plurality of capacitance elements 403_1 to 403_m. However, the present invention is not limited to this, and the transistors 402_1 to 402_m can be It is possible to omit it.

[0261] As in FIG. 25(C), in FIGS. 24(B) to (C) and FIG. 25(A) to (B), However, the semiconductor device includes a plurality of transistors 401_1 to 401_m. A plurality of transistors 402_1 to 402_m and a capacitance element 403_ It is possible to have a number of capacitance elements ranging from 1 to 403_m.

[0262] As shown in FIG. 25(D), a P-channel transistor is used as the transistor. It is possible to use the transistor 401_1p, the transistor 401_2p, The transistor 402_1p and the transistor 402_2p are , the transistor 401_2, the transistor 402_1, and the transistor 402_2. In the case where the polarity of the transistor is a P-channel type, As shown in (B), a voltage V2 is supplied to the wiring 112, and signals CK, CK_1, The signals CK_2, CKB_1, CKB_2, the potential Va, and the signal OUT are shown in FIG. In many cases, the timing is reversed compared to the timing chart in B).

[0263] As in FIG. 25(D), in FIGS. 24(B) to (C) and FIGS. 25(A) to (C), However, it is possible to use a P-channel transistor as the transistor.

[0264] (Embodiment 5) In this embodiment, an example of a shift register will be described. The system can include the semiconductor device according to the first to third embodiments. The soft resistor can be referred to as a semiconductor device or a gate driver. The contents described in the first to fourth embodiments will not be described. The contents described in the fourth embodiment can be freely combined with the contents described in this embodiment. do.

[0265] First, an example of a shift register will be described with reference to FIG. Multiple flip-flops named 501_1 to 501_N (N is a natural number) has.

[0266] The flip-flops 501_1 to 501_N are the same as those in the first to fourth embodiments, respectively. The semiconductor device in FIG. 26 corresponds to the semiconductor device described in the section 1. The semiconductor device shown in FIG. 7A is used as the semiconductor device 1_N. The flip-flops 501_1 to 501_N are not limited to those described in the first to fifth embodiments. The semiconductor device or circuit described in the fourth embodiment or various other semiconductor devices or circuits It is possible to use the path.

[0267] Next, the connection relationship of the shift register will be described. ~511_N, wiring 512, wiring 512_1, wiring 512_2, wiring 513, wiring 513 _1, wiring 513_2, wiring 514, wiring 515, and wiring 516 are connected. In the flip-flop 501_i (i is any one of 1 to N), the wiring 111, the wiring 21 1, wiring 211_1, wiring 211_2, wiring 114_1, wiring 114_2, wiring 112, The wiring 212 and the wiring 213 are respectively designated as wiring 511_i, wiring 512, wiring 512_1, Wiring 512_2, wiring 513_1, wiring 513_2, wiring 514, wiring 511_i-1, The odd-numbered flip-flops and the even-numbered flip-flops are connected to the wiring 511_i+1. In the flip-flop, the wiring 211, the wiring 211_1, the wiring 211_2, the wiring 114_1, In many cases, the connection destination of the wiring 114_2 is different. For example, in the i-th stage (i is one of 1 to N), In the first flip-flop, the wiring 211, the wiring 211_1, the wiring 211_2, the wiring 1 14_1, and the wiring 114_2 are respectively the wiring 512, the wiring 512_1, and the wiring 512_2. In this case, the flip-flop in the (i+1)th stage is connected to the wiring 513_1 and the wiring 513_2. In the flip-flop of the (i-1)th stage, the wiring 211, the wiring 211_ 1, the wiring 211_2, the wiring 114_1, and the wiring 114_2 are respectively the wiring 513, the wiring 513_1, the wiring 513_2, the wiring 512_1, and the wiring 512_2 are connected.

[0268] In addition, in the flip-flop 501_1, the wiring 212 may be connected to the wiring 515. In the flip-flop 501_N, the wiring 213 is connected to the wiring 516. In many cases

[0269] Next, an example of a signal or voltage input to or output from each wiring will be described. For example, signals GOUT_1 to GOUT_N are output from the inputs 1 to 511_N, respectively. The signals GOUT_1 to GOUT_N are respectively output from flip-flops 501_1 The signals GOUT_1 to GOUT_N are output signals of the signals OU Corresponding to T, output signal, selection signal, transfer signal, start signal, reset signal, gate signal The wiring 512, the wiring 512_1, and the wiring 512_2 can function as a scanning signal. For example, the line 512_2 is connected to the signals GCK, GCK_1, and GCK_2, respectively. The signal GCK corresponds to the signal CK or the signal CKB, and is a clock signal. The signal GCK_1 can function as a signal CK_1 or a signal CKB. The signal GCK_1 corresponds to the signal GCK_2, which can function as a clock signal. CK_2, or signal CKB_2, and can function as a clock signal. For example, the wiring 513, the wiring 513_1, and the wiring 513_2 are each connected to a signal GC Assume that the following signals are input: GCKB, signal GCKB_1, and signal GCKB_2. It corresponds to the signal CK or the signal CKB and can function as an inverted clock signal. The signal GCKB_1 corresponds to the signal CK_1 or the signal CKB_1, and is an inverted clock signal The signal GCKB_2 can function as the signal CK_2 or the signal CKB_3. The wiring 514 corresponds to the clock signal _2 and can function as an inverted clock signal. As an example, a voltage V1 is supplied to the wiring 515. As an example, a signal GSP The signal GSP corresponds to the signal SP and is a start signal or a vertical sync signal. The wiring 516 can function as a timing signal. For example, the signal GRE is input to the wiring 516. The signal GRE corresponds to the signal RE and functions as a reset signal. However, this is not the only possible case. These wirings can also carry various other signals, It is possible to input various voltages or various currents.

[0270] The wirings 511_1 to 511_N are used as signal lines, gate lines, scanning lines, or output signal lines. The wiring 512, the wiring 512_1, and the wiring 512_2 are capable of functioning as a signal The wiring 513 can function as a signal line, a clock signal line, or a clock signal line. 1 and the wiring 513_2 can function as a signal line or a clock signal line. The wiring 514 can function as a power supply line or a ground line. The wiring 516 can function as a signal line. However, this is not a limitation and these wirings can be used with various other types of wirings. It is possible for the system to function as such.

[0271] In addition, the wiring 512, the wiring 512_1, the wiring 512_2, the wiring 513, the wiring 513_1, A signal or The circuit 520 inputs a signal or a voltage to the shift register. By supplying the shift register with the signal, the shift register can be controlled. It is possible for the device to function as a controller, etc.

[0272] Note that the circuit 520 includes, for example, a circuit 521 and a circuit 522. The circuit 521 generates power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage. The circuit 52 has a function of supplying a power to the power supply circuit or a regulator. 2 is a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a It has the function of generating various signals such as video signals and functions as a timing generator. However, the present invention is not limited to this. The circuit 520 may be a circuit 521 or a circuit 522. In addition to the circuit 22, various circuits or elements may be included. For example, the circuit 52 0 is an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, AD conversion circuit, operational amplifier, shift register, look-up table, coil, transistor The input may include a resistor, a capacitance element, a resistance element, and / or a frequency divider.

[0273] Next, the operation of the shift register in FIG. 26 will be described with reference to the timing chart in FIG. 27. FIG. 27 is an example of a timing chart for explaining the operation of the shift register. FIG. 27 shows the signals GSP, GRE, GCK, GCK_1, and GC K_2, signal GCKB, signal GCKB_1, signal GCKB_2, signal GOUT_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal GOUT_N An example will be shown. The operations of the semiconductor devices according to the first to fourth embodiments are the same as those of the first to fourth embodiments. , the explanation of which will be omitted.

[0274] The operation of the flip-flop 501_i will be described. First, when the signal GOUT_i-1 is H, Then, the flip-flop 501_i starts its operation in the period T1. Then, the signal GOUT_i becomes L level. Then, the signals GCK and GCKB are inverted. Then, the flip-flop 501_i starts its operation in the period T2, and the signal GOU T_i becomes H level. The signal GOUT_i is reset to the flip-flop 501_i-1. The input signal is input to the flip-flop 501_i+1 as a start signal. Therefore, the flip-flop 501_i-1 starts the operation in the period T3. , the flip-flop 501_i+1 starts operation in the period T1. Then, the signal The GCK and GCKB signals are inverted again. Then, the flip-flop 501_i+1 The operation in the period T2 starts, and the signal GOUT_i+1 becomes H level. _i+1 is input to the flip-flop 501_i as a reset signal. , the flip-flop 501_i starts operating in the period T3, so that the signal GOUT_ After that, the signal GOUT_i-1 goes to the H level again. The flip-flop 501_i is inverted every time the signals GCK and GCKB are inverted during the period T4. The operation in period T3 and the operation in period T5 are repeated.

[0275] In addition, in the flip-flop 501_1, instead of the output signal of the previous stage flip-flop, In addition, the signal GSP is input from the circuit 520 through the wiring 515. When it becomes the H level, the flip-flop 501_1 starts the operation in the period T1.

[0276] In addition, in the flip-flop 501_N, instead of the output signal of the next stage flip-flop, The signal GRE is input from the circuit 520 through the wiring 516. When it becomes the H level, the flip-flop 501_N starts the operation in the period T3.

[0277] The operation of the shift register of this embodiment has been described above. By using the semiconductor device according to the first to fourth embodiments, It is possible to obtain the same advantages as the device.

[0278] It is possible to make the relationship between the signal GCK and the signal GCKB unbalanced. For example, FIG. As shown in the timing chart of 28(A), in the signals GCK and GCKB, It is possible to make the period when the signal is at the H level shorter than the period when the signal is at the L level. This prevents delays or distortions in the signals GOUT_1 to GOUT_N. It is possible to prevent a period during which these signals are simultaneously at H level. When a shift register of this type is used in a display device, it is necessary to prevent multiple rows from being selected at the same time. However, the present invention is not limited to this, and may be implemented by using the signal GCK and / or the signal GCKB. In this case, the period during which the signal is at the H level can be longer than the period during which the signal is at the L level.

[0279] It is possible to input multi-phase clock signals to the shift register. For example, see Figure 2. As shown in the timing chart of 8(B), a clock signal with M phases (M is a natural number) is used. In this case, in a certain stage of the signals GOUT_1 to GOUT_N, The period when the signal is at the H level in one stage may overlap with the period when the signal is at the H level in the previous or next stage. Therefore, when this embodiment is used in a display device, multiple rows can be selected at the same time. This causes the video signal to the pixels in the other rows to be selected as the precharge voltage. It becomes possible to use it.

[0280] In FIG. 28(B), it is preferable that M≦8. More preferably, M≦6. It is more preferable that M≦4. When the register is used in a scanning line driving circuit of a display device, if M is too large, the pixels may be overlapped. This is because several kinds of video signals are written to the pixel. This is because the period during which the signal is input becomes longer, which may result in a decrease in display quality.

[0281] As in FIG. 28(B), the timing chart in FIG. 28(A) also shows the multi-phase clock. A lock signal may be used.

[0282] It should be noted that the wiring 516 can be shared with other wiring or can be omitted. 516 is a wiring 512, a wiring 512_1, a wiring 512_2, a wiring 513, a wiring 513_1 , it can be shared with the wiring 513_2, the wiring 514, or the wiring 515. In this case, the wiring 516 is omitted, and in the flip-flop 501_N, the wiring 516 is 512, wiring 512_1, wiring 512_2, wiring 513, wiring 513_1, wiring 513_ 2, wiring 514, or wiring 515. 16 may be omitted. In this case, in the flip-flop 501_N, The transistor 302 and the transistor 303 may be omitted.

[0283] It is possible to add new wiring. For example, as a flip-flop, When a configuration that requires voltage V2 is used, such as 3(A), a new wiring is added. It is possible to supply the voltage V2 to the wiring. However, the present invention is not limited to this, and various wirings may be newly added depending on the configuration of the flip-flop. It is possible to reduce the number of wirings and to omit wiring.

[0284] It is possible to divide the output signal as shown in Fig. 29. In the example of Fig. 29, The semiconductor device shown in FIG. 17B is used as each of the flip-flops 501_1 to 501_N. In the flip-flop 501_i, the wiring 111, the wiring 211, the wiring 211 _1, wiring 211_2, wiring 114_1, wiring 114_2, wiring 112, wiring 212, wiring The line 213 and the wiring 212 are respectively a wiring 511_i, a wiring 512, a wiring 512_1, and a wiring The line 512_2, the wiring 513_1, the wiring 513_2, the wiring 514, the wiring 517_i-1, The line 511_i+1 is connected to the wiring 517_i. Even if a load such as a pixel or a gate line is connected to 1 to 511_N, the flip-flop of the next stage There is no distortion or delay in the transfer signal for driving the flop-flop. This can reduce the effect of delay in the shift register. The line 212 can be connected to the line 511_i-1. Or, the line 213 can be connected to the line 511_i-1. , it can be connected to wiring 517_i+1.

[0285] (Embodiment 6) In this embodiment, an example of a display device will be described.

[0286] First, with reference to FIG. 30(A), an example of a system block of a liquid crystal display device will be described. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, 2, a pixel portion 5364, a circuit 5365, and a lighting device 5366. In the example shown in FIG. 5, a plurality of wirings 5371 are arranged extending from a circuit 5362, and a plurality of wirings 5372 are arranged in a circuit. The circuit 5363_1 and the circuit 5363_2 are arranged to extend from each other. At the intersections of the line 5371 and the multiple wirings 5372, display elements such as liquid crystal elements are provided. Pixels 5367 corresponding to the pixel area are arranged in a matrix.

[0287] In response to a video signal 5360, a circuit 5361 is connected to a circuit 5362, a circuit 5363_1, a circuit 5364, a circuit 5365, a 363_2 and the circuit 5365, and has a function of supplying a signal, a voltage, a current, or the like to the controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a 362 is a signal line driver circuit start signal (SSP), a signal line driver circuit clock signal ( SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (DA TA), and a latch signal (LAT). Then, a start signal for the scanning line driver circuit (G SP), a clock signal for the scanning line driving circuit (GCK), and an inverted clock for the scanning line driving circuit Alternatively, the circuit 5361 may supply a signal (GCKB) to the circuit 5365. The BLC signal is provided by the circuit. 5361 also transmits various signals, various voltages, or various currents to a circuit 5362, a circuit It is possible to supply the signal to a circuit 5363_1, a circuit 5363_2, and a circuit 5365.

[0288] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB , DATA, LAT) to output video signals to a plurality of wirings 5371. The circuit 5363_1 and the circuit 536 3_2 runs according to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. In response to a signal (BLC) supplied from the circuit 5361, the circuit 5365 By controlling the amount or time of power supplied to the lighting device 5366, the lighting device It has the function of controlling the brightness (or average brightness) of the 5366 and can function as a power supply circuit. It is possible.

[0289] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wirings 53 can function as lines, video signal lines, source lines, or the like. When a scanning signal is input to 72, the multiple wirings 5372 are signal lines, scanning lines, or gate It can function as, but is not limited to, a line.

[0290] Note that the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2. In this case, the circuit 5363_1 outputs a scanning signal to a plurality of wirings 5372, and the circuit 5363 The timing of the scanning signals output from _2 to the multiple wirings 5372 is approximately the same. Therefore, the loads driven by the circuits 5363_1 and 5363_2 are often small. Therefore, the display device can be made larger. Alternatively, the circuit 5363_1 and the circuit 5363_2 may have a high resolution. Since the channel width of the transistor can be reduced, a display device with a narrow frame can be obtained. However, the present invention is not limited to this. The circuit 5361 can be implemented by a circuit 5363_1 and a circuit 536 It is possible to supply separate signals to 3_2 and 3_3.

[0291] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted.

[0292] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. It is possible. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0293] Note that the pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, the display element can emit light as shown in FIG. 365 and the lighting device 5366 may be omitted. In order to supply power, a plurality of wirings 5373 capable of functioning as power supply lines are provided in the pixel portion 53 64. Circuit 5361 distributes a power supply voltage called voltage (ANO). The wiring 5373 is connected to each color element of the pixel. It is possible for one pixel to be connected to the other pixel, or it is possible for one pixel to be connected in common to all pixels.

[0294] Note that in FIG. 30B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2 is supplied with separate signals. Start signal (GSP1), clock signal for the scanning line driving circuit (GCK1), and The inverted clock signal (GCKB1) for the operating circuit and other signals are supplied to the circuit 5363_1. The circuit 5361 outputs a start signal (GSP2) for the scanning line driver circuit, Clock signal (GCK2), inverted clock signal for scanning line driver circuit (GCKB2), etc. The circuit 5363_1 supplies the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings of the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, the power consumption can be reduced. Alternatively, the area in which one flip-flop can be laid out can be increased. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 30A, the circuit 5361 can be It is possible to output the same signal to the circuit 5363_1 and the circuit 5363_2.

[0295] 30B, the circuit 5361 in FIG. 30A is the same as the circuit 5363 in FIG. It is possible to supply separate signals to circuit 5363_1 and circuit 5363_2.

[0296] An example of the system block of the display device has been described above.

[0297] Next, an example of the configuration of the display device will be described with reference to FIGS. This will be explained with reference to E).

[0298] In FIG. 31A, a circuit having a function of outputting a signal to a pixel portion 5364 (for example, a circuit 5 362, a circuit 5363_1, and a circuit 5363_2, etc.) are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Since the number of signals or voltages input to the board 5380 is reduced, the board 5380 and the external components can be connected more efficiently. The number of connections can be reduced, which improves reliability and yield. can.

[0299] In addition, when the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta PE Automated Bonding (FPC) method Alternatively, the substrate may be implemented in a printed circuit board (PCB). 5364 is mounted on the same substrate 538 as the pixel part 5364 by the COG (Chip on Glass) method. It is possible to implement 0.

[0300] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is preferably made of a single crystal semiconductor. Therefore, a transistor formed on the substrate can be formed. The circuit has the advantages of improved drive frequency, improved drive voltage, and reduced output signal variation. You can get the points.

[0301] In addition, a signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0302] In FIG. 31B, a circuit with a low driving frequency (for example, a circuit 5363_1, a circuit 5363_ 2) is formed on the same substrate 5380 as the pixel portion 5364. The circuit 5362 is formed on a substrate different from that of the pixel portion 5364. The transistors make it possible to configure the circuits formed on the substrate 5380. For the semiconductor layer of the transistor, a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, It is possible to use an organic semiconductor, an oxide semiconductor, or the like. It is possible to achieve larger size, a reduction in the number of steps, a reduction in costs, and an improvement in yield.

[0303] As shown in FIG. 31C, a part of the circuit 5362 (a circuit 5362a) is The remaining circuit 5362 (circuit 5362b) is formed on the same substrate 5380 as the pixel portion 564. The circuit 5362a may be formed on a different substrate from the one 364. Circuits that can be constructed using transistors (e.g., shift registers, selectors, shift registers, etc.) In addition, the circuit 5362b has high mobility and characteristic variations. Circuits that are preferably constructed using transistors with low distortion (e.g., shift registers) In many cases, the IC has a built-in amplifier (e.g., a 32-bit amplifier ... By doing so, as in FIG. 31(B), a non-single layer can be used as the semiconductor layer of the transistor. A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used. This makes it possible to further reduce the number of external parts.

[0304] In FIG. 31D, a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0305] As in FIG. 31D, in FIGS. 31A to 31C, the circuit 5363_1 and The circuit 5363_2 can be formed on a substrate different from that of the pixel portion 5364.

[0306] In FIG. 31E, a part of the circuit 5361 (circuit 5361a) is formed on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. In some cases, the device has a circuit that can be used to The circuit 5361b uses transistors with high mobility and small variation. A circuit (e.g., a shift register, a timing generator, an o The input often has a built-in inverting resistor, regulator, or analog buffer.

[0307] In addition, in FIG. 31(A) to (D), the circuit 5361a and the pixel portion 5364 are mounted on the same substrate. In addition, the circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0308] Here, the circuits 5363_1 and 5363_2 are the circuits according to the first to fifth embodiments. In this case, the semiconductor device or shift register of the circuit 5363_ 1, the circuit 5363_2 and the pixel portion are formed on the same substrate, All transistors formed can be of either N-channel or P-channel type. Therefore, the number of steps can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. In particular, when all the transistors are N-channel type, As the semiconductor layer of a transistor, a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, Therefore, it is possible to increase the size of the display device and to reduce the cost. This can reduce costs and improve yields.

[0309] Alternatively, the semiconductor device or the shift register according to the first to fifth embodiments may include a transistor. This allows the channel width of the transistor to be reduced, thereby reducing the layout area. This allows the frame to be smaller, or the layout area to be reduced. This allows for a higher resolution.

[0310] Alternatively, the semiconductor device or shift register according to the first to fifth embodiments may have a parasitic capacitance. Therefore, the power consumption can be reduced. Alternatively, the size of the external circuit or the current capability of the external circuit can be reduced. The size of the display device can be reduced.

[0311] Note that the semiconductor layer may be a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. A transistor using a semiconductor layer made of a material such as a GaN-GaN nanotube has characteristics such as an increase in threshold voltage or a decrease in mobility. However, in the semiconductor device or shift register of the first to fifth embodiments, The resistive resistor can suppress the deterioration of transistor characteristics, thereby extending the life of the display device. It can be made longer.

[0312] As a part of the circuit 5362, the semiconductor device of any one of the first to fifth embodiments or For example, the circuit 5362a may be implemented by using a register similar to that described in the first to third embodiments. The semiconductor device of the fourth aspect may have a shift register.

[0313] (Embodiment 7) In this embodiment, an example of a signal line driver circuit will be described. It may be referred to as a conductor device or a signal generating circuit.

[0314] An example of a signal line driver circuit will be described with reference to FIG. A plurality of circuits 602_1 to 602_N (N is a natural number), a circuit 600, and a circuit 6 01. Each of the circuits 602_1 to 602_N includes a transistor 603_ The transistor 603 has a number of transistors 1 to 603_k (k is a natural number). 603_1 to 603_k are assumed to be N-channel type. However, this is not limited to this. For example, the transistors 603_1 to 603_k may be of the P-channel type. , it is possible to use a CMOS type switch.

[0315] The connection relationship of the signal line driver circuit will be described using the circuit 602_1 as an example. The first terminals of the transistors 603_1 to 603_k are connected to the wiring 605_1. The second terminals of the transistors 03_1 to 603_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 603_1 to 603_k are connected to the wirings 604_1 to 604_k, respectively. For example, a first terminal of the transistor 603_1 is connected to a wiring 605_1. A second terminal of the transistor 603_1 is connected to the wiring S1. The port is connected to the wiring 604_1.

[0316] The circuit 600 transmits signals to the circuits 602_1 to 602_k via the wirings 604_1 to 604_k. N, and can function as a shift register, decoder, etc. The signal is often a digital signal and can function as a selection signal. The wirings 604_1 to 604_k can function as signal lines. be.

[0317] The circuit 601 has a function of outputting signals to circuits 602_1 to 602_N, and generates a video signal. For example, the circuit 601 can function as a At the same time, a signal is supplied to the circuit 602_1 via the wiring 605_2. The signal is often an analog signal and functions as a video signal. The wirings 605_1 to 605_N can function as signal lines. It is possible.

[0318] The circuits 602_1 to 602_N select which wiring the output signal of the circuit 601 is to be output to. For example, the circuit 602 has a function of selecting an input signal from the input signal. _1 indicates which of the wirings S1 to Sk the signal output from the circuit 601 to the wiring 605_1 is to be transmitted to It has the function of selecting whether to output to

[0319] The transistors 603_1 to 603_k are connected to the wiring 6 in response to the output signal of the circuit 600. 05_1 and the wiring S1 to Sk, and functions as a switch. do.

[0320] Next, the operation of the signal line driver circuit of FIG. 32(A) will be described with reference to the timing chart of FIG. 32(B). FIG. 32B shows a signal 614_1 input to a wiring 604_1. , a signal 614_2 input to the wiring 604_2, a signal 614 input to the wiring 604_k _k, a signal 615_1 input to a wiring 605_1, and a signal 615_2 input to a wiring 605_2. An example of number 615_2 is shown below.

[0321] Note that one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. A gate selection period is a period during which pixels in a certain row are selected and a video signal is written to the selected pixels. This refers to the period during which it is possible to

[0322] One gate selection period is divided into periods T0, T1, and Tk. is a period for simultaneously applying a precharge voltage to the pixels in the selected row. The periods T1 to Tk can function as a precharge period. This is a period for writing video signals to pixels belonging to a row that has been selected, and functions as a write period. It is possible to do this.

[0323] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 602_1 as an example.

[0324] First, in a period T0, the circuit 600 applies an H-level signal to the wirings 604_1 to 604_k. Then, the transistors 603_1 to 603_k are turned on, so that the wiring 605 At this time, the circuit 601 is in a conductive state with the wiring 605_1 Since the precharge voltage Vp is supplied to the transistor 6, the precharge voltage Vp is The signals are output to the wirings S1 to Sk via the pre-transmitted signals 03_1 to 603_k. The charge voltage Vp is written to the pixels in the selected row, so that the charge voltage Vp is The pixels that correspond to the pixel are precharged.

[0325] Next, in a period T1, the circuit 600 outputs an H-level signal to the wiring 604_1. Then, the transistor 603_1 is turned on, so that the wiring 605_1 and the wiring S1 are in a conductive state. Then, the wiring 605_1 and the wirings S2 to Sk are in a non-conductive state. If the circuit 601 outputs a signal Data (S1) to the wiring 605_1, then the signal D The ata (S1) is output to the wiring S1 through the transistor 603_1. The signal Data(S1) is supplied to the pixels in the selected row among the pixels connected to the wiring S1. It is written in simple terms.

[0326] Next, in a period T2, the circuit 600 outputs an H-level signal to the wiring 604_2. Then, the transistor 603_2 is turned on, so that the wiring 605_2 and the wiring S2 are in a conductive state. Then, the wiring 605_1 and the wiring S1 are brought into a non-conductive state. The wirings S3 to Sk remain in a non-conductive state. At this time, the circuit 601 outputs the signal Data( S2) is output to the wiring 605_1, the signal Data (S2) is The signal Data (S1) is output to the wiring S2 via the input terminal 603_2. Of the pixels connected to line S1, those belonging to the selected row are written.

[0327] After that, until the period Tk, the circuit 600 outputs a high-level signal to the wirings 604_1 to 604_k. Since the signals are output in sequence, the signals are output in sequence from the period T3 to the period Tk in the same manner as in the periods T1 and T2. 00 outputs H-level signals to the wirings 604_3 to 604_k in sequence. Since the transistors 603_3 to 603_k are turned on in sequence, the transistors 603_1 to 603_k are turned on in sequence. Therefore, the signal output from the circuit 601 is transmitted to the wirings S1 to Sk in order. In this way, signals can be written in sequence to the pixels in the selected row. become.

[0328] An example of the signal line driver circuit has been described above. Since the semiconductor memory device has a circuit that functions as a connector, the number of signals or the number of wirings can be reduced. Or, the voltage for precharging before writing a video signal to the pixel (period T0) is written to the pixel, the video signal writing time can be shortened. This allows the display device to be enlarged and the resolution to be increased. It is possible to omit period T0 and not precharge the pixels.

[0329] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so k≦6 is preferred. More preferably, k≦3. Further preferably, k=2. It is.

[0330] In particular, if the color components of a pixel are divided into n (n is a natural number), it is possible to set k=n. For example, if a pixel's color components are divided into three, red (R), green (G), and blue (B), , k=3. In this case, one gate selection period includes a period T0, a period T1, , period T2, and period T3. In periods T1, T2, and T3, It is possible to write video signals to red (R), green (G), and blue (B) pixels. However, the order of the periods T1, T2, and T3 is not limited to this, and may be set arbitrarily. It is possible to do so.

[0331] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, k=n. In this case, one gate selection period is a period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible.

[0332] In addition, since the driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are often low, The circuit 600 and the circuits 602_1 to 602_N may be formed on the same substrate as the pixel portion. This makes it possible to reduce the number of connections between the substrate on which the pixel unit is formed and the external circuit. This allows for improved yield and reliability. As shown in FIG. 1(C), the scanning line driver circuit is also formed on the same substrate as the pixel section, so that This significantly reduces the number of connections to external circuits.

[0333] The circuit 600 may be a semiconductor device or a shift register according to any one of the first to fourth embodiments. In this case, the polarity of all the transistors in the circuit 600 can be changed to It can be made into either an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. The yield can be improved or the cost can be reduced.

[0334] In addition to the circuit 600, all the transistors included in the circuits 602_1 to 602_N are The polarity of the transistor can be either N-channel or P-channel. 00, and when the circuits 602_1 to 602_N are formed on the same substrate as the pixel portion, the number of steps In particular, it is possible to reduce the number of transistors, improve the yield, and reduce the cost. By making the polarity of the transistor N-channel type, A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. This is because the driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are Because it is often low.

[0335] (Embodiment 8) In this embodiment, a pixel configuration and pixel operation that can be applied to a liquid crystal display device will be described. explain.

[0336] 33A shows an example of a pixel. The pixel 3020 includes a transistor 3021, a liquid crystal element The first terminal of the transistor 3021 is connected to a first terminal of the transistor 3022 and a capacitor 3023. The second terminal of the transistor 3021 is connected to a wiring 3031, and the second terminal of the transistor 3021 is connected to a liquid crystal element 3022. one electrode of the transistor 3021 and one electrode of the capacitor 3023 are connected to the gate The other electrode of the liquid crystal element 3022 is connected to an electrode 3034. The other electrode of the capacitor 3023 is connected to a wiring 3033 .

[0337] For example, a video signal can be input to the wiring 3031. For example, a scan signal, a selection signal, or a gate signal may be input to the second input terminal. For example, a constant voltage can be supplied to the wiring 3033. As an example, the 034 may be supplied with a constant voltage. The line 3031 is not fixed, and a precharge voltage is supplied to the line 3031, thereby It is possible to shorten the writing time. Alternatively, a signal is input to the wiring 3033. By this, it is possible to control the voltage applied to the liquid crystal element 3022. By inputting a signal to the electrode 3034, frame inversion driving can be realized. It is Noh.

[0338] The wiring 3031 can function as a signal line, a video signal line, or a source line. The wiring 3032 can function as a signal line, a scanning line, or a gate line. The wiring 3033 can function as a power supply line or a capacitance line. 4 can function as a common electrode or a counter electrode, but is not limited thereto. When a voltage is supplied to the wiring 3031 and the wiring 3032, these wirings are power supply lines. Alternatively, when a signal is input to the wiring 3033, the wiring 3033 can function as a signal line.

[0339] The transistor 3021 controls the electrical continuity between the wiring 3031 and one electrode of the liquid crystal element 3022. By controlling the timing of writing a video signal to the pixel, The capacitor element 3023 can function as a switch. A potential difference is maintained between the electrode on the other side and the wiring 3033, and the voltage applied to the liquid crystal element 3022 is The capacitance C has a function of keeping the capacitance C constant and functions as a storage capacitor. However, the present invention is not limited to this.

[0340] FIG. 33B is a timing chart for explaining the operation of the pixel of FIG. 33A. FIG. 33B shows an example of a signal 3042_j (j is a natural number), a signal 3042_j+1 , signal 3041_i (i is a natural number), signal 3041_i+1, and voltage 3042 are shown. FIG. 33B shows the k-th (k is a natural number) frame and the k+1-th frame. In addition, the signal 3042_j, ​​the signal 3042_j+1, the signal 3041_i, and the signal 3041_i +1 and voltage 3042 are signals input to the wiring 3032 in the jth row, A signal input to the wiring 3032 in the i-th column, a signal input to the wiring 3031 in the i+1-th column 3 is an example of a signal input to the wiring 3031 and a voltage supplied to the wiring 3032.

[0341] The operation of the pixel 3020 in the jth row and the ith column will be described. When this occurs, the transistor 3021 is turned on. Since the signal 3041_j is connected to one electrode of the transistor 3022, The signal is input to one electrode of the liquid crystal element 3022 through a capacitor 3023. At this time, the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033 is maintained. Therefore, the liquid crystal element 302 is maintained at the H level until the signal 3042_j becomes H level again. The voltage applied to the liquid crystal element 3022 is constant. It expresses a gradation of tones.

[0342] In FIG. 33B, a positive polarity signal and a negative polarity signal are alternately arranged for each row selection period. This shows an example of a case where a signal is input to a line 3031. A positive signal is a signal whose potential is equal to or greater than a reference value (for example, A signal with a negative polarity is a signal with a potential higher than the reference potential (the potential of the electrode 3034). (for example, the potential of electrode 3034). However, this is not limited to this. The signal input to the wiring 3031 can have the same polarity during one frame period. do.

[0343] In addition, in FIG. 33(B), the polarity of the signal 3041_i and the polarity of the signal 3041_i+1 are different. The following shows an example of a case where the polarity and the phase of the signal 3041_i are different from each other. However, the present invention is not limited to this. The polarity of signal 3041_i+1 may be the same.

[0344] In addition, in FIG. 33B, there are periods when the signal 3042_j is at H level and periods when the signal 3042_j This is an example of a case where the period when +1 is at H level does not overlap. However, this is not limited to this. As shown in FIG. 33C, the signal 3042_j is at the H level and the signal 30 It is possible for the period during which the line 303_j+1 is at the H level to overlap with the period during which the line 303_j+1 is at the H level. It is preferable that signals of the same polarity are supplied to all of the inputs during one frame. The pixel in the j+1th row is written to the pixel in the jth row using the signal 3041_j written to the pixel in the jth row. This allows the time it takes to write a video signal to the pixel to be shortened. Therefore, the display device can have high resolution. Alternatively, the same display area can be displayed on the wiring 3031 during one frame period. Since a polarity signal is input, power consumption can be reduced.

[0345] In addition, when the pixel configuration of FIG. 34(A) and the timing chart of FIG. 33(C) are combined, In this way, dot inversion driving can be realized. The pixel 3020(i, j) is connected to the wiring 3031_i. j+1) is connected to the wiring 3031_i+1. In this way, the i-th row is connected to the wiring 3031_i and the wiring 3031_i+1 alternately. The pixels belonging to each eye are written with positive and negative polarity signals alternately, row by row. In this case, dot inversion driving can be realized. However, this is not limited to this. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 3031_i and the wiring 3031 _i+1.

[0346] As a pixel configuration, a sub-pixel structure can be used. 34(C) shows a configuration in which a pixel is divided into two sub-pixels. Figure 34(B) shows a subpixel structure called 1S+2G, and Figure 34(C) shows a subpixel structure called 2S+1 30 shows a sub-pixel structure called G. Sub-pixel 3020A and sub-pixel 3020B are The transistor 3021A corresponds to the pixel 3020. The transistor 3021A and the transistor 3021B correspond to the The liquid crystal element 3022A and the liquid crystal element 3022B correspond to the liquid crystal element The capacitance element 3023A and the capacitance element 3023B correspond to the capacitance element 3023 The wiring 3031A and the wiring 3031B correspond to the wiring 3031. 32A and wiring 3032B correspond to wiring 3032.

[0347] Here, the pixel of the present embodiment, the semiconductor device of the first to seventh embodiments, and the shift register By combining it with a display, a display device, or a signal line driver circuit, various advantages are obtained. For example, when a subpixel structure is used as a pixel, the display device is driven This increases the number of gate lines or source lines. As a result, the number of connections between the substrate on which the pixel unit is formed and the external circuitry increases significantly. However, even if the number of gate lines increases, as shown in the sixth embodiment, Therefore, it is possible to form the scanning line driver circuit on the same substrate as the pixel portion. The number of connections between the substrate on which the pixel is formed and the external circuitry is not significantly increased. Even if the number of source lines increases, the signal line driver of the sixth embodiment can be used. By using a driving circuit, the number of source lines can be reduced. The number of connections between the substrate on which the pixel is formed and the external circuitry is not significantly increased. A pixel can be used.

[0348] Or, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit Therefore, the semiconductor device according to the first to fifth embodiments is provided on the capacitance line. The signals can be provided using semiconductor devices or shift registers. The semiconductor device or shift register of the first to fifth embodiments is formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be significantly reduced. Therefore, a signal can be input to the capacitance line without increasing the capacitance.

[0349] Or, when AC driving is used, the time for writing a video signal to a pixel becomes short. As a result, there may not be enough time to write the video signal to the pixels. Similarly, when using pixels with a subpixel structure, the time it takes to write a video signal to the pixel is short. As a result, there may not be enough time to write the video signal to the pixel. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the seventh embodiment. In this case, a precharge voltage is applied to the pixel before writing a video signal to the pixel. Since the video signal is written to the pixel in a short time, the video signal can be written to the pixel in a short time. As shown in (B), the period in which one row is selected can overlap the period in which another row is selected. By this, it is possible to use a video signal of another row as a voltage for precharging. .

[0350] (Embodiment 9) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. This will be explained with reference to C).

[0351] FIG. 35A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. , or a signal line driver circuit.

[0352] FIG. 35(B) shows an example of a cross section taken along line AB of FIG. 35(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. A conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; A conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; A liquid crystal layer 5407 is formed on the insulating layer 5405. 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0353] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a planarizing film or a wiring. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0354] Here, parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Or, the power consumption will increase. However, as shown in FIG. As shown in FIG. 5, an insulating layer 5408 capable of functioning as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance between the driver circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node is Alternatively, the power consumption of the driver circuit 5392 can be reduced. This can be done.

[0355] As shown in FIG. 35C, a sealing material is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. Parasitic capacitance occurring between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, the present invention is not limited to this. It is possible that the insulating layer 5408 is not formed.

[0356] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0357] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and a semiconductor device or shift register according to any one of the first to fifth embodiments. For example, a non-single crystal semiconductor or an amorphous semiconductor can be used as a semiconductor layer of a transistor. When a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, the channel of the transistor However, as in this embodiment, the parasitic capacitance of the driver circuit is If the thickness can be reduced, the channel width of the transistor can be reduced. Since the area of ​​the outer periphery can be reduced, the frame of the display device can be narrowed. This allows the display device to have high resolution.

[0358] (Embodiment 10) In this embodiment, examples of the structure of a transistor will be described with reference to FIGS. ) will be referred to for explanation.

[0359] FIG. 36A shows an example of the structure of a top-gate transistor. FIG. 36B shows This is an example of the structure of a bottom-gate transistor. 1 is an example of a structure of a transistor manufactured by

[0360] FIG. 36A shows a substrate 5260, an insulating layer 5261 formed on the substrate 5260, A region 5262a, a region 5262b, a region 5262c, and a region 5262d are formed on an insulating layer 5261. A semiconductor layer 5262 having regions 5262d and 5262e and a semiconductor layer 5262 having a The insulating layer 5263 is formed as shown in FIG. A conductive layer 5264 having an insulating layer 5263 and a conductive layer 5264 having an opening is formed over the insulating layer 5263 and the conductive layer 5264. and a conductive layer 5265 formed on the insulating layer 5265 and in the opening of the insulating layer 5265. A layer 5266 and a conductive layer 5267 formed on the insulating layer 5265 and having an opening. An insulating layer 5267 and a conductive layer formed on the insulating layer 5267 and in the opening of the insulating layer 5267. 5268, and an insulating layer having an opening formed on the insulating layer 5267 and the conductive layer 5268. A border layer 5269 and a light-emitting layer 5 formed on the insulating layer 5269 and in the opening of the insulating layer 5269. 270 and a conductive layer 5271 formed on the insulating layer 5269 and on the light-emitting layer 5270. show.

[0361] FIG. 36B shows a substrate 5300, a conductive layer 5301 formed on the substrate 5300, An insulating layer 5302 formed to cover the conductive layer 5301, and a conductive layer 5301 and an insulating layer 5302 A semiconductor layer 5303a formed on the semiconductor layer 5303a and a semiconductor layer 5303b formed on the semiconductor layer 5303a. A conductor layer 5303b and a conductive layer formed on the semiconductor layer 5303b and on the insulating layer 5302. A layer 5304 is formed on the insulating layer 5302 and the conductive layer 5304 and has an opening. An insulating layer 5305 and a conductive layer formed on the insulating layer 5305 and in the opening of the insulating layer 5305. 5306, a liquid crystal layer 5307 disposed on the insulating layer 5305 and on the conductive layer 5306, 53, a conductive layer 5308 formed on the liquid crystal layer 5307 is shown.

[0362] FIG. 36C shows a semiconductor substrate 5352 having a region 5353 and a region 5355, An insulating layer 5356 formed on the semiconductor substrate 5352 and a A conductive layer 5357 is formed on the insulating layer 5356. 4. An insulating layer 535 having an opening formed on the insulating layer 5356 and the conductive layer 5357. 8 and a conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358. Thus, transistors are formed in each of the regions 5350 and 5351.

[0363] The insulating layer 5261 can function as a base film. The insulating layer 5263 serves as an isolation layer (e.g., a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as a gate electrode. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are an interlayer film or a flat The conductive layer 5266, the conductive layer 5304, and the conductive layer 5 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a bank. The conductive layer 5271 and the conductive layer 5308 function as a counter electrode, a common electrode, or the like. It is possible.

[0364] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, and a silicon substrate. (or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel substrate, Substrate with tungsten foil, tungsten substrate, tungsten foil An example of a glass substrate is a barium borosilicate glass substrate. Examples of flexible substrates include polyethylene terephthalate (PET) and aluminoborosilicate glass. Polyethylene naphthalate (PET), Polyethylene naphthalate (PEN), Polyether sulfo Plastics such as polyether ether sulphate (PES), or flexible synthetic resins such as acrylic. Other examples include laminated films (polypropylene, polyester, vinyl, polypropylene, etc.) Polyvinyl fluoride, polyvinyl chloride, etc.), paper containing fibrous materials, base film (polyester, Polyamide, polyimide, inorganic vapor deposition film, paper, etc.

[0365] The semiconductor substrate 5352 is, for example, a single crystal Si substrate having n-type or p-type conductivity. However, the present invention is not limited to this, and a plate similar to the substrate 5260 can be used. The region 5353 can be, for example, a semiconductor substrate 5352 with impurities. For example, if the semiconductor substrate 5352 is a p-type conductive region, If the region 5353 has an n-type conductivity, the region 5353 functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity, the region 5353 has a p-type conductivity. The region 5355 has a p-well function. 352 and function as a source region or a drain region. The conductive substrate 5352 may have LDD regions formed therein.

[0366] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon oxide nitride (SiOxNy)(x>y), silicon oxynitride (SiNxOy)(x>y) The insulating layer 5261 has a two-layer structure. As an example of the structure, a silicon nitride film is provided as the first insulating layer, and a silicon nitride film is provided as the second insulating layer. A silicon oxide film can be provided as the insulating film. The insulating layer 5261 is provided in a three-layer structure. In one example, a silicon oxide film is provided as the first insulating film and a silicon dioxide film is provided as the second insulating film. It is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the third insulating film.

[0367] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single Crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) , single crystal semiconductor, compound semiconductor or oxide semiconductor (ZnO, InGaZnO, SiG e, GaAs, IZO, ITO, SnO, TiO, AlZnSnO(AZTO)), organic Examples include semiconductors and carbon nanotubes.

[0368] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, a small amount of impurity is added to the region 5262a. The impurity added to the region 5262a can be added to the region 5262b, 5262c, 5262d, or 5262e. It is preferable that the regions 5262b and 5262d are lightly doped with impurities. This region functions as a Lightly Doped Drain (LDD) region. However, the area 5262b and the area 5262d can be omitted. The regions 5262c and 5262e are regions in which impurities are added to the semiconductor layer 5262 at a high concentration. It functions as a source region or a drain region.

[0369] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0370] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0371] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy)(x>y), silicon nitride oxide A film containing oxygen or nitrogen, such as silicon (SiNxOy) (x>y), or a laminate structure of these. There are various constructions.

[0372] A conductive layer 5264, a conductive layer 5266, a conductive layer 5268, a conductive layer 5271, a conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 An example of the conductive film 9 is a conductive film having a single layer structure or a laminated structure thereof. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. (Mo), Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni) , platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), Scandium (Sc), Zinc (Zn), Phosphorus (P), Boron (B), Arsenic (As) , Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O), Zirconium (Z r), cerium (Ce), or Examples of such compounds include compounds containing one or more elements selected from the above group. In the case of the above, an alloy containing one or more elements selected from the above group (indium tin oxide (I TO), indium zinc oxide (IZO), indium tin oxide with silicon oxide (ITS O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), alumina Odimium (Al-Nd), Aluminum Tungsten (Al-Ta), Aluminum Zirconium (Al -Zr), Aluminum Titanium (Al-Ti), Aluminum Cerium (Al-Ce), Magnesium Silver (Mg-Ag), Molybdenum Niobium (Mo-Nb), Molybdenum Tungsten (Mo- W), molybdenum-tantalum (Mo-Ta) alloy materials, and one or more selected from the above group or compounds of nitrogen with multiple elements (such as titanium nitride, tantalum nitride, molybdenum nitride, etc.) nitride film), or a compound of one or more elements selected from the above group with silicon (thin film) silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum silicide, Other examples include carbon nanotubes, organic Nanotube materials include nanotubes, inorganic nanotubes, or metallic nanotubes. .

[0373] Silicon (Si) is doped with n-type impurities (such as phosphorus) or p-type impurities (such as boron). The inclusion of impurities in silicon can improve electrical conductivity and / or It is possible for the wire or electrode to behave like a normal conductor. It will be easier to use as such.

[0374] Silicon can be classified into single crystal, polycrystalline (polysilicon), microcrystalline (microcrystalline) Silicon with various crystallinity such as crystalline silicon, or amorphous silicon As the silicon, single crystal silicon or the like can be used. By using crystalline silicon or polycrystalline silicon, wiring, electrodes, conductive layers, conductive films, The resistance of the silicon can be reduced. By using silicon, wiring and the like can be formed through simple processes.

[0375] When a semiconductor material such as silicon is used as the conductive layer, the semiconductor material such as silicon The material can be formed simultaneously with a semiconductor layer of the transistor.

[0376] Incidentally, aluminum or silver has high electrical conductivity, and therefore can reduce signal delay. Furthermore, aluminum or silver is easy to etch, making it easy to pattern and fine Fine processing can be performed.

[0377] In addition, copper has high conductivity, so it can reduce signal delay. When a laminated structure is used, it is preferable to use a laminated structure in order to improve adhesion.

[0378] Molybdenum or titanium is used in oxide semiconductors (ITO, IZO, etc.) or silicon It has the advantages of being less likely to cause defects even when in contact with metals, being easy to etch, and having high heat resistance. Therefore, the conductive layer in contact with the oxide semiconductor or silicon is preferably It is preferable to use molybdenum or titanium.

[0379] Tungsten is preferable since it has an advantage such as high heat resistance.

[0380] Neodymium is preferable because it has the advantage of being highly heat resistant. By using an alloy material of neodymium and aluminum, the aluminum does not form hillocks. However, this is not limited to aluminum, tantalum, zirconia, etc. Aluminum can also be alloyed with aluminum, titanium, or cerium to improve the In particular, alloy materials made of aluminum and cerium are less likely to cause arcing. It can be significantly reduced.

[0381] In addition, ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanotube Since the tubes and the like have light-transmitting properties, these materials can be used as pixel electrodes, counter electrodes, or common electrodes. It can be used for light transmitting parts such as electrodes. In particular, IZO is highly resistant to etching. IZO is desirable because it is easy to apply and process. When IZO is etched, it leaves no residue. Therefore, when IZO is used as a pixel electrode, To reduce the occurrence of defects (short circuits, alignment disturbances, etc.) in liquid crystal elements and light-emitting elements can be done.

[0382] The conductive layer may have a single-layer structure or a multi-layer structure. The single-layer structure simplifies the manufacturing process for wiring, electrodes, conductive layers, conductive films, terminals, etc. This allows for the shortening of the manufacturing process, shortening the number of days required for the process, and reducing costs. By using a layered structure, the advantages of each material are utilized while reducing their disadvantages. For example, low resistance materials (aluminum, By including a multilayer structure containing a metal such as ZnO, the resistance of the wiring can be reduced. For example, a low heat resistant material can be sandwiched between high heat resistant materials to form a laminated structure. This makes it possible to improve the heat resistance of wiring, electrodes, etc. while taking advantage of the advantages of heat-resistant materials. One example of such a laminate structure is a layer containing aluminum, a layer containing molybdenum, titanium, It is preferable to have a laminated structure in which the material is sandwiched between layers containing neodymium or the like.

[0383] In addition, when wiring, electrodes, etc. are in direct contact with each other, they may have a detrimental effect on each other. For example, one wiring or electrode may penetrate into the other wiring or electrode, changing the properties of the material. As another example, a high resistance part may be formed. Or, problems may occur during production, making it impossible to produce normally. In this case, a material that changes its properties when it reacts with other materials is replaced with a material that does not react easily to those other materials. For example, ITO and aluminum can be sandwiched or covered with When connecting, neodymium alloy, titanium, molybdenum are used between ITO and aluminum. For example, when connecting silicon and aluminum, Neodymium alloy, titanium, and molybdenum can be sandwiched between silicon and aluminum. These materials are used for wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. It can also be used for

[0384] An insulating layer 5265, an insulating layer 5267, an insulating layer 5269, an insulating layer 5305, and an insulating layer 535 An example of the insulating film 8 is a single-layer insulating film or a laminated structure thereof. As an example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride ( SiOxNy) (x>y), silicon oxynitride (SiNxOy) (x>y), etc. Nitrogen-containing films, carbon-containing films such as DLC (Diamond-Like Carbon), or siloxane San resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene Examples of the material include organic materials such as acrylic and the like.

[0385] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, and a hole transport layer made of a hole transport material. a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, etc., or a layer in which a plurality of these materials are mixed, or Often these include laminated structures.

[0386] Examples of the liquid crystal layer 5307 include nematic liquid crystal, cholesteric liquid crystal, and smectic liquid crystal. crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals, low molecular weight liquid crystals, high molecular weight liquid crystals Molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, Examples include chain-type polymer liquid crystal, plasma-addressed liquid crystal (PALC), and banana-shaped liquid crystal. The LCD driving method is Twisted Nematic (TN) mode. , STN (Super Twisted Nematic) mode, IPS (In-Pl Fringe Field Switching mode, FFS (Fringe Field Switching) mode hing mode, MVA (Multi-domain Vertical Alignment ment) mode, PVA (Patterned Vertical Alignment t) mode, ASV (Advanced Super View) mode, ASM (Ax ally Symmetric aligned Micro-cell) mode, O CB (Optically Compensated Birefringence) Electrically Controlled Birefring (ECB) ence) mode, FLC (Ferroelectric Liquid Crystal l) Mode, AFLC (AntiFerroelectric Liquid Crys) tal) mode, PDLC (Polymer Dispersed Liquid Crystal ystal mode, guest host mode, Blue Phase mode, etc. There are some.

[0387] Note that an insulating layer functioning as an alignment film was provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0388] Note that a color filter, a black matrix, or a protrusion is provided on the conductive layer 5308. An insulating layer or the like that functions as a conductive layer can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0389] In the cross-sectional structure of FIG. 36A, the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 is omitted, and the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 36(B) are replaced with the insulating layer 526 7 and conductive layer 5268.

[0390] In the cross-sectional structure of FIG. 36(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted. 36(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed on the insulating layer 530. 5 and on the conductive layer 5306.

[0391] In the cross-sectional structure of FIG. 36C, 36(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed. Alternatively, the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 36(B) may be formed as an insulating layer. It is possible to form a conductive layer 5358 and a conductive layer 5359 .

[0392] The transistor of this embodiment can be applied to the first to ninth embodiments. In particular, in FIG. 36B, a non-single crystal semiconductor, an amorphous semiconductor, a micro When a crystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, the transistor deteriorates. However, the semiconductor device and the shift register according to the first to ninth embodiments may In the case of a display device, the present invention is useful because deterioration of a transistor can be suppressed.

[0393] (Embodiment 11) In this embodiment mode, a layout diagram (hereinafter also referred to as a top view) of a shift register will be described. In this embodiment, as an example, the layout of the shift register described in the fifth embodiment is The contents of the present embodiment are the same as those of the fifth embodiment. In addition to the shift register described above, the semiconductor device and the shift register according to the first to tenth embodiments are also The present invention can be applied to a display device or a transistor. It should be noted that the above is merely an example and the present invention is not limited to this.

[0394] The layout diagram of this embodiment will be described with reference to FIGS. 37 and 38. FIG. 38 shows an example of a layout diagram of a part of a shift register. 7(A) shows a layout diagram of the semiconductor device.

[0395] The transistors or wirings shown in FIGS. 37 and 38 include a conductive layer 701, a semiconductor layer 70 2, a conductive layer 703, a conductive layer 704, and a contact hole 705. However, the present invention is not limited to this, and another conductive layer, an insulating film, or another contact hole may be newly formed. For example, a contact for connecting the conductive layer 701 and the conductive layer 703 can be formed. It is possible to add new cut holes.

[0396] The conductive layer 701 can include a portion that functions as a gate electrode or a wiring. The conductor layer 702 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 703 may include a portion that functions as a wiring, a source, or a drain. The conductive layer 704 may include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 705 has a function of connecting the conductive layer 701 and the conductive layer 704. Alternatively, it has a function of connecting the conductive layer 703 and the conductive layer 704 .

[0397] In the example of FIG. 37, the wiring has an opening 711. In this way, the wiring has an opening. By doing so, it is possible to reduce the parasitic capacitance. However, this is not limited to this, and the wiring may have an opening. It is possible that this is not the case.

[0398] In the example shown in FIG. 37, openings are provided at the intersections of the wirings and in the surrounding areas. This reduces the cross capacitance of the wiring, thus reducing noise. Alternatively, signal delay or distortion can be reduced.

[0399] In the example of FIG. 37, a conductive layer 704 is formed on a part of a conductive layer 703 of the wiring. The conductive layer 704 is connected to the conductive layer 703 through a contact hole 705. In this way, the wiring resistance can be reduced, resulting in a reduction in voltage drop, or It is possible to reduce the delay or distortion of the signal. However, this is not limited to this. It is possible to omit layer 704 and the contact hole 705 .

[0400] In the example of FIG. 37, the width of the wiring 512 is the width of the wiring 512_1 and the width of the wiring 512_ It is preferable that the width of the wiring 512 is larger than that of the wiring 512 of FIG. 2 because a large current flows in the wiring 512. For the same reason, the width of the wiring 513 is set to be equal to or larger than the width of the wiring 513_1. It is preferable that the width of the wiring 513_1 is larger than that of the wiring 513_2, but is not limited to this.

[0401] In the example of FIG. 38, transistor 101_1, transistor 101_2, transistor 1 02_1, transistor 102_2, and / or transistor 201, The area where the conductive layer 701 and the conductive layer 703 of the terminal overlap is It is preferable that the area of ​​the transistor is smaller than the area of ​​the transistor overlapping with the layer 703. It is possible to reduce noise in the gate of the transistor 201 or the wiring 111. This can suppress the concentration of electric fields at the terminals of the transistors, preventing the deterioration of the transistors or This makes it possible to suppress damage to the sta.

[0402] Note that a semiconductor layer 702 is formed in a portion where the conductive layer 701 and the conductive layer 703 overlap each other. By doing so, the parasitic capacitance between the conductive layer 701 and the conductive layer 703 can be reduced. For the same reason, the conductive layer A semiconductor layer 702 or a conductive layer 703 is formed in the portion where the conductive layer 704 overlaps with the semiconductor layer 701. It is possible.

[0403] A conductive layer 704 is formed on a part of the conductive layer 701. It is possible to connect to the conductive layer 704 through the through hole 705. By this, the wiring resistance can be reduced. The conductive layer 701 is connected to the contact hole 705 through the contact hole 705. The conductive layer 703 is connected to the conductive layer 704 through another contact hole 705. It is possible to connect to the conductive layer 704. By doing so, the wiring resistance can be further reduced. It can be lowered further.

[0404] Note that the conductive layer 704 is formed on a part of the conductive layer 703. It is possible to connect to the conductive layer 704 through the through hole 705. This makes it possible to reduce the wiring resistance.

[0405] Note that the conductive layer 701 or the conductive layer 703 is formed under a part of the conductive layer 704. 704 is connected to the conductive layer 701 or the conductive layer 703 through a contact hole 705. By doing so, the wiring resistance can be reduced. .

[0406] As already mentioned, the parasitic capacitance between the gate and the first terminal of the transistor 201 In this case, the parasitic capacitance between the gate and the second terminal of the transistor 201 can be increased. As shown in FIG. 38, the first electrode of the transistor 201 can be The width of the conductive layer 703 that can be formed is indicated as width 731, and the conductive layer 703 that can function as a second electrode of the transistor 201 is indicated as width 731. The width of the conductive layer 703 that can be used is shown as width 732. This allows the gate of transistor 201 and The parasitic capacitance between the gate and the second terminal of the transistor 201 is smaller than the parasitic capacitance between the gate and the first terminal of the transistor 201. It is possible to increase the parasitic capacitance, but this is not a limitation.

[0407] (Embodiment 12) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process in the case where an oxide semiconductor is used as the oxide semiconductor layer will be described. For InMO3(ZnO) m It is possible to use layers represented by (m>0). M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. Metal elements. For example, M can be Ga, Ga and Ni, or G In some cases, the above metal elements other than Ga, such as Ga and Fe, may be included. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In-Ga thin films are known to contain elements such as In, Ga, and oxides of the transition metals. The oxide semiconductor can be represented as a Zn-O-based non-single crystal film. Note that a mobile ion in the oxide semiconductor layer, typically sodium ion, can be used. The concentration of is 5×10 18 / cm 3 Below, and further 1×10 18 / cm 3 If it is less than this, This is preferable because it can suppress changes in the electrical characteristics of the transistor. The semiconductor layer is not limited to the above, and oxide semiconductors of various other materials can be used. Alternatively, the semiconductor layer may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystal (microcrystal), or a crystalline (stal or nanocrystalline) semiconductors, amorphous semiconductors, or various non-crystalline A single crystal semiconductor or the like can be used.

[0408] Referring to FIGS. 46A to 46C, an example of a manufacturing process of a transistor and a capacitor will be described. 46A to 46C are diagrams illustrating a transistor 5441 and a capacitor 5442. This is an example of a manufacturing process. The transistor 5441 is an example of an inverted staggered thin film transistor. A wiring is provided over the oxide semiconductor layer with a source electrode or a drain electrode interposed therebetween. This is an example of a transistor.

[0409] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. However, this is not limited to this. The conductive layer 5421 and the conductive layer 5422 are used as a wiring, a gate electrode, or an electrode of a capacitor. After that, the resist mask is removed.

[0410] Next, an insulating layer 5423 is formed on the entire surface by using a plasma CVD method or a sputtering method. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421 can The insulating layer 5423 is formed so as to cover the insulating layer 5421 and the conductive layer 5422. It is often between 200 and 250 nm.

[0411] When a silicon oxide layer is used as the insulating layer 5423, an organic silane gas is used. It is possible to form a silicon oxide layer by the CVD method using organic silane gas. is ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TM S: Chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMD S), triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane ( Silicon-containing compounds such as SiH(N(CH3)2)3) or yttrium oxide (Y2 O3) can be used.

[0412] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After that, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After the formation of the contact hole 5424, the contact hole 5424 can be formed. The cross-sectional view corresponds to FIG.

[0413] Next, an oxide semiconductor layer is formed on the entire surface by a sputtering method. An oxide semiconductor layer is formed by sputtering, and a n + Forming layers The thickness of the oxide semiconductor layer is preferably 5 nm to 200 nm. many.

[0414] Before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. It is preferable to perform reverse sputtering to generate plasma. This removes dust adhering to the surface of the insulating layer 5423 and the bottom of the contact hole 5424. Reverse sputtering is a process in which the target is not applied with a voltage. A voltage is applied to the substrate side using an RF power source in a argon atmosphere to generate plasma on the substrate surface. However, this is not limited to this, and the argon atmosphere may be replaced by nitrogen, helium, etc. Alternatively, oxygen, hydrogen, N2O, etc. can be used in an argon atmosphere. Alternatively, the atmosphere may be mixed with Cl2, CF4, etc. In addition, when reverse sputtering is performed, the insulating layer 54 The surface of 23 is preferably removed by about 2 to 10 nm. After such plasma treatment, By forming the oxide semiconductor layer without exposing it to heat, the boundary between the gate insulating layer and the semiconductor layer can be prevented. This is useful in that it does not allow dirt or moisture to adhere to the surface.

[0415] Next, the oxide semiconductor layer is selectively etched using a third photomask. Then, the resist mask is removed.

[0416] Next, a second conductive layer is formed on the entire surface by sputtering. Next, a fourth photomask is The second conductive layer is selectively formed using a resist mask formed by the photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the layers. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. It is possible to include

[0417] In addition, if a heat treatment (for example, at 200°C to 600°C) is performed after this, It is preferable to impart heat resistance to the second conductive layer. Therefore, the second conductive layer is made of Al and Heat-resistant conductive materials (e.g., Ti, Ta, W, Mo, Cr, Nd, Sc, Zr, Ce, etc.) Elements of these elements, alloys combining these elements, or nitrides containing these elements, etc. However, it is not limited thereto, and the second conductive layer By forming the second conductive layer into a laminated structure, it is possible to provide the second conductive layer with heat resistance. For example, Heat-resistant conductive materials such as Ti or Mo can be provided above and below the Al.

[0418] Before forming the second conductive layer by sputtering, argon gas was introduced to the Reverse sputtering is performed to generate a smear, and the surface of the insulating layer 5423 and the surface of the oxide semiconductor layer are It is preferable to remove dust adhering to the surface of the contact hole 5424 and the bottom surface of the contact hole 5424. However, the present invention is not limited to this, and nitrogen, helium, etc. may be used instead of the argon atmosphere. Alternatively, it can be performed in an argon atmosphere with oxygen, hydrogen, N2O, etc. added. Alternatively, it can be performed in an argon atmosphere with Cl2, CF4, etc. added. It is possible.

[0419] When etching the second conductive layer, a part of the oxide semiconductor layer is also etched. By this etching, an oxide semiconductor layer 5425 overlapping with the conductive layer 5421 is formed. The oxide semiconductor layer 5425 in the portion where the second conductive layer is not formed or the oxide semiconductor layer 5425 in the portion where the second conductive layer is not formed is The oxide semiconductor layer 5425 is often thinned by being removed. Therefore, the oxide semiconductor layer may not be etched. Layer on top + When a layer is formed, the oxide semiconductor layer is often etched. After this etching, the resist mask is removed. The cross section at this stage corresponds to FIG. 46(B). do.

[0420] Here, if reverse sputtering is performed before forming the second conductive layer by a sputtering method, The exposed portion of the insulating layer 5423 may be removed, preferably by about 2 to 10 nm. A recess may be formed in the edge layer 5423. Alternatively, the second conductive layer may be etched, After forming the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431, a reverse sputtering process is performed. As a result, as shown in FIG. 46(B), a conductive layer 5429, a conductive layer 5430, and The ends of the conductive layer 5431 may be curved.

[0421] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The treatment causes atomic-level rearrangement of the In-Ga-Zn-O non-single crystal layer. The heat treatment (light annealing) here releases the distortion that inhibits carrier movement. The timing of this heat treatment is not limited, and the oxide semiconductor This can be done at various times after the body is formed.

[0422] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 has a single-layer structure. For example, the insulating layer 5432 may be an organic EL device. When an insulating layer is used, a composition that is a material for the organic insulating layer is applied, and then heated under air or nitrogen atmosphere. A heat treatment is carried out at 200°C to 600°C in an atmosphere to form an organic insulating layer. By forming an organic insulating layer in contact with the oxide semiconductor layer, a thin, highly reliable semiconductor device with high electrical properties can be obtained. A thin film transistor can be manufactured. Note that an organic insulating layer is used as the insulating layer 5432. In this case, a silicon nitride film or a silicon oxide film can be provided under the organic insulating layer.

[0423] In FIG. 46C, the insulating layer 5432 is formed using a non-photosensitive resin. For illustration, in the cross section of the region in which the contact hole is to be formed, the end of the insulating layer 5432 is However, when the insulating layer 5432 is formed using a photosensitive resin, the contact In the cross section of the region where the cut hole is formed, the end of the insulating layer 5432 may be curved. As a result, the coverage of the third conductive layer or pixel electrode to be formed later is improved.

[0424] Instead of applying the composition, it may be applied by dipping, spraying, or ink depending on the material. Jet method, printing method, doctor knife, roll coater, curtain coater, knife coater It is possible to use a meter or the like.

[0425] In addition, the composition which is the material of the organic insulating layer is not subjected to heat treatment after the oxide semiconductor layer is formed. The heat treatment can also serve as heat treatment for the oxide semiconductor layer.

[0426] The insulating layer 5432 is formed to a thickness of 200 nm to 5 μm, preferably 300 nm to 1 μm. It is possible.

[0427] Next, a third conductive layer is formed on the entire surface. Next, a fifth photomask is used to perform photolithography. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross-sectional view of the above stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, In particular, the conductive layer 5434 can function as a transparent electrode or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, the present invention is not limited to this, and any other suitable material may be used that has a function of connecting the first conductive layer and the second conductive layer. For example, by connecting the conductive layer 5433 and the conductive layer 5434, The conductive layer 5422 and the conductive layer 5430 are connected to a third conductive layer (conductive layer 5433 and conductive layer 5434). ) can be connected.

[0428] Note that the capacitor 5442 is formed by the conductive layer 5422 and the conductive layer 5434. Since the capacitor 5442 has a structure in which the capacitor 5442 is sandwiched, the capacitance of the capacitor 5442 can be increased. However, the present invention is not limited thereto, and one of the conductive layer 5422 and the conductive layer 5434 may be omitted. It is Noh.

[0429] After removing the resist mask by wet etching, the wafer was etched in air or nitrogen. It is possible to carry out a heat treatment at 200°C to 600°C in air.

[0430] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0431] As shown in FIG. 46D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. The insulating layer 5435 can be used to prevent oxidation when the second conductive layer is patterned. It has the function of preventing the nitride semiconductor layer from being etched away and functions as a channel stop film. Therefore, the thickness of the oxide semiconductor layer can be reduced, and the driving voltage of the transistor can be reduced. Reduction of on / off current, improvement of drain current on / off ratio, improvement of S value, etc. Note that the insulating layer 5435 can be formed by successively forming an oxide semiconductor layer and an insulating layer over the entire surface. Then, a resist pattern is formed by a photolithography process using a photomask. The insulating layer can be selectively patterned using a mask to form a After that, a second conductive layer is formed on the entire surface, and an oxide semiconductor layer is patterned simultaneously with the second conductive layer. That is, the oxide semiconductor layer and the second conductive layer are patterned using the same mask (reticle). In this case, an oxide semiconductor layer is necessarily formed under the second conductive layer. In this way, the insulating layer 5435 is formed without increasing the number of steps. In such a manufacturing process, an oxide semiconductor layer is formed under the second conductive layer. However, the present invention is not limited to this, and may be formed by patterning an oxide semiconductor layer. After that, an insulating layer is formed on the entire surface and then patterned to form an insulating layer 54. It is possible to form 35.

[0432] In FIG. 46D, the capacitor 5442 includes a conductive layer 5422 and a conductive layer 5431. The insulating layer 5423 and the oxide semiconductor layer 5436 are sandwiched between the insulating layer 5423 and the oxide semiconductor layer 5436. The oxide semiconductor layer 5436 can be omitted. The third conductive layer is patterned to form a conductive layer 5437, which is connected to the third conductive layer 5431. Such a structure can be used, for example, in the pixels of a liquid crystal display device. For example, the transistor 5441 functions as a switching transistor and has a capacitance The element 5442 can function as a storage capacitor. The conductive layer 5422, the conductive layer 5429, and the conductive layer 5437 are a gate line, a capacitance line, and a source line, respectively. 4, it can function as a pixel electrode. However, it is not limited to this. 46(C) as well, the conductive layer 5430 and the conductive layer 5431 are connected to the third The connection can be made via a conductive layer.

[0433] As shown in FIG. 46(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425. By doing so, the second conductive layer can be patterned. When the oxide semiconductor layer is removed, the oxide semiconductor layer is not formed. Therefore, the thickness of the oxide semiconductor layer can be reduced, and therefore the driving Reduction of dynamic voltage, reduction of off-current, improvement of on / off ratio of drain current, improvement of S value, etc. Note that the oxide semiconductor layer 5425 is formed by patterning the second conductive layer. After that, an oxide semiconductor layer is formed on the entire surface, and then photolithography is performed using a photomask. The oxide semiconductor layer is selectively patterned using a resist mask formed by a photolithography process. It can be formed by:

[0434] In FIG. 46E, the capacitor element is formed by patterning the conductive layer 5422 and the third conductive layer. The insulating layer 5423 and the insulating layer 5432 are sandwiched between the conductive layer 5439 formed by bonding the insulating layer 5423 and the conductive layer 5439. The conductive layer 5422 and the conductive layer 5430 are formed by patterning the third conductive layer. The conductive layer 5439 is connected to the first conductive layer 5438 formed by The conductive layer 5440 is formed by patterning the conductive layer 5440. 46(C) and (D), the conductive layer 5430 and the conductive layer 5422 are , can be connected via conductive layer 5438.

[0435] The thickness of the oxide semiconductor layer (or the channel layer) is determined by the thickness of the depletion layer when the transistor is off. By making the thickness thinner than 100 nm, it is possible to create a fully depleted state. In order to achieve this, the thickness of the oxide semiconductor layer is set to 2 It is preferably 0 nm or less, more preferably 10 nm or less, and even more preferably It is preferable that the thickness is 6 nm or less.

[0436] In addition, the operating voltage of transistors is reduced, the off-current is reduced, and the on / off ratio of the drain current is improved. In order to improve the S value, the thickness of the oxide semiconductor layer is set to be equal to the thickness of the layers constituting the transistor. For example, the oxide semiconductor layer is preferably thinner than the insulating layer 5423. The thickness of the oxide semiconductor layer is preferably thinner than that of the insulating layer 5423. It is preferably 1 / 2 or less, and more preferably 1 / 5 or less. More preferably, it is 1 / 10 or less. However, it is not limited to this. In order to improve reliability, the oxide semiconductor layer may be thicker than the insulating layer 5423. In particular, when the oxide semiconductor layer is removed as shown in FIG. Since the conductor layer is preferably thick, the oxide semiconductor layer is preferably thicker than the insulating layer 5423. It is possible to make the thickness of the film thicker.

[0437] In order to increase the withstand voltage of the transistor, the thickness of the insulating layer 5423 is set to be thicker than that of the first conductive layer. More preferably, the thickness of the insulating layer 5423 is 5 / 4 that of the first conductive layer. More preferably, it is 4 / 3 or more. However, the present invention is not limited to this, and the thickness of the insulating layer 5423 may be increased in order to increase the mobility of the transistor. may be thinner than the first conductive layer.

[0438] The substrate, insulating film, conductive film, and semiconductor layer of this embodiment may be the same as those of other embodiments ( For example, the material described in embodiment 10) or similar to the material described in this specification It is possible to use.

[0439] The transistor of this embodiment may be used in the semiconductor device of the first to ninth embodiments, or in the shift register. By using the same in a computer or display device, the display area can be enlarged. The display can be made highly precise.

[0440] (Embodiment 13) In this embodiment, an example of an electronic device will be described.

[0441] 39(A) to 39(H) and 40(A) to 40(D) ​​are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and an LED. A lamp 5004, an operation key 5005 (including an operation switch or a power switch), a connection terminal Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 5008, etc.

[0442] FIG. 39(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, The portable terminal 5010 may have an infrared port 5010. FIG. A type of image reproducing device (for example, a DVD reproducing device) that, in addition to the above, also has a second display 39C shows a goog In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. FIG. 39(D) shows a portable game machine. In addition to the above, the device may have a recording medium reading unit 5011, etc. In addition to the above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 39(F) shows a portable gaming machine, which, in addition to the above, has a second display unit. 5002, a recording medium reading unit 5011, etc. In addition to the above, the image sensor may also include a tuner, an image processor, etc. 39(H) is a portable television receiver, capable of transmitting and receiving signals in addition to the above. FIG. 40(A) shows a display, and the above-mentioned In addition to the above, a support stand 5018 and the like can be provided. FIG. 40(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 40(C) is a computer, In addition, there is a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 40(D) ​​shows a mobile phone, which, in addition to the above, In addition, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a nozzle, etc.

[0443] The electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) ​​are For example, various information (still images, videos, text images, etc.) Function to display on the display unit, touch panel function, calendar, date or time display, etc. Functions, functions to control processing by various software (programs), wireless communication functions, A function to connect to various computer networks using wireless communication functions, A function to transmit or receive various data using a program recorded on a recording medium The data can be read out and displayed on the display unit. In electronic devices with displays, one display unit is used primarily to display image information, and another A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a stereoscopic image. In electronic devices having an image receiving unit, the functions of taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or in the camera) It can have functions such as storing the captured image on a built-in memory and displaying the captured image on the display unit. Note that the electronic devices shown in FIGS. The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0444] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of the present embodiment and the semiconductor device of the first to ninth embodiments are By combining it with a semiconductor memory device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, reduced costs, and a larger, more precise display. .

[0445] Next, application examples of the semiconductor device will be described.

[0446] FIG. 40(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. The semiconductor device is a wall-mounted type that is integrated with the building and requires a large space to install. It can be installed without requiring a large space.

[0447] FIG. 40(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 and is The display panel 5026 becomes viewable.

[0448] In this embodiment, a wall and a unit bath are used as examples of structures. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various structures.

[0449] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0450] FIG. 40G is a diagram showing an example in which the semiconductor device is provided in an automobile. 5028 is attached to a vehicle body 5029 of a vehicle, and is configured to detect the movement of the vehicle body or the inside and outside of the vehicle. The information entered can be displayed on demand. It is okay to do so.

[0451] FIG. 40(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 40(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge portion 5032. This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0452] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorail, etc.) They can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0453] 101 Circuit 102 Circuit 103 Circuit 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 121 Routes 122 Routes 123 Routes 200 circuits 201 Transistor 202 Capacitive element 203 Transistor 211 Wiring 212 Wiring 213 Wiring 214 Wiring 231 Circuit 232 circuits 300 circuits 301 Transistor 302 Transistor 303 Transistor 304 Transistor 305 Transistor 400 circuits 401 Transistor 402 Transistor 403 Capacitive element 501 Flip-flop 511 Wiring 512 Wiring 513 Wiring 514 Wiring 515 Wiring 516 Wiring 517 Wiring 520 Circuit 521 Circuit 522 circuits 540 pixels 600 circuits 601 Circuit 602 Circuit 603 Transistor 604 Wiring 605 Wiring 614 signal 615 Signal 701 Conductive layer 702 Semiconductor layer 703 Conductive layer 704 Conductive layer 705 Contact Hole 711 Opening 731 Width 732 Width 101a Diode 101p transistor 102a Diode 102p transistor 112A Wiring 112B Wiring 112C Wiring 112D Wiring 112G Wiring 112H Wiring 112I Wiring 112J Wiring 200a terminal 200b terminal 200c terminal 200d Terminal 200e Terminal 200f terminal 200g Terminal 200h terminal 200i terminal 200j terminal 200k terminal 201p transistor 300a terminal 300b terminal 300c terminal 300d Terminal 300e Terminal 300f terminal 300g terminal 300h terminal 300i terminal 301p transistor 302p transistor 303p transistor 3020 pixels 3021 Transistor 3022 Liquid crystal element 3023 Capacitive element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3042 Voltage 3041_j signal 3042_j signal 400a terminal 400b terminal 400c terminal 400d Terminal 400e Terminal 400f terminal 403a Transistor 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bath 5028 Display Panel 5029 Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection Lens 5260 PCB 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5270 Light-emitting layer 5271 Conductive layer 5300 Board 5301 Conductive layer 5302 Insulating layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 Video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 Input terminal 5391 Substrate 5392 Drive circuit 5393 Pixel section 5400 Board 5401 Conductive layer 5402 Insulating layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5408 Insulating layer 5409 Conductive layer 5410 Substrate 5420 PCB 5421 Conductive layer 5422 Conductive layer 5423 Insulating layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulating layer 5433 Conductive layer 5434 Conductive layer 5435 Insulation Layer 5436 Oxide Semiconductor Layer 5437 Conductive layer 5438 Conductive layer 5439 Conductive layer 5440 Conductive layer 5441 Transistor 5442 Capacitor 3020A Subpixel 3020B Subpixel 3021A Transistor 3021B Transistor 3022A Liquid crystal element 3022B Liquid crystal element 3023A Capacitive Element 3023B Capacitive Element 3031A Wiring 3031B Wiring 3032A Wiring 3032B Wiring 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a Circuit 5361b circuit 5362a Circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer

Claims

[Claim 1] A semiconductor device having a first switch electrically connected between a first wiring and a second wiring, a second switch electrically connected between the first wiring and the second wiring, a third switch electrically connected between the first wiring and the second wiring, and a fourth switch electrically connected between the first wiring and the second wiring.

Images