Semiconductor device

Abstract

To provide a transistor including an oxide semiconductor and capable of a high-speed operation and provide a highly reliable semiconductor device including the transistor.SOLUTION: A semiconductor device comprises an oxide semiconductor layer including a pair of low-resist regions and a channel formation region and provided on an electrode layer buried in a groove in a base insulation layer. The channel formation region is formed at a position overlapping a gate electrode layer having a sidewall on lateral walls. The groove has a deeper region and a shallower region, the sidewall overlaps the shallower region and connection with wiring overlaps the deeper region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a technology for miniaturizing semiconductor integrated circuits. In addition to silicon semiconductors, semiconductor integrated circuits are also made up of compound semiconductors. Examples of the semiconductor device include an oxide semiconductor device and a manufacturing method thereof. Regarding.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] In recent years, semiconductor devices have been developed and are used as LSIs, CPUs, and memories. A CPU is a semiconductor integrated circuit (at least transistors and It is an assembly of semiconductor elements having a memory and on which electrodes that serve as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards. It is mounted on a wiring board and used as one of the components in various electronic devices.

[0005] Silicon-based semiconductor materials that can be used as semiconductor materials for transistors used in semiconductor circuits For example, in Patent Document 1, in order to achieve high integration, A structure has been proposed that shortens the distance between the contact and the contact portion, thereby reducing the resistance between them. There are.

[0006] In addition to silicon, oxide semiconductors are also attracting attention as materials other than silicon. For example, Transistors were fabricated using zinc oxide and In-Ga-Zn oxide as oxide semiconductors. The technology for using the semiconductor device in a switching element of a pixel of a display device is disclosed in Patent Documents 2 and 3. It has been disclosed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2004-327617 A [Patent Document 2] JP 2007-123861 A [Patent Document 3] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0008] The channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories is shortened. By reducing the size of the transistors, we can increase the operating speed of the circuits. One of the objectives is to reduce power consumption.

[0009] According to one embodiment of the present invention, there is provided a transistor including an oxide semiconductor and capable of high-speed operation, and a method for manufacturing the same. Another object of the present invention is to provide a method for manufacturing a semiconductor device including the transistor. One object of the present invention is to provide a body device and a method for manufacturing the same. [Means for solving the problem]

[0010] By removing impurities that act as electron donors in the oxide semiconductor, intrinsic or substantially Oxide semiconductors are fully intrinsic semiconductors with a larger energy gap than silicon semiconductors. Using transistors in which the channel formation region is formed in the body, A semiconductor integrated circuit is manufactured.

[0011] Contact resistance occurs between the oxide semiconductor and the conductive layer. It is necessary to ensure sufficient contact area.

[0012] Therefore, a conductive layer in contact with the upper surface of the oxide semiconductor layer and a conductive layer in contact with the lower surface of the oxide semiconductor layer are By providing a sufficient contact area, the contact resistance is reduced.

[0013] One aspect of the present invention disclosed in this specification is a semiconductor substrate, an insulating layer on the semiconductor substrate, and a a gate insulating layer on the oxide semiconductor layer; and an oxide semiconductor layer on the gate insulating layer. A gate electrode layer overlapping the conductor layer and a sidewall on the side of the gate electrode layer, and an insulating layer A trench having a deep region and a shallow region, and a conductive region in the trench, and the sidewall is a shallow The semiconductor device is characterized in that it overlaps with the region.

[0014] In the above structure, the conductive layer is in contact with the sidewall and the oxide semiconductor layer. Both are characteristics.

[0015] In the above-mentioned structure, an interlayer insulating layer is further provided on the gate electrode layer, and a gate insulating film is provided on the interlayer insulating layer. The wiring also has a conductive type region and is electrically connected to the deep region. It is one.

[0016] In the above configuration, the conductive region is a shallow region having a first width in a channel length direction. and a deep region having a second width in the channel length direction. .

[0017] Also, a semiconductor device that has multiple semiconductor integrated circuits mounted in one package to increase integration. , so-called MCP (Multi Chip Package) may also be used.

[0018] In addition, when mounting a semiconductor integrated circuit on a circuit board, the semiconductor integrated circuit may be mounted in a face-up form. Alternatively, a flip chip type (face down type) may be used.

[0019] The present invention also provides a method for producing the semiconductor device, which comprises forming a first insulating film on a first electrode layer. A first planarization process is performed to expose the upper surface of the first electrode layer. forming a second electrode layer in contact with the second electrode layer; forming a second insulating film on the second electrode layer; A second planarization process is performed to expose the upper surface of the second electrode layer. a gate insulating layer is formed on the oxide semiconductor film; and a gate electrode layer and a gate insulating layer are formed on the gate insulating layer. and forming an insulating film covering the upper surface of the gate electrode layer, the insulating film overlapping the first electrode layer and A sidewall is formed in contact with a side surface of the electrode layer, and the gate electrode layer and the sidewall are covered. a conductive film is formed on and in contact with the oxide semiconductor film; The present invention relates to a method for manufacturing a semiconductor device, and a third planarization treatment is performed to remove the insulating portion. Effect of the Invention

[0020] The channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories is shortened. In the case of increasing the contact resistance of the oxide semiconductor layer, the operating speed of the circuit can be increased by reducing the contact resistance of the oxide semiconductor layer. Furthermore, it will achieve a reduction in power consumption. [Brief description of the drawings]

[0021] [Figure 1]1A and 1B are examples of a cross-sectional view and a top view illustrating one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Figure 4] 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Diagram 5] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 6] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 8] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0023] (Embodiment 1) 1A and 1B are a cross-sectional view and a top view of a transistor 420 as an example of a semiconductor device. FIG. 1A is a cross-sectional view of a transistor 420. In FIG. 1(B), in order to avoid complication, Therefore, some of the components of the transistor 420 (for example, the insulating film 407, the insulating film 410, the interlayer Insulating film 415 and the like are omitted in the drawing.

[0024] The transistor 420 shown in FIG. 1A and FIG. 1B is formed on a substrate 400 having an insulating surface. At least one of the insulating layers 436 and 436 is embedded in the insulating layer 436 and has an upper surface. The electrode layer 425a and the electrode layer 425b are exposed from the base insulating layer 436, and a pair of low resistance Regions 404a and 404b, and a channel sandwiched between the low resistance region 404a and the low resistance region 404b An oxide semiconductor layer 403 including a panel formation region 409 and a A gate insulating layer 402 is provided on the channel forming region 409 through the gate insulating layer 402. A gate electrode layer 401 is formed on the side of the gate electrode layer 401. A sidewall insulating layer 412 is formed on the side of the gate electrode layer 401. a, 412b, an insulating film 413 provided on the gate electrode layer 401, and a source electrode layer 40 An insulating film 410 is provided on the drain electrode layer 405a and the drain electrode layer 405b. an insulating film 407 provided on the interlayer insulating film 415; 07, the source electrode layer 40 is formed through an opening provided in the interlayer insulating film 415 and the insulating film 410. 5a and the drain electrode layer 405b. and a second wiring layer 465b.

[0025] The interlayer insulating film 415 is provided to flatten the unevenness caused by the transistor 420. The height of the upper surface is approximately the same as that of the sidewall insulating layers 412a and 412b and the insulating film 410. The wall insulating layers 412a and 412b are also called side walls. The height of the upper surface of the drain electrode layer 405b is determined by the height of the interlayer insulating film 415, the sidewall insulating layer 412a, 12b and the upper surface of the insulating film 413, and The height here refers to the height from the upper surface of the substrate 400.

[0026] In addition, in FIG. 1, the electrode layer 425a and the electrode layer 425b are formed in a deep region in the base insulating layer 436. The sidewall insulating layers 412a, 412b are formed to fill the trench having a deep region and a shallow region. b overlaps with the shallow region. Also, the first wiring layer 465a and the second wiring layer 465b are disposed at positions overlapping with the deep region. A wiring layer 465b is formed.

[0027] In addition, in FIG. 1, the insulating film 407 includes an interlayer insulating film 415, a source electrode layer 405a, a drain the sidewall insulating layers 412a and 412b, the insulating film 413, and the insulating film 410. It is set up as such.

[0028] Note that the gate electrode layer 401 is used as a mask to form a dopant layer on the oxide semiconductor film 403 in a self-aligned manner. The oxide semiconductor film 403 is formed by introducing a channel-forming region 409 between the channel-forming region 409 and the oxide semiconductor film 403. The low resistance regions 404a and 404b are formed by doping the dopant. The dopant is an impurity that changes the electrical conductivity of the oxide semiconductor film 403. The methods of introducing ions include ion implantation, ion doping, and plasma immersion ion implantation. For example, a ion implantation method can be used.

[0029] The low resistance regions 404a and 404b are disposed on either side of the channel forming region 409 in the channel length direction. The oxide semiconductor film 403 and the source electrode layer 40 in contact with a part of the upper surface of the oxide semiconductor film 403 5a and the drain electrode layer 405b, and the electrode layer 4 25a and electrode layer 425b, the transistor 420 has an on-characteristic (e.g. For example, the on-state current and field effect mobility are high, enabling high-speed operation and high-speed response.

[0030] The oxide semiconductor used for the oxide semiconductor film 403 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. The oxide semiconductor is used as a stabilizer for reducing oxygen vacancies in the oxide semiconductor. In addition, it is preferable to have gallium (Ga) in addition to them. It is preferable to use tin (Sn) as a stabilizer. It is preferable that the stabilizer is aluminum (Al). It is preferable that the stabilizer contains zirconium (Zr). It is nice.

[0031] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0032] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0033] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0034] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. It indicates one or more metal elements. In2SnO5 (ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0035] For example, In:Ga:Zn=1:1:1(=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxide with an atomic ratio of (=1 / 2:1 / 6:1 / 3) and its neighboring compositions Alternatively, the oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use -Zn-based oxides or oxides having a composition close to that.

[0036] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate.

[0037] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by lowering the defect density in the bulk. It can be done.

[0038] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1) is close to the oxide composition by r, and a, b, and c are (aA) 2 +(bB ) 2 +(cC) 2 ≦r 2 For example, if r is set to 0.05, The same is true for other oxides.

[0039] The oxide semiconductor film 403 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0040] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0041] Here, CAAC (C Axis Aligned Crystal) means that the c axis is aligned with the oxide. The three are perpendicular to the surface on which the semiconductor film is formed or the surface, and are perpendicular to the ab plane. It has a square or hexagonal atomic arrangement, and the metal atoms are arranged in layers or in a layered fashion when viewed perpendicular to the c-axis. This refers to a mixed phase structure of crystals and amorphous materials in which metal atoms and oxygen atoms are arranged in layers. In the multiphase structure, the a-axis and b-axis directions of the CAACs may be different. stomach.

[0042] CAAC Oxide Semiconductor (CAAC-OS:C Axis Aligned Crysta The thin film of a single-line oxide semiconductor (SOI) is not completely single crystal. The CAAC-OS film is an oxide semiconductor film with a crystalline-amorphous mixed phase structure. The size of the crystals is estimated to be several nm to several tens of nm. Observation using a Transmission Electron Microscope In the CAAC-OS film, the boundary between the amorphous portion and the CAAC portion is not necessarily clear. In addition, no crystal grain boundaries were observed in the CAAC-OS film. Since the CAAC-OS film does not have grain boundaries, the decrease in electron mobility caused by the grain boundaries is not observed. is less likely to occur.

[0043] In the CAAC-OS film, the distribution of crystalline regions in the film does not need to be uniform. For example, when crystals grow from the surface side of the CAAC-OS film, The proportion of crystals is higher near the surface where the material is formed, and the proportion of amorphous material is higher near the surface where the material is formed. There is.

[0044] The c-axis of the crystalline part of the CAAC is perpendicular to the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film (cross-sectional shape of the surface on which it is formed or cross-sectional shape of the surface) Therefore, the direction of the c-axis may be different. Note that the c-axis of the crystalline part of CAAC is The direction of the CAAC-OS film is approximately perpendicular to the surface on which the film is formed. CAAC is formed by performing a crystallization process such as heat treatment during or after the film formation. It is done.

[0045] By using the CAAC-OS film, the electrical characteristics of the transistors can be improved by irradiating them with visible light or ultraviolet light. Since the variation in the resistance is reduced, a highly reliable transistor can be obtained.

[0046] Note that part of oxygen contained in the oxide semiconductor film may be replaced with nitrogen.

[0047] The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). m or less) and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Dep The oxide semiconductor film 403 can be formed by a spatulation method or the like. Film deposition is performed on multiple substrate surfaces set approximately perpendicular to the target surface. The so-called CP sputtering equipment (Columner Plasma Sputtering) The film may be formed using a tering system.

[0048] 2A to 2E and 3A to 3D show a semiconductor device having a transistor 420. An example of a method for manufacturing the device is shown below.

[0049] First, electrode layers 422a and 422b are formed on a substrate 400 having an insulating surface. 22a and 422b are, for example, Al, Cr, Cu, Ta, Ti, Mo, and W. Metal films containing the selected elements or metal nitride films containing the above elements (e.g. titanium nitride) Films such as Al, C, molybdenum nitride, and tungsten nitride can be used. A high melting point metal film such as Ti, Mo, W, etc. is applied to the upper or lower side or both sides of the metal film such as u. or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) A laminated structure may also be used.

[0050] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. In addition, a silicon substrate, a silicon carbide substrate, etc. can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A semiconductor device having a semiconductor element on a substrate such as a silicon-on-insulator (SOI) substrate can also be used. may be used as the substrate 400.

[0051] Next, an insulating film 423 is formed to cover the electrode layers 422a and 422b. The answer is 2(A).

[0052] The insulating film 423 is formed by depositing silicon oxide, oxide film, or the like by plasma CVD or sputtering. Silicon nitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide The material may be a combination of these.

[0053] Next, the insulating film 423 and the electrode layers 422a and 422b are cut (grinded or polished). The grinding and polishing method is chemical mechanical polishing. A chemical polishing (CMP) method can be preferably used.

[0054] Next, electrode layers 424a and 424b are formed to overlap the electrode layers 422a and 422b. The electrode layers 424a and 424b may be made of, for example, Al, Cr, Cu, Ta, Ti, Mo, A metal film containing an element selected from W, or a metal nitride film containing the above-mentioned elements ( Titanium nitride film, molybdenum nitride film, tungsten nitride film, etc. can be used. A high melting point metal such as Ti, Mo, W is applied to the upper or lower side or both sides of the metal film such as Al, Cu, etc. Metal films or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) A laminated structure of a tantalum film may also be used.

[0055] Next, an insulating film 426 is formed to cover the electrode layers 424a and 424b. 2(B). Note that the boundary between the insulating film 423 and the insulating film 426 is indicated by a dotted line. When using the insulating film, the boundary is no longer clear, so the dotted lines indicating the boundary are omitted in the following figures. A stack of the electrode layer 422a and the insulating film 426 is illustrated as a base insulating layer 436. If the same material is used for the electrode layers 422a and 422b and the electrode layers 424a and 424b, there will be no clear boundary. Therefore, in the following figures, the dotted lines indicating the boundaries are omitted, and the electrode layers 422a, 422b and the electrode layer 42 The stack of layers 424a and 424b is illustrated as electrode layers 425a and 425b.

[0056] Next, the insulating film 426 and the electrode layers 424a and 424b are cut (grinded or polished). The CMP method is used as the grinding and polishing method.

[0057] Next, the oxide semiconductor film 403 is formed over the base insulating layer 436 and the electrode layers 425a and 425b. do.

[0058] Note that in this embodiment, the oxide semiconductor film 403 is formed by a sputtering method. The target for this purpose is a composition ratio of In:Ga:Zn=3:1:2 [atomic ratio]. An In-Ga-Zn oxide film (IGZO film) is formed using an oxide target.

[0059] The oxide semiconductor film 403 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or an arsenic compound. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0060] The substrate is held in a film-forming chamber that is kept in a reduced pressure state. Then, the remaining moisture in the film-forming chamber is removed. A sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the above target. In order to remove residual moisture in the deposition chamber, an oxide semiconductor film 403 is formed on the substrate. type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps It is preferable to use a turbo molecular pump with a cold trap as the exhaust means. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen atoms, water (H2O) and other compounds that contain hydrogen atoms (preferably compounds that contain carbon atoms) Since gases such as impurities and impurities are exhausted from the deposition chamber, the oxide semiconductor film 403 formed in the deposition chamber is The concentration of substances can be reduced.

[0061] The oxide semiconductor film 403 is formed by forming an island-like oxide semiconductor film into a film-like oxide semiconductor film by a photolithography process. The insulating film can be formed by processing the oxide semiconductor film.

[0062] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0063] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. For example, an etchant used for wet etching of an oxide semiconductor film may be used. The cleaning solution can be a mixture of phosphoric acid, acetic acid, and nitric acid. O-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Dry etching using the Inductively Coupled Plasma (ICP) etching method For example, the IGZO film can be etched by ICP etching. Then, etching was performed (etching conditions: etching gas (BCl3:Cl2 = 60 sccm: 20sccm), power supply power 450W, bias power 100W, pressure 1.9Pa), and It can be processed into.

[0064] In addition, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300° C. or higher and 700° C. or lower. The temperature should be below ℃ or below the distortion point of the substrate. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor The film 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0065] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0066] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0067] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not included. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than ppm.

[0068] Note that the timing of the heat treatment for dehydration or dehydrogenation is determined based on the time when the oxide semiconductor film is heated to 1000° C. The step may be performed after the formation of the island-shaped oxide semiconductor film 403 or after the formation of the island-shaped oxide semiconductor film 403.

[0069] The heat treatment for dehydration or dehydrogenation may be carried out multiple times or may be carried out in combination with other heat treatments. You can sleep.

[0070] In addition, oxygen (at least oxygen) is added to the oxide semiconductor film 403 that has been subjected to the dehydration or dehydrogenation treatment. oxygen radicals, oxygen atoms, or oxygen ions) are introduced into the film to supply oxygen. This is also fine.

[0071] In addition, oxygen, which is a main component material of an oxide semiconductor, can be removed by the dehydration or dehydrogenation treatment. In the oxide semiconductor film, oxygen is released and the amount of the oxide semiconductor film is reduced. In the area where the oxygen is removed, oxygen vacancies exist, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. Therefore, donor levels are generated.

[0072] Oxygen is introduced into the oxide semiconductor film 403 that has been subjected to dehydration or dehydrogenation treatment. By supplying the oxide semiconductor film 403, the oxide semiconductor film 403 is highly purified and electrically made to be i-type (intrinsic). The oxide semiconductor film 403 that has been highly purified and electrically i-type (intrinsic) can be used. The transistor thus formed has suppressed fluctuations in electrical characteristics and is electrically stable.

[0073] The oxygen introduction method includes ion implantation, ion doping, plasma immersion An implantation method, a plasma treatment, or the like can be used.

[0074] In the step of introducing oxygen into the oxide semiconductor film 403, The ions may be introduced directly or through other films such as the gate insulating layer 402 into the oxide semiconductor film 40. 3. When oxygen is introduced through another membrane, it is possible to use an ion implantation method, an ion drop method, or the like. The plasma immersion ion implantation method, etc. can be used. In the case where oxygen is directly introduced into the exposed oxide semiconductor film 403, plasma treatment or the like may be used. There can be.

[0075] Oxygen is preferably introduced into the oxide semiconductor film 403 after dehydration or dehydrogenation treatment. However, the present invention is not particularly limited to this. Oxygen may be introduced into 3 multiple times.

[0076] Next, a gate insulating layer 402 is formed to cover the oxide semiconductor film 403 (see FIG. 2C). .

[0077] The thickness of the gate insulating layer 402 is set to 1 nm or more and 20 nm or less. Methods such as a CVD method, a pulsed laser deposition method, and an ALD method can be used as appropriate. The insulating layer 402 is formed by forming a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. Even if a film is formed using a sputtering device that performs film formation in a set state, a so-called CP sputtering device, good.

[0078] The material of the gate insulating layer 402 is a silicon oxide film, a gallium oxide film, an aluminum oxide film, or the like. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a nitride oxide film. The gate insulating layer 402 can be formed using a silicon film. It is preferable that the gate insulating layer 402 contains oxygen in the portion in contact with the gate insulating layer 402. It is preferred that there is at least a stoichiometric amount of oxygen present (in the bulk), e.g. For example, when a silicon oxide film is used as the gate insulating layer 402, SiO 2+α (just In this embodiment, the gate insulating layer 402 is made of SiO 2+α (Ta The silicon oxide film is used as the gate insulating layer 40. By using the oxide semiconductor film 403 as the second oxide semiconductor film, oxygen can be supplied to the oxide semiconductor film 403, and the characteristics of the oxide semiconductor film 403 can be improved. In addition, the gate insulating layer 402 can be formed according to the size and thickness of the transistor to be manufactured. It is preferable to form the gate insulating layer 402 in consideration of the step coverage thereof.

[0079] The material of the gate insulating layer 402 may be hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and the use of high-k materials such as lanthanum oxide for the gate In addition, the gate insulating layer 402 may have a single layer structure or a stacked layer structure. It may also be a structure.

[0080] Next, a conductive film and an insulating film are stacked over the gate insulating layer 402, and the conductive film and the insulating film are Etching is performed to form a stack of a gate electrode layer 401 and an insulating film 413 (see FIG. 2C). see).

[0081] The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, aluminum, etc. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as their main components The gate electrode layer 401 can be formed using a gold material. Semiconductor films such as element-doped polycrystalline silicon films, nickel silicide, etc. The gate electrode layer 401 may have a single layer structure or a stacked layer structure. The structure may also be used.

[0082] The insulating film 413 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. , aluminum oxynitride film, silicon nitride film, aluminum nitride film, silicon nitride oxide film For example, an inorganic insulating film such as an aluminum nitride oxide film can be used as the insulating layer 413. The insulating film 11 can be formed by using a plasma CVD method, a sputtering method, or the like.

[0083] Next, the oxide semiconductor film 403 is doped with the gate electrode layer 401 and the insulating film 413 as masks. A pant 421 is introduced to form low resistance regions 404a and 404b (see FIG. 2(D)).

[0084] The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor film 403. The 421st group of elements includes group 15 elements (typically phosphorus (P), arsenic (As), and antimony). Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) , neon (Ne), indium (In), titanium (Ti), or zinc (Zn) One or more selected from the above can be used.

[0085] The dopant 421 is implanted through other films (e.g., the gate insulating layer 402) to The dopant 421 can also be introduced into the oxide semiconductor film 403. Ion implantation, ion doping, plasma immersion ion implantation Methods such as the above can be used.

[0086] The dopant 421 introduction process is performed by controlling the injection conditions such as the acceleration voltage and the dose amount, and the membrane through which the dopant 421 passes. In this embodiment, phosphorus is used as the dopant 421. The phosphorus ions are implanted by ion implantation using the dopant 421 at a dose of is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 The following would suffice.

[0087] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0088] The dopant 421 may be introduced while the substrate 400 is being heated.

[0089] Note that the treatment of introducing the dopant 421 into the oxide semiconductor film 403 may be performed multiple times. A plurality of dopants may be used.

[0090] After the dopant 421 is introduced, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be carried out.

[0091] In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The phosphorus (P) ion implantation conditions were an acceleration voltage of 30 kV and a dose of 1.0×1. 0 15 ions / cm 2 Let us assume that.

[0092] When the oxide semiconductor film 403 is a CAAC-OS film, the following can be achieved by introducing the dopant 421: In this case, a heat treatment is performed after the introduction of the dopant 421. As a result, the crystallinity of the oxide semiconductor film 403 can be restored.

[0093] By the above process, low resistance regions 404a and 404b are provided on either side of a channel forming region 409. An oxide semiconductor film 403 is formed.

[0094] Next, an insulating film is formed on the gate electrode layer 401 and the insulating film 413, and the insulating film is etched. Then, sidewall insulating layers 412a and 412b are formed. Using the edge layers 412a and 412b as a mask, the gate electrode layer 401 and the sidewall insulating layers 412a and The gate insulating layer is etched except for the area overlapping with 412b to form the gate insulating layer 402. (See Figure 3(A)).

[0095] The sidewall insulating layers 412a and 412b are formed using the same material and method as the insulating film 413. In this embodiment, a silicon oxynitride film formed by a CVD method is used. .

[0096] Next, the oxide semiconductor film 403, the gate insulating layer 402, the gate electrode layer 401, and the sidewall insulating layer On the insulating film 413, a source electrode layer and a drain electrode layer (and A conductive film is formed to become a wiring (including wiring formed in the same layer).

[0097] The conductive film is made of a material that can withstand a heat treatment to be performed later. The conductive film used is selected from, for example, Al, Cr, Cu, Ta, Ti, Mo, and W. Metal films containing the above elements, or metal nitride films containing the above elements (titanium nitride film, Molybdenum nitride film, tungsten nitride film, etc. can be used. In addition, Al, Cu, etc. A high melting point metal film such as Ti, Mo, W, etc. on either or both of the upper and lower sides of any metal film These metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) are laminated It may also be configured as such.

[0098] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After forming the island-shaped conductive film 445 by etching, the resist mask is removed. In this etching step, the conductive film 445 on the gate electrode layer 401 is not removed.

[0099] When a tungsten film having a thickness of 30 nm is used as the conductive film, the conductive film is etched as follows: For example, a tungsten film is etched by dry etching (etching conditions: Gas (CF4:Cl2:O2 = 55sccm:45sccm:55sccm, power supply voltage The tungsten island was formed under the conditions of 3000W power, 140W bias power, and 0.67Pa pressure. A film may be formed.

[0100] An insulating film 410 and an insulating film 446 are laminated on the island-shaped conductive film 445 to become an interlayer insulating film (FIG. 3(B)).

[0101] The insulating film 410 is made of a highly dense inorganic insulating film (typically an aluminum oxide film). It may be a layer or a laminate, and preferably contains at least an aluminum oxide film.

[0102] The insulating film 446 can be formed using a material and a method similar to those of the insulating film 413. The insulating film 446 is formed to a thickness that can flatten the unevenness caused by the transistor 420. In this embodiment, a silicon oxynitride film is formed to a thickness of 300 nm by a CVD method.

[0103] Next, the insulating film 446 and the conductive film 445 are polished by chemical mechanical polishing. Part of the insulating film 446, the insulating film 410, and the conductive film 445 are removed so that 13 is exposed.

[0104] By this polishing treatment, the insulating film 446 is processed into an interlayer insulating film 415, and the gate electrode layer 401 is The conductive film 445 is removed, and the source electrode layer 405a and the drain electrode layer 405b are formed. .

[0105] In this embodiment, the insulating film 446, the insulating film 410, and the conductive film 445 are removed by chemical mechanical etching. Although a polishing method was used, other cutting (grinding, polishing) methods may be used. In the process of removing the conductive film 445 on the substrate 01, cutting (grinding, polishing) such as chemical mechanical polishing is performed. In addition to the polishing method, etching (dry etching, wet etching) and plasma treatment For example, a chemical mechanical polishing process may be followed by a dry etching process. By using a sputtering method or plasma treatment (reverse sputtering, etc.), the flatness of the treated surface is improved. Cutting (grinding, polishing) method may be combined with etching method, plasma treatment, etc. In this case, the order of steps is not particularly limited, and the materials of the insulating film 446, the insulating film 410, and the conductive film 445 may be This may be appropriately set depending on the material, film thickness, and surface irregularities.

[0106] In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are The insulating layer 412a and the insulating layer 412b are provided on the side surfaces of the first electrode layer 401. The side surfaces of the sidewall insulating layers 412a and 412b are covered to a position slightly lower than the upper ends. The source electrode layer 405a and the drain electrode layer 405b are formed by removing the conductive film 445. As shown in this embodiment, the sidewall insulating layers 412a and 4 12b, the shape may be recessed in the film thickness direction from the polished surface of the insulating film 413. However, depending on the conditions of the polishing process, the source electrode layer 405a and the drain electrode layer 405 In some cases, the upper end of the insulating layer 412b may roughly coincide with the upper ends of the sidewall insulating layers 412a and 412b.

[0107] Through the above steps, the transistor 420 of this embodiment is manufactured (see FIG. 3C).

[0108] By such a manufacturing method, the source electrode layer 405a or the drain electrode layer 405b and the oxide The distance between the gate electrode layer 401 and the region (first contact region) where the semiconductor film 403 is in contact with the gate electrode layer 401 is In addition, the distance between the electrode layers 425a and 425b and the oxide semiconductor film 403 can be reduced. It is also possible to shorten the distance between the region (second contact region) where the gate electrode layer 401 comes into contact with the gate electrode layer 401. Therefore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film The resistance between the gate electrode layer 401 and the region (first contact region) where the gate electrode layer 403 is in contact with the gate electrode layer 401 is reduced. This makes it possible to slightly improve the on-characteristics of the transistor 420.

[0109] In addition, the gate electrode in the step of forming the source electrode layer 405a and the drain electrode layer 405b In the step of removing the conductive film 445 on the layer 401, a part of the insulating film 413 or the insulating film 4 Alternatively, the entirety of the gate electrode layer 13 may be removed. Also, an upper part of the gate electrode layer 401 may be removed. The transistor structure in which the gate electrode layer 401 is exposed is not intended to prevent other wiring or It is useful in integrated circuits in which semiconductor elements are stacked.

[0110] A highly dense inorganic insulating film (typically, aluminum oxide) is formed on the transistor 420 as a protective insulating film. A thin film (titanium film) may be provided.

[0111] In this embodiment, the insulating film 413, the source electrode layer 405a, the drain electrode layer 405b, An insulating film 412 is formed on the wall insulating layers 412a and 412b, the insulating film 410, and the interlayer insulating film 415. 07 (see Figure 3(D)).

[0112] The insulating film 407 may be a single layer or a multilayer, and preferably includes at least an aluminum oxide film. I wish.

[0113] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. This can be done.

[0114] Besides the aluminum oxide film, the insulating films 407 and 410 are typically silicon oxide films. , an inorganic insulating film such as a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film Also, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, etc. can be used. aluminium oxide film, lanthanum oxide film, barium oxide film, or a metal nitride film (e.g. aluminium nitride A thin film (aluminum film) can also be used.

[0115] In this embodiment, the insulating films 407 and 410 are made of aluminum oxide by sputtering. The aluminum oxide film is formed at a high density (film density 3.2 g / cm 3 The above is preferable. is 3.6g / cm 3 By setting the transistor 420 to a value of 0.1 V or more, stable electrical characteristics can be obtained. The film density can be measured by Rutherford backscattering spectroscopy (RBS). d Backscattering Spectrometry) and X-ray reflectivity measurement It can be measured by X-Ray Reflection (XRR).

[0116] The oxide semiconductor film 403 may be formed of an oxide semiconductor film having an oxide layer. The aluminum oxide membrane does not allow impurities such as hydrogen and moisture, and oxygen to pass through the membrane. It has a high blocking effect.

[0117] In addition, in FIG. 1A, the insulating film 410, the interlayer insulating film 415, and the insulating film 407 are provided with a source electrode. An opening is formed that reaches the wiring layer 435a and the drain electrode layer 405b. The wiring layers 435a and 435b are used to form other transistors and By connecting it to elements, various circuits can be configured.

[0118] The wiring layer 435a and the wiring layer 435b are connected to the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b. The layer 405b can be formed using the same material and method as the layer 405b. For example, Al a metal film containing an element selected from the group consisting of Cr, Cu, Ta, Ti, Mo, and W, or Metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) In addition, either the upper or lower side of a metal film such as Al or Cu can be used. A high melting point metal film such as Ti, Mo, W, etc. or a metal nitride film of these metals (titanium nitride) is used on both sides. A laminate of a nitride film, a molybdenum nitride film, and a tungsten nitride film may be used.

[0119] (Embodiment 2) In this embodiment mode, the transistor described in Embodiment 1 is used, and the transistor is used in a case where power is not supplied. An example of a semiconductor device that can retain memory contents and has no limit on the number of times it can be written to is as follows: The semiconductor device of this embodiment mode will be described with reference to the drawings. The transistor 420 described in the first embodiment is used.

[0120] FIG. 4 shows an example of the configuration of a semiconductor device. FIG. 4(A) shows a cross-sectional view of the semiconductor device, and FIG. 4(A) is a plan view of the semiconductor device, and FIG. 4(C) is a circuit diagram of the semiconductor device. FIG. 4A corresponds to the cross sections taken along lines C1-C2 and D1-D2 in FIG. 4B.

[0121] The semiconductor device shown in FIG. 4(A) and FIG. 4(B) has a transistor using a first semiconductor material in the lower part. 160 and a transistor 162 made of a second semiconductor material on top. The transistor 162 has the same structure as the transistor 420 described in Embodiment 1. It can be said that:

[0122] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0123] The transistor 162 is a transistor including an oxide semiconductor and has a low off-state current. By using this transistor, it is possible to retain memory contents for a long period of time. In other words, no refresh operation is required, or the frequency of refresh operations is extremely low. Since it is possible to provide a semiconductor memory device with a smaller number of elements, it is possible to sufficiently reduce power consumption. can.

[0124] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. Since the semiconductor device is used in a semiconductor device, the semiconductor device is The specific configuration of the is not necessarily limited to that shown here.

[0125] The transistor 160 in FIG. 4A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on the substrate 100, and a an impurity region 120 provided in the semiconductor substrate 10 and a metal compound region 124 in contact with the impurity region 120; A gate insulating layer 108 is provided on the channel forming region 116. and a gate electrode layer 110. Note that in the figure, the source electrode However, for convenience, the term "transistor" includes such a state. In this case, the source is sometimes called the transistor in order to explain the connection relationship. The source electrode and drain electrode may include the source region and drain region. In this specification, the term "source electrode" may include a source region.

[0126] An element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. An insulating layer 130 is provided to cover the transistor 160. To achieve this, the transistor 160 is provided with a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, In this case, a sidewall insulating layer is provided on the side of the gate electrode layer 110, and the impurity concentration is different. The impurity region 120 may include a region.

[0127] A transistor 162 illustrated in FIG. 4A is a transistor in which an oxide semiconductor is used for a channel formation region. The oxide semiconductor layer 144 includes a low resistance region 144a and a low resistance region 14 The low-resistance region 144a includes a conductive layer 143a and a channel formation region 144c. The low resistance region 144b is formed on and in contact with the conductive layer 143b. The formation region 144c is in contact with the insulating layer 154 sandwiched between the conductive layer 143a and the conductive layer 143b. It is formed.

[0128] In the manufacturing process of the transistor 162, the gate electrode 148, the insulating film 137, and the sidewall insulating film 138 are formed. removing the conductive film provided on the edge layers 136a and 136b by chemical mechanical polishing; The electrode layers 142a and 142b functioning as a source electrode layer and a drain electrode layer are formed using the above-mentioned Complete.

[0129] Therefore, the transistor 162 has an electrode layer functioning as a source electrode layer or a drain electrode layer. A region (contact region) where the oxide semiconductor layer 144 contacts the gate electrodes 142a and 142b, Since the distance to the electrode 148 can be shortened, the electrode layers 142a and 142b and the oxide semiconductor The resistance between the gate electrode 148 and the contact region with the conductor layer 144 is reduced. As a result, the on-characteristics of the transistor 162 can be improved.

[0130] On the transistor 162, an insulating film 149, an interlayer insulating film 135, and an insulating film 150 are formed in a single layer or a multilayer structure. In this embodiment, the insulating film 149 and the insulating film 150 are formed as a stack. The aluminum oxide film is made of high density aluminum oxide (film density 3.2 g / cm 3 End , preferably 3.6 g / cm 3 By setting the transistor 162 to a stable Electrical properties can be imparted.

[0131] The conductive layer 143 a and the insulating layer 144 are connected via the insulating film 149, the interlayer insulating film 135, and the insulating film 150. A conductive layer 153 is provided in the overlapping region, and the conductive layer 143a and the insulating film 149 are The interlayer insulating film 135, the insulating film 150, and the conductive layer 153 constitute a capacitance element 164. That is, the conductive layer 143a functions as one electrode of the capacitor element 164. The electrode layer 153 functions as the other electrode of the capacitor 164. Alternatively, the capacitor 164 may not be provided. , may be provided above the transistor 162.

[0132] An insulating film 152 is provided over the transistor 162 and the capacitor 164. On the insulating film 152, a transistor 162 and wiring for connecting other transistors are provided. The wiring 156a is provided between the insulating film 149 and the interlayer insulating film 13. 5, the insulating film 150, the insulating film 152, etc., are formed through an electrode formed in an opening. The wiring 156b is electrically connected to the insulating film 149 and the interlayer insulating film 135. , and the insulating film 150 and the insulating film 152 are electrically connected via electrodes formed in openings formed therein. It is electrically connected to layer 143b.

[0133] In FIG. 4A and FIG. 4B, the transistor 160 and the transistor 162 are The source region of the transistor 160 is provided so as to overlap at least a portion of the It is preferable that the drain region is provided so as to partially overlap the oxide semiconductor layer 144. In addition, the transistor 162 and the capacitor 164 are at least For example, the conductive layer 153 of the capacitor 164 is At least a portion of the gate electrode layer 110 of the transistor 160 is overlapped therewith. By adopting such a planar layout, the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0134] Next, an example of a circuit configuration corresponding to FIG. 4(A) and FIG. 4(B) is shown in FIG. 4(C).

[0135] In FIG. 4C, the first wiring (1st Line) and the source voltage of the transistor 160 The electrodes are electrically connected to the second wiring (2nd Line) and the drain of the transistor 160. The third line and the drain electrode are electrically connected. The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode. The wiring (4th Line) and the gate electrode layer of the transistor 162 are electrically connected. The gate electrode layer of the transistor 160 and the source layer of the transistor 162 are One of the source electrode and the drain electrode is electrically connected to the other electrode of the capacitor 164. The fifth wiring (5th Line) and the other electrode of the capacitor 164 are electrically connected to each other. There are.

[0136] In the semiconductor device illustrated in FIG. 4C, the potential of the gate electrode layer of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0137] The writing and holding of data will be described. First, the potential of the fourth wiring is set to the potential of the transistor 1. The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring is connected to the gate electrode layer of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the node FG. Here, the charge that gives two different potential levels (hereafter, Low level) is Then, a fourth charge (called a low-level charge or a high-level charge) is applied. The potential of the wiring is set to a potential at which the transistor 162 is turned off, By turning off the node FG, the charge applied to the node FG is held (retained).

[0138] Since the off-state current of the transistor 162 is extremely small, the gate electrode layer of the transistor 160 The charge is retained for a long time.

[0139] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the charge held in node FG In general, the transistor 160 is an n-channel In this case, the node FG (which can also be called the gate electrode of the transistor 160) The apparent threshold voltage V when a high level charge is applied to th_H is node F The apparent threshold voltage V when a low-level charge is applied to G th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is in the "on" state. Therefore, the potential of the fifth wiring is defined as V th_H and V th_L By setting the potential V0 between the two, the potential applied to the node FG is For example, if a high level charge is applied during writing, The potential of the fifth wire is V0 (> V th_H ), transistor 160 is "on" When a low-level charge is applied, the potential of the fifth wire becomes V0 ( <V th_L ), transistor 160 remains in the "off state." The stored data can be read out by monitoring the potential of the second wiring.

[0140] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 160 is in the "off state" regardless of th_H Alternatively, a smaller potential may be applied to the fifth wiring regardless of the state of the gate electrode layer. The potential at which transistor 160 is “on”, i.e., V th_L Larger current Just give the digits to the fifth wire.

[0141] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0142] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0143] In the transistor 162, the low-resistance region 144a of the oxide semiconductor layer is In order to contact and electrically connect the conductive layer 143a and the electrode layer 142a embedded in the layer, It is possible to reduce the contact resistance and provide excellent electrical characteristics (e.g., high on-current characteristics). Therefore, the transistor 162 can be used as a By doing so, it is possible to achieve high performance of the semiconductor device. Since the transistor is highly reliable, the reliability of the semiconductor device can be improved.

[0144] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0145] (Embodiment 3) In this embodiment mode, the transistor described in Embodiment 1 is used, and a A semiconductor device that can retain memory contents even in a difficult situation and has no limit on the number of times it can be written to. Regarding the configuration, which is different from the configuration shown in the second embodiment, will be described with reference to FIG. 5 and FIG. 6. Note that the semiconductor device of this embodiment has the same structure as the transistor 162 described in Embodiment 1. The transistor 162 is the transistor shown in the first embodiment. Any of the transistor structures can be applied.

[0146] FIG. 5(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 5(B) shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 5(A) will be explained, followed by the semiconductor device shown in FIG. The semiconductor device shown in FIG.

[0147] In the semiconductor device shown in FIG. 5A, the bit line BL and the source electrode of the transistor 162 The drain electrode is electrically connected to the word line WL and the gate of the transistor 162. The electrode layer is electrically connected to the source electrode or drain electrode of the transistor 162. The first terminal of the capacitance element 254 is electrically connected.

[0148] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long period of time. It is possible to retain it.

[0149] Next, data is written and held in the semiconductor device (memory cell 250) shown in FIG. The following describes how to do this.

[0150] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal of the transistor 1 By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the quantum element 254 is held (held).

[0151] Since the off-state current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitive element) can be held for a long period of time.

[0152] Next, the reading of information will be described. When the transistor 162 is turned on, The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0153] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is In this case, the potential of the first terminal of the capacitance element 254 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=CB×VB0+C×V1) / (CB+C) is the potential of the bit line BL when the potential V0 is held (=CB×VB0 +C×V0) / (CB+C)).

[0154] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0155] As described above, in the semiconductor device illustrated in FIG. 5A, the off-state current of the transistor 162 is extremely small. Due to its small size, the charge stored in the capacitance element 254 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to extremely reduce the power consumption, Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0156] Next, the semiconductor device shown in FIG. 5B will be described.

[0157] The semiconductor device shown in FIG. 5B has a memory cell 2 shown in FIG. 5A as a memory circuit in the upper portion. 50, and a memory cell array 251a and a memory cell array 251b each having a plurality of In addition, the memory cell array 251a and the memory cell array 251b are operated The peripheral circuit 253 includes a memory cell array 251a and a memory It is electrically connected to the recell array 251b.

[0158] By using the configuration shown in FIG. 5B, the peripheral circuit 253 is In addition, since it can be provided directly under the memory cell array 251b, the semiconductor device can be made smaller. It is possible.

[0159] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. In addition, organic semiconductor materials may be used. The transistor can operate at a sufficiently high speed. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require high speed operation. be.

[0160] In the semiconductor device shown in FIG. 5B, the memory cell array 251a and the memory cell array In the example shown, two memory cell arrays 251b are stacked. The number of memory cell arrays is not limited to this. is also good.

[0161] Next, a specific configuration of the memory cell 250 shown in FIG. 5(A) will be described with reference to FIG. conduct.

[0162] 6 shows an example of the configuration of the memory cell 250. FIG. 6A shows a plan view of the memory cell 250. 6(B) shows a cross-sectional view taken along line AB in FIG. 6(A).

[0163] The transistor 162 shown in FIGS. 6A and 6B has the same structure as that described in Embodiment 1. It is possible to have a single configuration.

[0164] As shown in FIG. 6B, a transistor 162 is provided over the electrode 502 and the electrode 504. The electrode 502 is a wiring that functions as the bit line BL in FIG. The electrode 504 is provided in contact with the low resistance region of the transistor 162. ) serves as one electrode of the capacitor 254 in the low resistance region of the transistor 162. In the transistor 162, a region overlapping with the electrode 504 is provided The electrode 506 functions as the other electrode of the capacitor 254 .

[0165] As shown in FIG. 6A, the other electrode 506 of the capacitor 254 is connected to a capacitor line 508. The gate insulating layer 146 is electrically connected to the oxide semiconductor layer 144. The port electrode 148 is electrically connected to a word line 509 .

[0166] FIG. 6C is a cross-sectional view of a connection portion between the memory cell array and the peripheral circuits. The peripheral circuit includes, for example, an n-channel transistor 510 and a p-channel transistor 51 2. The n-channel transistor 510 and the p-channel transistor The semiconductor material used for the transistor 512 is a semiconductor material other than an oxide semiconductor (silicon By using such a material, the transistors included in the peripheral circuits can be This allows the transistor to operate at high speed.

[0167] By adopting the planar layout shown in FIG. 6(A), the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0168] As described above, the memory cells formed in multiple layers on the upper portion are transistors using oxide semiconductors. The transistor is made of a highly purified and intrinsic oxide semiconductor. Since the off-current of a transistor is small, the memory contents can be maintained for a long period of time by using the transistor. In other words, the frequency of refresh operations can be reduced significantly. Therefore, the power consumption can be sufficiently reduced. As shown in FIG. 1B, the electrode 504, the oxide semiconductor layer 144, the gate insulating layer 146, and the electrode 506 are stacked to form the film.

[0169] In this way, transistors using materials other than oxide semiconductors (in other words, transistors that operate at sufficiently high speed) The peripheral circuits are made of transistors that can be operated with a semiconductor oxide. In a broader sense, the off-state current of the transistor is sufficiently small. This makes it possible to realize a semiconductor device having unprecedented features. By forming the gate and the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0170] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0171] (Embodiment 4) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, An example of application to a portable device such as a child book will be described with reference to FIGS.

[0172] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following. SRAM or DRAM is used The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: do.

[0173] In a normal SRAM, as shown in FIG. 7(A), one memory cell is made up of transistors 801 to 808. It is composed of six transistors, X decoder 807 and Y decoder 807. The transistor 803, the transistor 805, and the transistor 808 are driven by the 4 and transistor 806 form an inverter, enabling high-speed operation. The memory cell is composed of six transistors, so the cell area is large. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. stomach.

[0174] On the other hand, in a DRAM, the memory cell is made up of a transistor 811, a storage The signal is driven by an X decoder 813 and a Y decoder 814. Each cell is composed of one transistor and one capacitance, and has a small area. The memory cell area of ​​a RAM is usually 10F 2 However, DRAM is always refreshed. It requires a write operation and consumes power even if the data is not being rewritten.

[0175] However, the memory cell area of ​​the semiconductor device described in the above embodiment is 10F 2 Before and after and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0176] A block diagram of the portable device is shown in FIG. 8. The portable device shown in FIG. 8 includes an RF circuit 901, an analog base station, and a a digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply circuit 905, application processor 906, flash memory 910, display controller controller 911, memory circuit 912, display 913, touch sensor 919, voice The display 913 is a display unit 9 14, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 9 09. Generally, the memory circuit 912 is composed of SRAM or DRAM. By adopting the semiconductor device described in the previous embodiment for this portion, writing of information is possible. It has high speed read and write, long-term memory retention, and low power consumption. It is possible.

[0177] FIG. 9 shows a display memory circuit 950 using the semiconductor device described in the previous embodiment. The memory circuit 950 shown in FIG. 954, a switch 955, and a memory controller 951. The memory circuit includes a signal line from image data (input image data), memory 952, and memory 9 A display controller that reads and controls the data (stored image data) stored in 53. The display controller 956 controls the display to be displayed based on a signal from the display controller 956. Play 957 is connected.

[0178] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then The image is sent to a display 957 via a switch 955 and a display controller 956. , will be displayed.

[0179] When there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. The display controller 956 reads the data from the memory 952 via the switch 955. It is revealed.

[0180] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This readout is followed by the next new image data being stored in the memory. This continues until the data is stored in the memory 952.

[0181] In this way, the memory 952 and the memory 953 alternately write image data and receive image data. The display 957 is displayed by reading out the data from the memory 9 The memory 52 and the memory 953 are not limited to being separate memories, but may be one memory divided and used. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, information can be written and read at high speeds and memory can be retained for long periods of time. Moreover, power consumption can be sufficiently reduced.

[0182] FIG. 10 shows a block diagram of an electronic book. FIG. 10 shows a battery 1001, a power supply circuit 1002, and , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard A code 1006, a memory circuit 1007, a touch panel 1008, a display 1009, The display controller 1010 is configured as a display controller.

[0183] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The memory circuit 1007 has a function of temporarily storing the contents of a book. For example, when a user is reading an e-book, a certain part can be marked (changed in color). When you want to make changes to text (such as highlighting, underlining, making text bold, or changing the font), It has the function of temporarily storing and retaining information specified by the user. If the data is to be stored for a long period of time, it may be copied to the flash memory 1004. By adopting the semiconductor device described in the above embodiment, It has high speed read and write, long-term memory retention, and low power consumption. It is possible.

[0184] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. Thus, a portable device with reduced noise is realized.

[0185] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0186] 100 Substrates 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Gate electrode layer 116 Channel formation region 120 Impurity region 124 Metal compound area 130 Insulating layer 135 Interlayer insulating film 136a Sidewall insulating layer 136b Sidewall insulating layer 137 Insulating Film 142a Electrode layer 142b Electrode layer 143a Conductive layer 143b Conductive layer 144 Oxide semiconductor layer 144a Low resistance area 144b Low resistance region 144c Channel forming region 146 Gate Insulation Layer 148 gate electrodes 149 Insulating Film 150 Insulating film 152 Insulating film 153 Conductive Layer 154 Insulating Layer 156a Wiring 156b Wiring 160 Transistors 162 Transistor 164 Capacitive element 250 memory cells 251a Memory Cell Array 251b Memory Cell Array 253 Peripheral Circuits 254 Capacitive element 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 Oxide Semiconductor Film 404a Low resistance area 404b Low resistance region 405 Electrode layer 405a Electrode layer 405b Electrode layer 407 Insulating Film 409 Channel formation region 410 Insulating film 412a Sidewall insulating layer 412b Sidewall insulating layer 413 Insulating film 415 Interlayer insulating film 420 Transistor 421 Dopant 422a Electrode layer 422b Electrode layer 423 Insulating Film 424a Electrode layer 424b Electrode layer 425a Electrode layer 425b Electrode layer 426 Insulating Film 436 Undercoat insulation layer 445 Conductive Film 446 Insulating Film 502 Electrode 504 Electrode 506 Electrode 508 Capacitive Line 509 Word Line 510 n-channel transistor 512 p-channel transistor 801 Transistors 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X Decoder 808 Y Decoder 811 Transistor 812 holding capacity 813X Decoder 814 Y decoder 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 Keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

1. A first transistor, a second transistor, and a capacitor element, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; a semiconductor device in which one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor; a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitance element; the third conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film has a first region that does not overlap with the third conductive film; the first region of the first conductive film functions as one electrode of the capacitor element; the first region of the first conductive film has a region overlapping with the fifth conductive film with the insulating film therebetween and without the oxide semiconductor film therebetween; Semiconductor device.

2. A first transistor, a second transistor, and a capacitor element, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor element; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor; a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitance element; the third conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film has a first region that does not overlap with the third conductive film; the first region of the first conductive film functions as one electrode of the capacitor element; the first region of the first conductive film has a region overlapping with the fifth conductive film with the insulating film therebetween and without the oxide semiconductor film therebetween; Semiconductor device.

3. A first transistor, a second transistor, and a capacitor element, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; a semiconductor device in which one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor; a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitance element; the third conductive film has a region in contact with the oxide semiconductor film, the fourth conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film has a first region that does not overlap with the third conductive film; the first region of the first conductive film functions as one electrode of the capacitor element; the first region of the first conductive film has a region overlapping with the fifth conductive film with the insulating film therebetween and without the oxide semiconductor film therebetween; Semiconductor device.

4. A first transistor, a second transistor, and a capacitor element, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor element; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor; a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitance element; the third conductive film has a region in contact with the oxide semiconductor film, the fourth conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film has a first region that does not overlap with the third conductive film; the first region of the first conductive film functions as one electrode of the capacitor element; the first region of the first conductive film has a region overlapping with the fifth conductive film with the insulating film therebetween and without the oxide semiconductor film therebetween; Semiconductor device.

Images