High frequency device

Abstract

To provide a high frequency device capable of suppressing an oscillation.SOLUTION: A high frequency device 100 includes: a semiconductor chip 10 including a semiconductor substrate 11, and an amplifier that amplifies a high frequency signal, the amplifier being provided on a front surface of the semiconductor substrate; a first reference potential layer 38 which is provided to an upper direction of the semiconductor chip in a direction of an upper position vertical from the front surface of the semiconductor substrate so as to be overlapped with the semiconductor chip in a plan view from the upper direction, and to which a reference potential is supplied; and a resonator which is provided between the semiconductor chip and the first reference potential layer in the direction of the upper position vertical from the front surface of the semiconductor substrate. The resonator includes: an electrode that forms a capacitance between the electrode and the first reference potential layer; and a line that has a first end connected to the electrode and a second end electrically connected to the first reference potential layer, that forms an inductance, and that surrounds the electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a high frequency device, for example, a high frequency device having a semiconductor chip. [Background technology]

[0002] 2. Description of the Related Art High-frequency devices in which a semiconductor chip is mounted on a lead frame are known (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-050891 Summary of the Invention [Problem to be solved by the invention]

[0004] When a high-frequency signal amplified by a semiconductor chip having at least a part of an amplifier leaks to the input of the semiconductor chip, the amplifier may oscillate.

[0005] The present disclosure has been made in consideration of the above problems, and has an object to suppress oscillation. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a high-frequency device comprising: a semiconductor chip including a semiconductor substrate and an amplifier provided on a surface of the semiconductor substrate for amplifying a high-frequency signal; a first reference potential layer provided above the semiconductor chip in a direction perpendicular to the surface of the semiconductor substrate, overlapping the semiconductor chip in a planar view when viewed from above, and to which a reference potential is supplied; and a resonator provided between the semiconductor chip and the first reference potential layer in a direction perpendicular to the surface of the semiconductor substrate, the resonator comprising an electrode that forms a capacitance between the first reference potential layer, and a line surrounding the electrode, the first end of which is connected to the electrode and the second end of which is electrically connected to the first reference potential layer. Effect of the Invention

[0007] According to the present disclosure, oscillation can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a high-frequency device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view mainly showing the lower surface of the substrate in the high-frequency device according to the first embodiment, as viewed from above. [Diagram 3] FIG. 3 is a plan view mainly showing the upper surface of the lead frame in the high-frequency device according to the first embodiment. [Figure 4A] FIG. 4A is a plan view illustrating an example of the resonator in the first embodiment. [Figure 4B] FIG. 4B is a plan view illustrating another example of the resonator in the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view of the high-frequency device according to the first comparative example. [Figure 6] FIG. 6 is a cross-sectional view of a high-frequency device in Comparative Example 2. As shown in FIG. [Figure 7] FIG. 7 is a schematic diagram of a high-frequency device in Comparative Example 2. As shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view of a high-frequency device according to a third comparative example. [Figure 9]FIG. 9 is a schematic diagram of the high-frequency device in the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a high-frequency device according to a first modified example of the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a high-frequency device according to a second modification of the first embodiment. [Figure 12] FIG. 12 is a block diagram of a high-frequency device according to the second embodiment. [Figure 13] FIG. 13 is a plan view of the high-frequency device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a high-frequency device comprising: a semiconductor chip including a semiconductor substrate and an amplifier provided on a surface of the semiconductor substrate for amplifying a high-frequency signal; a first reference potential layer provided above the semiconductor chip in a direction perpendicular to the surface of the semiconductor substrate so as to overlap the semiconductor chip in a plan view when viewed from above, and to which a reference potential is supplied; and a resonator provided between the semiconductor chip and the first reference potential layer in a direction perpendicular to the surface of the semiconductor substrate, the resonator comprising an electrode forming a capacitance with the first reference potential layer, and a line surrounding the electrode, the first end of which is connected to the electrode and the second end of which is electrically connected to the first reference potential layer, which suppresses oscillation of the amplifier. (2) It is preferable that at least a portion of the resonator overlaps with at least a portion of the semiconductor chip in plan view from above. (3) It is preferable that the semiconductor chip further includes a substrate having a dielectric layer and a plurality of conductive layers stacked thereon, the plurality of conductive layers including the first reference potential layer, the resonator, and a signal line for transmitting the high-frequency signal to be input to or output from the semiconductor chip. (4) It is preferable that the semiconductor device further comprises a second reference potential layer provided between the first reference potential layer and the resonator and supplied with a reference potential, an electrode forming a capacitance between the resonator and the second reference potential layer, and a line surrounding the electrode having a first end connected to the electrode and a second end connected to the second reference potential layer to form an inductance. (5) It is preferable that the resonator has an electrical length greater than 1 / 8 and less than 3 / 8 of the wavelength of a signal at a center frequency of the operating frequency band of the amplifier, and comprises a distributed constant line having a first end connected to a reference potential and the other end open. (6) It is preferable that the semiconductor chip is mounted on a lead frame having a base portion connected to the semiconductor chip on a back side opposite to the front side of the semiconductor substrate, and a signal lead portion electrically connected to an electrode formed on the front side of the semiconductor substrate, and the signal lead portion is joined to the signal line. (7) It is preferable that the semiconductor device further comprises bumps provided on the surface of the semiconductor substrate for connecting the signal lines and the semiconductor chip. (8) It is preferable that the semiconductor device further comprises a heat dissipation member provided on a rear surface opposite to the front surface of the semiconductor substrate.

[0010] [Details of the embodiment of the present disclosure] Specific examples of high-frequency devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] FIG. 1 is a cross-sectional view of the high-frequency device according to the first embodiment. FIG. 2 is a plan view mainly showing the lower surface of the substrate in the high-frequency device according to the first embodiment from above. FIG. 3 is a plan view mainly showing the upper surface of the lead frame in the high-frequency device according to the first embodiment. FIG. 1 corresponds to the AA cross section of FIGS. 2 and 3. In FIG. 1, the lead 43 located behind the leads 46a and 46b is shown in white. The stacking direction of the heat sink 44, the lead frame 40, and the substrate 20 is the Z direction, the direction from the signal lines 36a to 36b is the X direction, and the direction perpendicular to the X direction and the Z direction is the Y direction.

[0012] As shown in FIGS. 1 to 3, in the high-frequency device 100 of the first embodiment, the semiconductor chip 10 is mounted on the base 42 of the lead frame 40, and the substrate 20 is provided on the lead 43 of the lead frame 40. The semiconductor chip 10 has at least a part of an amplifier for amplifying a high-frequency signal on its upper surface, and the high-frequency signal is supplied from the substrate 20 to the semiconductor chip 10 via the lead 46a or 46b, and the high-frequency signal amplified in the semiconductor chip 10 is output to the substrate 20 via the lead 46a or 46b. A heat sink 44 is provided below the semiconductor chip 10 via the base 42. Heat generated in the amplifier formed on the upper surface of the semiconductor chip 10 is released from the lower surface of the semiconductor chip 10 to the heat sink 44 via the base 42. In this way, electrical connection with the semiconductor chip 10 is made from above, that is, in the direction of the upper surface (+Z direction) when viewed in a cross section of the semiconductor chip 10 as shown in FIG. 1, and heat dissipation from the semiconductor chip 10 is made from below, that is, toward the lower surface (-Z direction) when viewed in a cross section of the semiconductor chip 10 as shown in FIG. 1. Provided above the substrate 20 and further above the semiconductor chip 10 is a conductive plate 49 which forms part of a housing in which the high-frequency device 110 is mounted. A reference potential is supplied to the conductive plate 49.

[0013] The lead frame 40 includes a base 42, and leads 43, 46a, and 46b. The lead 43 is connected to the base 42 and has the same potential as the base 42. The leads 46a and 46b are separated from the base 42. The lead frame 40 is a metal layer such as a copper layer. The semiconductor chip 10 is mounted on the base 42.

[0014] The semiconductor chip 10 includes a semiconductor substrate 11, electrodes 12 and 13 provided on the upper surface of the semiconductor substrate 11, and an electrode 14 formed on the lower surface of the semiconductor substrate 11. An amplifier is provided on the surface of the semiconductor substrate 11. When the amplifier included in the semiconductor chip 10 is a FET (Field Effect Transistor) such as a GaN-HEMT (Gallium Nitride High Electron Mobility Transistor), the electrodes 12, 13, and 14 are a gate electrode, a drain electrode, and a source electrode, respectively, and the electrodes 12 and 13 are an input pad and an output pad, respectively. The electrodes 12, 13, and 14 are metal layers such as a gold layer. The electrode 14 is electrically connected to the base 42 by a bonding material 15 and is short-circuited. The bonding material 15 is conductive, and is, for example, a brazing material such as solder or a metal paste such as silver paste.

[0015] The lead 46a and the electrode 12 are electrically connected by a bonding wire 16a, and the lead 46b and the electrode 13 are electrically connected by a bonding wire 16b. The bonding wires 16a and 16b are metal wires such as gold wires. The lead frame 40 and the semiconductor chip 10 are sealed in a sealing portion 48. The sealing portion 48 is an insulator such as epoxy resin. The lower surfaces of the base 42 and the sealing portion 48 are joined to the upper surface of the heat sink 44 by a bonding material 45. The bonding material 45 is a material with high thermal conductivity such as a heat conductive sheet. The heat sink 44 is a material with high thermal conductivity such as copper.

[0016] The substrate 20 is, for example, a PCB (Printed Circuit Board) and includes a dielectric layer 21, a via wiring 23, and conductive layers 22 and 24. The dielectric layer 21 is a single layer or a multilayer, and is, for example, a resin layer such as FR-4 (Flame Retardant Type 4) or a ceramic layer. The conductive layers 22 and 24 are provided on the upper and lower surfaces of the dielectric layer 21, respectively. The via wiring 23 penetrates the dielectric layer 21. The via wiring 23 and the conductive layers 22 and 24 are, for example, metal layers such as copper layers. The conductive layer 22 is provided on almost the entire upper surface of the dielectric layer 21, and is a reference potential layer 38 to which a reference potential such as a ground potential is supplied. The conductive layer 24 forms a resonator pattern 30, signal lines 36a, 36b, pads 37a, 37b, and a pattern 39. The planar layout shape of the resonator pattern 30 appears to overlap the planar shape of the semiconductor chip 10 when viewed from the Z direction. A part of the resonator pattern 30 is electrically connected to the reference potential layer 38 through the via wiring 23 and short-circuited.

[0017] The signal lines 36a and 36b are connected to pads 37a and 37b, respectively. The signal line 36a and the reference potential layer 38 form a microstrip line, which is a transmission line, and the signal line 36b and the reference potential layer 38 form a microstrip line. The pads 37a and 37b are respectively bonded to leads 46a and 46b via a bonding material 25. A high-frequency signal is transmitted to the electrode 12 of the semiconductor chip 10 via the signal line 36a, the pad 37a, the lead 46a, and the bonding wire 16a. The high-frequency signal amplified by the semiconductor chip 10 and output to the electrode 13 is output via the bonding wire 16b, the lead 46b, the pad 37b, and the signal line 36b. The pattern 39 is bonded to the lead 43 by a bonding material. The pattern 39 is connected to the reference potential layer 38 and short-circuited, so that a reference potential is supplied to the base 42. A reference potential is supplied to the base 42 via the pattern 39 and the lead 43.

[0018] FIG. 4A is a plan view showing an example of a resonator pattern in the first embodiment. As shown in FIG. 4A, the resonator pattern 30 includes an electrode 31 and a line 32. The electrode 31 faces the reference potential layer 38 via the dielectric layer 21. The electrode 31 and the conductor layer 22 sandwiching the dielectric layer 21 form a capacitor. A first end of the line 32 is connected to the electrode 31 by a connection portion 33. A second end of the line 32 is connected to the reference potential layer 38 via the via wiring 23. The line 32 forms an inductor laid out in a ring shape surrounding the electrode 31. As a result, a capacitor and an inductor are connected in parallel between the electrode 31 and the reference potential layer 38. From another perspective, the capacitor and the inductor are a ring-shaped series resonator in which the capacitor and the inductor are connected in series from the reference potential layer 38 to the reference potential layer 38, and function as a series resonator that resonates at the frequency of a high-frequency signal. The series resonator formed by the resonator pattern 30 has a minimum impedance at the resonant frequency.

[0019] FIG. 4B is a plan view showing another example of the resonator pattern in the first embodiment. As shown in FIG. 4B, the resonator pattern 30 includes a distributed constant line 34 laid out in a spiral shape that forms a microstrip line between the semiconductor chip 10 and the reference potential layer 38. A first end of the distributed constant line 34 is open (i.e., open). A second end of the distributed constant line 34 is connected to the reference potential layer 38 through the via wiring 23. The electrical length of the distributed constant line 34 is about λ / 4, where λ is the wavelength of the high-frequency signal amplified by the semiconductor chip 10. The wavelength λ is the wavelength in the dielectric layer 21. This allows the distributed constant line 34 to function as a series resonator that resonates at the frequency of the high-frequency signal. The resonator formed by the resonator pattern 30 has a minimum impedance at the resonant frequency. A part of the high-frequency signal amplified by the semiconductor chip 10 is radiated into space. The resonator formed by the resonator pattern 30 attenuates a part of the radiated high-frequency signal. Details will be described later. Although the planar shape of the resonator pattern 30 has been described as being substantially square or circular, the planar shape of the resonator pattern 30 may be arbitrarily set to a rectangular, polygonal, elliptical or other shape.

[0020] [Comparative Example 1] FIG. 5 is a cross-sectional view of a high-frequency device according to Comparative Example 1. As shown in FIG. 5, in the high-frequency device 110 according to Comparative Example 1, the semiconductor chip 10 is mounted on the lead frame 40, and the substrate 20 is provided below the lead frame 40. A heat sink 44 is provided below the substrate 20. In Comparative Example 1, the substrate 20 for handling electrical signals, such as the high-frequency signal input to the semiconductor chip 10, the high-frequency signal output from the semiconductor chip 10, and the reference potential supplied to the semiconductor chip 10, outside the semiconductor chip 10 is located below the semiconductor chip 10. Heat dissipation from the lower surface of the semiconductor chip 10 is also performed from the heat sink 44 via the substrate 20, that is, similarly from below the semiconductor chip 10. In this way, electrical connection with the semiconductor chip 10 is performed from below, that is, in the direction of the lower surface (-Z direction) as viewed in the cross section of the semiconductor chip 10 as shown in FIG. 5, and heat dissipation from the semiconductor chip 10 is also performed from below, that is, in the direction of the lower surface (-Z direction) as viewed in the cross section of the semiconductor chip 10 as shown in FIG. 5.

[0021] In the lead frame 40, the semiconductor chip 10 is mounted on the base 42. The leads 46a and 46b are electrically connected to the electrodes 12 and 13 via the bonding wires 16a and 16b, respectively. The lead frame 40 and the semiconductor chip 10 are sealed by a sealing part 48. In the substrate 20, the conductive layer 22 forming the reference potential layer 38 is provided on the lower surface of the dielectric layer 21, and the conductive layer 24 is provided on the upper surface of the dielectric layer 21. The conductive layer 24 includes signal lines 36a and 36b, pads 37a and 37b, and a pattern 24a. The pads 37a and 37b and the pattern 24a are connected to the leads 46a and 46b of the lead frame 40 and the base 42 by the bonding material 25. The pattern 24a is connected to the reference potential layer 38 by a plurality of via wirings 23. The reference potential layer 38 is bonded to the heat sink 44 via the bonding material 45.

[0022] In Comparative Example 1, the distance between the semiconductor chip 10 and the conductive plate 49 forming a part of the housing in which the high frequency device 110 is mounted is long. Therefore, even if a part of the high frequency signal amplified in the semiconductor chip 10 is radiated into the space, the signal reflected by the conductive plate 49 and returned to the input side of the semiconductor chip 10 is very small. This makes it unlikely that the amplifier including the semiconductor chip 10 will oscillate. However, the heat generated in the semiconductor chip 10 is released to the heat sink 44 via the base 42, the pattern 24a, the via wiring 23, and the conductive layer 22. Thus, the heat dissipation path is long, resulting in poor heat dissipation performance.

[0023] [Comparative Example 2] FIG. 6 is a cross-sectional view of a high-frequency device according to Comparative Example 2. As shown in FIG. 6, in the high-frequency device 112 according to Comparative Example 2, electrical connection with the semiconductor chip 10 is made from above, and heat dissipation from the semiconductor chip 10 is made from below. Electrical connection with the semiconductor chip 10 is made from above, that is, in the direction of the upper surface (+Z direction) as viewed in the cross section of the semiconductor chip 10 as shown in FIG. 6, and heat dissipation from the semiconductor chip 10 is made from below, that is, in the direction of the lower surface (-Z direction) as viewed in the cross section of the semiconductor chip 10 as shown in FIG. 6. As a result, since the heat sink 44 is joined to the base 42, the heat dissipation path from the semiconductor chip 10 to the heat sink 44 is short, and the heat dissipation is better than that of Comparative Example 1. However, the reference potential layer 38 to which a reference potential is supplied is located on the upper surface of the substrate 20. The reference potential layer 38 is provided to provide a transmission line such as a microstrip line in the substrate 20.

[0024] FIG. 7 is a schematic diagram of a high-frequency device 112 in Comparative Example 2. The substrate 20 and the semiconductor chip 10 are shown in schematic form. As shown in FIG. 7, the semiconductor chip 10 amplifies an input high-frequency signal 51. Then, the semiconductor chip 10 outputs an amplified high-frequency signal 52. A part 50 of the amplified high-frequency signal is emitted into space. The thickness of the dielectric layer 21 is, for example, 3 mm or less. Therefore, the part 50 of the high-frequency signal emitted into space reaches the reference potential layer 38 without its amplitude being significantly attenuated. Thereafter, the part 50 of the high-frequency signal is reflected by the reference potential layer 38, input to the input side of the semiconductor chip 10, and further amplified inside the semiconductor chip 10, thus performing a positive feedback of the signal. This increases the risk of the amplifier including the semiconductor chip 10 oscillating.

[0025] [Comparative Example 3] FIG. 8 is a cross-sectional view of the high-frequency device 114 according to Comparative Example 3. As shown in FIG. 8, in the high-frequency device 114 according to Comparative Example 3, the substrate 20 has an opening 29. The opening 29 is located above the semiconductor chip 10. Since the conductive layer 22 serving as a reference potential layer is not provided above the semiconductor chip 10, a part of the high-frequency signal radiated into the space is not reflected by the reference potential layer 38, and as a result, the amplifier is unlikely to oscillate. However, if a conductive plate 49 forming a part of the housing of the high-frequency device 114 is provided near the high-frequency device 114, a part of the high-frequency signal radiated into the space is reflected by the conductive plate 49, and the amplifier may oscillate as in Comparative Example 2. In this way, the characteristics of the amplifier change depending on the environment in which the high-frequency device 114 is installed. In addition, since a transmission line or the like cannot be formed in the opening 29, there is a risk of a problem occurring in terms of the degree of freedom in designing the high-frequency device.

[0026] [Principle of Example 1] FIG. 9 is a schematic diagram of a high-frequency device 100 in the first embodiment. The substrate 20 and the semiconductor chip 10 are illustrated in a schematic side view of the high-frequency device 100. As shown in FIG. 9, in the first embodiment, a resonator pattern 30 is provided on the substrate 20. When a part 50 of a high-frequency signal amplified and radiated into space is irradiated to the resonator pattern 30, the resonator pattern 30 operates as a series resonator 35 in which a capacitor C and an inductor L are connected in series. Although a resistor R is a parasitic resistor, a resistive element may be added. The resonator pattern 30 is designed so that the resonant frequency of the series resonator 35 is the frequency of the high-frequency signals 51 and 52 or a frequency close to the frequency. Therefore, when a part 50 of the amplified high-frequency signal is radiated into space and irradiated to the resonator pattern 30, the resonator pattern 30 operates as a series resonator 35, and the impedance becomes minimal at the resonant frequency of the series resonator 35. Therefore, the part 50 of the high-frequency signal radiated into space is attenuated by the resistor R while resonating. As a result, a portion 50 of the high frequency signal radiated into the space is absorbed by the resonator pattern 30 and does not reach the reference potential layer 38 located further above. Alternatively, a portion 50 of the high frequency signal radiated into the space is reflected by the reference potential layer 38 and is not input to the input side of the semiconductor chip 10. Thus, the positive feedback as in Comparative Example 2 is suppressed, and oscillation of the amplifier including the semiconductor chip 10 can be suppressed. Furthermore, even if the conductor plate 49 is provided near the high frequency device, the conductor plate 49 is less likely to be affected because the reference potential layer 38 is provided. Thus, the characteristics of the high frequency device can be made constant regardless of the environment in which the high frequency device is installed.

[0027] The resonator pattern 30 is not connected to any power source, and a current flows due to a self-induced electromotive force generated by a change in magnetic flux passing through the inside of the coil of the coiled inductor when a high-frequency signal irradiated from outside is applied. Since the resonator pattern 30 can be regarded as a series resonator 35, the impedance of the resonator pattern 30 becomes smaller as the frequency of the irradiated high-frequency signal approaches the resonant frequency of the series resonator 35, and the impedance becomes a minimum at that resonant frequency. As a result, the current flowing through the resonator pattern 30 becomes larger as the frequency of the irradiated high-frequency signal approaches the resonant frequency of the series resonator 35. Energy is not consumed in the capacitor C and inductor L that constitute the resonator pattern 30, and the energy of the high-frequency signal irradiated from outside is attenuated and consumed only in the resistor R, which is a parasitic resistor. As long as the resonator pattern 30 does not prevent the self-induced electromotive force from being generated by the high-frequency signal irradiated from outside, the resistor R may be a parasitic resistor or an external resistor element. When the resonator pattern 30 generates a self-induced electromotive force due to an externally irradiated high-frequency signal and a current flows, the greater the resistance value of the resistor R, the greater the energy consumed.

[0028] In Comparative Example 2, a reference potential layer 38 (first reference potential layer) to which a reference potential is supplied is provided above the semiconductor chip 10 in an upward direction (Z direction) perpendicular to the surface (front surface) of the semiconductor substrate 11 so as to overlap with the semiconductor chip 10 in a plan view seen from above. This causes oscillation in an amplifier including the semiconductor chip 10, as shown in Fig. 7. Therefore, according to Example 1, a series resonator 35 (resonator) is provided between the semiconductor chip 10 and the reference potential layer 38 in an upward direction (Z direction) perpendicular to the surface of the semiconductor substrate 11, as shown in Fig. 9.

[0029] The amplifier has an amplifiable operating frequency band Δf. The center frequency fo of the operating frequency band Δf is, for example, 0.5 GHz to 10 GHz. The operating frequency band Δf is, for example, 0.05×fo to 0.2×fo. For example, fo is 2 GHz to 4 GHz, and Δf is 0.2 GHz to 0.4 GHz. Since the series resonator 35 absorbs high-frequency signals within the operating frequency band Δf, the resonant frequency of the series resonator 35 is included within the operating frequency band Δf, that is, within the range of fo±Δf / 2. The resonant frequency of the series resonator 35 is preferably within the range of fo±2×Δf / 5, and more preferably within the range of fo±Δf / 4. When the impedance of the series resonator 35 becomes minimum at the resonant frequency, a part 50 of the high-frequency signal is reflected by the series resonator 35. Therefore, the impedance of the series resonator 35 becomes minimum at the resonant frequency of the series resonator 35. As a result, the part 50 of the high-frequency signal is absorbed by the resonator pattern 30. Therefore, the oscillation of the amplifier can be suppressed.

[0030] When viewed from above, the resonator pattern 30 only needs to be provided in the vicinity of the semiconductor chip 10. As shown in Fig. 7, a portion 50 of the high frequency signal that is positively fed back to the input side of the semiconductor chip 10 passes directly above the semiconductor chip 10. Therefore, when viewed from above, it is preferable that at least a portion of the series resonator 35 overlaps with at least a portion of the semiconductor chip 10. This makes it possible to prevent the portion 50 of the high frequency signal from being positively fed back to the input side of the semiconductor chip 10. Therefore, oscillation of the amplifier can be further suppressed.

[0031] The substrate 20 is provided on the semiconductor chip 10, and a dielectric layer 21 and a plurality of conductor layers 22 and 24 are laminated. The conductor layer 24 includes signal lines 36a and 36b that transmit high-frequency signals to be input or output to the semiconductor chip 10. The conductor layer 22 includes a reference potential layer 38 for the signal lines 36a and 36b. In this manner, the substrate 20 is electrically connected to the semiconductor chip 10 from above. In this case, the reference potential layer 38 is provided near the top of the semiconductor chip 10. Therefore, a part 50 of the high-frequency signal is reflected by the conductor layer 22, which makes it easier for the amplifier to oscillate. Therefore, it is preferable to provide the resonator pattern 30 using the conductor layer 24 in the substrate 20. By forming the resonator pattern 30 using the conductor layer 24, the resonator pattern 30 can be made smaller.

[0032] Although the example in which the signal lines 36a, 36b and the resonator pattern 30 are formed by the conductor layer 24 provided on the lower surface of the substrate 20 has been described, at least one of the signal lines 36a, 36b and the resonator pattern 30 may be formed by a conductor layer in the inner layer of the substrate 20. In addition, although the example in which the reference potential layer 38 is formed by the conductor layer 22 provided on the upper surface of the substrate 20 has been described, the reference potential layer 38 may be formed by a conductor layer in the inner layer of the substrate 20.

[0033] 4A, the resonator pattern 30 includes an electrode 31 that forms a capacitance between itself and the reference potential layer 38, and a line 32 that forms an inductance surrounding the electrode 31, the line 32 having a first end connected to the electrode 31 and a second end electrically connected to the reference potential layer 38. This allows the formation of a series resonant circuit.

[0034] As shown in Fig. 4B, the resonator pattern 30 has an electrical length of about 1 / 4 of the wavelength λ (i.e., the length of one period) at the center frequency fo of the amplifier's operating frequency band Δf, and includes a distributed constant line 34 with a first end connected to a reference potential and the other end open. This allows the resonator pattern 30 to be formed. If the electrical length of the distributed constant line 34 is longer than λ / 8 and shorter than 3λ / 8, it functions as a resonator that obtains attenuation at the frequency fo. It is preferable that the electrical length of the distributed constant line 34 is longer than 3λ / 16 and shorter than 5λ / 16.

[0035] The lead frame 40 includes a base 42 (base portion) on which the semiconductor chip 10 is mounted and which is connected to the semiconductor chip 10 on the back surface (back surface opposite to the front surface) of the semiconductor substrate 11, and leads 46a and 46b (signal lead portions) which are electrically connected to electrodes provided on the top surface of the semiconductor substrate 11. The leads 46a and 46b are joined to the signal lines 36a and 36b. This allows the semiconductor chip 10 and the substrate 20 to be electrically connected. A chip other than the semiconductor chip 10, such as a matching circuit, can be mounted on the base 42 of the lead frame 40.

[0036] The substrate 20 is provided on the back surface of the semiconductor substrate 11, and the heat sink 44 (i.e., heat dissipation member) is provided under the semiconductor chip 10. This improves heat dissipation since heat is not dissipated via the substrate 20 as in the comparative example 1.

[0037] [Modification 1 of Example 1] FIG. 10 is a cross-sectional view of a high-frequency device according to a first modified example of the first embodiment. As shown in FIG. 10, in a high-frequency device 102, a substrate 20 includes laminated dielectric layers 21a and 21b. A conductor layer 26 is provided between the dielectric layers 21a and 21b. The conductor layer 26 forms a reference potential layer 38a to which a reference potential such as a ground is supplied. The resonator pattern 30 is connected to the reference potential layer 38a through a via wiring 23. The reference potential layer 38a may be electrically connected to and short-circuited with the reference potential layer 38 through a via wiring or the like. A reference potential different from that between the reference potential layers 38 and 38a may be supplied. The other configurations are the same as those of the first embodiment, and a description thereof will be omitted.

[0038] When the signal lines 36a and 36b and the reference potential layer 38 form a microstrip line, the characteristic impedance of the microstrip line is determined by the dielectric constant of the dielectric layer 21, the width of the signal lines 36a and 36b, and the distance T1 between the signal lines 36a and 36b and the reference potential layer 38. When the power of the high-frequency signal is large, it is required to increase the width of the signal lines 36a and 36b and to make the current density flowing through the signal lines 36a and 36b equal to or less than a specified value. As an example, when the power of the high-frequency signal amplified by the semiconductor chip 10 is 50 W and the frequency is 2 to 3 GHz, the width of the signal line 36b is 1 mm or more. When the relative dielectric constant of the dielectric layer 21 is about 5 and the characteristic impedance is 50 Ω, the distance T1 is 0.5 mm or more. The capacitance of the resonator pattern 30 is determined by the resonator frequency of the resonator pattern 30. When the area of ​​the electrode 31 in FIG. 4A is 10 mm 2 In order to achieve this, the distance T2 between the resonator pattern 30 and the reference potential layer 38a is preferably about 0.1 mm. In this manner, it may be preferable to set the distances T1 and T2 to different values.

[0039] According to the first modification of the first embodiment, a reference potential layer 38a (second reference potential layer) is provided between the reference potential layer 38 and the resonator pattern 30 to supply a reference potential. The resonator pattern 30 includes an electrode that forms a capacitance with the reference potential layer 38a, and a line that forms an inductance with a first end connected to the electrode and a second end connected to the reference potential layer 38a. This allows the transmission line formed by the signal lines 36a and 36b and the reference potential layer 38 and the capacitance to be set independently. A reference potential layer 38a may be provided separately from the reference potential layer 38 in a resonator including the distributed constant line 34 laid out in a spiral shape as shown in FIG. 4B.

[0040] [Modification 2 of Example 1] FIG. 11 is a cross-sectional view of a high-frequency device according to a second modified example of the first embodiment. As shown in FIG. 11, in the high-frequency device 104, the lead frame 40 is not provided, and the semiconductor chip 10 is flip-chip mounted on the substrate 20 by the bumps 27 or the like. The bumps 27 are, for example, solder or copper pillars. The semiconductor chip 10 is bonded onto a heat sink 44 by a bonding material 45. The semiconductor chip 10 includes a substrate 17a, an active layer 17b, and a wiring layer 17c. The surface of the substrate 17a on which the active layer 17b is located is the front surface of the semiconductor chip 10, and an amplifier is formed on the front surface. The surface of the substrate 17a opposite to the surface on which the active layer 17b is located is the back surface of the semiconductor chip 10. The amplifier includes, for example, a GaN-HEMT. In the case of a GaN-HEMT, the substrate 17a is, for example, a SiC substrate, a sapphire substrate, a silicon substrate, or a GaN substrate. The active layer 17b is, for example, a GaN channel and an AlGaN barrier layer, and an active element such as a GaN-HEMT is formed on the active layer 17b. The wiring layer 17c rearranges the electrodes of the GaN-HEMT. In the case of an MMIC (Monolithic Microwave Integrated Circuit), a matching circuit consisting of a capacitor and an inductor may be provided in the wiring layer 17c. A lead frame or the like may be provided as a heat spreader between the semiconductor chip 10 and the heat sink 44. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0041] As in the second modification of the first embodiment, bumps 27 are provided on the surface of the semiconductor substrate 11 to connect the signal lines 36a and 36b to the semiconductor chip 10. This allows electrical connection between the semiconductor chip 10 and the substrate 20. The semiconductor chip 10 can be bonded to the heat sink 44 without the lead frame 40. This improves heat dissipation.

[0042] [Example 2] The second embodiment is an example of a high-frequency power amplifier used in a base station as a high-frequency device. FIG. 12 is a block diagram of a high-frequency device according to the second embodiment. As shown in the second embodiment, the high-frequency device 106 includes amplifiers 61, 63a, and 63b, and matching circuits 60, 62a, 62b, 64a, and 64b. The high-frequency device 106 is a two-stage amplifier. A high-frequency signal inputted from an input terminal Tin is amplified by the amplifier 61, and further amplified by the amplifiers 63a and 63b, and outputted from an output terminal Tout. The matching circuit 60 is mounted on the chip 18a, the matching circuits 62a and 62b are mounted on the chip 18b, and the matching circuits 64a and 64b are mounted on the chip 18c. The amplifiers 61, 63a, and 63b are, for example, transistors, such as FETs (Field Effect Transistors), and are mounted on the semiconductor chips 10a to 10c, respectively.

[0043] The input terminal Tin is connected to the amplifier 61 via a matching circuit 60. The matching circuit 60 matches the input impedance of the input terminal Tin with the input impedance of the amplifier 61. The matching circuit 60 supplies a gate bias to the amplifier 61 from a bias terminal Tg1. The output of the amplifier 61 is connected to a node Nm via a matching circuit 62c. The matching circuit 62c matches the output impedance of the amplifier 61 with the impedance of the matching circuits 62a and 62b seen from the node Nm. The matching circuit 62c supplies a drain bias to the amplifier 61 from a bias terminal Td1. The output of the amplifier 61 is branched at the node Nm and connected to the amplifiers 63a and 63b via the matching circuits 62a and 62b, respectively. The matching circuit 62a matches the impedance of the matching circuits 62a and 62b seen from the node Nm with the input impedance of the amplifier 63a. The matching circuit 62a supplies a gate bias to the amplifier 63a from a bias terminal Tg2a. The matching circuit 62b matches the impedance of the matching circuits 62a and 62b seen from the node Nm with the input impedance of the amplifier 63b. The matching circuit 62b supplies a gate bias to the amplifier 63b from a bias terminal Tg2b. The outputs of the amplifiers 63a and 63b are combined via matching circuits 64a and 64b, respectively, and connected to an output terminal Tout. The matching circuit 64a matches the output impedance of the amplifier 63a with the output impedance of the output terminal Tout. The matching circuit 64a supplies a drain bias to the amplifiers 63a and 63b from a bias terminal Td2. The matching circuit 64b matches the output impedance of the amplifier 63b with the output impedance of the output terminal Tout.

[0044] FIG. 13 is a plan view of a high-frequency device according to a second embodiment. In FIG. 13, the resonator pattern 30 in the substrate 20 is illustrated by a broken line. As shown in FIG. 13, the lead frame 40 includes a base 42, leads 46a, 46b, and leads 47a to 47e. The leads 46a and 46b are connected to the input terminal Tin and the output terminal Tout, respectively. The leads 47a to 47e are electrically connected to the bias terminals Tg1, Td1, Tg2a, Tg2b, and Td2, respectively. The semiconductor chips 10a to 10c and the chips 18a to 18c are mounted on the base 42. The bonding wires 16 electrically connect the leads 46a, 46b, and the leads 47a to 47e to the semiconductor chips 10a to 10c and the chips 18a to 18c, and electrically connect the semiconductor chips 10a to 10c to the chips 18a to 18c.

[0045] The resonator patterns 30a to 30c are provided above the semiconductor chips 10a to 10b. As in the second embodiment, it is preferable that the resonator patterns 30a to 30c are provided so as to overlap all of the semiconductor chips 10a to 10b when viewed from above. This makes it possible to suppress a part of the high-frequency signal amplified by the semiconductor chips 10a to 10c from being fed back to the input side of the semiconductor chips 10a to 10c. In the second embodiment, the resonator patterns 30a to 30c are provided so as to overlap the semiconductor chips 10a and 10b, respectively. However, one resonator may be provided so as to overlap the multiple semiconductor chips 10a to 10c, or multiple resonators may be provided so as to overlap one semiconductor chip 10a to 10c. The other configurations are the same as those in the first embodiment, and the description will be omitted. As in the second embodiment, matching circuits 60, 62a, 62b, 64a, and 64b may be provided between the signal line and the semiconductor chips 10a to 10c. Although a two-stage amplifier has been described as an example of a high frequency power amplifier, a one-stage amplifier or a three or more stage amplifier may also be used.

[0046] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0047] 10, 10a to 10c Semiconductor chip 11 Semiconductor substrate 12~14, 31 electrodes 15, 25, 45 Bonding material 16, 16a, 16b Bonding wire 17a Substrate 17b active layer 17c wiring layer 18a~18c Chip 20 Substrate 21, 21a, 21b Dielectric layers 22, 24, 26 Conductive layers 23 Via wiring 24a Pattern 27 Bump 29 Aperture 30, 30a to 30c Resonator patterns 32 railroad tracks 33 Connection 34 Distributed constant line 35 series resonator 36a, 36b signal line 37a, 37b pads 38, 38a Reference potential layer 40 Lead Frame 42 Base 44 Heat sink (heat dissipation component) 43, 46a, 46b, 47a~47e Lead 48 Sealing part 49 Conductor Plate 50 Part of a high-frequency signal 51, 52 High frequency signals 60, 62a, 62b, 64a, 64b matching circuit 61, 63a, 63b Amplifiers 100, 102, 104, 106, 110, 112, 114 High frequency device

Claims

1. A semiconductor chip including a semiconductor substrate and an amplifier provided on a surface of the semiconductor substrate for amplifying a high-frequency signal; a first reference potential layer provided above the semiconductor chip in a direction perpendicular to the surface of the semiconductor substrate and overlapping the semiconductor chip in a plan view viewed from above, the first reference potential layer being supplied with a reference potential; a resonator provided between the semiconductor chip and the first reference potential layer in an upward direction perpendicular to the surface of the semiconductor substrate; The resonator is a high-frequency device comprising: an electrode that forms a capacitance between the electrode and the first reference potential layer; and a line surrounding the electrode that forms an inductance, the line having a first end connected to the electrode and a second end electrically connected to the first reference potential layer.

2. The high frequency device according to claim 1 , wherein at least a portion of the resonator overlaps with at least a portion of the semiconductor chip in a plan view seen from above.

3. a substrate provided above the semiconductor chip, the substrate including a dielectric layer and a plurality of conductor layers stacked thereon; 3. The high frequency device according to claim 1, wherein the plurality of conductive layers include the first reference potential layer, the resonator, and a signal line for transmitting the high frequency signal input to or output from the semiconductor chip.

4. a second reference potential layer provided between the first reference potential layer and the resonator and supplied with a reference potential; 4. The high-frequency device according to claim 1, wherein the resonator comprises an electrode that forms a capacitance between the electrode and the second reference potential layer, and a line surrounding the electrode that forms an inductance, the line having a first end connected to the electrode and a second end connected to the second reference potential layer.

5. 4. The high-frequency device according to claim 1, wherein the resonator has an electrical length greater than 1 / 8 and shorter than 3 / 8 of the wavelength of a signal at a center frequency of the operating frequency band of the amplifier, and comprises a distributed constant line having a first end connected to a reference potential and the other end open.

6. a lead frame including a base portion on which the semiconductor chip is mounted and which is connected to the semiconductor chip on a back surface side opposite to the front surface of the semiconductor substrate, and a signal lead portion electrically connected to an electrode formed on the front surface of the semiconductor substrate; The high frequency device according to claim 3 , wherein the signal lead portion is joined to the signal line.

7. 4. The high frequency device according to claim 3, further comprising a bump provided on the surface of the semiconductor substrate for connecting the signal line and the semiconductor chip.

8. The high frequency device according to claim 3 , further comprising a heat dissipation member provided on a rear surface of the semiconductor substrate opposite to the front surface.

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