Nitride structure and semiconductor device

Abstract

To provide a nitride structure and a semiconductor device, capable of improving characteristics.SOLUTION: According to one embodiment, a nitride structure includes a base, a nitride member, and a semiconductor member including Ga and N. The nitride member is provided between the base and the semiconductor member in a first direction. The nitride member includes a first nitride region, a second nitride region, and a third nitride region. The first nitride region is provided between the base and the third nitride region. The second nitride region is provided between the first nitride region and the third nitride region. The first nitride region includes AlN. The second nitride region includes Alx2Ga1-x2 N (0<x2<1). The third nitride region includes Alx3Ga1-x3 N (0<x3≤1, x2<x3). A second thickness of the second nitride region along the first direction is thinner than a third thickness of the third nitride region along the first direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a nitride structure and a semiconductor device.

Background Art

[0002] For example, in a semiconductor device based on a nitride structure, improvement in characteristics is desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a nitride structure and a semiconductor device capable of improving characteristics.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, the nitride structure includes a substrate, a nitride member, and a semiconductor member containing Ga and N. The nitride member is provided between the substrate and the semiconductor member in a first direction. The nitride member includes a first nitride region, a second nitride region, and a third nitride region. The first nitride region is provided between the substrate and the third nitride region. The second nitride region is provided between the first nitride region and the third nitride region. The first nitride region contains AlN. The second nitride region contains Al x2 Ga 1-x2 N (0 <x2 <1). The third nitride region contains Al x3 Ga 1-x3 N (0 <x3 ≦ 1, x2 <x3). A second thickness of the second nitride region along the first direction is thinner than a third thickness of the third nitride region along the first direction.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating the nitride structure according to the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view illustrating the nitride structure according to the first embodiment. [Diagram 3] FIG. 3 is a schematic cross-sectional view illustrating the nitride structure according to the first embodiment. As shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating the nitride structure according to the first embodiment. 1, the nitride structure 110 according to the embodiment includes a base 61s, a nitride member 60M, and a semiconductor member 10M. The semiconductor member 10M includes Ga and N. The semiconductor member 10M may include at least one of GaN and AlGaN.

[0009] The nitride member 60M is provided between the substrate 61s and the semiconductor member 10M in the first direction D1. The first direction D1 is the Z-axis direction. The direction perpendicular to the Z-axis direction is the X-axis direction. The direction perpendicular to the X-axis direction and the Z-axis direction is the Y-axis direction.

[0010] The nitride member 60M is layered along the X-Y plane. The semiconductor member 10M is layered along the X-Y plane.

[0011] The nitride member 60M includes a first nitride region 61, a second nitride region 62, and a third nitride region 63. The first nitride region 61 is provided between the substrate 61s and the third nitride region 63. The second nitride region 62 is provided between the first nitride region 61 and the third nitride region 63. The first nitride region 61, the second nitride region 62, and the third nitride region 63 are layered along the X-Y plane.

[0012] The first nitride region 61 contains AlN. The second nitride region 62 contains Al x2 Ga 1-x2 N (0 < x2 < 1). The third nitride region 63 contains Al x3 Ga 1-x3 N (0 < x3 ≤ 1, x2 < x3). In one example, the composition ratio x2 is 0.15 or more and less than 0.7. The composition ratio x3 is 0.7 or more and 1 or less.

[0013] As shown in FIG. 1, the thickness along the first direction D1 of the second nitride region 62 is defined as the second thickness t2. The thickness along the first direction D1 of the third nitride region 63 is defined as the third thickness t3. In the embodiment, the second thickness t2 is thinner than the third thickness t3.

[0014] The nitride structure 110 is, for example, a nitride wafer. As will be described later, at least a part of the nitride structure 110 may be included in a semiconductor device. The semiconductor device may be, for example, a transistor or the like. For example, the semiconductor member 10M functions as a functional layer in the semiconductor device. In a semiconductor device based on the nitride structure 110, a leakage current may occur. For example, the breakdown voltage decreases due to the leakage current.

[0015] In the embodiment, the second nitride region 62 and the third nitride region 63 are provided. This can suppress leakage current. This can provide a high breakdown voltage. For example, the second nitride region 62 and the third nitride region 63 can suppress carriers from moving from the base 61s to the semiconductor member 10M. This is believed to suppress leakage current. The second nitride region 62 and the third nitride region 63 can function as, for example, a carrier block layer. According to the embodiment, it is possible to provide a nitride structure capable of improving characteristics.

[0016] In the embodiment, the Al composition ratio in the second nitride region 62 is lower than the Al composition ratio in the third nitride region 63. For example, the second nitride region 62 functions as a well layer. The third nitride region 63 functions as a barrier layer. In the embodiment, the third thickness t3 of the third nitride region 63 is thicker than the second thickness t2 of the second nitride region 62. This effectively suppresses the movement of carriers. The carriers are, for example, electrons.

[0017] The substrate 61s includes, for example, silicon. The substrate 61s may be, for example, a silicon substrate. The nitride member 60M is, for example, a crystal. The semiconductor member 10M is, for example, a crystal.

[0018] 1, a first nitride region 61 may be in contact with a substrate 61s. A second nitride region 62 may be in contact with the first nitride region 61. A third nitride region 63 may be in contact with the second nitride region 62.

[0019] By providing the first nitride region 61 of AlN, for example, the base body 61s is suppressed from being altered (for example, by melt-back etching).

[0020] 1, the thickness of the first nitride region 61 along the first direction D1 is defined as a first thickness t1. In one example, the first thickness may be 100 nm or more and 300 nm or less. When the first thickness is 100 nm or more, for example, deterioration of the base body 61s can be effectively suppressed. When the first thickness is 300 nm or less, for example, warpage of the wafer can be suppressed.

[0021] In the embodiment, for example, the second thickness t2 may be thinner than the first thickness t1. For example, the third thickness t3 may be thicker than the first thickness t1. Such a thickness relationship makes it easier to suppress, for example, warpage of the wafer.

[0022] In the embodiment, for example, the second thickness t2 is preferably 10 nm or more and less than 100 nm. When the second thickness t2 is 10 nm or more, for example, carriers are less likely to tunnel. When the second thickness t2 is less than 100 nm, for example, carriers are more likely to be confined.

[0023] The third thickness t3 is preferably, for example, not less than 100 nm and not more than 300 nm. When the third thickness t3 is 100 nm or more, carriers can be easily and effectively confined in the second nitride region 62. When the third thickness t3 is 300 nm or less, for example, cracks are less likely to occur.

[0024] In one example, the first nitride region 61 does not contain carbon. Alternatively, the carbon concentration in the first nitride region 61 is lower than the carbon concentration in the second nitride region 62. When the carbon concentration in the second nitride region 62 is high, for example, it becomes easier to suppress leakage current from the base 61s.

[0025] In the embodiment, the Al composition ratio in the second nitride region 62 may be substantially constant. The Al composition ratio in the third nitride region 63 may be substantially constant. For example, the Al composition ratio changes stepwise between the first nitride region 61 and the second nitride region 62. For example, the Al composition ratio changes stepwise between the second nitride region 62 and the third nitride region 63. The movement of carriers is effectively blocked.

[0026] The second nitride region 62 and the third nitride region 63 may be included in one set. A plurality of sets may be provided along the first direction D1. The number of the sets may be 1 or more and 3 or less. By providing a plurality of sets, the movement of carriers can be more efficiently suppressed. The leakage current can be more effectively suppressed.

[0027] 1, the nitride member 60M may further include a fourth nitride region 64. The fourth nitride region 64 includes Al, Ga, and N. The fourth nitride region 64 is provided between the third nitride region 63 and the semiconductor member 10M.

[0028] In one example, the Al composition ratio may vary in the fourth nitride region 64. As shown in FIG. 1, for example, the fourth nitride region 64 includes a first region 64p and a second region 64q. The second region 64q is provided between the first region 64p and the semiconductor member 10M. The Al composition ratio in the second region 64q is lower than the Al composition ratio in the first region 64p.

[0029] The Al composition ratio in the first region 64p is, for example, not less than 0.6 and less than 1. The Al composition ratio in the second region 64q is, for example, not less than 0.05 and not more than 0.2. The first region 64p may be in contact with, for example, the third nitride region 63. The second region 64q may be in contact with, for example, the semiconductor member 10M.

[0030] For example, the Al composition ratio in the fourth nitride region 64 may decrease in the direction from the third nitride region 63 toward the semiconductor member 10M. The fourth nitride region 64 may be, for example, a gradient layer with respect to the Al composition ratio. By providing the gradient layer fourth nitride region 64, for example, stress caused by a difference in the lattice constant of crystals is easily alleviated. For example, warping or cracks are suppressed.

[0031] The fourth nitride region 64 may be in contact with the third nitride region 63. The fourth nitride region 64 may be in contact with the semiconductor member 10M.

[0032] As shown in FIG. 1, the thickness along the first direction D1 of the fourth nitride region 64 is defined as the fourth thickness t4. The fourth thickness t4 may be, for example, 1 μm or more and 5 μm or less.

[0033] As shown in FIG. 1, in this example, the semiconductor member 10M includes a first semiconductor region 10 and a second semiconductor region 20. The first semiconductor region 10 is provided between the nitride member 60M and the second semiconductor region 20. The first semiconductor region 10 contains Al z1 Ga 1-z1 N (0 ≦ z1 < 1). The first semiconductor region 10 contains, for example, GaN. The second semiconductor region contains Al z2 Ga 1-z2 N (z1 < z2 < 1). The second semiconductor region 20 contains, for example, AlGaN. The composition ratio z1 is, for example, 0 or more and 0.13 or less. The composition ratio z2 is, for example, 0.15 or more and 0.35 or less.

[0034] FIG. 2 is a schematic cross-sectional view illustrating a nitride structure according to the first embodiment. As shown in FIG. 2, in the nitride structure 111 according to the embodiment, the configuration of the fourth nitride region 64 is different from the configuration of the fourth nitride region 64 in the nitride structure 110. The configuration of the nitride structure 111 may be the same as the configuration of the nitride structure 110 except for this.

[0035] As shown in FIG. 2, in the nitride structure 111, the fourth nitride region 64 includes a plurality of first films 64a and a plurality of second films 64b. One of the plurality of first films 64a is provided between one of the plurality of second films 64b and another one of the plurality of second films 64b. One of the plurality of second films 64b is between one of the plurality of first films 64a and another one of the plurality of first films 64a. For example, the first film 64a and the second film 64b are provided alternately.

[0036] For example, the Al composition ratio in the plurality of first films 64a is higher than the Al composition ratio in the plurality of second films 64b. In the nitride structure 111, the fourth nitride region 64 is a superlattice layer. By providing such a fourth nitride region 64, for example, stress is easily relaxed.

[0037] The first film thickness ta of each of the first films 64a is, for example, not less than 1 nm and not more than 10 nm. The second film thickness tb of each of the second films 64b is, for example, not less than 10 nm and not more than 50 nm.

[0038] In the nitride structure 111, the average Al composition ratio in the fourth nitride region 64 may decrease in a direction from the third nitride region 63 to the semiconductor member 10M. For example, in the first films 64a, the Al composition ratio may decrease in a direction from the third nitride region 63 to the semiconductor member 10M. For example, in the first films 64a, the first film thickness ta may decrease in a direction from the third nitride region 63 to the semiconductor member 10M. For example, in the second films 64b, the second film thickness tb may increase in a direction from the third nitride region 63 to the semiconductor member 10M.

[0039] FIG. 3 is a schematic cross-sectional view illustrating the nitride structure according to the first embodiment. As shown in FIG. 3, in the nitride structure 112 according to the embodiment, the configuration of the semiconductor member 10M is different from the configuration of the semiconductor member 10M in the nitride structure 110 or the nitride structure 111. Except for this, the configuration of the nitride structure 112 may be similar to the configuration of the nitride structure 110 or the nitride structure 111.

[0040] As shown in FIG. 3, in the nitride structure 112, the semiconductor member 10M further includes a third semiconductor region 30. The third semiconductor region 30 is provided between the nitride member 60M and the first semiconductor region 10. The third semiconductor region 30 is made of Al z3 Ga 1-z3It includes N (0 ≦ z3 < z2). The composition ratio z3 is, for example, 0 or more and 0.13 or less. The third semiconductor region 30 includes, for example, GaN. The third semiconductor region 30 includes carbon. On the other hand, the first semiconductor region 10 does not include carbon. Or, the concentration of carbon in the third semiconductor region 30 is higher than the concentration of carbon in the first semiconductor region 10. For example, the first semiconductor region 10 is i-GaN. By providing such a third semiconductor region 30, for example, it becomes easier to obtain higher crystal quality. For example, carbon can compensate for carriers that cause leakage current. By providing the third semiconductor region 30 containing carbon, for example, leakage current can be more effectively suppressed.

[0041] (Second Embodiment) The second embodiment relates to a semiconductor device. The semiconductor device according to the embodiment includes the nitride structure according to the first embodiment. Hereinafter, an example in the case where the semiconductor device includes the nitride structure 110 will be described. The semiconductor device may include the nitride structure 111 or the nitride structure 112.

[0042] FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. As shown in FIG. 4, the semiconductor device 120 according to the embodiment includes the nitride structure 110 according to the first embodiment, a first electrode 51, a second electrode 52, and a third electrode 53. The semiconductor device 120 may further include an insulating member 41.

[0043] The direction from the first electrode 51 to the second electrode 52 is along a second direction D2 that intersects the first direction D1. The second direction D2 is, for example, the X-axis direction. The position of the third electrode 53 in the second direction D2 is between the position of the first electrode 51 in the second direction D2 and the position of the second electrode 52 in the second direction D2.

[0044] The semiconductor member 10M includes the first semiconductor region 10 and the second semiconductor region 20. The semiconductor member 10M may further include the third semiconductor region 30 (see FIG. 3).

[0045] The first semiconductor region 10 includes a first partial region 10a, a second partial region 10b, a third partial region 10c, a fourth partial region 10d, and a fifth partial region 10e. The direction from the first partial region 10a to the first electrode 51 is along the first direction D1. The direction from the second partial region 10b to the second electrode 52 is along the first direction D1. The third partial region 10c is between the first partial region 10a and the second partial region 10b in the second direction D2. The direction from the third partial region 10c to the third electrode 53 is along the first direction D1. The fourth partial region 10d is between the first partial region 10a and the third partial region 10c in the second direction D2. The fifth partial region 10e is between the third partial region 10c and the second partial region 10b in the second direction D2.

[0046] The second semiconductor region 20 includes a sixth partial region 20f and a seventh partial region 20g. The direction from the fourth partial region 10d to the sixth partial region 20f is along the first direction D1. The direction from the fifth partial region 10e to the seventh partial region 20g is along the first direction D1.

[0047] For example, at least a portion of the insulating member 41 is provided between the semiconductor member 10M and the third electrode 53. For example, the insulating member 41 includes a first insulating region 41p. The first insulating region 41p is provided between the third partial region 10c and the third electrode 53 in the first direction (Z-axis direction).

[0048] The first electrode 51 is electrically connected to the sixth partial region 20f. The second electrode 52 is electrically connected to the seventh partial region 20g. The first electrode 51, the second electrode 52, and the third electrode 53 may extend, for example, along a third direction D3. The third direction D3 intersects with a plane including the first direction D1 and the second direction D2.

[0049] In the semiconductor device 120, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 is, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as, for example, a drain electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 120 is, for example, a HEMT (High Electron Mobility Transistor).

[0050] According to the embodiment, leakage current is suppressed. For example, a high breakdown voltage is obtained. According to the embodiment, a semiconductor device capable of improving characteristics can be provided.

[0051] In the semiconductor device 120, at least a portion of the third electrode 53 is provided between the sixth partial region 20f and the seventh partial region 20g in the second direction D2. At least a portion of the third electrode 53 may be provided between the fourth partial region 10d and the fifth partial region 10e in the second direction D2. The first insulating region 41p may be provided between the fourth partial region 10d and the fifth partial region 10e. The semiconductor device 120 is, for example, a normally-off type.

[0052] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. As shown in Fig. 5, the semiconductor device 121 according to the embodiment includes the nitride structure 110 according to the first embodiment, a first electrode 51, a second electrode 52, a third electrode 53, and an insulating member 41. In the semiconductor device 121, the third electrode 53 does not overlap the sixth partial region 20f and the seventh partial region 20g in the second direction D2. The third electrode 53 does not overlap the fourth partial region 10d and the fifth partial region 10e in the second direction D2. The semiconductor device 121 is, for example, a normally-on type. The semiconductor device 121 can also suppress leakage current. A semiconductor device capable of improving characteristics can be provided.

[0053] In an embodiment, information regarding the shape of the nitride region, etc. can be obtained, for example, by electron microscope observation. Information regarding the composition and element concentration in the nitride region can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy), or SIMS (Secondary Ion Mass Spectrometry), etc. Information regarding the composition in the nitride region may be obtained, for example, by X-ray reciprocal lattice space mapping, etc.

[0054] The embodiment may include the following technical solutions. (Technical solution 1) A substrate, A nitride member, A semiconductor member containing Ga and N, Comprising, The nitride member is provided between the substrate and the semiconductor member in a first direction, The nitride member includes a first nitride region, a second nitride region, and a third nitride region, The first nitride region is provided between the substrate and the third nitride region, The second nitride region is provided between the first nitride region and the third nitride region, The first nitride region contains AlN, The second nitride region contains Al x2 Ga 1-x2 N (0 < x2 < 1), The third nitride region contains Al x3 Ga 1-x3 N (0 < x3 ≤ 1, x2 < x3), A nitride structure in which a second thickness of the second nitride region along the first direction is thinner than a third thickness of the third nitride region along the first direction.

[0055] (Technical solution 2) The first nitride region is in contact with the substrate, The second nitride region is in contact with the first nitride region, The nitride structure according to Technical solution 1, wherein the third nitride region is in contact with the second nitride region.

[0056] (Technical proposal 3) The nitride structure of Technical Solution 1, wherein the second thickness is smaller than a first thickness of the first nitride region along the first direction.

[0057] (Technical proposal 4) The nitride structure according to Technical Solution 3, wherein the third thickness is greater than the first thickness.

[0058] (Technical proposal 5) The nitride structure according to Technical Scheme 3 or 4, wherein the first thickness is 100 nm to 300 nm or less.

[0059] (Technical proposal 6) The second thickness is equal to or greater than 10 nm and less than 100 nm; The nitride structure according to any one of Technical Schemes 1 to 5, wherein the third thickness is 100 nm or more and 300 nm or less.

[0060] (Technical proposal 7) The x2 is equal to or greater than 0.15 and less than 0.7, The nitride structure according to any one of Technical Schemes 1 to 6, wherein x3 is 0.7 or more and 1 or less.

[0061] (Technical proposal 8) the nitride member further includes a fourth nitride region including Al, Ga, and N; the fourth nitride region is provided between the third nitride region and the semiconductor member, the fourth nitride region includes a first region and a second region; The second region is provided between the first region and the semiconductor member, The nitride structure according to any one of Technical Schemes 1 to 7, wherein the Al composition ratio in the second region is lower than the Al composition ratio in the first region.

[0062] (Technical proposal 9) The nitride structure according to Technical Proposal 8, wherein the Al composition ratio in the fourth nitride region decreases in a direction from the third nitride region toward the semiconductor member.

[0063] (Technical proposal 10) the fourth nitride region includes a plurality of first films and a plurality of second films; one of the plurality of first films is provided between one of the plurality of second films and another one of the plurality of second films; the one of the plurality of second films is between the one of the plurality of first films and another one of the plurality of first films; The nitride structure according to Technical Proposal 8 or 9, wherein an Al composition ratio in the plurality of first films is higher than an Al composition ratio in the plurality of second films.

[0064] (Technical proposal 11) the nitride member further includes a fourth nitride region including Al, Ga, and N; the fourth nitride region is provided between the third nitride region and the semiconductor member, the fourth nitride region includes a plurality of first films and a plurality of second films; one of the plurality of first films is provided between one of the plurality of second films and another one of the plurality of second films; the one of the plurality of second films is between the one of the plurality of first films and another one of the plurality of first films; The nitride structure according to any one of Technical Schemes 1 to 7, wherein an Al composition ratio in the plurality of first films is higher than an Al composition ratio in the plurality of second films.

[0065] (Technical proposal 12) a first film thickness of each of the plurality of first films is equal to or greater than 1 nm and less than 10 nm; The nitride structure according to Technical Solution 10 or 11, wherein the second film thickness of each of the plurality of second films is 10 nm or more and 50 nm or less.

[0066] (Technical proposal 13) The nitride structure according to any one of Technical Solutions 8 to 12, wherein the fourth nitride region is in contact with the third nitride region.

[0067] (Technical proposal 14) The substrate is a nitride structure according to any one of Technical Solutions 1 to 13, containing Si.

[0068] (Technical Solution 15) The first nitride region does not contain carbon, or the concentration of carbon in the first nitride region is lower than the concentration of carbon in the second nitride region. The nitride structure according to any one of Technical Solutions 1 to 14.

[0069] (Technical Solution 16) The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region is provided between the nitride member and the second semiconductor region. The first semiconductor region contains Al z1 Ga 1-z1 N (0 ≦ z1 < 1), The second semiconductor region contains Al z2 Ga 1-z2 N (z1 < z2 < 1). The nitride structure according to any one of Technical Solutions 1 to 15.

[0070] (Technical Solution 17) The semiconductor member further includes a third semiconductor region. The third semiconductor region is provided between the nitride member and the first semiconductor region. The third semiconductor region contains Al z3 Ga 1-z3 N (0 ≦ z3 < z2), The third semiconductor region contains carbon. The nitride structure according to Technical Solution 16.

[0071] (Technical Solution 18) The nitride structure according to Technical Solution 16 or 17, a first electrode, a second electrode, a third electrode, and, The direction from the first electrode to the second electrode is along a second direction intersecting the first direction. a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction, the first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region; A direction from the first partial region to the first electrode is along the first direction, a direction from the second partial region to the second electrode is along the first direction; the third partial region is between the first partial region and the second partial region in the second direction, and a direction from the third partial region to the third electrode is along the first direction; the fourth partial region is between the first partial region and the third partial region in the second direction, the fifth partial region is between the third partial region and the second partial region in the second direction, the second semiconductor region includes a sixth partial region and a seventh partial region, a direction from the fourth partial region to the sixth partial region is along the first direction, A semiconductor device, wherein a direction from the fifth partial region to the seventh partial region is along the first direction.

[0072] (Technical proposal 19) Further comprising an insulating member; A semiconductor device as described in Technical Proposal 18, wherein at least a portion of the insulating member is between the semiconductor member and the third electrode.

[0073] (Technical proposal 20) The semiconductor device according to Technical Proposal 18 or 19, wherein at least a portion of the third electrode is located between the sixth partial region and the seventh partial region in the second direction.

[0074] According to the embodiment, it is possible to provide a nitride structure and a semiconductor device capable of improving characteristics.

[0075] In this specification, "vertical" and "parallel" do not only mean strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may mean substantially vertical and substantially parallel.

[0076] In this specification, "electrically connected" includes a state in which multiple conductors are in physical contact with each other and a current flows between the multiple conductors. "Electrically connected" includes a state in which a conductor is inserted between multiple conductors and a current flows between the multiple conductors.

[0077] The above describes the embodiment of the present invention with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the nitride structure, such as the base, nitride member, nitride region, semiconductor member, and semiconductor region, are included in the scope of the present invention as long as a person skilled in the art can carry out the present invention in the same manner and obtain the same effect by appropriately selecting them from the known range.

[0078] Furthermore, any combination of two or more elements of each of the specific examples, within the scope of technical feasibility, is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0079] In addition, all nitride structures and semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the nitride structures and semiconductor devices described above as embodiments of the present invention also belong to the scope of the present invention as long as they include the gist of the present invention.

[0080] In addition, within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0081] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0082] 10, 20, 30: first, second, third semiconductor regions, 10M: semiconductor member, 10a-10e: first to fifth partial regions, 20f, 20g: sixth and seventh partial regions, 41: insulating member, 41p: first insulating region, 51-53: first to third electrodes, 60M: nitride member, 61-64: first to fourth nitride regions, 61s: base, 64a, 64b: first and second films, 64p, 64q: first and second regions, 110-112: nitride structure, 120, 121: semiconductor device, D1-D3: first to third directions, t1-t4: first to fourth thicknesses, ta, tb: first and second film thicknesses

Claims

1. A substrate; A nitride member; A semiconductor member containing Ga and N; Equipped with the nitride member is provided between the base and the semiconductor member in a first direction, the nitride member includes a first nitride region, a second nitride region, and a third nitride region; the first nitride region is provided between the substrate and the third nitride region; the second nitride region is provided between the first nitride region and the third nitride region; the first nitride region comprises AlN; The second nitride region is Al ｘ２ G １－ｘ２ N (0<x2<1), The third nitride region is Al ｘ３ G １－ｘ３ N (0<x3≦1, x2<x3), A nitride structure, wherein a second thickness of the second nitride region along the first direction is less than a third thickness of the third nitride region along the first direction.

2. the first nitride region is in contact with the substrate; the second nitride region is in contact with the first nitride region; The nitride structure of claim 1 , wherein the third nitride region is in contact with the second nitride region.

3. The nitride structure of claim 1 , wherein the second thickness is less than a first thickness of the first nitride region along the first direction.

4. The nitride structure of claim 3 , wherein the third thickness is greater than the first thickness.

5. The second thickness is equal to or greater than 10 nm and less than 100 nm; The nitride structure of claim 1 , wherein the third thickness is greater than or equal to 100 nm and less than or equal to 300 nm.

6. the nitride member further comprises a fourth nitride region comprising Al, Ga, and N; the fourth nitride region is provided between the third nitride region and the semiconductor member; the fourth nitride region includes a first region and a second region; The second region is provided between the first region and the semiconductor member, The nitride structure according to claim 1 , wherein an Al composition ratio in said second region is lower than an Al composition ratio in said first region.

7. the nitride member further comprises a fourth nitride region comprising Al, Ga, and N; the fourth nitride region is provided between the third nitride region and the semiconductor member; the fourth nitride region includes a plurality of first films and a plurality of second films; one of the plurality of first films is provided between one of the plurality of second films and another one of the plurality of second films; the one of the plurality of second films is between the one of the plurality of first films and another one of the plurality of first films; The nitride structure according to claim 1 , wherein an Al composition ratio in said plurality of first films is higher than an Al composition ratio in said plurality of second films.

8. The nitride structure according to any one of claims 1 to 7, wherein the first nitride region does not contain carbon, or the concentration of carbon in the first nitride region is lower than the concentration of carbon in the second nitride region.

9. The semiconductor member includes a first semiconductor region and a second semiconductor region, the first semiconductor region is provided between the nitride member and the second semiconductor region, The first semiconductor region is Al ｚ１ G １－ｚ１ N (0≦z1<1), The second semiconductor region is Al ｚ２ G １－ｚ２ The nitride structure of claim 1 comprising N, where z1<z2<1.

10. The nitride structure according to claim 9 ; A first electrode; A second electrode; A third electrode; Equipped with a direction from the first electrode to the second electrode is along a second direction intersecting the first direction; a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction, the first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region; A direction from the first partial region to the first electrode is along the first direction, a direction from the second partial region to the second electrode is along the first direction; the third partial region is between the first partial region and the second partial region in the second direction, and a direction from the third partial region to the third electrode is along the first direction; the fourth partial region is between the first partial region and the third partial region in the second direction, the fifth partial region is between the third partial region and the second partial region in the second direction, the second semiconductor region includes a sixth partial region and a seventh partial region, a direction from the fourth partial region to the sixth partial region is along the first direction; A semiconductor device, wherein a direction from the fifth partial region to the seventh partial region is along the first direction.

11. The semiconductor device according to claim 10 , wherein at least a portion of the third electrode is located between the sixth partial region and the seventh partial region in the second direction.

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