Plasma processing using pulsed-voltage and radio-frequency power

Abstract

To provide an apparatus and method for the plasma processing of a substrate in a processing chamber.SOLUTION: More specifically, embodiments of the present disclosure describe a biasing scheme that is configured to provide a radio frequency (RF) waveform from an RF power supply to one or more electrodes within a processing chamber and provide a pulsed-voltage (PV) waveform delivered from one or more pulsed-voltage (PV) generators to the one or more electrodes within the processing chamber. A plasma process disclosed in the present specification can be used to control the shape of an ion energy distribution function (IEDF) and control the interaction of the plasma with a surface of a substrate during plasma processing.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] TECHNICAL FIELD The embodiments described herein relate generally to semiconductor device manufacturing hardware and processes, and more specifically to an apparatus and method for controlling the supply of power to a plasma formed in a plasma processing chamber used in semiconductor manufacturing. [Background technology]

[0002] Reliably generating high aspect ratio features is one of the key technological challenges for very large scale integration (VLSI) and ultra large scale integration (ULSI) of next generation semiconductor devices. One method for forming high aspect ratio features is to use a plasma assisted etching process, such as a reactive ion etch (RIE) plasma process, to form high aspect ratio openings in a material layer, such as a dielectric layer, of a substrate. In a typical RIE plasma process, a plasma is formed in a RIE processing chamber, and ions from the plasma are accelerated toward the surface of the substrate to form openings in a material layer disposed under a mask layer formed on the substrate surface.

[0003] A typical reactive ion etch (RIE) plasma processing chamber includes a radio frequency (RF) bias power supply that supplies an RF voltage to a "power electrode" (e.g., bias electrode), such as a metal plate positioned adjacent to an "electrostatic chuck" (ESC) assembly, usually referred to as the "cathode." The power electrode may be capacitively coupled to the plasma of the processing system through a thick layer of dielectric material (e.g., ceramic material) that is part of the ESC assembly. In a capacitively coupled gas discharge, the plasma is generated by using a radio frequency (RF) power supply coupled ("RF matched") to the RF electrode through an RF matching network that adjusts the apparent load to 50 Ohms to minimize reflected power and maximize power delivery efficiency. Application of an RF voltage to the power electrode forms an electron-donating plasma sheath (also referred to as a "cathode sheath") over the processing surface of a substrate that is placed on the substrate support surface of the ESC assembly during processing. The applied RF field is rectified by the diode-like nonlinear nature of the plasma sheath, resulting in the appearance of a direct current (DC) voltage drop or "self-bias" between the substrate and the plasma, making the substrate potential negative with respect to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerated toward the substrate, and therefore the etch anisotropy. More specifically, the ion directionality, feature profile, and etch selectivity relative to the mask and stop layers are controlled by the ion energy distribution function (IEDF). In a plasma with RF bias, the IEDF typically has two non-discrete peaks, a low energy and a high energy, and an ion population with energies ranging between the two peaks. The presence of an intermediate ion population between the two peaks in the IEDF reflects the fact that the voltage drop between the substrate and the plasma oscillates with the RF bias frequency. When a lower frequency RF bias power supply is used to achieve a higher self-bias voltage, the energy difference between these two peaks can be significant, and the etch profile with ions from the low energy peak is more isotropic, which can cause the walls of the etched feature to bow.Low energy ions cannot reach the corners as effectively as high energy ions at the bottom of the etched feature (e.g., due to charging effects), resulting in under-sputtering of mask material. This is important in high aspect ratio etch applications such as hard mask opening or dielectric mold etch. As feature sizes continue to shrink and aspect ratios increase while feature profile control requirements become more stringent, it becomes more desirable to have a well-controlled IEDF at the substrate surface during processing.

[0004] It has been found that in other conventional plasma processes and processing chamber designs, a wide variety of RF frequencies may be supplied to one or more of the electrodes in the plasma processing chamber to control various plasma characteristics, such as plasma density, ion energy, and / or plasma chemistry. However, it has been found that the supply of multiple conventional sinusoidal waveforms from two or more RF sources, each configured to supply a different RF frequency, does not adequately or desirably control the sheath characteristics, resulting in undesirable arcing problems. Furthermore, due to direct or capacitive coupling between the RF sources during processing, each RF source may induce RF currents that are supplied to the output of the other connected RF sources (e.g., often referred to as "crosstalk"), diverting power from the intended load (plasma) and possibly causing damage to each of the RF sources.

[0005] Therefore, there is a need in the art for novel, robust, and reliable plasma processing and biasing methods that maintain a nearly constant sheath voltage to produce a repeatable, desirable IEDF at the surface of a substrate, allowing precise control over the shape of the IEDF, and in some cases, even to form the etch profile of features at the surface of the substrate. Summary of the Invention

[0006] The present disclosure generally includes a plasma processing chamber including a substrate support assembly, a pulsed voltage waveform generator, a first filter assembly, a radio frequency (RF) power source, and a second filter assembly. The substrate support assembly includes a substrate support surface, a support base, and a bias electrode disposed between the support base and the substrate support surface, with a first dielectric layer disposed between the support base and the bias electrode, and a second dielectric layer disposed between the bias electrode and the substrate surface. A pulsed voltage waveform generator configured to generate a pulsed voltage signal including a pulsed voltage waveform is electrically coupled to the bias electrode. The first filter assembly is electrically coupled between the pulsed voltage waveform generator and the bias electrode. A radio frequency (RF) power source configured to generate an RF signal including a radio frequency waveform is electrically coupled to the support base or the bias electrode. The second filter assembly is electrically coupled between the radio frequency power source and the support base or the bias electrode. In some configurations, the second filter assembly is electrically coupled between the radio frequency power source and a radio frequency match, and the radio frequency match is electrically coupled between the radio frequency power source and the support base or the bias electrode. In some other configurations, the high frequency match is disposed between the second filter assembly and the support base or bias electrode.

[0007]

[0010] An embodiment of the present disclosure may further provide a method of processing a substrate in a plasma processing chamber, the method including: providing a radio frequency signal to a support base disposed within a substrate support assembly using a radio frequency power supply electrically coupled to the support base through a pulsed voltage filter assembly; and establishing a first pulsed voltage waveform to a bias electrode disposed within the substrate support assembly using a first pulsed voltage waveform generator electrically coupled to the bias electrode through a first radio frequency filter assembly. The bias electrode is disposed between the support base and a substrate support surface of the substrate support assembly. A first dielectric layer is disposed between the support base and the bias electrode, and a second dielectric layer is disposed between the bias electrode and the substrate support surface.

[0008] An embodiment of the present disclosure may further provide a method of processing a substrate in a plasma processing chamber, the method including: supplying a radio frequency signal to a support base disposed within a substrate support assembly using a radio frequency power supply electrically coupled to the support base via a pulse voltage filter assembly; establishing a first pulse voltage waveform to a bias electrode disposed within the substrate support assembly using a first pulse voltage waveform generator electrically coupled to the bias electrode via a first radio frequency filter assembly; and establishing a second pulse voltage waveform to an edge control electrode disposed within the substrate support assembly using a second pulse voltage waveform generator electrically coupled to the edge control electrode via a second radio frequency filter assembly. The bias electrode is disposed between the support base and a substrate support surface of the substrate support assembly. A first dielectric layer is disposed between the support base and the bias electrode, a second dielectric layer is disposed between the bias electrode and the substrate support surface, and the edge control electrode surrounds at least a portion of the bias electrode.

[0009] An embodiment of the present disclosure may further provide a plasma processing chamber including a substrate support assembly, a pulsed voltage waveform generator, a radio frequency filter assembly, a radio frequency power supply, and a pulsed voltage filter assembly. The substrate support assembly includes a substrate support surface, a support base, and a first bias electrode disposed between the support base and the substrate support surface, with a first dielectric layer disposed between the support base and the first bias electrode, and a second dielectric layer disposed between the first bias electrode and the substrate support surface. The pulsed voltage waveform generator is configured to establish a pulsed voltage waveform at the first bias electrode and is electrically coupled to the first bias electrode via a first conductor. The radio frequency filter assembly is electrically coupled between the pulsed voltage waveform generator and the first conductor. The radio frequency power supply is configured to establish a radio frequency voltage waveform at the support base or the first bias electrode and is electrically coupled to the support base or the first bias electrode via a second conductor. The pulsed voltage filter assembly is electrically coupled between the radio frequency power supply and the second conductor.

[0010] The disclosed embodiment may further provide a plasma processing chamber including a substrate support assembly, a first pulsed voltage waveform generator, a first radio frequency filter assembly, a second pulsed voltage waveform generator, a second radio frequency filter assembly, a radio frequency power supply, and a pulsed voltage filter assembly. The substrate support assembly includes a substrate support surface, a support base, a first bias electrode disposed between the support base and the substrate support surface, and an edge control electrode, with a first dielectric layer disposed between the support base and the first bias electrode, and a second dielectric layer disposed between the first bias electrode and the substrate support surface. The first pulsed voltage waveform generator is configured to establish a pulsed voltage signal waveform at the first bias electrode and is electrically coupled to the first bias electrode via a first conductor. The first radio frequency filter assembly is electrically coupled between the first pulsed voltage waveform generator and the first conductor. The second pulsed voltage waveform generator is configured to establish a pulsed voltage waveform at the edge control electrode and is electrically coupled to the edge control electrode via a second conductor. The second radio frequency filter assembly is electrically coupled between the second pulsed voltage waveform generator and the second conductor. The radio frequency power source is configured to establish a radio frequency waveform in the support base or the first bias electrode and is electrically coupled to the support base or the first bias electrode via the third conductor. The pulsed voltage filter assembly is electrically coupled between the radio frequency power source and the third conductor.

[0011] An embodiment of the present disclosure may provide a pulse voltage subsystem assembly including a pulse voltage generating unit housing and a junction box housing. The pulse voltage generating unit housing may include a first pulse voltage waveform generator electrically coupled to a first generator output coupling assembly. The junction box housing may include a first bias compensation module section and a radio frequency filter section. The first bias compensation module section includes a first blocking capacitor electrically coupled between the output coupling assembly of the first bias compensation module section and the first generator output coupling assembly, and a first DC power source has a positive terminal and a negative terminal electrically coupled to the output coupling assembly of the first bias compensation module section. The radio frequency filter section includes a first radio frequency filter assembly electrically coupled between the first radio frequency filter output coupling assembly and the output coupling assembly of the first bias compensation module section. The pulse voltage subsystem assembly is configured to couple to a plasma processing chamber. The first radio frequency filter output coupling assembly is configured to electrically couple to a first electrode disposed within the plasma processing chamber.

[0012] The disclosed embodiment may further provide a pulse voltage subsystem assembly including a pulse voltage generating unit housing and a junction box housing. The pulse voltage generating unit housing includes a first pulse voltage waveform generator electrically coupled to the first generator output coupling assembly and a second pulse voltage waveform generator electrically coupled to the second generator output coupling assembly. The junction box housing includes a first bias compensation module section, a second bias compensation module section, and a high frequency filter section. The first bias compensation module section includes a first blocking capacitor electrically coupled between the output coupling assembly of the first bias compensation module section and the first generator output coupling assembly, and the first DC power supply has a positive terminal and a negative terminal electrically coupled to the output coupling assembly of the first bias compensation module section. The second bias compensation module section includes a second blocking capacitor electrically coupled between the output coupling assembly of the second bias compensation module section and the second generator output coupling assembly, and the second DC power supply has a positive terminal and a negative terminal electrically coupled to the output coupling assembly of the second bias compensation module section. The high frequency filter section includes a first high frequency filter assembly electrically coupled between the first high frequency filter output coupling assembly and the output coupling assembly of the first bias compensation module section, and a second high frequency filter assembly electrically coupled between the second high frequency filter output coupling assembly and the output coupling assembly of the second bias compensation module section. The pulse voltage subsystem assembly is configured to couple to the plasma processing chamber. The first high frequency filter output coupling assembly is configured to be electrically coupled to a first electrode and a second electrode disposed within the plasma processing chamber.

[0013] So that the above-listed features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above should be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate exemplary embodiments, and therefore should not be considered as limiting the scope of the exemplary embodiments, which are open to other equally effective embodiments. [Brief description of the drawings]

[0014] [Figure 1A] 1 is a schematic cross-sectional view of a processing chamber configured to perform the methods described herein, according to one embodiment. [Figure 1B] 1 is a schematic cross-sectional view of a processing chamber configured to perform the methods described herein, according to one embodiment. [Figure 1C] 1 is a schematic cross-sectional view of a packaging assembly coupled to a processing chamber according to one embodiment. [Figure 1D] 1 is a schematic cross-sectional view of an alternative version of a packaging assembly coupled to a processing chamber, according to one embodiment. [Diagram 2] FIG. 2 is a simplified schematic diagram of a biasing scheme that may be used with the processing chamber shown in FIG. 1A or FIG. 1B, according to one embodiment. [Figure 3A] FIG. 2 is a functional equivalent circuit diagram of a negative pulse bias scheme that may be implemented in the processing chamber shown in FIG. 1A or FIG. 1B, according to one embodiment. [Figure 3B] FIG. 2 is a functional equivalent circuit diagram of a positive pulse bias scheme that may be implemented in the processing chamber shown in FIG. 1A or FIG. 1B, according to one embodiment. [Figure 3C] FIG. 2 is a functional equivalent circuit diagram of a Coulomb electrostatic chuck (ESC) that may be used in the processing chamber shown in FIG. 1A or FIG. 1B, according to one embodiment. [Figure 3D] FIG. 1C is a functional equivalent circuit diagram of a Johnsen-Rahbek type ESC that may be used in the processing chamber shown in FIG. 1A or FIG. 1B, according to one embodiment. [Figure 4A] FIG. 2 illustrates an example of a negative pulsed voltage (PV) waveform established on a bias electrode and a substrate, according to one embodiment. [Figure 4B] FIG. 2 illustrates an example series of pulse voltage (PV) waveform bursts, according to one or more embodiments. [Figure 4C] FIG. 2 illustrates an example series of pulse voltage (PV) waveform bursts, according to one or more embodiments. [Figure 4D] FIG. 2 illustrates an example of an ion energy distribution function (IEDF) formed by a series of pulsed voltage (PV) waveform bursts in accordance with one or more embodiments. [Figure 5A] FIG. 2 illustrates an example of a negative pulsed voltage (PV) waveform established on a bias electrode, according to one embodiment. [Figure 5B] FIG. 2 illustrates an example of a shaped pulse voltage (PV) waveform established on a bias electrode, according to one embodiment. [Figure 5C] FIG. 2 illustrates an example of a positive pulsed voltage (PV) waveform established on a bias electrode, according to one embodiment. [Figure 5D] FIG. 2 illustrates a comparison of negative and positive pulse voltage (PV) waveforms established on a substrate during processing, according to one embodiment. [Figure 6A] FIG. 2 illustrates an example of a radio frequency (RF) waveform, according to one embodiment. [Figure 6B] FIG. 2 illustrates an example of a pulsed radio frequency (RF) waveform, according to one embodiment. [Figure 6C] FIG. 1 illustrates an example of radio frequency (RF) and pulse voltage (PV) waveforms that may be delivered to one or more electrodes according to one or more embodiments. [Figure 6D] FIG. 1 illustrates examples of radio frequency (RF) and pulse voltage (PV) waveforms that may be delivered to one or more electrodes according to one or more embodiments. [Figure 6E] FIG. 1 illustrates examples of radio frequency (RF) and pulse voltage (PV) waveforms that may be delivered to one or more electrodes according to one or more embodiments. [Figure 6F] FIG. 1 illustrates examples of radio frequency (RF) and pulse voltage (PV) waveforms that may be delivered to one or more electrodes according to one or more embodiments. [Figure 6G] FIG. 1 illustrates examples of radio frequency (RF) and pulse voltage (PV) waveforms that may be delivered to one or more electrodes according to one or more embodiments. [Figure 6H] FIG. 1 illustrates examples of radio frequency (RF) and pulse voltage (PV) waveforms that may be delivered to one or more electrodes according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] For ease of understanding, the same reference numerals have been used where possible to designate identical elements common to each of the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0016] The embodiments of the present disclosure provided herein include apparatus and methods for plasma processing a substrate in a processing chamber. More specifically, the embodiments of the present disclosure describe a biasing scheme configured to provide a radio frequency (RF) waveform from an RF power source to one or more electrodes in the processing chamber and a pulsed voltage (PV) waveform provided from one or more pulsed voltage (PV) generators to one or more electrodes in the processing chamber. In general, the generated radio frequency waveform is configured to establish and maintain a plasma inside the processing chamber and the provided PV waveform is configured to establish a substantially constant sheath voltage across the surface of the substrate, thus resulting in a desired ion energy distribution function (IEDF) at the surface of the substrate during one or more plasma processing steps performed in the processing chamber. The plasma processes disclosed herein may be used to control the shape of the IEDF to control the interaction of the plasma with the surface of the substrate during processing. In some configurations, the plasma processes disclosed herein are used to control the profile of features formed on the surface of the substrate during processing. In some embodiments, the pulsed voltage waveform is established by a PV power source electrically coupled to a bias electrode disposed in a substrate support assembly disposed in the plasma processing chamber.

[0017] During some semiconductor plasma processes, ions are intentionally accelerated toward a substrate by a voltage drop across an electron donating sheath that occurs above a substrate placed on top of a substrate support assembly 136 (FIGS. 1A-1C). Without intending to limit the scope of the disclosure provided herein, the substrate support assembly 136 is often referred to herein as a "cathode assembly" or "cathode." In some embodiments, the substrate support assembly 136 includes a substrate support 105 and a support base 107. The substrate support 105 may include an electrostatic chuck (ESC) assembly configured to chuck (e.g., hold) a substrate on a substrate receiving surface 105A.

[0018] In some embodiments of the disclosure provided herein, the process chamber is configured to provide a capacitively coupled gas discharge such that the plasma is generated by using an RF power supply assembly including an RF power source coupled to an RF electrode via an RF matching network ("RF match"). The RF matching network is configured to tune the apparent load to 50Ω to minimize reflected power and maximize power delivery efficiency. In some embodiments, the RF electrode includes a metal plate positioned parallel to the plasma-facing surface of the substrate.

[0019] In addition, during plasma processing methods disclosed herein, a sheath of ion accelerating cathodes is typically formed during plasma processing by using a pulsed voltage (PV) generator configured to establish a pulsed voltage waveform on one or more bias electrodes 104 (FIGS. 1A-1B) disposed within the substrate support assembly 136. In some embodiments, the one or more bias electrodes 104 include a chucking electrode separated from the substrate by a thin layer of dielectric material formed within the substrate support assembly 136 (e.g., an electrostatic chuck (ESC) assembly) and an optional edge control electrode disposed within or below an edge ring 114 that surrounds the substrate 103 when the substrate 103 is disposed on a substrate support surface 105A of the substrate support assembly 136. This pulsed voltage waveform (PVWF), as discussed further below, may be configured to provide an approximately constant sheath voltage (e.g., the difference between the plasma potential and the substrate potential) for a significant portion of the PV waveform's pulse period, which portion corresponds to a single (narrow) peak containing the ion energy distribution function (IEDF) of the ions arriving at the substrate during this portion of the pulse period, which single peak is also referred to herein as the "ion current phase."

[0020] However, as previously discussed, due to direct or capacitive coupling between the RF power supply assembly and the PV generator assembly during processing, the interaction between the output from the RF power supply and the output from the PV generator can cause power to be diverted from the intended (plasma) load, and possibly even cause damage to each of the RF and PV sources, even without the use of the filtering schemes and / or processing methods disclosed herein. Accordingly, the apparatus and methods disclosed herein are configured to provide a way to combine RF and PV power to one or more electrodes (e.g., cathodes) of a plasma processing chamber by coupling each generator to its respective electrode through one or more waveform-dependent filter assemblies such that the one or more waveform-dependent filter assemblies do not significantly disrupt the power delivery from the respective RF and PV power supplies to the plasma.

[0021] Examples of Plasma Processing Chambers FIG. 1A is a schematic cross-sectional view of a processing chamber 100 in which a composite load 130 (FIGS. 3A-3B) is formed during plasma processing. FIGS. 3A-3B are respective examples of simplified electrical circuits 140 of pulsed voltage and RF biasing schemes that may be implemented using components of the processing chamber 100. The processing chamber 100 is configured to implement one or more of the biasing schemes according to one or more embodiments proposed herein. In one embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etch (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma-enhanced deposition chamber, e.g., a plasma-enhanced chemical vapor deposition (PECVD) chamber, a plasma-enhanced physical vapor deposition (PEPVD) chamber, or a plasma-enhanced atomic layer deposition (PEALD) chamber. In some other embodiments, the processing chamber is a plasma processing chamber or a plasma-based ion implantation chamber, e.g., a plasma doping (PLAD) chamber. In some embodiments, the plasma source is a capacitively coupled plasma (CCP) source that includes an electrode (e.g., chamber lid 123) disposed within the process volume facing the substrate support assembly 136. As shown in FIG. 1A, the opposing electrode, such as the chamber lid 123, disposed on the opposite side of the substrate support assembly 136 is electrically grounded. However, in other alternative embodiments, the opposing electrode is electrically coupled to a radio frequency power source, as shown in FIG. 1B. In yet other embodiments, the process chamber alternatively or additionally includes an inductively coupled plasma (ICP) source electrically coupled to a radio frequency (RF) power source.

[0022] The processing chamber 100 also includes a chamber body 113 including a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which define a processing volume 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized and shaped to provide structural support for the elements of the processing chamber 100 and are configured to withstand pressures and energy applied thereto while a plasma 101 is generated in a vacuum environment maintained within the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or stainless steel. A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more processing gases to the processing volume 129 from a processing gas source 119 in fluid communication therewith. The substrate 103 enters and leaves the processing volume 129 through an opening (not shown) in one of the one or more side walls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103. Here, the substrate 103 is moved to and from the substrate receiving surface 105A of the ESC substrate support 105 using a lift pin system (not shown).

[0023] In some embodiments, the RF power assembly 160 is configured to provide RF power to a support base 107 disposed within the substrate support assembly 136 and proximate to the ESC substrate support 105. The RF power provided to the support base 107 is configured to ignite and sustain a processing plasma 101 formed using processing gases distributed within the processing volume 129. In some embodiments, the support base 107 is an RF electrode electrically coupled to the RF power source 118 via an RF matching circuit 161 and a first filter assembly 162, both disposed within the RF power assembly 160. In some embodiments, the plasma generator assembly 160 and the RF power source 118 are used to ignite and sustain the processing plasma 101 using the processing gases distributed within the processing volume 129 and a field generated by the RF power provided by the RF power source 118 to the support base 107. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps via a vacuum inlet connection 120 to evacuate the processing gases and / or other gases and maintain a reduced pressure. A substrate support assembly 136 disposed within the process volume 129 is positioned on a grounded support shaft 138 that extends through the chamber base 124. However, in some embodiments, a radio frequency power assembly 160 is configured to provide RF power to a bias electrode 104 disposed within the substrate support 105 relative to the support base 107.

[0024] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107, as briefly discussed above. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a ground plate 112, as further discussed below. The substrate support 105 is disposed on and thermally coupled to the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed thereon during substrate processing. In some embodiments, one or more cooling channels (not shown) disposed within the support base 107 are in fluid communication with a coolant source (not shown), such as a cooling or water source having a relatively high electrical resistance. In some embodiments, a heater (not shown), such as a resistive heating element, is embedded in the dielectric material of the substrate support 105. Here, the support base 107 is formed from a corrosion-resistant, heat-conducting material, for example a corrosion-resistant metal such as aluminum, an aluminum alloy, or stainless steel, and is bonded to the substrate support using an adhesive or by mechanical means.

[0025] The support base 107 is electrically insulated from the chamber base 124 by an insulator plate 111, and a ground plate 112 is inserted between the insulator plate 111 and the chamber base 124. In some embodiments, the process chamber 100 further includes a quartz pipe 110 or collar that at least partially surrounds a portion of the substrate support assembly 136 to prevent the ESC substrate support 105 and / or the support base 107 from contacting corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof, so as to prevent corrosion. Typically, the quartz pipe 110, the insulator plate 111, and the ground plate 112 are surrounded by a liner 108, where a plasma screen 109 is approximately flush with the substrate receiving surface of the ESC substrate support 105 to prevent plasma formation in the volume between the liner 108 and one or more side walls 122.

[0026] The substrate support 105 is typically formed from a dielectric material such as a bulk sintered ceramic material, a corrosion resistant metal oxide or metal nitride material such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded within these dielectric materials. In one configuration, the bias electrode 104 is a chucking electrode used to chuck the substrate 103 to the substrate receiving surface 105A of the substrate support 105, also referred to herein as the ESC substrate support, and bias the substrate 103 against the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed from one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof. In some embodiments, the bias electrode 104 is electrically coupled to a chucking module 116 and is provided with a chucking voltage, such as a static DC voltage of about -5000V to about 5000V, from the chucking module 116 using an electrical conductor, such as a coaxial transmission line 106 (e.g., a coaxial cable). As discussed further below, the chucking module 116 includes a bias compensation circuit element 116A (FIGS. 3A-3B), a DC power supply 155, and a blocking capacitor 153. A chucking module blocking capacitor, also referred to herein as blocking capacitor 153, is disposed between the output of a pulsed voltage waveform generator (PVWG) 150 and the bias electrode 104.

[0027] The bias electrode 104 is spaced from the substrate receiving surface 105A of the substrate support 105, and thus from the substrate 103, by a layer of dielectric material of the substrate support 105. The effective circuit elements used to model the electrical coupling of the bias electrode 104 to the plasma 101 will vary depending on the type of electrostatic chucking method, such as a Coulomb ESC or a Johnsen-Rahbek type ESC, utilized within the substrate support 105 to hold the substrate 103 during processing. FIGS. 3C and 3D show the effective circuit elements 191 that are generated when a Coulomb ESC or a Johnsen-Rahbek type ESC, respectively, is utilized during plasma processing. Generally, the parallel plate-like structure formed by the bias electrode 104 and the layer of dielectric material will have an effective capacitance C, typically between about 5 nF and about 50 nF. E Typically, the thickness of the layer of dielectric material (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) is from about 0.1 mm to about 1 mm, such as from about 0.1 mm to about 0.5 mm, e.g., about 0.3 mm. Here, the bias electrode 104 is electrically coupled to the output of a pulsed voltage waveform generator (PVWG) 150 using an external conductor, such as a transmission line 106 disposed within the support shaft 138. In some embodiments, the dielectric material and layer thickness are determined by the chuck capacitance C of the layer of dielectric material. ESC may be selected to be between about 5 nF and about 50 nF, such as between about 7 and about 10 nF.

[0028] In the more complex model of a Johnsen-Rahbek type ESC shown in FIG. 3D, the circuit model includes the chuck capacitance C of the ESC dielectric material, as shown. ESC and the resistance R of the ESC dielectric material CER and the capacitance of the gap, C abt and the capacitance of the board, C sub and the resistance of the board R sub The capacitance of the gap C abt generally consists of the gas-containing space above and below the substrate disposed on the substrate support 105. The capacitance of the gap C abtis the chuck capacitance C ESC It is expected that the capacitance will be in the same range as

[0029] In some applications, the substrate 103 is typically made of a thin layer of semiconductor and / or dielectric material and may therefore be considered electrically as part of the ESC dielectric layer disposed between the bias electrode 104 and the substrate receiving surface 105A. Thus, in some applications, the chuck capacitance C ESC is the ESC capacitance and the substrate capacitance (i.e., the substrate capacitance C sub However, in the case of a Coulomb chuck, the capacitance of the substrate C sub is typically very large (>10 nF) or the substrate may be conductive (infinite capacitance), so the series capacitance is primarily the capacitance C ESC In this case, the effective capacitance C E is effectively the chuck capacitance C, as shown in FIG. ESC In the case of a "Johnsen-Rahbek type ESC," the ESC dielectric layer is "leaky" in that it is not a perfect insulator but has some conductivity, for example the dielectric material may be doped aluminum nitride (AlN) with a dielectric constant (ε) of about 9. However, the effective capacitance of the Johnsen-Rahbek type ESC should be similar to that of a Coulomb Chuck. In one example, the volume resistivity of the dielectric layer in a Johnsen-Rahbek type ESC is about 10 12 Less than ohm-cm (Ω-cm), or about 10 10 Less than Ω-cm, even 10 8 Ω-cm~10 12 It can be Ω-cm.

[0030] The substrate support assembly 136 further includes an edge control electrode 115 that underlies the edge ring 114 and surrounds the bias electrode 104 and, when biased, can affect or change a portion of the generated plasma 101 that is at or outside the edge of the substrate 103, depending on its position relative to the substrate 103. The edge control electrode 115 is biased using a pulsed voltage waveform generator (PVWG) 150 that is separate from the PVWG 150 used to bias the bias electrode 104. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to bias the bias electrode 104 and a second PV waveform generator 150 of a second PV source assembly 197 is configured to bias the edge control electrode 115. In one embodiment, the edge control electrode 115 is disposed within the region of the substrate support 105, as shown in FIG. 1A. In general, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular, made from a conductive material, and configured to surround at least a portion of the bias electrode 104, as shown in FIGS. 1A-1B. In some embodiments, the edge control electrode 115 comprises a conductive mesh, foil, or plate disposed at a similar distance (i.e., in the Z direction) from the surface 105A of the substrate support 105 as the bias electrode 104, as shown in FIG. 1A. In some other embodiments, the edge control electrode 115 comprises a conductive mesh, foil, or plate disposed on or within a region of a dielectric pipe 110 (e.g., AlN or Al2O3), which surrounds at least a portion of the bias electrode 104 and / or the substrate support 105, as shown in FIG. 1B. Alternatively, in some other embodiments, the edge control electrode 115 is disposed within or coupled to an edge ring 114 disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (eg, AlN, Al2O3, etc.).

[0031] 1B, in some embodiments, the substrate support 105 further includes a secondary electrode 104L (e.g., a metal mesh, foil, or plate) electrically coupled to the bias electrode 104 using a plurality of conductive vias 114V. One or more of the vias 114V have a first end in electrical contact with the bias electrode 104 and a second end in electrical contact with the secondary electrode 104L. The secondary electrode 104L disposed below the bias electrode 104 is dimensioned, positioned, and aligned to improve control of the plasma sheath and / or plasma uniformity across the surface of the substrate 103 during processing. In some configurations, as shown in FIG. 1B, the edge control electrode 115 is disposed adjacent to the secondary electrode 104L such that when the bias electrode 104, the secondary electrode 114L, and the edge control electrode 115 are used in combination, the edge control electrode 115 is disposed adjacent to the secondary electrode 104L to desirably change the generated plasma 101 at or outside the edge of the substrate 103.

[0032] 1A and 1B, the support base 107 is spaced from the bias electrode 104 by a portion of dielectric material. In some configurations, the portion of dielectric material is the dielectric material used to form the substrate support 105 and extends from the backside of the substrate support 105 to the bias electrode 104. The portion of dielectric material of the substrate support 105 defines a support base capacitance C CL which has an ESC capacitance C, as shown diagrammatically in FIG. 3A and FIG. 3B. E In some embodiments, the portion of the dielectric material disposed between the support base 107 and the bias electrode 104 is thicker than the dielectric material disposed between the bias electrode 104 and the substrate 103, and these dielectric materials are the same material as and / or form part of the substrate support 105. In one example, the portion of the dielectric material (e.g., Al2O3 or AlN) of the substrate support 105 disposed between the support base 107 and the bias electrode 104 has a thickness of more than 1 mm, such as from about 1.5 mm to about 20 mm.

[0033] Generally, when low pressure is created in the process volume 129 of the process chamber 100, the thermal conduction between the surfaces of the hardware components disposed therein, such as between the dielectric material of the substrate support 105 and the substrate 103 disposed on the substrate receiving surface of the substrate support 105, deteriorates, and the substrate support becomes less effective in heating and cooling the substrate 103. Therefore, in some processes, a thermally conductive inert heat transfer gas, typically helium, is introduced into the volume disposed therein (not shown) to improve the heat transfer between the non-device surface of the substrate 103 and the substrate receiving surface 105A of the substrate support 105. The heat transfer gas supplied by the heat transfer gas source (not shown) flows through a gas transfer path (not shown) disposed through the support base 107 to the backside volume and is further distributed through the substrate support 105.

[0034] The processing chamber 100 further includes a controller 126, also referred to herein as a processing chamber controller, where the controller 126 includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The controller 126 is used to control the processing sequence used to process the substrate 103, including the substrate bias method described herein. The CPU 133 is a general-purpose computer processor and associated sub-processors configured for use in an industrial setting to control a processing chamber. The memory 134 described herein is generally a non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 135 are conventionally coupled to the CPU 133 and include caches, clock circuits, input / output subsystems, power supplies, and the like, as well as combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 for instructing the processor in the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the controller 126 determines tasks executable by the components of the process chamber 100. Preferably, the program readable by the CPU 133 in the controller 126 contains code that, when executed by the processor (CPU 133), performs tasks associated with monitoring and executing the electrode biasing schemes described herein. This program will include instructions used to control the various hardware and electrical components in the process chamber 100 to perform the various process tasks and various process sequences used to implement the electrode biasing schemes described herein.

[0035] During processing, the PV generators 314 within the PV waveform generators 150 of the first PV source assembly 196 and the second PV source assembly 197 establish a pulsed voltage waveform across a load (e.g., the composite load 130) disposed with the processing chamber 100. For ease of discussion and without limitation with respect to the disclosure provided herein, the components within the second PV source assembly 197 used to bias the edge control electrode 115 are not shown in schematic form in FIGS. 3A-3B. The delivery of the PV waveforms from each of the PV waveform generators 150 is generally controlled using signals provided from the controller 126. In one embodiment, the PV waveform generator 150A is configured to maintain a substantially constant, predetermined positive voltage at its output (i.e., output relative to ground) by repeatedly opening and closing its internal switch S1 at a predetermined rate through a periodically repeating, predetermined length of time interval, as shown in FIG. 3A. Alternatively, in one embodiment, the PV waveform generator 150B maintains a substantially constant predetermined negative voltage at its output (i.e., output relative to ground) by repeatedly opening and closing its internal switch S1 at a predetermined rate through a periodically repeating time interval of predetermined length, as shown in FIG. 3B. In FIGS. 3A-3B, the PV waveform generators 150A, 150B are summarized to a minimal combination of components important for understanding their role in establishing a desired pulsed voltage waveform at the bias electrode 104. As shown generally in FIGS. 3A-3B, each PV waveform generator 150 will include a PV generator 314 (e.g., a DC power source) and one or more electrical components, such as a high repetition rate switch, a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown), configured to provide a PV waveform at an output 350. An actual PV waveform generator 150 may be based on a more complex electrical circuit than that shown in FIGS. 3A-3B, may include any number of internal components, and may be configured as a nanosecond pulse generator.Each of the schematic diagrams in Figures 3A-3B provides only functionally equivalent representations of the components and electrical circuitry of PV waveform generator 150 to the extent necessary to explain the basic principles of operation, its interaction with the plasma in the process volume, and its role in establishing pulsed voltage waveforms, such as input pulsed voltage waveforms 401, 431, 441 (Figures 4A-4C) at bias electrode 104. As can be inferred from the schematic diagrams shown in Figures 3A-3B, switch S1, when moved from an open (off) position to a closed (on) position, connects the output of PV waveform generator 150 to PV generator 314, which generates a substantially constant output voltage. PV waveform generator 150 may be used primarily as a charge injector (current source) rather than a constant voltage power supply, and therefore no strict requirement for output voltage stability is necessary, since the output voltage may vary over time even when the switch is closed (on). Further, in some configurations, the PV generator 314 is essentially a source rather than a sink, in that it only passes current in one direction (e.g., the output can charge but not discharge a capacitor). In addition, when switch S1 remains in the open (OFF) position, the voltage across the output of PV waveform generator 150 (V0) is not controlled by PV generator 314, but is determined by the interaction of the internal components of PV waveform generator 150 with other circuit elements.

[0036] Current feedback output stage 314A has one end connected to ground and the other end connected to a node at the output of PV waveform generator 150 (i.e., one side of a generator output combining assembly (not shown)). Current feedback output stage 314A may include elements such as a resistor, a series combination of a resistor and an inductor, switch S2, and / or a more complex combination of electrical elements including a parallel capacitor that allows positive current flow toward ground.

[0037] Transmission line 131, which forms part of PV transmission line 157 (FIGS. 1A-1B), electrically connects output 350 of PV waveform generator 150 to second filter assembly 151. The following discussion will primarily discuss PV transmission line 157 of first PV source assembly 196 used to couple PV waveform generator 150 to bias electrode 104, but PV transmission line 158 of second PV source assembly 197 will include the same or similar components to couple PV waveform generator 150 to edge control electrode 115. Thus, in general, output 350 of PV waveform generator 150 is terminal, and output of PV pulse generator 314 is connected by internal conductors to output 350 of PV waveform generator 150 and current feedback output stage 314A. Transmission line 131 connects generator output coupling assembly 181 (FIG. 1C) located at output 350 of PV waveform generator 150 to second filter assembly 151. The internal conductors of the various parts of the PV transmission lines 157, 158 may include: (a) a coaxial transmission line (e.g., coaxial line 106), which may include a flexible coaxial cable connected in series with a rigid coaxial transmission line; (b) an insulated high voltage corona resistant hook-up wire; (c) bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements (a)-(e). The portion of the PV transmission line 157 inside the support shaft 138 and the outer conductor portion of the PV transmission line 157, such as the bias electrode 104 (e.g., the first conductor), have some combined stray capacitance C to ground. stray (FIGS. 3A-3B). Although not shown in the figures, the outer conductor portion (e.g., the second conductor) of the PV transmission line 158 and the edge control electrode 115 also have some combined stray capacitance to ground, C strayThe internal conductors of PV waveform generator 150 may include the same basic elements as the external conductors. In most practical applications, transmission line 131 will include line inductance 159, which may include a portion generated by internal components of PV waveform generator 150 (i.e., to the left of generator output combining assembly 181 (FIGS. 3A-3B)) and / or a portion generated by an external line / cable connecting PV waveform generator 150 to second filter assembly 151 (i.e., to the right of generator output combining assembly 181).

[0038] Returning to FIG. 1A, the processing chamber 100 includes a grounded chamber lid 123. In this configuration, which is a total departure from conventional plasma processing chamber designs, RF power is instead delivered through the substrate support. Thus, by coupling the radio frequency power supply 118 to the support base 107, the entire ESC, which is functionally part of the cathode assembly, may ground the top electrode and maximize the current return area. For plasma processes utilizing RF power delivery and PV waveform delivery, maximizing the current return area by maximizing the ground area inside the plasma processing chamber minimizes plasma potential jumps during the recharge / sheath collapse phase of the ESC of the PV waveform cycle generated by the output of the PV waveform generator 150, as discussed further below. Thus, the apparatus and methods provided herein improve plasma processing efficiency by minimizing power loss to the chamber walls. The RF power and PV pulse waveform delivery methods described herein also provide certain processing benefits by enabling improved control of plasma characteristics and affecting radical generation. However, as mentioned above, because there is strong capacitive coupling between the support base 107 and the bias electrode 104 via the ESC ceramic layer, and also strong capacitive coupling between the RF transmission line 167 and the PV transmission line 157, when both types of power are supplied through the substrate support assembly 136 (i.e., the cathode assembly), each generator will induce a current through the other, not only diverting power from the intended (plasma) load, but also damaging either generator.

[0039] In another alternative chamber lid 123 configuration that may be used with one or more of the other embodiments disclosed herein, the chamber lid 123 (i.e., the opposing electrode) is electrically insulated from one or more sidewalls 122 and electrically coupled to the radio frequency power source 118 via the plasma generator assembly 160, as shown in FIG. 1B. In this configuration, the chamber lid 123 may be driven by the radio frequency power source 118 to ignite and sustain a processing plasma 101 inside the processing volume 129. In one example, the radio frequency power source 118 is configured to supply an RF signal to the chamber lid 123 at an RF frequency greater than about 300 kHz, such as a frequency between about 300 kHz and 60 MHz, or even between about 2 MHz and about 40 MHz.

[0040] Bias Subsystem Assembly 1C is a schematic diagram of a processing chamber 100 including a bias subsystem assembly 170 configured to enclose and separately insulate various electrical components used to generate, control, and deliver radio frequency and pulsed voltage waveforms to one or more electrodes, such as the substrate support assembly 136, inside the processing chamber 100. Due to at least the configuration and positioning of the bias subsystem assembly 170 inside the processing chamber 100, a more repeatable and more efficient delivery of generated RF and PV waveforms may be achieved during processing. It is believed that the use of the bias subsystem assembly 170 inside each of multiple similarly configured processing chambers may help reduce the variability in processing results found in substrate processing facilities containing many processing chambers, as well as other substrate processing facilities containing many processing chambers around the world.

[0041] The bias subsystem assembly 170 will generally include a pulsed voltage generating unit housing 172 and a junction box housing 169. The bias subsystem assembly 170 will generally include an electrical circuit including active power and voltage sources, and passive components. The active power sources may include one or more pulsed voltage waveform generators, one or more radio frequency power sources, and / or one or more direct current power sources. The passive components within the electrical circuit may include resistors, capacitors, inductors, and diodes. In use, the bias subsystem assembly 170 may be used to combine various types of power sources such that their outputs can be applied to the same load (e.g., composite load 130). The load may include the plasma 101 formed in the processing chamber 100, the cathode sheath, the cathode and its power supply system (e.g., transmission lines), and stray inductive and capacitive elements.

[0042] In some embodiments, the junction box housing 169 includes one or more bias compensation module compartments 171 and a radio frequency (RF) filter compartment 173. In some embodiments, the bias subsystem assembly 170 also includes an RF supply housing 174. Each of the compartments 171, 172, and 173 and the RF supply housing 174 includes one or more walls 171A, 172A, 173A, and 174A, which are at least partially configured to enclose and isolate electrical components therein from electrical components within adjacently disposed housings and from electrical components in the environment external to the processing chamber 100. Typically, only one wall is used to isolate adjacent compartments from each other. Although two walls are disposed in a directly adjacent relationship in some areas as shown diagrammatically in FIG. 1C and FIG. 1D, this is not intended to limit the scope of the disclosure provided herein, as a single wall may be used in place of two separate adjacent walls. The bias subsystem assembly 170 is disposed or coupled to one or more of the walls of the processing chamber 100, such as the base 124, in a manner that provides a rigid mount, repeatably defines the distance between the components, and avoids strain on any connections between the bias subsystem assembly 170 and other components in the processing chamber 100 (e.g., the connection with the substrate support assembly 136). In some embodiments, a surface of the bias subsystem assembly 170 (e.g., the exposed surface of the wall 173A) is disposed adjacent to one or more of the walls of the processing chamber 100 (e.g., the base 124). In some embodiments, the exposed surface of the bias subsystem assembly 170 (e.g., the surface of the wall 173A) is disposed a distance 124A (FIG. 1C) less than 24 inches, such as less than 12 inches, or even less than 6 inches, from the base 124. In one example, the exposed surface of the wall 173A is directly coupled to the lower surface of the base 124.It is believed that by optimizing the routing of the current carrying elements interconnecting electrical components within sections 171, 172, and 173 of the bias subsystem assembly 170 and / or the RF supply housing 174 to minimize coupling lengths, such as the connections between components of the bias compensation section and components of the high frequency filter section 173, the stray inductance and capacitance formed in each of these regions of the system may be minimized. In practice, the bias subsystem assembly 170 may be used to significantly reduce variations in the waveforms it generates and establishes, thus improving the integrity and repeatability of high voltage signals supplied to electrodes within the processing chamber 100, such as electrodes within the substrate support assembly 136.

[0043] The pulsed voltage generating unit housing 172 includes at least one PV waveform generator 150 insulated from electrical components, such as the high frequency filter section 173 and the RF supply housing 174 in the bias compensation module section 171, by at least a wall 172A. The wall 172A may include a grounded sheet metal box (e.g., an aluminum or SST box) configured to support the one or more PV waveform generators 150 and insulate them from any electromagnetic interference generated by components inside the RF supply housing 174 and / or components outside the process chamber 100. At the interface between the pulsed voltage generating unit housing 172 and the bias compensation module section 171, a generator output coupling assembly 181 is used to connect an output 350 of the PV waveform generator 150 to a first portion of the transmission line 131 and electrical components (e.g., blocking capacitor 153) disposed in the bias compensation module section 171. As used herein, the term "coupling assembly" generally describes one or more electrical components, such as one or more electrical connectors, electrical discrete elements (e.g., capacitors, inductors, and resistors), and / or conductive elements, configured to connect current carrying elements that electrically couple two or more electrical components.

[0044] The one or more bias compensation module compartments 171 include bias compensation circuit element 116A (FIGS. 3A-3B) and blocking capacitor 153, insulated from electrical components in pulse voltage generating unit housing 172, radio frequency filter compartment 173, and RF supply housing 174 by at least wall 171A. In one embodiment, bias compensation circuit element 116A is coupled to an externally located DC power source 155 using a DC power coupling assembly 185 of the bias compensation module compartment formed in wall 171A. Alternatively, in one embodiment (not shown), bias compensation circuit element 116A and DC power source 155 are both disposed inside bias compensation module compartment 171 and surrounded by wall 171A. Wall 171A may include a grounded sheet metal box configured to insulate components inside bias compensation module compartment 171 from components inside pulse voltage generating unit housing 172, any electromagnetic interference generated by RF supply housing 174, and / or electromagnetic interference outside process chamber 100. At the interface between the bias compensation module section 171 and the high frequency filter section 173, an output coupling assembly 182 of the bias compensation module section is used to connect the bias compensation circuit element 116A, the DC power supply 155 and the blocking capacitor 153 to a second portion of the transmission line 131 and to electrical components (e.g., the second filter assembly 151) disposed within the high frequency filter section 173.

[0045] The high frequency filter section 173 includes one or more second filter assemblies 151 and the chamber interconnect components, insulated by at least a wall 173A from the electrical components in the pulsed voltage generating unit housing 172, the one or more bias compensation module housings 171, and the RF supply housing 174. The wall 173A may include a grounded sheet metal box configured to insulate the components inside the high frequency filter section 173 from the components inside the pulsed voltage generating unit housing 172, any electromagnetic interference generated by the RF supply housing 174, and / or electromagnetic interference outside the processing chamber 100. At the interface between the high frequency filter section 173 and the base 124 of the processing chamber 100, a cathode coupling assembly 183 is used to connect the output connection point of the high frequency filter section 173 to a portion of the PV transmission lines 157, 158, which electrically connect the bias subsystem assembly 170 to one of the electrodes inside the processing chamber 100, such as an electrode inside the substrate support assembly 136.

[0046] The RF supply housing 174 includes the RF matching circuit 161, the first filter assembly 162, the optional radio frequency power supply 118, and other chamber interconnect components, insulated from the electrical components in the pulsed voltage generating unit housing 172 and one or more bias compensation module housings 171 by at least a wall 174A. The wall 174A may include a grounded sheet metal box configured to insulate the components inside the RF supply housing 174 from any electromagnetic interference generated by the components inside the pulsed voltage generating unit housing 172 and / or from electromagnetic interference outside the processing chamber 100. At the interface between the RF supply housing 174 and the base 124 of the processing chamber 100, a cathode coupling assembly 184 is used to connect the output connection point of the RF supply housing 174 to a portion of the RF transmission line 167, which electrically connects the RF supply housing 174 of the bias subsystem assembly 170 to one of the electrodes inside the processing chamber 100, such as an electrode inside the substrate support assembly 136. The portion of the RF transmission line 167 inside the support shaft 138 and the outer conductor portion of the RF transmission line 167, such as the support base 107 (e.g., a third conductor), have some combined stray capacitance C to ground. stray should have.

[0047] 1D is a schematic diagram of a processing chamber 100 including an alternative version of the bias subsystem assembly 170 shown in FIG. 1C. As shown in FIG. 1D, the first filter assembly 162 has been removed from the RF supply housing 174 and relocated into the radio frequency filter section 173. In this configuration, the radio frequency power supply 118 is configured to supply an RF waveform through the RF matching circuit 161, the cathode coupling assembly 184, the first RF coupling assembly 186, the first filter assembly 162, the second RF coupling assembly 187, the RF transmission line 167 to the electrode with the substrate support assembly 136. In this configuration, the radio frequency filter section 173 includes one or more second filter assemblies 151, the first filter assembly 162, and other chamber interconnect components.

[0048] Plasma processing bias method and process FIG 2 is a simplified schematic diagram of a biasing scheme that may be used with the process chamber shown in FIG 1A or FIG 1B. As shown in FIG 2, the radio frequency power supply 118 and the PV waveform generator 150 are configured to supply RF and pulsed voltage waveforms, respectively, to one or more electrodes disposed within the chamber body 113 of the process chamber 100. In one embodiment, the radio frequency power supply 118 and the PV waveform generator 150 are configured to simultaneously supply RF and pulsed voltage waveforms to one or more electrodes disposed within the substrate support assembly 136. In one non-limiting example, as discussed above, the radio frequency power supply 118 and the PV waveform generator 150 are configured to supply RF and pulsed voltage waveforms, respectively, to the support base 107 and the bias electrode 104, both of which are disposed within the substrate support assembly 136. In another example, the high frequency power supply 118, the first PV waveform generator 150 and the second PV waveform generator 150 are configured to supply an RF waveform, a first pulsed voltage waveform and a second pulsed voltage waveform, respectively, to the support base 107, the bias electrode 104 and the edge control electrode 115, all disposed within the substrate support assembly 136.

[0049] 2, the radio frequency power supply 118 is configured to supply a sinusoidal RF waveform to one or more electrodes disposed within the chamber body 113 by supplying an RF signal including a sinusoidal RF waveform 601 (FIGS. 6A-6G) through a plasma generator assembly 160 including an RF matching circuit 161 and a first filter assembly 162. In addition, each of the PV waveform generators 150 is configured to supply a PV waveform, typically including a series of voltage pulses (e.g., nanosecond voltage pulses), to one or more electrodes disposed within the chamber body 113 by establishing a PV waveform 401 (FIGS. 4A, 5A), 441 (FIG. 5B), or 431 (FIG. 5C) to the bias electrode 104 through a second filter assembly 151. Components within the chucking module 116 may optionally be disposed between the respective PV waveform generators 150 and the second filter assembly 151.

[0050] As briefly discussed above, Figures 3A-3B are functionally equivalent simplified examples of the pulsed voltage electrical circuit 140 and RF bias scheme proposed herein, respectively, including a representation of a plasma in a process volume. Figure 3A illustrates a simplified pulsed voltage electrical circuit 140 and RF bias scheme that utilizes a PV waveform generator 150 internal to the first PV source assembly 196 configured to supply a positive voltage during a portion of a process of establishing a PV waveform, such as PV waveform 431 (Figure 5C), to the bias electrode 104. Figure 3B illustrates a simplified pulsed voltage electrical circuit 140 and RF bias scheme that utilizes a PV waveform generator 150 internal to the first PV source assembly 196 configured to supply a negative voltage during a portion of a process of establishing a PV waveform, such as PV waveform 401 (Figures 4A and 5A), to the bias electrode 104. These circuits show a simplified model of the interaction between the pulsed voltage waveform generator 150 of the first PV source assembly 196 and the RF power supply 118 inside the process chamber 100, generally illustrating the basic elements used during operation of the process chamber 100. For clarity, the following definitions are used throughout this disclosure: (1) All potentials are referenced to ground unless a reference is specified. (2) The voltage of any physical point (such as the substrate or bias electrode) is similarly defined as the potential of this point relative to ground (the zero potential point). (3) Cathode sheath refers to the electron-donating ion acceleration sheath that corresponds to the negative substrate potential relative to the plasma. (4) Sheath voltage (sometimes referred to as "sheath voltage drop") V sh is defined as the absolute value of the potential difference between the plasma and an adjacent surface (e.g., the substrate or the chamber wall). (5) The substrate potential is the potential at the substrate surface facing the plasma.

[0051] The composite load 130 shown in Figures 3A-3B is illustrated in terms of a standard electrical plasma model that represents the processing plasma 101 as three elements in series. The first element is an electron-donating cathode sheath (sometimes referred to as the "plasma sheath" or simply the "sheath") adjacent the substrate 103. The cathode sheath is represented in Figures 3A-3B as (a) a diode D which, when open, represents sheath collapse; SH and (b) the current source I i and (c) a capacitor C that represents the sheath for the major part of the bias cycle where ion acceleration and etching occurs (i.e., the ion current phase of the PV waveform). SH (e.g., about 100-300 pF). The second element is a single resistor R plasma (e.g. resistor 146 = about 5-10 Ω). The third element is the electron donative wall sheath that forms on the chamber wall. This wall sheath is also shown in FIG. 3 as (a) diode D wall and (b) a current source I iwall and (c) a capacitor C that primarily represents the wall sheath during the ESC recharge phase of the PV waveform (described later in the text). wall (e.g., about 5-10 nF). The inner surface of the grounded metal wall is also represented by a large capacitor C in FIG. coat (e.g., about 300-1000 nF).

[0052] As shown in FIGS. 3A and 3B, the high frequency power supply 118 transmits an RF signal and a generated RF power through a first filter assembly 162, an RF matching circuit 161, a line inductance L Line , supporting base capacitance C CL , and the effective capacitance C E, to the support base 107 and ultimately to the composite load 130. In one embodiment, the RF matching circuit 161 includes a series inductance element L SER and an adjustable series capacitance element C that can be controlled by an input from the controller 126. SER and an adjustable shunt capacitance element C Shunt and . In some embodiments, the RF matching circuit 161 may alternatively be formed using other configurations of circuit elements, such as, for example, an L-network, a π-network, or a transformer match circuit. As mentioned above, the RF matching circuit 161 is typically configured to tune the apparent load to 50Ω to minimize reflected power generated by providing an RF signal from the high frequency power source 118 and maximize its power delivery efficiency. In some embodiments, the RF matching circuit 161 is optional, and in these cases, other RF signal matching techniques (e.g., variable frequency tuning) may be used during plasma processing of the substrate to avoid inefficient delivery of RF power to the composite load 130.

[0053] First filter assembly 162, also referred to herein as a pulse voltage filter assembly, includes one or more electrical elements configured to substantially prevent current generated by the output of PV waveform generator 150 from flowing through RF transmission line 167 and damaging radio frequency power source 118. First filter assembly 162 acts as a high impedance (e.g., high Z) to the PV signal generated from PV pulse generator 314 inside PV waveform generator 150, thus inhibiting current flow to radio frequency power source 118. In one embodiment, first filter assembly 162 includes a blocking capacitor C disposed between RF matching circuit 161 and radio frequency power source 118. BC In this configuration, the RF matching element 161, when adjusting the apparent load to the RF power source 118, includes a blocking capacitor C BCIn one example, the first filter assembly 162 includes a capacitor of 35-100 pF to prevent a nanosecond PV waveform (e.g., a pulse period of 10-100 nanoseconds) provided by the PV waveform generator 150 from damaging the high frequency power supply 118. In another example, the first filter assembly 162 includes a blocking capacitor C BC Includes.

[0054] In some embodiments, it may be desirable to utilize two or more sets of high frequency power sources 118 and RF plasma generator assemblies 160, each configured to separately supply RF power at a separate RF frequency to the support base 107 or other electrodes within the substrate support assembly 136. In one example, a first high frequency power source 118A (not shown) and a first RF plasma generator assembly 160A (not shown) are configured to supply RF signals to the support base 107 at an RF frequency between about 300 kHz and 13.56 MHz, and a second high frequency power source 118B (not shown) and a second RF plasma generator assembly 160B (not shown) are configured to supply RF signals to the support base 107 at an RF frequency of about 40 MHz or greater. In this example, each of the high frequency power source assemblies 160A, 160B includes a first filter assembly 162 (e.g., having a capacitance of 0.10 .mu.m) adapted and similarly configured to prevent current generated by the output of the PV waveform generator 150 from flowing in the respective transmission lines and damaging the respective high frequency power sources. BCIn addition, each of the high frequency power supply assemblies 160A, 160B may also include an individual RF filter assembly, such as a second filter assembly 151, configured to block other RF frequencies supplied from the other high frequency power supply assembly and connected in series with the respective high frequency power supply assembly, to further prevent RF currents generated by the outputs of the other high frequency power supplies from flowing through the transmission line and damaging the respective high frequency power supplies. In this configuration, the individual RF filter assembly may include a low pass filter, a notch filter, or a high pass filter that can pass the generated RF waveform and block the RF waveforms generated by the other high frequency power supplies.

[0055] In some embodiments, it may be desirable to utilize two or more sets of PV generators, each configured to separately supply a PV waveform to the bias electrodes 104 and / or edge control electrodes 115. In this example, each of the PV waveform generators 150 (only one is shown in FIG. 3A or 3B ) is fitted with a PV filter assembly (e.g., with a capacitance of C ) adapted to prevent currents generated by the output of the other PV generators from flowing into the respective PV transmission lines 157 and damaging the respective PV generator. BC In addition, each of the PV waveform generators 150 will also include an RF filter assembly, such as second filter assembly 151, configured to block RF frequencies provided by the other PV waveform generators and connected in series with the respective PV waveform generator.

[0056] In some embodiments, as shown in FIGS. 1A-3B , each of the PV waveform generators 150 couples the generated pulsed voltage waveform to a blocking capacitor 153 of the chucking module 116, a second filter assembly 151, and a high voltage line inductance L. HV and the effective capacitance C Eand configured to provide a pulsed voltage waveform signal to the bias electrode 104 and ultimately to the composite load 130. In this case, the system optionally includes a chucking module 116 used for chucking, such as "electrical clamping," of the substrate to the substrate receiving surface of the ESC substrate support. Once the substrate is chucked, the gap can be filled with helium gas (He) to provide good thermal contact between the substrate receiving surface and the non-device side of the substrate to allow temperature control of the substrate by regulating the temperature of the ESC substrate support. When the pulsed voltage generated by the PV waveform generator 150 and the DC chucking voltage generated by the chucking module 116 are combined at the bias electrode 104, an additional voltage offset of the pulsed voltage waveform is equal to the DC chucking voltage generated by the chucking module. The additional voltage offset can be added / subtracted to the offset ΔV shown in FIG. 4A and FIG. 5A-FIG. 5B. The effect of the chucking module 116 on the operation of the PV pulse generator 314 of the PV waveform generator 150 can be neglected by appropriately selecting a large blocking capacitor 153 and blocking resistor 154. The blocking resistor 154 is shown diagrammatically as a resistor located inside the component that connects the chucking module 116 to a point inside the transmission line 131. The main function of the blocking capacitor 153 in the simplified electrical circuit is to protect the PV pulse generator 314 from the DC voltage generated by the direct current power supply 155, so that this DC voltage drops across the blocking capacitor 153 and does not disturb the output of the PV waveform generator. The value of the blocking capacitor 153 is selected so that it blocks only the DC voltage and does not become a load on the pulsed voltage output of the pulsed bias generator. By selecting a sufficiently large capacitance (e.g., 10-80 nF), the blocking capacitor 153 is much larger than any other relevant capacitance in the system, and the voltage drop across it is much larger than the chuck capacitance C E and sheath capacitance C SHIn addition, in some embodiments, the capacitance of blocking capacitor 153 is substantially transparent to the 400 kHz PV waveform signal generated by PV waveform generator 150 in that the capacitance of blocking capacitor 153 is very small compared to the voltage drop across other associated capacitors such as blocking capacitor C BC In some embodiments, the capacitance of the blocking capacitor 153 is substantially greater than the capacitance of the blocking capacitor C BC In one example, the capacitance of the blocking capacitor C BC has a capacitance of about 38 pF, and the capacitance of blocking capacitor 153 is about 40 nF.

[0057] 3A-3B, the purpose of the blocking resistor 154 of the chucking module 116 is to block the voltage of the high frequency pulse bias generator to minimize the current it induces in the DC voltage power supply 155. The blocking resistor 154 is set large enough to effectively minimize the current passing through it. For example, a resistance of 1 MΩ or more is used to make the 400 kHz current from the PV waveform generator 150 to the chucking module 116 negligible. In one example, the blocking resistor has a resistance value of greater than about 500 kΩ. The resulting average induced current of approximately 0.5-1 mA is actually much smaller than the typical limit for the chucking module power supply, which is a DC current of approximately 5 mA. The components of the bias compensation circuit element 116A, including the capacitance 155B, the diode 155C, the resistor 155A, and the blocking resistor 154, together form a current suppression / filtering circuit for the pulse voltage, so that the pulse voltage does not induce a current through the chucking module 116. Blocking resistor 154 is disposed between DC power source 155 and output 350 and / or generator output combining assembly 181 (FIG. 1C). In some embodiments, diode 155C is connected in parallel with blocking resistor 154, oriented with the anode side connected to PV transmission line 157.

[0058] The second filter assembly 151 includes one or more electrical elements configured to prevent current generated by the output of the high frequency power supply 118 from flowing through the PV transmission line 157 and damaging the PV pulse generator 314 of the PV waveform generator 150. As discussed above, the PV transmission line 157 is an assembly that includes the coaxial transmission line 106 and the transmission line 131. In one embodiment, the second filter assembly 151 includes a filter having a capacitance C FC A filter capacitor 151A having an inductance of L connected in parallel with the filter capacitor 151A and disposed in the transmission line 157 between the PV pulse generator 314 and the bias electrode 104. FLIn some configurations, the second filter assembly 151 is disposed between the blocking capacitor 153 of the chucking module 116 and the bias electrode 104. The second filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated from the high frequency power supply 118, thus inhibiting current flow to the PV pulse generator 314. In some embodiments, the capacitance C of the filter capacitor 151A is FC is significantly smaller than the capacitance of the blocking capacitor 153, at most 1 / 10, at most 1 / 100, or at most 1 / 1000. FC is about 51 pF, and the capacitance of blocking capacitor 153 is about 40 nF.

[0059] As discussed above, the second filter assembly 151 is configured to block the RF signal and any associated harmonics from passing through to the PV pulse generator 314. In some embodiments, the RF signal generated by the radio frequency power supply is configured to provide an RF frequency greater than 400 kHz, such as an RF frequency of 1 MHz or greater, 2 MHz or greater, 13.56 MHz or greater, or 40 MHz or greater. In some embodiments, to prevent the RF power provided by the radio frequency power supply 118 from damaging the PV pulse generator 314, the second filter assembly 151 includes a filter capacitor 151A having a capacitance of about 25 pF to 100 pF and a filter inductor 151B having an inductance of about 0.1 to 1 μH. In one example, to prevent the RF power having a frequency of 40 MHz supplied from the high frequency power supply 118 from damaging the PV pulse generator 314, the second filter assembly 151 includes a filter capacitor 151A having a capacitance of about 51 pF and a filter inductor 151B having an inductance of about 311 nH. BCThe capacitance value of filter capacitor 151A of second filter assembly 151 is within 10 times the capacitance value of filter capacitor 151A of second filter assembly 151.

[0060] 3A-3B, the second filter assembly 151 further includes a second filter inductor 151C having an inductance L2 and a second filter capacitor 151E having a capacitance C2 coupled between the transmission line 157 and ground, and a third filter inductor 151D having an inductance L3 and a third filter capacitor 151F having a capacitance C3 also coupled between the transmission line 157 and ground. In some configurations, the inductances of the second filter inductor 151C and the third filter inductor 151D may be about 0.1-1 μH, and the capacitances of the second filter capacitor 151E and the third filter capacitor 151F are about 25 pF-100 pF.

[0061] Pulse Waveform Example As previously mentioned, the novel substrate bias methods provided by the embodiments of the present disclosure allow for maintaining a nearly constant sheath voltage during processing, thus generating a desired IEDF at the surface of the substrate, while also providing the ability to separately control aspects of the plasma formed in the processing volume of the plasma processing chamber by using one or more RF source assemblies. In some embodiments, the novel substrate bias apparatus and methods disclosed herein may be used to form a single-peak (mono-energetic) IEDF at the surface of the substrate during processing. In other embodiments, the novel substrate bias apparatus and methods disclosed herein may be used to form a two-peak (bi-energetic) IEDF at the surface of the substrate during processing, as shown in FIG. 4D. Some configurations of the apparatus disclosed herein, such as that shown in FIG. 1A, may also maximize the area of ​​grounded surfaces inside the plasma processing chamber, thus minimizing power loss to the chamber walls to improve plasma processing efficiency.

[0062] As discussed further below in connection with FIGS. 4A-4C and 5A-5C, a novel substrate biasing method that enables maintaining a nearly constant sheath voltage during plasma processing includes providing a series of pulses and / or bursts of pulses during a plasma processing sequence performed on a substrate during a plasma process performed in a plasma processing chamber. The embodiments of the disclosure provided herein include providing pulses having a desired pulse voltage waveform (PVWF), each of which includes a plurality of distinct phases. As discussed further below, each PV waveform includes at least one of a plurality of phases that is controlled by providing a voltage signal, or possibly a constant current signal, from a PV waveform generator 150. Generally, for purposes of discussion, each pulse of a PV waveform may be segmented into two main regions, including a first region 405 and a second region 406, as shown in FIGS. 5A-5C. Generally, each PV waveform may include a pulse having an amplitude (V out ), offset (e.g. ΔV), pulse period (T P ), and pulse repetition frequency (F P =1 / T P )

[0063] FIG. 4A illustrates a negative pulse bias type PV waveform that may be established at the bias electrode 104 and / or edge control electrode 115 by using a PV waveform generator 150 internal to the PV source assembly. In some embodiments, the PV waveform illustrated in FIG. 4A is established separately at the bias electrode 104 and edge control electrode 115 using a PV waveform generator 150 of the first PV source assembly 196 and a PV waveform generator 150 of the second PV source assembly 197, respectively. FIG. 5A illustrates a negative pulse bias type pulse voltage waveform, where the PV waveform generator 150 is configured to control the generation of a series 550 of multi-phase negative pulse waveforms 401 to establish a PV waveform at the bias electrode 104 or edge control electrode 115. In some embodiments, the multi-phase negative pulse waveform 401 includes a series of repeating periods, with the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval. The multi-phase negative pulse waveform 401 will include positive voltage pulses that are present only during at least a portion of the first time interval, and the pulse voltage waveform is substantially constant through at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a negative voltage source during at least a portion of the second time interval.

[0064] The substrate PV waveform 425 is a series of PV waveforms established at the substrate by PV waveforms formed and established at the bias electrode 104 or edge control electrode 115 by the PV waveform generator 150 as shown in FIG. 4A. The substrate PV waveform 425 is established at the surface of the substrate during processing and includes a sheath collapse and ESC recharge phase 450 (or sheath collapse phase 450 for ease of discussion) that extends between points 420 and 421 of the exemplary substrate PV waveform 425, a sheath formation phase 451 that extends between points 421 and 422, and an ion current phase 452 that extends from point 422 to the start point 420 of the next pulse voltage waveform established in succession. As shown in FIG. 4A-4C, the plasma potential curve 433 shows the local plasma potential during the delivery of the negative pulse waveform 401 established at the bias electrode 104 and / or edge control electrode 115 using one or more PV waveform generators 150.

[0065] In some embodiments, during processing in the process chamber 100, the multi-phase negative pulse waveform 401 is formed when the PV waveform generator 150 supplies and controls the supply of a negative voltage during two of the phases of an established multi-phase negative pulse waveform 401, such as the negative going portions of the PV waveform and / or the portions that are held at a negative voltage level (e.g., the ion current phase). For example, these portions of the negative pulse waveform 401 that contain negative voltages are related by analogy to the sheath formation phase 451 and the ion current phase 452 shown in FIG. 4A for the substrate PV waveform 425. In this case, for the multi-phase negative pulse waveform 401, the supply of negative voltage from the PV waveform generator 150 occurs during the second phase 406, as shown in FIG. 4A, extending from point 411 (i.e., the peak of the multi-phase negative pulse waveform 401) to point 413, which coincides with the start of the sheath collapse phase 450 of the substrate PV waveform. In some embodiments, the PV waveform generator 150 may be configured to generate a constant negative voltage (e.g., V OUT For example, during the ion current phase 452, the ion current (I i) accumulates positive charge on the substrate surface, causing the voltage at the substrate surface to rise over time as seen in the upward and rightward slope of the line between points 422 and 420 (FIG. 4A). The voltage rise at the substrate surface over time causes the sheath voltage to fall and the ion energy to spread. Therefore, to minimize the effects of sheath voltage fall and ion energy spread, the frequency of the PV waveform (1 / T PD T PD is the period of the PV waveform (Figure 5A).

[0066] 5B illustrates a shaped pulse bias type PV waveform, where the PV waveform generator 150 is configured to control the generation of a series 551 of multi-phase shaped pulse waveforms 441 established on the bias electrodes 104 and / or edge control electrodes 115. In some embodiments, the PV waveform generator 150 that forms the multi-phase shaped pulse waveform 441 is configured to use one or more internal switches and a DC power supply to provide a positive voltage during one or more phases of the voltage pulse (e.g., first region 405) and a negative voltage during one or more phases of the voltage pulse (e.g., second region 406).

[0067] In some embodiments, the PV waveform generator 150 is configured to supply to the bias electrode 104 and the edge control electrode 115 a series 552 of multi-phase positive pulse waveforms 431 as shown in FIG. 5C. Each positive pulse phase in the positive pulse waveform 431 may include multiple phases, such as a sheath collapse phase, an ESC recharge phase, a sheath formation phase, and an ion current phase. In this example, the first region 405 generally includes a sheath collapse phase and an ESC recharge phase. The second region 406 generally includes a sheath formation phase and an ion current phase. In some embodiments, the multi-phase positive pulse waveform 431 includes a series of repeating periods, with the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval. The multi-phase positive pulse waveform 431 will include a positive voltage pulse that is present only during at least a portion of the first time interval and is substantially constant during at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a positive voltage source during at least a portion of the first time interval.

[0068] The various pulsed voltage waveforms 401, 441, and 431 shown in Figures 5A, 5B, and 5C, respectively, represent pulsed voltage waveforms supplied to the input of chucking module 116 and therefore may differ from the pulsed voltage waveforms established at bias electrode 104 and edge control electrode 115 shown in Figure 4A. The DC offset of ΔV in each PV waveform depends on various characteristics of the configuration of PV waveform generator 150 used to establish the PV waveform.

[0069] In the process illustrated in FIG. 4B, a series of pulse voltage waveform bursts 462 are established on the bias electrode 104 and / or edge control electrode 115 to be established on the substrate surface. In the example illustrated in FIG. 4B, a number of pulses 461 in each burst 462 include a series of negative pulse waveforms 401 established on the bias electrode 104 and / or edge control electrode 115. In this example, each of the bursts 462 includes a PV waveform with a consistent pulse voltage shape (e.g., a constant voltage amplitude is provided during a portion of each PV waveform 401) and a burst delivery period T that is consistent between one burst 462 and another burst. ON and a certain period of burst rest T OFF The burst rest period T OFF is the burst supply period T ON In this example, the length of time that multiple pulses are delivered during a burst (i.e., burst delivery period T ON ) and the duration of the burst period (i.e., T BD =T ON +T OFF ) is also constant. It will be appreciated that in other processing methods, the plurality of pulses 461 may include a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, or combinations thereof. As shown in FIG. 4B, the burst rest period T OFF During this time, the bias electrode potential curve 436 is primarily controlled by the chucking voltage applied and controlled by the chucking module 116, and therefore may be at a different voltage level than the plasma potential.

[0070] In the process shown in FIG. 4C, multiple bursts of differently configured pulses, such as bursts 462 and 463, are established on the bias electrode 104 and / or edge control electrode 115 to establish at the substrate surface. FIG. 4D shows an IEDF graph of the effect of performing the process shown in FIG. 4C during plasma processing. By performing the process shown in FIG. 4C, it is believed that by controlling the delivery of multiple differently configured bursts within a repetition period, it is possible to control the distribution of ion energy to form an IEDF that includes two or more discrete IEDF peaks, such as the two discrete IEDF peaks shown in FIG. 4D. In contrast, in conventional plasma processes utilizing RF biasing, the IEDF will generally have two peaks, which are formed at low and high energies and some population of ions with energies between the two peaks, and will not form the desired discrete IEDF peaks. An example of a conventionally formed IEDF curve is shown in FIG. 1B of U.S. Pat. No. 10,555,412, which is incorporated herein by reference in its entirety. In these conventional biasing schemes, the applied RF voltage (having a waveform such as that shown in FIG. 6A) modulates the cathode sheath throughout the RF cycle, thus excessively varying the sheath voltage drop at all times resulting in a dual-peak IEDF. As discussed above, the range of ion energies between the two IEDF peaks formed during conventional processing (i.e., the formation of non-discrete IEDF peaks) affects the profile of etched feature walls formed within the range of the substrate surface during plasma processing.

[0071] In some embodiments of the method illustrated in FIG. 4C, the differently configured bursts may be differently configured with different lengths of repetition period (T Train) from the multiple pulses 461 having burst 462. Each of burst 462 and burst 463 includes a plurality of pulses 461 that may include a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, or a combination thereof. In some embodiments, the differentially configured plurality of bursts includes at least two differentially configured bursts such that the characteristics of the multiple pulses 461 formed between at least two of the bursts in the differentially configured plurality of bursts are different characteristics. In one example, as shown in FIG. 4C, the characteristics of the multiple pulses 461 having burst 462 include a different pulse voltage amplitude (e.g., a different V OUT ), thus forming two IEDF peaks with different peak heights (FIG. 4D). In some embodiments, the pulse 461 has a pulse voltage amplitude (V) of about 1 kilovolt (kV) to about 10 kV. OUT In some embodiments, the characteristics of the multiple pulses 461 that differ between at least two of the bursts in the repetition period include different individual PV waveform periods, different pulse voltage amplitudes, different shapes (e.g., voltage amplitudes, slopes (dV / dt)), or other PV waveform characteristics of at least a portion of the PV waveform within the first region 405 and the second region 406. Each of the bursts 462 and 463 has a burst delivery period T ON and the burst rest period T OFF Furthermore, the burst period T BD and the burst duty cycle (e.g., T ON / T BD ) is the burst supply period T ON and burst period T BD In some embodiments, the burst supply period T ON is about 50 μs to about 50 milliseconds (ms), such as about 200 μs to about 5 milliseconds, and the duty cycle of the burst is about 5% to 100%, such as about 50% to about 95%. ONThe pulse duration is approximately 800 μs and the duty cycle of the bursts is approximately 80% for both bursts 462 and 463. More specifically, FIG. 4C includes an example of multiple bursts (each containing multiple waveform cycles) of an input pulse voltage waveform originating from the generator end of a generator output coupling assembly 181 that terminates at the output of the PV waveform generator 150 that feeds the bias electrode 104 of the substrate support assembly 136. The differently configured bursts have differently configured offsets (ΔV), burst periods (T BD ), burst frequency (fB=1 / T BD ), and / or the duty cycle of the burst (Duty=T on / T BD ) Thus, by varying the characteristics of the multiple pulses 461 during two or more differently configured bursts, two or more discrete IEDF peaks can be created to adjust or vary the plasma processing results achieved on a substrate during processing.

[0072] 5D illustrates a series of PV waveforms formed at the substrate during processing by establishing a positive pulse waveform 431 (not shown) or a negative pulse waveform 401 (not shown) on the bias electrodes 104 and / or edge control electrodes 115 using one or more PV waveform generators 150. The PV waveforms formed at the substrate include a substrate PV waveform 425 formed by establishing a negative pulse waveform 401, or a substrate PV waveform 531 formed by establishing a positive pulse waveform 431. In some embodiments, the negative pulse waveform 401 is applied for a period of time T N1 and time T N23B, the negative pulse waveform 401 is formed by establishing a negative voltage on the bias electrode 104 and / or the edge control electrode 115 during a period T t . In some embodiments, the negative voltage delivered to the output 350 of the PV waveform generator 150 is delivered to the bias electrode 104 and / or the edge control electrode 115 and is substantially constant throughout at least a portion of the second region 406 of the negative pulse waveform 401. In one example, the negative voltage delivered to the output 350 of the PV waveform generator 150 is substantially constant throughout the entire second region 406, except for any switching associated voltage oscillations or transitions at the beginning and / or end of the second region 406. With reference to FIG. N1 and time T N2 A negative voltage is provided by keeping switch S1 closed and switch S2 open during T N2 From T N1 During the other time periods up to 1000 s, switch S1 will be kept open and switch S2 will be kept closed.

[0073] In some embodiments, the positive pulse waveform 431 is P1 and time T P2 3A, by establishing a positive voltage on the bias electrode 104 and / or the edge control electrode 115 during a time T P1 and time T P2 A positive voltage is provided by keeping switch S1 closed and switch S2 open during T P2 From T P1 During other periods up to, switch S1 will be held open and switch S2 will be held closed. In some embodiments, the positive voltage supplied to output 350 of PV waveform generator 150 is supplied to bias electrode 104 and / or edge control electrode 115 and is substantially constant throughout at least a portion of the first region 405 of positive pulse waveform 431.

[0074] 5D, the process of establishing a negative pulse waveform 401 or a positive pulse waveform 431 on the bias electrode 104 and / or the edge control electrode 115 will form a substrate PV waveform 425 or a substrate PV waveform 531, respectively, that may have different waveform characteristics. In one example, when using a negative pulsing process, a longer period of the waveform cycle where no sheath (i.e., the sheath formed during the ESC recharge phase 560) is present (T NNSH ), whereas during the positive pulsing process, there is a shorter period of the waveform cycle where there is no sheath (i.e., the sheath formed during the ESC recharge phase 570) (T PNSH ) during the negative PV waveform. NNSH can be about 175 nanoseconds (ns), whereas the period T during which the sheath is absent during a positive PV waveform PNSH may be about 80 nanoseconds.

[0075] In any of the processes of establishing a pulsed voltage waveform, such as a process of establishing a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, on the bias electrode 104 and / or the edge control electrode 115, it may be possible to keep the sheath voltage approximately constant during the plasma process for a large percentage of the substrate processing time (e.g., 85%-90%). The waveforms shown in Figures 4A-5D are intended only to show simplified schematics of pulsed voltage waveforms that may be used with one of the methods that may be used during plasma processing of a substrate described herein. The actual waveforms generated by the PV waveform generator 150 may be much more complex and may contain multiple fine-scale features (e.g., high frequency oscillations due to the presence of inductive elements) that are not shown in Figures 3A-3B. However, these fine-scale features are not necessary to understand the underlying physical phenomena that determine the overall shape of the actual pulsed voltage waveforms generated by the pulsed voltage biasing and control methods proposed herein.

[0076] Pulse voltage waveform phase In general, a pulse voltage waveform, such as a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, that is established has a period T PD In one example, the pulse length is 1.5 s, which is a periodic sequence of short pulses that repeats with a period of T PD is about 1 μs to 5 μs, such as about 2.5 μs. The waveform within each period (repetition period) includes:

[0077] (1) Sheath Capacitor C sh (FIGS. 3A-3B) discharges, and the substrate potential reaches the level of the local plasma potential (e.g., plasma potential curve 433 in FIG. 4A). The sheath collapse phase causes the chuck capacitor C E This allows for rapid recharging.

[0078] (2) A charge of the opposite polarity to the total charge stored on the substrate surface during the ion current phase (4) after (2) is suddenly injected or stored on the chuck capacitor C during the ESC recharge phase. E During the ESC recharge phase, the plasma current is also conducted by the electrons, i.e., the electrons reach the substrate without the cathode sheath and thus the capacitor C E Charging the surface builds up a charge.

[0079] (3) Jump to a negative voltage to discharge stray capacitors in the processing chamber. Re-form the sheath during the sheath formation phase to lower the sheath voltage (V SH Set the value of sheath formation (C sh The onset of charge (charge) can be clearly identified as the point at which the substrate potential begins to drop below the local plasma potential.

[0080] (4) A generally long (e.g., longer than 50%, e.g., about 80-90% of the PV waveform cycle period, T) ion current phase in which positive charge accumulates on the substrate surface, the sheath capacitor and chuck capacitor gradually discharge, the sheath voltage slowly drops, and the substrate potential approaches zero. This results in a voltage droop in the substrate voltage waveforms 425 (FIG. 4A) and 531 (FIG. 5D). It is this sheath voltage droop that requires a pulse waveform to transition to the next cycle as described in (1)-(3) above.

[0081] As discussed above, in some embodiments, the process chamber 100 will include at least one or more radio frequency power sources 118 and associated first filter assembly 162, and one or more PV generators 314 and associated second filter assembly 151, which together are configured to provide a desired waveform to one or more electrodes disposed within the substrate support assembly 136. The memory of the controller 126 has stored therein software instructions configured to generate RF waveforms configured to establish, maintain, and control one or more aspects of a plasma formed within the process chamber. The one or more aspects of the plasma that are controlled may include, but are not limited to, the plasma density, plasma chemistry, and ion energy of the plasma formed in the process volume 129.

[0082] FIG. 6A shows the frequency (i.e., 1 / T RF 6 illustrates a typical sinusoidal RF waveform 601 having a frequency of 100 Hz to 100 Hz. In general, one or more aspects of the plasma will select a desired RF frequency and amount of RF power, and possibly a duty cycle (i.e., the time that the sinusoidal RF signal is “on” (T RFON ) versus the time that the sinusoidal RF signal is "off" (T RFOFFThe ratio of the RF power to the RF power of the selected RF frequency may also be controlled by selecting a desired RF frequency. Selection of the desired RF frequency is typically performed by selecting a radio frequency power source (e.g., a 2 MHz, 13.56 MHz, or 40 MHz radio frequency power source) configured to provide various amounts of RF power at one or more frequencies within a selected narrow RF frequency range.

[0083] 6B illustrates a pulsed RF waveform 602 that may be provided by the RF power supply 118 during a plasma process. The pulsed RF waveform 602 is formed with a period T of an RF pulse within an RF pulsed sequence. RFP and the “on” time (i.e., T RFON ) and the "off" time when no power is supplied (i.e., T RFOFF )

[0084] 6C illustrates a method for synchronizing a pulsed RF waveform 602 provided by the radio frequency power supply 118 with a series of bursts 612, 622, or 632 provided to the bias electrode 104 and / or edge control electrode 115 using one or more PV waveform generators 150 and controller 126. While each burst 615, 625, 635 in the series of bursts 612, 622, 632 includes a single burst of a consistent type (i.e., pulse 461 has the same pulse characteristics) as shown in FIG. 6C, it is contemplated that each burst in the series of bursts generated by one or more PV waveform generators 150 may include differently configured bursts, such as bursts 462, 463 of FIG. 4C. Similarly, in some embodiments, the RF pulses in the RF waveform 602 may include a series of differently configured RF pulses. The bursts 615, 625 or 635 each include a plurality of pulses 461, which may include a negative pulse waveform 401, a shaped pulse waveform 441 or a positive pulse waveform 431, or a combination thereof, which may be established in either or both of the bias electrode 104 and the edge control electrode 115.

[0085] In one example, during processing, a series of bursts 612 including a plurality of bursts 615 are delivered to the bias electrode 104 and / or edge control electrode 115 and synchronized with the delivery of the pulsed RF waveform 602. In this example, the burst delivery period, burst pause period, and burst period of each of the plurality of bursts 615 are equal to or longer than the RF pulse delivery period T of the RF pulse in the pulsed RF waveform 602, respectively. RFON , RF pulse pause period T RFOFF , and the RF pulse period T RFP is equivalent to.

[0086] In another example, during processing, a series of bursts 622 including multiple bursts 625 are delivered to the bias electrode 104 and / or edge control electrode 115 and synchronized with the delivery of the pulsed RF waveform 602. In this example, the burst delivery period, burst rest period, and burst period of each of the multiple bursts 625 are equal to or longer than the RF pulse delivery period T of the RF pulse in the pulsed RF waveform 602, respectively. RFON , RF pulse pause period T RFOFF , and the RF pulse period T RFP However, in this example, a delay period T, also referred to herein as a positive delay period, is added such that each burst 625 begins some time after at least a portion of each of the RF pulses in the pulsed RF waveform 602 is delivered. DE Additionally, or alternatively, it may be desirable to delay the delivery of the RF pulse relative to the delivery of burst 625 (i.e., a negative delay period) such that the RF pulse is delivered after at least a portion of burst 625 has been delivered.

[0087] In another example, during processing, a series of bursts 632 including multiple bursts 635 are delivered to the bias electrode 104 and / or edge control electrode 115 and synchronized with the delivery of the pulsed RF waveform 602. In this example, each of the multiple bursts 635 has the same burst period as the RF pulses in the pulsed RF waveform 602. However, in this example, the burst delivery duration and burst pause duration are different from the RF pulses in the pulsed RF waveform 602. As shown in FIG. 6C, the burst delivery duration of each burst 635 is equal to or longer than the RF pulse delivery duration T RFON T than period DS In this case, the duty cycle of the delivery of the burst 635 and the duty cycle of the delivery of the pulsed RF waveform 602 are different.

[0088] Although the series of bursts 612, 622, 632 shown in FIG. 6C each include a fixed burst delivery duration and duty cycle, it is contemplated that the burst delivery duration and / or duty cycle in the series of bursts may vary over time. Also, the series of bursts 622 shown in FIG. 6C each include a fixed delay period T DE 6C includes a fixed burst delivery period and a fixed delay period, it is contemplated that the burst delivery period in the series of bursts may vary over time and / or it may be desirable to delay the delivery of the RF pulse relative to the delivery of burst 625.

[0089] In another example, as shown in FIG. 6D, during processing, a series of bursts 642 including a plurality of bursts 645 are delivered to the bias electrode 104 and / or edge control electrode 115 and synchronized with the delivery of the pulsed RF waveform 602. In this example, the burst delivery period, burst rest period, and burst period of each of the plurality of bursts 645 are each equal to or longer than the RF pulse delivery period T of the RF pulse in the pulsed RF waveform 602. RFON , and the RF pulse pause period T RFOFFIn this example, the start delay period T is set so that each burst 645 begins some time after at least a portion of each of the RF pulses in the pulsed RF waveform 602 is delivered. DE is given, and the RF pulse period T RFP The end delay period T ED In this example, the duty cycle of each burst 645 is less than the RF pulse.

[0090] In another example, as shown in FIG. 6E, during processing, a series of bursts 652 including multiple bursts 655 and 656 are provided to the bias electrode 104 and / or edge control electrode 115 and are synchronized with the provision of a multi-level pulsed RF waveform 603. The multi-level pulsed RF waveform 603 includes multiple RF pulse power levels 604 and 605 formed by providing a sinusoidal RF waveform 601 at different power levels using a high frequency power source. In this example, each of the multiple bursts 655 and 656 is synchronized with a change in the RF pulse power levels 604 and 605. Each of the multiple bursts 655 and 656 includes multiple negative pulse waveforms 401 that are provided at different voltage levels as indicated by the difference in the negative level of each of the voltage level peaks applied for each of the bursts 655 and 656. In some embodiments, the transition between the bursts 655 and 656 and / or the transition between the RF pulse power levels 604 and 605 are synchronized with a burst rest period T, as shown in FIG. 6E. OFF or RF pulse rest period T RFOFF are not separated by time.

[0091] FIG. 6F includes the series of bursts 652 and the multi-level pulsed RF waveform 603 shown in FIG. 6E and illustrates a schematic of a TTL signal waveform used to synchronize the delivery of the series of bursts 652 and the multi-level pulsed RF waveform 603. In some embodiments, the TTL signal waveform is provided by the controller 126 to each PV waveform generator 150 and the radio frequency power supply 118 such that the delivery of the series of bursts 652 and the multi-level pulsed RF waveform 603 may be synchronized. In other embodiments, the TTL signal waveform is provided by the master radio frequency power supply 118 to each PV waveform generator 150 such that the delivery of the series of bursts 652 and the multi-level pulsed RF waveform 603 provided by the master radio frequency power supply 118 may be synchronized. The TTL signal waveform may include a multi-level pulse including one or more signal characteristics that each PV waveform generator 150 and / or radio frequency power supply 118 uses to determine the desired PV waveform characteristics or RF signal waveform characteristics to deliver. In one example, the amplitudes (e.g., voltage levels) of the signal waveforms at various times during the processing sequence are used by each PV waveform generator 150 to determine the desired PV waveform output voltage levels and by the radio frequency power supplies 118 to determine the desired RF power levels to supply.

[0092] In another example, as shown in FIG. 6G, during processing, a series of bursts 662 including multiple bursts 665 and 667 are delivered to the bias electrode 104 and / or edge control electrode 115 and synchronized with the delivery of a multi-level pulsed RF waveform 606. The multi-level pulsed RF waveform 606 includes multiple RF pulse power levels 607 and 608 formed by delivering a sinusoidal RF waveform 601 at different power levels using a radio frequency power source. The multi-level pulsed RF waveform 606 is provided with an RF pulse pause period T indicated by an RF pause time 609. RFOFF , which is between the transition from the first power level 607 to the second power level 608. In some embodiments, the RF pulse pause period T RFOFFThe time of each of the plurality of bursts 665 and 667 is at the respective transition between the RF pulse power levels 607 and 608. The transition between each of the plurality of bursts 665 and 667 is synchronized with the change in the RF pulse power levels 607 and 608. The plurality of bursts 665 and 667 each include a plurality of negative pulse waveforms 401 that are provided at different voltage levels as indicated by the difference in the negative level of each of the peaks for each of the bursts 665 and 667. In some embodiments, the transition from burst 667 to burst 665 occurs at a burst rest period T OFF The transition from burst 665 to burst 667 occurs during the burst quiescence period T OFF However, in some embodiments, the transition from burst 665 to burst 667 is not separated by a burst pause period T OFF The transition from burst 667 to burst 665 occurs during the burst quiescence period T OFF The transitions from burst 665 to burst 667 and from burst 667 to burst 665 are not separated by a burst rest period T OFF may be separated by a time.

[0093] 6G also illustrates a TTL signal waveform that may be used to help synchronize the delivery of the series of bursts 662 and the multi-level pulsed RF waveform 606. As also discussed above, the TTL signal waveform is provided by the controller 126 to each PV waveform generator 150 and the radio frequency power supply 118, or provided from the master radio frequency power supply 118 to each PV waveform generator 150, such that the delivery of the series of bursts 662 and the multi-level pulsed RF waveform 606 may be synchronized. As shown in FIG. 6G, the amplitude of the signal waveform at various times during the processing sequence is used by each PV waveform generator 150 to determine the voltage level of the desired PV waveform output, and by the radio frequency power supply 118 to determine the desired RF power level. In some configurations, information provided at one or more of the levels of the TTL signal waveform, such as the LS2 level in FIG. 6G, is used to determine a desired duty cycle, number of pulses in a burst and / or pulse amplitude for one or more of bursts 665 and 667, such as burst 667, and / or the duty cycle and / or RF pulse amplitude of RF waveform 606 are determined from the characteristics of the TTL signal waveform.

[0094] Figure 6H shows an alternative version of the pulse sequence shown in Figure 6G. The pulse configuration shown in Figure 6H is referred to herein as an L-to-H (LH) PV pulse sequence, as opposed to the H-to-L (HL) PV pulse sequence shown in Figure 6G. As shown in Figure 6H, bursts 665 and 667 of the series of bursts 662 and RF pulse power levels 607 and 608 of the multi-level pulsed RF waveform 606 are arranged sequentially at separate times. In this configuration, bursts 665 and 667 and RF pulse power levels 607 and 608 are reordered in time such that burst 667 precedes the delivery of burst 665, and RF pulse power level 607 precedes the delivery of RF pulse power level 608.

[0095] In some embodiments, a series of bursts, such as series of bursts 612, 622 or 632, are synchronized and delivered separately to the bias electrode 104 and the edge control electrode 115 using one or more PV waveform generators 150 and controller 126. Additionally, as discussed above, the pulsed RF waveform 602 may be synchronized with the series of bursts 612, 622 or 632 that may be delivered to the bias electrode 104 and the edge control electrode 115 using one or more PV waveform generators 150 and controller 126. In one example, a series of bursts 612 is delivered from a PV waveform generator 150 of a first PV source assembly 196 to the bias electrode 104, and a series of bursts 612 is delivered from a PV waveform generator 150 of a second PV source assembly 197 to the edge control electrode 115, which are synchronized with the delivery of the pulsed RF waveform 602.

[0096] In some embodiments, the burst and / or series of bursts supplied to the bias electrode 104 and the burst and / or series of bursts supplied to the edge control electrode have one or more different characteristics. In one example, the pulse voltage waveform of a burst supplied to the bias electrode 104 is different from the pulse voltage waveform of a burst simultaneously supplied to the edge control electrode 115. In another example, a burst in the series of bursts supplied to the bias electrode 104 (e.g., burst 615) has a different burst supply duration than a burst in the series of bursts supplied to the edge control electrode 115 (e.g., burst 635). In another example, a burst in the series of bursts supplied to the bias electrode 104 is offset in time from a burst in the series of bursts supplied to the edge control electrode 115. In this example, burst 615 of the series of bursts 612 is supplied to the bias electrode 104 and burst 625 of the series of bursts 622 is supplied to the edge control electrode 115, and thus the timing of the supply of bursts to the bias electrode 104, the edge control electrode and the pulsed RF waveform 602 can be adjusted separately from each other.

[0097] In some embodiments, the PV waveforms supplied to the bias electrode 104 and the edge control electrode 115 may be synchronized and identical in shape but with different amplitudes of the individual pulses supplied to each electrode. Different PV waveform amplitudes applied to the bias electrode 104 and the edge control electrode 115 may be used to control the "edge slope" of the etched features formed on the substrate. In one example, the PV waveforms in a first burst supplied to the bias electrode 104 and the edge control electrode 115 are synchronized and identical in shape, and the PV waveform applied to the edge control electrode 115 has a higher peak-to-peak voltage than the PV waveform applied to the bias electrode 104. In another example, the PV waveforms in a second burst supplied to the bias electrode 104 and the edge control electrode 115 are synchronized and identical in shape, and the PV waveform applied to the edge control electrode 115 has a lower peak-to-peak voltage than the PV waveform applied to the bias electrode 104.

[0098] In some embodiments, software instructions stored in the storage device of the controller 126 are configured to generate a pulsed voltage (PV) waveform and / or bursts of pulsed voltage (PV) waveforms that are used to establish a substantially constant sheath voltage to generate a desired IEDF at the surface of the substrate during plasma processing in the processing chamber. Controlling the pulsed voltage (PV) waveform and / or bursts of pulsed voltage (PV) waveforms can provide precise control over the shape of the IEDF and the number of peaks that comprise the IEDF, allowing for better control over the profile of features formed at the surface of the substrate. Controlling the pulsed voltage (PV) waveform and / or bursts of pulsed voltage (PV) waveforms generally involves providing a desired voltage signal during one or more of the pulsed voltage (PV) waveform phases and then a waveform period T PDThe software stored in the memory of the controller 126 would also include instructions used to control the various hardware and electrical components within the process chamber 100 and the processing system in which the process chamber 100 is disposed to perform various process tasks and various process sequences necessary to synchronize the delivery of RF waveforms, pulsed voltage (PV) waveforms and / or bursts of pulsed voltage (PV) waveforms to one or more electrodes within the process chamber 100.

[0099] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the invention, the scope of which is determined by the following claims.

Claims

1. 1. A method for processing a substrate in a plasma processing chamber, comprising: providing a high frequency signal to a support base disposed within a substrate support assembly using a high frequency power source, the high frequency power source being electrically coupled to the support base through a pulse voltage filter assembly; establishing a first pulsed voltage waveform at a bias electrode disposed within the substrate support assembly using a first pulsed voltage waveform generator, the first pulsed voltage waveform generator being electrically coupled to the bias electrode through a first high frequency filter assembly; A method comprising: the bias electrode is disposed between the support base and a substrate support surface of the substrate support assembly; a first dielectric layer disposed between the support base and the bias electrode; a second dielectric layer disposed between the bias electrode and the substrate support surface; method.

2. the first pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a negative voltage source for at least a portion of the second time interval; the pulsed voltage waveform is substantially constant during at least a portion of the second time interval; The method of claim 1.

3. The method of claim 2 , wherein the second time interval occupies at least 50% of each cycle of the series of repeating periods.

4. the first pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a positive voltage source for at least a portion of a first time interval; the pulsed voltage waveform is substantially constant during at least a portion of the second time interval; The method of claim 1.

5. the first pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the voltage waveform generator is connected to a positive voltage source for at least a portion of the first time interval; the second time interval being longer than the first time interval; The method of claim 1.

6. The method of claim 5 , wherein the first time interval occupies less than about 15% of each cycle of the series of repeating periods.

7. The method of claim 1 , wherein the second dielectric layer comprises a material having a finite resistivity.

8. The method of claim 1 , wherein the second dielectric layer has a thickness of about 0.1 mm to about 2 mm.

9. a chucking module coupled to a bias electrode through the first radio frequency filter assembly; a first generator output coupling assembly that couples an output of the first pulsed voltage waveform generator to the chucking module, the first generator output coupling assembly being coupled to a blocking capacitor disposed between the first generator output coupling assembly and the bias electrode; 10. The method of claim 1, further comprising chucking the substrate to the substrate support assembly by establishing a voltage drop between the substrate and the bias electrode using a biasing electrode.

10. (a) establishing a first burst of a pulsed voltage waveform on the bias electrode for a first time period, the first burst of a pulsed voltage waveform comprising the first pulsed voltage waveform; (b) interrupting the establishing of the first burst of a pulsed voltage waveform for a second period of time; Repeating (a) and (b) at least once. The method of claim 1 further comprising:

11. (c) establishing a second burst of a pulsed voltage waveform at the bias electrode for a third time period, the second burst of a pulsed voltage waveform comprising a second pulsed voltage waveform different from the first pulsed voltage waveform; (d) interrupting the establishing of the second burst of a pulsed voltage waveform for a fourth period of time; Repeating (c) and (d) at least once. The method of claim 10 further comprising:

12. 12. The method of claim 11, further comprising sequentially repeating (a), (b), (c) and (d) at least one time.

13. the first pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a negative voltage source for at least a portion of the second time interval; the pulsed voltage waveform is substantially constant during at least a portion of the second time interval; The method of claim 10.

14. the first pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a positive voltage source for at least a portion of a first time interval; the pulsed voltage waveform is substantially constant during at least a portion of the second time interval; The method of claim 10.

15. 1. A method for processing a substrate in a plasma processing chamber, comprising: providing a high frequency signal to a support base disposed within a substrate support assembly using a high frequency power source, the high frequency power source being electrically coupled to the support base through a pulse voltage filter assembly; establishing a first pulsed voltage waveform at a bias electrode disposed within the substrate support assembly using a first pulsed voltage waveform generator, the first pulsed voltage waveform generator being electrically coupled to the bias electrode through a first high frequency filter assembly; establishing a second pulsed voltage waveform at an edge control electrode disposed within the substrate support assembly using a second pulsed voltage waveform generator, the second pulsed voltage waveform generator being electrically coupled to the edge control electrode through a second high frequency filter assembly; and establishing a second pulsed voltage waveform at a bias electrode. A method comprising: the bias electrode is disposed between the support base and a substrate support surface of the substrate support assembly; a first dielectric layer disposed between the support base and the bias electrode; a second dielectric layer disposed between the bias electrode and the substrate support surface; the edge control electrode surrounds at least a portion of the bias electrode; method.

16. the first pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a negative voltage source for at least a portion of the second time interval; the pulsed voltage waveform is substantially constant throughout at least a portion of the second time interval; The method of claim 15.

17. the second pulse voltage waveform includes a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a negative voltage source for at least a portion of the second time interval; the pulsed voltage waveform is substantially constant during at least a portion of the second time interval; 17. The method of claim 16.

18. (a) establishing a first burst of a pulsed voltage waveform on the bias electrode for a first time period, the pulsed voltage waveform of the first burst including the first pulsed voltage waveform; (b) interrupting the establishing of the first burst of a pulsed voltage waveform for a second period of time; Repeating (a) and (b) at least once. The method of claim 15 further comprising:

19. the first pulsed voltage waveform and the second pulsed voltage waveform each include a series of repeating periods; the waveform in each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval; a positive voltage pulse is present during only at least a portion of the first time interval; an output of the first pulsed voltage waveform generator is connected to a negative voltage source for at least a portion of the second time interval; the pulsed voltage waveform is substantially constant during at least a portion of the second time interval; 20. The method of claim 18.

20. (c) establishing a second burst of a pulsed voltage waveform at the bias electrode for a third time period, the second burst of a pulsed voltage waveform comprising a second pulsed voltage waveform different from the first pulsed voltage waveform; (d) interrupting the establishing of the second burst of a pulsed voltage waveform for a fourth period of time; Repeating (c) and (d) at least once.

20. The method of claim 18, further comprising:

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