Semiconductor device

Abstract

To provide a semiconductor device including an oxide semiconductor, which has a structure capable of preventing deterioration in electrical characteristics, the deterioration becoming more significant with miniaturization.SOLUTION: There is provided a semiconductor device which includes: an oxide semiconductor layer including a plurality of channel formation regions arranged in a channel width direction and parallel to each other; and a gate electrode layer overlapping with a side surface and a top surface of each channel formation region through a gate insulating layer. With this configuration, an electric field is applied to each channel formation region from a side surface direction and a top surface direction, so that a threshold voltage of a transistor can be favorably controlled and an S value thereof can be improved. Further, with the plurality of channel formation regions, an effective channel width of the transistor can be increased, so that a decrease in on-state current can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the disclosed invention relates to a semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general term, including semiconductor elements such as transistors, power devices, and In addition to integrated circuits, power supply circuits, or power conversion circuits having the above, electro-optical devices, semiconductor circuits, electronic The device falls within the category of or includes semiconductor equipment. [Background technology]

[0003] A transistor using a semiconductor thin film formed on a substrate having an insulating surface as an active layer is Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) It is widely used.

[0004] Generally, miniaturization of transistors is an essential technology for forming highly integrated circuits. Thin film transistors are so-called planar transistors, which are formed by stacking a semiconductor film, an insulating film, and an electrode on a flat surface. The current trend is to use a transistor with a MOSFET that can be integrated more highly. In addition, a transistor having a fin structure using a polysilicon film for an active layer is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-206306 A Summary of the Invention [Problem to be solved by the invention]

[0006] To achieve high-speed response and high-speed operation of semiconductor devices, the on-characteristics of miniaturized transistors (e.g. For example, improvements in on-state current and field effect mobility are desirable. As the device becomes thinner, the channel width also shrinks, raising concerns about a decrease in on-current. When transistors are miniaturized, the threshold voltage shifts negatively and the S value (subthreshold It is known that this can cause deterioration and variation in the electrical characteristics of transistors, such as degradation of the capacitance (value). do.

[0007] Therefore, one embodiment of the present invention is a structure capable of suppressing deterioration of electrical characteristics that becomes significant with miniaturization. Another object of the present invention is to provide a semiconductor device having a low power consumption. Another object of the present invention is to provide a semiconductor device having high reliability. This is one of the targets.

[0008] Note that the description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. Problems other than these are not necessarily solved. These issues will become clear from the description in the specification, etc., and other issues will not be identified from the description in the specification, etc. It is possible to extract [Means for solving the problem]

[0009] The semiconductor device according to one aspect of the present invention includes at least first and second semiconductor layers arranged in parallel to each other in a channel width direction. The oxide semiconductor layer includes a first channel formation region and a second channel formation region. , and a gate insulating layer is formed between the gate electrodes so as to overlap the side and upper surfaces of the channel forming regions. With this structure, the electrode layer is provided for each channel forming region. Since an electric field is applied from the side and top directions, the threshold voltage of the transistor can be controlled satisfactorily. In addition, the S value can be improved by controlling the temperature at which the semiconductor device is formed. This increases the effective channel width of the transistor, which reduces the on-state current. The decrease can be suppressed.

[0010] In addition, in the semiconductor device of one embodiment of the present invention, an oxide semiconductor layer and an insulating layer overlapping with the oxide semiconductor layer are At least one metal element among the metal elements constituting the oxide semiconductor layer is formed between the insulating layer and the oxide semiconductor layer. When the oxide semiconductor layer is in contact with the insulating layer, the oxide semiconductor A trap level may be formed at the interface between the oxide semiconductor layer and the insulating layer. By using the above-mentioned structure having an oxide layer on the semiconductor substrate, the formation of the trap level is suppressed. Therefore, deterioration of the electrical characteristics of the transistor can be suppressed.

[0011] More specifically, for example, the following configuration can be adopted.

[0012] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer including at least first and second channel formation regions. A first oxide layer is provided in contact with a lower surface of the oxide semiconductor layer, and a second oxide layer is provided on an upper surface of the oxide semiconductor layer. a source electrode layer electrically connected to the second oxide layer and the oxide semiconductor layer; and a drain electrode layer, and a first and a second channel formation region provided over the oxide semiconductor layer. a gate electrode layer overlapping each of the side surfaces and the top surface of the oxide semiconductor layer and a gate electrode layer and a gate insulating layer provided on the gate insulating layer.

[0013] Another embodiment of the present invention is a semiconductor device including at least first and second channel formation regions. a first oxide layer provided in contact with the lower surface of the oxide semiconductor layer; a second oxide layer provided in contact with the upper surface; and a source electrode electrically connected to the oxide semiconductor layer. An electrode layer and a drain electrode layer, and a first and a second channel type a first gate electrode layer overlapping each side surface and an upper surface of the oxide semiconductor layer; a second gate electrode layer provided on the first channel formation region and overlapping the first and second channel formation regions, respectively; a first gate insulating layer provided between the second oxide layer and the first gate electrode layer; and a second gate insulating layer provided between the oxide layer and the second gate electrode layer. It is a semiconductor device.

[0014] In the above semiconductor device, the first oxide layer and the second oxide layer are each an oxide semiconductor. The metal layer contains at least one metal element as a constituent element.

[0015] In the above semiconductor device, the second oxide layer is formed on a side surface of the first channel forming region and a top surface of the second channel formation region and a side surface and a top surface of the second channel formation region on the oxide semiconductor layer; and in a region between the first channel formation region and the second channel formation region, It may be in contact with the first oxide layer.

[0016] Alternatively, in the above semiconductor device, the first oxide layer, the oxide semiconductor layer, and the second oxide The material layers may have coincident ends in cross-sectional shape.

[0017] Alternatively, in the above semiconductor device, the source electrode layer and the drain electrode layer are formed of a first oxide The insulating layer may be provided in contact with a side surface of the insulating film layer and a side surface and a top surface of the oxide semiconductor layer. Effect of the Invention

[0018] According to one embodiment of the present invention, there is provided a semiconductor device having a structure capable of suppressing deterioration in electrical characteristics that becomes significant with miniaturization. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one aspect of the present invention, a highly reliable semiconductor device can be provided. An apparatus can be provided. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are diagrams illustrating band diagrams of a stacked structure included in a semiconductor device. [Diagram 3] 1A and 1B are a plan view and a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. [Diagram 5] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 8] 1 shows ultramicroelectron beam diffraction patterns of oxide semiconductors. [Figure 9] FIG. 1 is a circuit diagram of a semiconductor device of one embodiment of the present invention. [Figure 10] 1A and 1B are a circuit diagram and a conceptual diagram of a semiconductor device of one embodiment of the present invention. [Figure 11] FIG. 1 is a block diagram of a semiconductor device of one embodiment of the present invention. [Figure 12] FIG. 1 is a block diagram of a semiconductor device of one embodiment of the present invention. [Figure 13] FIG. 1 is a block diagram of a semiconductor device of one embodiment of the present invention. [Figure 14] An electronic device to which the semiconductor device of one embodiment of the present invention can be applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The invention disclosed in this specification is not limited to the following description, and the modes and details may be variously modified. This is easily understood by those skilled in the art. Therefore, the invention disclosed in this specification is It should not be construed as being limited to the description of the embodiment modes.

[0021] In the configuration of one embodiment of the present invention shown below, the same parts or parts having similar functions In the drawings, the same reference numerals are used in common and the repeated explanations are omitted. When referring to similar functions, the hatch pattern may be the same and no particular symbol may be used. do.

[0022] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not intended to be a numerical limiting factor.

[0023] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it.

[0024] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. 1 to 7. In this embodiment, a semiconductor device using an oxide semiconductor 1 shows a transistor with a fin structure having a conductive layer.

[0025] <Example of semiconductor device configuration> FIG. 1 illustrates a configuration example of a transistor 200 as a semiconductor device. FIG. 1(B) is a plan view of the rotor 200, and FIG. 1(B) is a cross-sectional view taken along line V1-W1 of FIG. 1(A). 1C is a cross-sectional view taken along the line X1-Y1 in FIG. 1A. For simplicity, some of the components of transistor 200 (e.g., the second oxide In addition, the oxide layer 108 and other layers are omitted in the drawings. This also applies to the subsequent plan views.

[0026] The transistor 200 shown in FIG. 1 is a transistor including a base insulating layer provided on a substrate 100 having an insulating surface. A first oxide layer 104 is formed on the layer 102, and an island-shaped oxide semiconductor is formed on and in contact with the first oxide layer 104. The oxide semiconductor layer 106 includes a conductor layer 106 and a second oxide layer 108 in contact with the oxide semiconductor layer 106. The stack 110 and the source electrode layer 112a and the drain electrode layer 112b electrically connected to the oxide semiconductor layer 106 are A gate electrode layer 112b and a gate insulating layer 114 on the second oxide layer 108 and a gate insulating layer 114 on the second oxide layer 108. and a gate electrode layer 116 overlapping with the oxide semiconductor layer 106 with the layer 114 interposed therebetween.

[0027] As shown in the plan view of FIG. 1A, the oxide semiconductor layer 106 is a gate electrode layer between the source electrode layer 112a and the drain electrode layer 112b. The opening has a substantially rectangular shape in plan view and a long side of the opening is 116. The direction of the oxide semiconductor layer 106 is preferably parallel to the channel length direction. Since no channel is formed in the opening, the oxide semiconductor layer 106 is The oxide semiconductor layer has a plurality of channel formation regions arranged in parallel to each other. By providing an opening in 106, the channel forming region is divided into a plurality of parts in the channel width direction. Specifically, the oxide semiconductor layer 106 in which the channel is formed has a channel length L. Nel width W _1 and a first channel forming region 106a having a channel length L and a channel Width W _2 and a second channel forming region 106b having a channel length L and a channel width W _3 and a third channel formation region 106c which is

[0028] The oxide semiconductor layer 106 has openings, so that the oxide semiconductor layers 106 are arranged in parallel to each other at a predetermined interval. The pair of rectangular regions includes a plurality of rectangular regions. One of the regions is provided in contact with one end of each of the plurality of strip-shaped regions, and the pair of rectangular regions The other end of each of the plurality of rectangular regions is provided in contact with the other end of the oxide semiconductor layer. At least a part of the pair of rectangular regions included in 106 is a source electrode layer 112a and a drain electrode layer 112b. The oxide semiconductor layer 106 includes a plurality of rectangular electrodes 112b. Each of the regions at least partially overlaps the gate electrode layer 116 .

[0029] Note that the first oxide layer 104 and the oxide stack 110 in the transistor 200 The second oxide layer 108 is a layer formed by arranging the openings of the oxide semiconductor layer 106 and the island-shaped oxide semiconductor layer 1 06 has a contact area on the outer periphery.

[0030] As shown in the cross-sectional view in the channel width direction of FIG. 1B, the oxide included in the transistor 200 In the semiconductor layer 106, one of the channel formation regions and one of the adjacent channel formation regions A gate electrode layer 116 is provided between the gate insulating layer 114. In the channel width direction, the first channel formation region 106a to the third channel formation region 1 A gate electrode layer 116 is provided so as to overlap with the side and top surfaces of each of the gate electrodes 06c.

[0031] The gate electrode layer 116 is provided so as to overlap with the side and top surfaces of the channel formation region. An electric field can be applied from the side of the channel forming region to the gate electrode layer 116. By adopting such a structure, an electric field is applied to each channel formation region as a whole. As a result, the threshold voltage of the transistor 200 can be well controlled. In addition, the S value can be improved.

[0032] Here, the channel width (W _1 or W _3 ) too much, The electric field of the gate electrode layer 116 is hardly applied from the side of the channel forming region, and the threshold The controllability of the low voltage is decreased. In order to effectively apply an electric field to the gate electrode layer 116 from the side of the region 106c, e.g. For example, when the thickness of the gate insulating layer 114 is 20 nm, the channel Width (W _1 or W _3 It is preferable that the thickness is 40 nm or more and 100 nm or less. The preferred channel width (W _1 or W _3 ) is the film of the gate insulating layer 114 For example, when the thickness of the gate insulating layer 114 is 1 / 2 the above value (10 nm), In this case, the channel width (W _1 or W _3) is twice the range mentioned above (80 nm or less) It is preferable that the thickness is set to 200 nm or less.

[0033] On the other hand, there is a concern that reducing the channel width may result in a decrease in the on-state current of the transistor. However, the transistor 200 of the present embodiment is a channel to which an electric field can be effectively applied from the side. By providing a plurality of channel forming regions each having a channel width, the effective channel width can be increased. The transistor 200 is a transistor having a fin structure connected in parallel. It can be said that this is a transistor with a multi-fin structure.

[0034] In the present embodiment, the transistor 200 has a first channel formation region 106a In the case where the semiconductor device is configured to include three channel formation regions, ie, the first channel formation region 106c, the second channel formation region 106d, and the third channel formation region 106e, The embodiment of the present invention is not limited to this. It is sufficient to have one channel formation region, and it is also sufficient to have four or more divided channel formation regions. It's okay to do that.

[0035] In order to improve the on-state current, the thickness of the oxide semiconductor layer 106 in which the channel is formed is set to For example, it is effective to increase the thickness of the oxide semiconductor layer 106 relative to the channel width (W _1 or W _3 ) is set to 10 times or more and 100 times or less, the on However, the oxide layer included in the transistor 200 is preferably formed in the same manner as the oxide layer. The thickness of the compound semiconductor layer 106 is not limited to this range.

[0036] In addition, in the transistor 200 of this embodiment, as shown in the plan view of FIG. The width of the source electrode layer 112a and the drain electrode layer 112b in the channel width direction is The width of the conductive layer 106 in the channel width direction is smaller than the width of the oxide semiconductor layer 106 in the channel width direction. The gate electrode layer 11 is formed so as to cover the end portion in the longitudinal direction. 6 to the side of the oxide semiconductor layer 106, the obstacle to the application of the electric field can be reduced. Therefore, the effect of controlling the threshold voltage of the transistor and improving the S value by using the fin-type structure is improved. It can be lengthened.

[0037] Note that the source electrode layer 112a and the drain electrode layer 112b are formed using a conductive material that is easily bonded to oxygen. Materials such as Al, Cr, Cu, Ta, Ti, Mo, and W can be preferably used. Since the subsequent process temperature can be relatively high, It is particularly preferable to use W, which is easy to bond with oxygen. Easy materials are also included.

[0038] When such a conductive material is brought into contact with the oxide semiconductor layer 106, The oxygen is absorbed into the conductive material that easily bonds with oxygen. Since there are several heating steps, the oxygen is transferred to the oxide semiconductor layer 106. As a result, oxygen deficiency occurs in the region near the interface in contact with the source electrode layer 112a and the drain electrode layer 112b. Losses occur, and an n-type region (shown in the figure as a shaded region) can be formed. The region can function as the source or drain of the transistor 200. The n-type region is a region in the first oxide layer 104 and the second oxide layer 108. The insulating film 112 may also be formed in a region in contact with the source electrode layer 112a and the drain electrode layer 112b.

[0039] The transistor 200 has an n-type region that functions as a source or drain. This makes it easier for current to flow in the on-state, thereby increasing the on-current. In particular, when the oxide semiconductor layer 106 is thick, the thickness of the oxide semiconductor layer 106 is large. It is possible to provide an n-type region that functions as a source or drain at the end of the channel length direction. is valid.

[0040] In the n-type region, the constituent elements of the source electrode layer 112a and the drain electrode layer 112b are In addition, the source electrode layer 112a and the drain electrode layer 112b in contact with the n-type region may be mixed with silicon. In the n-type electrode layer 112b, a region with a high oxygen concentration may be formed in a part. In the source electrode layer 112a and the drain electrode layer 112b in contact with the oxide stack 11 The constituent elements of 0 may be mixed in.

[0041] In addition, when forming a transistor with an extremely short channel length, the occurrence of the oxygen vacancies causes The shaped region may extend in the channel length direction of the transistor. In this case, The electrical characteristics of transistors are difficult to control, such as threshold voltage shift and on / off control by gate voltage. Therefore, a transistor with an extremely short channel length is formed. In this case, a conductive material which is not easily bonded to oxygen is used for the source electrode layer and the drain electrode layer. As the conductive material, for example, tantalum nitride, titanium nitride, etc. are used. It is preferable that the conductive material is not easily bonded to oxygen. Can be enjoyed.

[0042] As described above, the transistor 200 includes the base insulating layer 102 and the gate insulating layer 114. The first oxide layer 104, the oxide semiconductor layer 106, and the second oxide layer 108 are interposed between the first oxide layer 104, the oxide semiconductor layer 106, and the second oxide layer 108. The first oxide layer 104 and the second oxide layer 108 are formed of an oxide stack 110. The semiconductor layer 106 is an oxide layer containing one or more metal elements.

[0043] The oxide semiconductor layer 106 is made of at least indium, zinc, and M (Al, Ga, Ge). In-M-Zn oxide containing metals such as Y, Zr, Sn, La, Ce or Hf When the oxide semiconductor layer 106 contains indium, the carrier This is preferred because it increases the mobility.

[0044] The first oxide layer 104 below the oxide semiconductor layer 106 is made of In-M-Zn oxide (M is represented by metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf. The oxide semiconductor layer 106 includes an oxide layer having a higher atomic ratio of M to In than the oxide semiconductor layer 106. Specifically, the first oxide layer 104 contains 1.5% of the above-mentioned element compared to the oxide semiconductor layer 106. an oxide layer having an atomic ratio higher than that of the oxide layer, preferably at least two times, more preferably at least three times The aforementioned elements bind more strongly to oxygen than indium, so oxygen vacancies form in the oxide layer. That is, the first oxide layer 104 has a function of suppressing the generation of the oxide semiconductor layer 10. This oxide layer is less susceptible to oxygen vacancies than oxide layer 6.

[0045] The second oxide layer 108 on the oxide semiconductor layer 106 is made of the first oxide layer 1 As in 04, In-M-Zn oxide (M is Al, Ti, Ga, Ge, Y, Zr, Sn, L a, Ce, Hf, or other metal), and Specifically, the second oxide layer 108 includes an oxide layer having a high atomic ratio of The above elements are contained in the conductive layer 106 in an amount 1.5 times or more, preferably 2 times or more, more preferably The oxide layer contains M at an atomic ratio three times higher than In. If the second oxide layer 108 is too thin, the band gap of the second oxide layer 108 becomes large and the second oxide layer 108 can function as an insulating layer. Therefore, the atomic ratio of M is adjusted to such an extent that the second oxide layer 108 can function as a semiconductor layer. However, depending on the atomic ratio of M, the second oxide layer 108 may become a part of the gate insulating layer. It may also function as a division.

[0046] The first oxide layer 104, the oxide semiconductor layer 106, and the second oxide layer 108 are at least Indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or When the first oxide layer 104 is an In-M-Zn oxide containing In: M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 106 is In:M:Zn=x 2:y2:z2 [atomic ratio], and the second oxide layer 108 is In:M:Zn=x 3: y 3: z 3 [atomic ratio], y1 / x1 and y3 / x3 are greater than y2 / x2. It is preferable that y1 / x1 and y3 / x3 are 1.5 times or more larger than y2 / x2. The thickness of the oxide semiconductor layer 106 is preferably 2 times or more, more preferably 3 times or more. When y2 is equal to or larger than x2, the electrical characteristics of the transistor can be stabilized. If y2 is three times or more larger than x2, the field effect mobility of the transistor decreases. , y2 is preferably less than three times x2.

[0047] When the first oxide layer 104 is an In-M-Zn oxide, the sum of In and M is 1 When the atomic percentage of In is 0.00, it is preferable that In is less than 50 atomic percent and M is less than 50 atomic percent. % or more, more preferably In is less than 25 atomic %, and M is 75 atomic % or more. When the oxide semiconductor layer 106 is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. % or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more. In addition, the second oxide layer 108 is made of In-M-Zn oxide. When the sum of In and M is 100 atomic %, it is preferably In. is less than 50 atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic%, and M is 75 atomic% or more.

[0048] The first oxide layer 104 and the second oxide layer 108 are layers containing different constituent elements. Alternatively, the layers may be layers containing the same constituent elements in the same atomic ratio or in different atomic ratios. good.

[0049] The first oxide layer 104, the oxide semiconductor layer 106, and the second oxide layer 108 may include, for example, For example, an oxide semiconductor containing indium, zinc, and gallium can be used.

[0050] The thickness of the first oxide layer 104 is determined based on the thickness of the oxide layer 104 formed at the interface between the insulating underlayer 102 and the first oxide layer 104. The thickness is made thick enough to suppress the influence of possible trap levels on the channel. However, the first oxide layer 104 is preferably formed between the base insulating layer 102 and the oxide semiconductor layer 103. Since this layer is the path for oxygen to be supplied to 06, if the film thickness is too thick, the supply of oxygen is inhibited, which is undesirable.

[0051] The second oxide layer 108 is formed on the gate insulating layer 114, which is an impurity for the oxide semiconductor. The thickness of the first insulating film 104 is set to be equal to or greater than the thickness at which the constituent elements of the first insulating film 104 are prevented from being mixed into the oxide semiconductor layer 106. The oxide layer 108 of the second insulating layer 102 is connected to the gate electrode layer 116 and the oxide semiconductor layer 103 which functions as a channel. Since this layer is provided between the gate insulating layer 06 and the gate insulating layer 07, it is possible to improve the on-state current of the transistor. It is preferable to make the thickness as thin as possible. Specifically, the thickness of the second oxide layer 108 is, for example, The thickness may be 0.3 nm or more and less than 10 nm, preferably 0.3 nm or more and 5 nm or less. do.

[0052] The first oxide layer 104 and the second oxide layer 108 constitute an oxide semiconductor layer 106. the energy of the conduction band minimum is lower than that of the oxide semiconductor layer 106, 0.05 eV, 0.07 eV, 0.1 eV, 0.15 eV or more, and V, 1 eV, 0.5 eV, or 0.4 eV. It is preferable for it to be formed in the body.

[0053] In such a structure, when an electric field is applied to the gate electrode layer 116, The oxide semiconductor layer 106 is a layer having the smallest conduction band minimum energy in the stacked structure including the oxide semiconductor layer 106. That is, a channel is formed between the oxide semiconductor layer 106 and the gate insulating layer 114. The second oxide layer 108 is formed on the gate of the transistor. A structure in which the insulating layer 114 is not in contact with the insulating layer 114 can be used.

[0054] In addition, oxide semiconductors are provided in contact with the upper and lower sides of the oxide semiconductor layer 106 that forms a channel. By providing an oxide layer in which oxygen vacancies are less likely to occur than in the layer 106, the channel of the transistor The formation of oxygen vacancies in the semiconductor device can be suppressed.

[0055] <Band structure of stacked structures included in transistors> Here, the base insulating layer 102, the first oxide layer 104, and the oxide The band structures of the compound semiconductor layer 106, the second oxide layer 108, and the gate insulating layer 114 are This will be explained with reference to FIG. 2.

[0056] In Figure 2, EcI1, EcS1, EcS2, EcS3, and EcI2 are the insulating substrates, respectively. layer 102, a first oxide layer 104, an oxide semiconductor layer 106, a second oxide layer 108, and The energy of the conduction band minimum of the gate insulating layer 114 is shown in schematic form. The thickness of each layer in Figure 1 above is not taken into account.

[0057] Here, the difference between the vacuum level and the conduction band minimum (also called the electron affinity) is The energy gap is calculated from the difference between the energy of the electron and the top of the valence band (also called the ionization potential). The energy gap is calculated by subtracting the energy gap from the energy gap measured by a spectroscopic ellipsometer (e.g., H It can be measured using ORIBA JOBIN YVON UT-300. The energy difference between the level and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). Photoelectron Spectroscopy (PHOS) equipment (e.g. Measurements can be performed using a VersaProbe (manufactured by IHI).

[0058] As shown in FIG. 2, a first oxide layer 104, an oxide semiconductor layer 106, a second oxide layer 10 8, the energy of the conduction band minimum changes continuously without any barrier between them. The first oxide layer 104, the oxide semiconductor layer 106, and the second oxide layer 108 have similar compositions. This can be understood as being because oxygen is easily diffused between the layers, forming a mixed layer.

[0059] In FIG. 2, the first oxide layer 104 and the second oxide layer 108 have the same energy gap. The case of oxide layers with different energy gaps has been shown. It may be an oxide layer having a groove.

[0060] As shown in FIG. 2, in the oxide stack 110 including the oxide semiconductor layer 106, the oxide semiconductor layer 106 In a transistor including the oxide stack 110, the channel is an oxide well. The oxide stack 110 is formed on the oxide semiconductor layer 106 at the bottom of the conduction band. Because the energy changes continuously, it is also called a U Shape Well. A channel formed in this way is called a buried channel. It is also possible.

[0061] The first oxide layer 104 and the second oxide layer 108 are formed of the same metal as that constituting the oxide semiconductor layer 106. Since these layers are oxide layers containing one or more metal elements, the laminated structure containing these layers has a common main component. The oxide stack that is stacked with the same main component can be said to be an oxide stack. Instead of simply stacking layers, the layers are connected in series (where the energy of the conduction band edge is The structure is fabricated so that a U-shaped well structure (with a continuously changing temperature) is formed. Impurities that form defect levels such as trap centers and recombination centers are present at the interface. When this happens, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. This is because they will disappear more easily.

[0062] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. (sputtering equipment) to continuously stack each layer without exposing them to the air Each chamber in the sputtering equipment must be free of impurities for oxide semiconductors. In order to remove as much water as possible, a vacuum pump of the adsorption type like a cryopump is used. High vacuum pumping (5×10 -7 Pa or more 1×10 -4 It is preferable to use a pressure of about 100 Pa or less. Alternatively, a turbomolecular pump and cold trap can be combined to vent the gas from the exhaust system to the chamber. It is preferable to prevent gas from flowing back into the tank.

[0063] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using highly purified gas, the incorporation of moisture into the oxide semiconductor is minimized. It can be prevented.

[0064] The first oxide layer 104 and the second oxide layer 105 are provided above or below the oxide semiconductor layer 106. The oxide layer 108 functions as a barrier layer and is in contact with the insulating layer (underlying insulating layer 10 2 and the gate insulating layer 114) and the oxide stack 110. The influence of the oxide semiconductor layer 10, which is the main carrier path of the transistor, This can prevent the rate from reaching 6.

[0065] For example, oxygen vacancies in an oxide semiconductor layer are This manifests itself as a localized level that exists at a deep energy position. When ions are trapped in the oxide semiconductor layer, the reliability of the transistor decreases. In the transistor 200 of this embodiment, the oxygen vacancies are reduced. The oxide layer is less likely to have oxygen vacancies than the oxide semiconductor layer 106. By providing the oxide semiconductor layer 106 above and below, oxygen vacancies in the oxide semiconductor layer 106 can be reduced. For example, the oxide semiconductor layer 106 can be measured by a constant current measurement (CPM). The absorption coefficient due to the localized level measured by the photocurrent method is 1×10 -3 / cm, preferably less than 1×10 -4 / cm.

[0066] In addition, the oxide semiconductor layer 106 may be formed by interposing an insulating layer having a different constituent element (e.g., a silicon oxide film). When the semiconductor comes into contact with a layer (including an insulating underlayer), an interface state is formed at the interface between the two layers, and the interface state becomes a channel. In such a case, a second transistor with a different threshold voltage appears. This can cause the apparent threshold voltage of the transistor to fluctuate. In the transistor 200 according to the embodiment, the metal element constituting the oxide semiconductor layer 106 is Since the first oxide layer 104 is composed of one or more of these, the first oxide layer 104 and the oxide The interface state is less likely to be formed at the interface of the semiconductor layer 106. By using this method, it is possible to reduce the variation in electrical characteristics such as the threshold voltage of the transistor. can be done.

[0067] In addition, when a channel is formed at the interface between the gate insulating layer 114 and the oxide semiconductor layer 106, However, interface scattering occurs at the interface, which reduces the field effect mobility of the transistor. In the transistor 200 of this embodiment, the metal constituting the oxide semiconductor layer 106 Since the second oxide layer 108 contains one or more elements, the oxide semiconductor layer 106 and At the interface with the second oxide layer 108, carrier scattering is unlikely to occur, and the electric field of the transistor The effective mobility can be increased.

[0068] The first oxide layer 104 and the second oxide layer 108 are also formed on the insulating base layer 102 and the gate The constituent elements of the insulating layer 114 are mixed into the oxide semiconductor layer 106, and an impurity level is formed. It also functions as a barrier layer to prevent damage to the material.

[0069] For example, the insulating underlayer 102 in contact with the first oxide layer 104 or the second oxide layer 108, When an insulating layer containing silicon is used as the gate insulating layer 114, the silicon in the insulating layer The carbon, which may be mixed into the insulating layer, is added to the first oxide layer 104 or the second oxide layer 10. Impurities such as silicon and carbon may enter the oxide film 8 from the interface to a depth of a few nm. When the electrons enter the semiconductor layer, they form impurity levels, which generate electrons, resulting in n It can become stylized.

[0070] However, if the thickness of the first oxide layer 104 and the second oxide layer 108 is greater than a few nm, If the thickness is large, impurities such as silicon and carbon do not reach the oxide semiconductor layer 106. Therefore, the influence of the impurity level is reduced.

[0071] In order to make the oxide semiconductor layer 106 intrinsic or substantially intrinsic, In the analysis, the silicon concentration was set at 1×10 19 atoms / cm 3 Less than 5x, preferably 10 18 atoms / cm 3 Less than 3 x 10 18 atoms / cm 3 Less than, good Preferably 1×10 18 atoms / cm 3 The hydrogen concentration is less than 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is more preferred: 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 The nitrogen concentration is 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0072] The impurity concentration in the oxide semiconductor layer was measured using secondary ion mass spectrometry (SIMS). It can be measured by y Ion Mass Spectrometry.

[0073] In addition, when the oxide semiconductor layer 106 contains crystals and silicon or carbon at a high concentration, This may cause a decrease in the crystallinity of the oxide semiconductor layer 106. In order not to decrease the silicon concentration, 19 atoms / cm 3 Less than, preferred 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 The carbon concentration should be less than 1×10 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 It is sufficient to set it to less than.

[0074] In addition, a transistor in which the highly purified oxide semiconductor layer 106 is used for a channel formation region can be The off-state current is extremely small. For example, a transistor using a highly purified oxide semiconductor layer When the transistor is off, the drain current is 1×10 -18 A or below, good Preferably 1×10 -21 A or less, more preferably 1×10 -24 A or below, or 85℃ 1×10 -15 A or less, preferably 1×10 -18 A or less, more preferably 1×1 0 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. If the gate voltage is 1V or more, 2V or more, or 3V or more less than the threshold voltage, The transistor is turned off.

[0075] <Method for manufacturing semiconductor device> An example of a method for manufacturing the transistor 200 illustrated in FIG. 1 will be described with reference to FIGS.

[0076] 3 and 4A, a process for manufacturing the transistor 200 is shown. (B) shows a cross-sectional view taken along line V1-W1 in (A), and (C) shows a 3(A) shows a cross-sectional view taken along the line X1-Y1 in FIG. 3(B1). FIG. 3(C1) is a cross-sectional view taken along line V1-W1 of FIG. 3(A1), and FIG. 3(C2) is a cross-sectional view taken along line X1-Y1 of FIG. 3(A1). FIG.

[0077] First, a base insulating layer 102 is formed over a substrate 100 having an insulating surface.

[0078] The substrate 100 is not limited to being a simple support member, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 116 of the transistor 200, the source electrode At least one of the layers 112a and 112b is electrically connected to the other devices. The electrodes may be electrically connected.

[0079] The insulating underlayer 102 has a role of preventing the diffusion of impurities from the substrate 100 and also serves to prevent the diffusion of impurities from the substrate 100. The oxygen supplying layer 104 and / or the oxide semiconductor layer 106 is Therefore, an insulating layer containing oxygen is used as the base insulating layer 102. When oxygen is supplied from the base insulating layer 102, It is possible to reduce oxygen vacancies in the oxide semiconductor layer 106. The base insulating layer 102 may be a single layer or a multilayer. Plasma CVD (Chemical Vapor Deposition) method, MOCVD (Metal Organic Chemical Vapor Deposition Thermal CVD methods such as the ALD (Atomic Layer Deposition) method and the ALD (Atomic Layer Deposition) method. It can be formed using the above.

[0080] In addition, as described above, when the substrate 100 is a substrate on which other devices are formed, the base insulating layer 102 also functions as an interlayer insulating film. In that case, the CM Flattening process using P (Chemical Mechanical Polishing) method etc. It is preferable to carry out the following.

[0081] In the transistor 200 of this embodiment, the base insulating layer 102 containing oxygen is The insulating film is provided below a stacked structure including an oxide semiconductor layer. By this, oxygen contained in the base insulating layer 102 can be supplied to the channel formation region. The base insulating layer 102 has a region that contains oxygen in excess of the stoichiometric composition. When the base insulating layer 102 contains excess oxygen, the channel formation region is This promotes the supply of oxygen to the blood vessels.

[0082] Note that in this specification and the like, the term "excess oxygen" refers to oxygen that has been added to an oxide semiconductor layer or an oxide semiconductor layer by heat treatment. The oxygen that can move in silicon oxynitride or silicon oxynitride, or in the original stoichiometric ratio, Oxygen vacancy (Vo) is a condition caused by an excess of oxygen or a shortage of oxygen. )) indicates oxygen having the function of filling or replenishing it.

[0083] In order to make the base insulating layer 102 contain excess oxygen, for example, the base insulating layer 102 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the base insulating layer 102 after the film formation to remove excess oxygen. or a combination of both measures.

[0084] In addition, since the base insulating layer 102 is an insulating layer in contact with the first oxide layer 104, the water in the film Therefore, after the base insulating layer 102 is formed, hydrogen is removed. It is preferable to carry out a heat treatment (dehydration treatment or dehydrogenation treatment) for the purpose of removing the hydrogen.

[0085] The temperature of the heat treatment is 250° C. or more and 650° C. or less, preferably 350° C. or more and 600° C. or less, For example, the substrate is introduced into an electric furnace, which is one type of heat treatment device, and The insulating underlayer 102 is subjected to a heat treatment at 450° C. for one hour in a vacuum (reduced pressure) atmosphere. .

[0086] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction or heat radiation from a heating element such as a resistance heating element. Therefore, a device for heating the object to be treated may be used. For example, a GRTA (Gas Rapid Atomic Pressure Transmitter) d Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal RTA (Rapid Thermal Anneal) equipment such as The LRTA device can be used with halogen lamps, metal halide lamps, Xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from lamps such as G The RTA device is a device that performs heat treatment using high-temperature gas. The high-temperature gas is argon. Inert gases such as rare gases or nitrogen that do not react with the workpiece during heat treatment are used. When a GRTA device is used as the heat treatment device, the treatment time is short. Therefore, the substrate may be heated in an inert gas atmosphere at a high temperature of 650°C to 700°C. stomach.

[0087] The heat treatment is carried out in a nitrogen, oxygen or ultra-dry air (water content less than 20 ppm, preferably less than 1 ppm). or less, preferably 10 ppb or less of air), or rare gases (argon, helium, etc.) The reaction may be carried out under an atmosphere of nitrogen, oxygen, ultra-dry air, or a rare gas, etc. It is preferable that hydrogen and the like are not included. In addition, nitrogen, oxygen, or The purity of rare gas is 6N (99.9999%) or more, preferably 7N (99.99999%). ) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). I wish.

[0088] Note that oxygen may be released from the base insulating layer 102 by the heat treatment. The base insulating layer 102 that has been subjected to hydrogenation or dehydrogenation treatment is treated with oxygen (at least oxygen radicals). ozone, oxygen atoms, or oxygen ions (including molecular ions and cluster ions) It is preferable to carry out a process to introduce the

[0089] The introduction of oxygen into the insulating base layer 102 can be performed by, for example, ion implantation, ion doping, plasma Micro-ion implantation, plasma treatment, etc. can be used. For the gas containing oxygen, a gas containing oxygen can be used. The oxygen introduction process can be performed by using oxygen gas such as nitrogen dioxide, carbon dioxide, and carbon monoxide. In the process, a rare gas may be contained in the gas containing oxygen. The oxygen absorption treatment can compensate for the oxygen that may be released by the heat treatment.

[0090] Next, the first oxide layer 104 and the oxide semiconductor layer 106 are formed on the base insulating layer 102 by a laser. Sputtering method, CVD method, MBE (Molecular Beam Epitaxy) method, ALD method, or PLD (Pulse Laser Deposition) method. A film is formed.

[0091] The first oxide layer 104 and the oxide semiconductor layer 106 can be formed using the above-mentioned materials. .

[0092] For example, when the first oxide layer 104 is formed by a sputtering method, the atomic ratio is In A sputtering target with an atomic ratio of In:Ga:Zn=1:3:2 Sputtering target with a ratio of 1:6:4, or an atomic ratio of In:Ga:Zn=1:9:6 or a sputtering target having a composition close to that of the sputtering target. It is preferable to use

[0093] In addition, for example, when the oxide semiconductor layer 106 is formed by a sputtering method, the atomic ratio A sputtering target with an atomic ratio of In:Ga:Zn=1:1:1 or In:Ga A sputtering target with a:Zn=3:1:2 or a sputtering target with a composition close to that It is preferable to use a tarring target.

[0094] The composition of the film formed by sputtering may differ from the composition of the target. For example, a sputtering target containing ZnO is used to form an oxide semiconductor layer. When the ZnO film is formed, the ZnO may sublimate during the film formation, and the oxide semiconductor layer may be damaged. The atomic ratio of Zn to In and / or Ga in the sputtering target and / or the atomic ratio of Zn to Ga may be reduced compared to that of Ga.

[0095] However, as described above, the first oxide layer 104 is more electron-philic than the oxide semiconductor layer 106. Select materials so that the sum force is small.

[0096] Note that the first oxide layer 104 and the oxide semiconductor layer 106 are formed by a sputtering method. The sputtering method is preferably an RF sputtering method, a DC sputtering method, or an AC sputtering method. In particular, it is possible to reduce dust generated during film formation and to achieve a uniform film thickness distribution. It is preferable to use the DC sputtering method in order to obtain a uniform

[0097] When the first oxide layer 104 and the oxide semiconductor layer 106 are formed, it is preferable to form the oxide semiconductor layer It is preferable to reduce the hydrogen concentration. When a film is formed by a sputtering method, it is supplied into the film formation chamber of the sputtering device. The atmospheric gas is a high-purity dilute gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. A gas (typically argon), oxygen, and a mixed gas of a rare gas and oxygen are appropriately used.

[0098] In addition, the residual moisture in the film formation chamber is removed and a sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the film in this manner, the hydrogen concentration in the film can be reduced. To remove residual moisture, use an adsorption type vacuum pump, such as a cryopump or ion pump. It is preferable to use a turbo molecular pump or a titanium sublimation pump. A cryopump may be a pump that pumps, for example, hydrogen molecules. , water (H2O) and other compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) The high pumping capacity of the cryopump allows the deposition of oxide layers and The concentration of impurities contained in the oxide semiconductor layer can be reduced.

[0099] Note that after the first oxide layer 104 is formed and before the oxide semiconductor layer 106 is formed, Oxygen may be introduced into the layer 104. The oxygen introduction process reduces the first oxide layer 10 4 contains excess oxygen, and the excess oxygen is oxidized by heat treatment in the subsequent film formation process. The semiconductor layer 106 can be supplied with the

[0100] After the first oxide layer 104 and the oxide semiconductor layer 106 are formed, heat treatment is preferably performed. The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C. If the process is carried out in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or a reduced pressure atmosphere, In addition, after heat treatment in an inert gas atmosphere, an oxidizing agent is added to compensate for the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 10 ppm or more of the gas. At least one of the base insulating layer 102, the first oxide layer 104, and the oxide semiconductor layer 106 Impurities such as hydrogen and water can be removed from the oxide semiconductor layer. This may be performed after processing 106 into an island shape.

[0101] Next, the oxide semiconductor layer 106 is patterned to form an island-shaped oxide semiconductor layer having an opening. The opening is then processed into a gate layer 106 (see FIG. 3(A1)(B1)(C1)). The insulating film 114 is selectively formed in a region overlapping the insulating film 116 .

[0102] Note that when the oxide semiconductor layer 106 is etched, the oxide semiconductor layer 106 may be overgrown. A part of the first oxide layer 104 (exposed from the island-shaped oxide semiconductor layer 106) is removed by etching. The area where the film is removed may be etched, resulting in a decrease in the film thickness.

[0103] Next, a semiconductor layer 106 is formed on the first oxide layer 104 so as to cover the side and top surfaces of the island-shaped oxide semiconductor layer 106. A second oxide layer 108 is formed on the second oxide layer 108 (see FIGS. 3(A2), 3(B2), and 3(C2)). The oxide layer 108 can be formed by a thermal deposition method such as a sputtering method, a plasma CVD method, an MOCVD method, or an ALD method. The oxide stack 110 can be formed by using a CVD method or the like. can be.

[0104] The second oxide layer 108 may be made of the above-mentioned materials. For example, the second oxide layer When 108 is formed by sputtering, the atomic ratio is In:Ga:Zn=1:3: The sputtering target No. 2 has an atomic ratio of In:Ga:Zn=1:6:4. sputtering target with an atomic ratio of In:Ga:Zn=1:9:6 It is preferable to use a sputtering target having a composition similar to or close to that of the above-mentioned target.

[0105] Note that the oxide semiconductor layer 106 and the second oxide layer 108 are provided at the interface between them. A mixed layer (or region) may be formed with the second oxide layer 108. In the transistor 200, the interface between the oxide semiconductor layer 106 and the second oxide layer 108 is unclear. The formation of a mixed layer (or mixed region) at the interface between the layers can cause the oxide The interface scattering between the semiconductor layer 106 and the second oxide layer 108 is reduced. The same is true for the interface between 6 and the first oxide layer 104.

[0106] After the second oxide layer 108 is formed, a heat treatment may be performed. The heat treatment can be performed under the same conditions as those after the formation of the oxide semiconductor layers 104 and 106.

[0107] Next, a conductive film is formed on the second oxide layer 108, and the conductive film is processed to form the source electrode layer 11. 2a and the drain electrode layer 112b are formed (see FIGS. 4(A1), 4(B1), and 4(C1)). The source electrode layer 112a and the drain electrode layer 112b are formed by sputtering or plasma CVD. The thin-film transistor can be formed by a thermal CVD method such as a MOCVD method or an ALD method.

[0108] Although not shown, the ends of the source electrode layer 112a and the drain electrode layer 112b are stepped. The end portion may be formed in a shape having a plurality of steps. This can be achieved by repeating the steps of retracting the mask and etching multiple times. The thicker the source electrode layer 112a and the drain electrode layer 112b are, the greater the number of steps can be. It is preferable to increase it.

[0109] The source electrode layer 112a and the drain electrode layer 112b are formed in a shape having a plurality of steps as described above. By doing so, the films formed thereover, specifically, the gate insulating layer 114 and other films, can be prevented from being damaged. The covering property is improved, and the electrical characteristics and long-term reliability of the transistor can be improved.

[0110] When the source electrode layer 112a and the drain electrode layer 112b are processed, the conductive film is overcoated. By etching, a part of the second oxide layer 108 (the source electrode layer 112a and the drain In some cases, the exposed area of ​​the gate electrode layer 112b may be etched, resulting in a decrease in the thickness of the gate electrode layer 112b.

[0111] Next, a gate insulating layer 114 is formed over the source electrode layer 112a and the drain electrode layer 112b. It is formed by the sputtering method, the MBE method, the CVD method, the PLD method, the ALD method, or the like.

[0112] The gate insulating layer 114 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, A silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film If the gate insulating layer 114 is a film containing oxygen, the second oxide film can be used. This is preferable because oxygen can be supplied to the gate insulating layer 108 or the oxide semiconductor layer 106. The edge layer 114 may include hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate, hafnium aluminium minate (HfAl x O y (x>0, y>0)), lanthanum oxide, etc. may be used. The gate insulating layer 114 may have either a single layer structure or a stacked layer structure.

[0113] The gate insulating layer 114 is formed by, for example, high-frequency radiation using microwaves (for example, at a frequency of 2.45 GHz). By forming the film using high-density plasma CVD, it becomes a dense film with high dielectric strength. This is preferable because it is possible to

[0114] Next, a gate electrode layer 116 is formed on the gate insulating layer 114 (FIGS. 4(A2) and (B2)). (See (C2)).

[0115] The material of the gate electrode layer 116 is molybdenum, titanium, tantalum, tungsten, aluminum, etc. A metal film containing an element selected from the group consisting of aluminum, copper, chromium, neodymium, and scandium, or Metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) The gate electrode layer 116 can be formed of a silicon film containing an impurity element such as phosphorus. Semiconductor films such as doped polycrystalline silicon films, and silicide films such as nickel silicide Alternatively, a side film may be used. Indium Zinc Oxide with Tungsten Oxide, Indium Zinc Oxide with Titanium Oxide Oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as doped indium tin oxide can also be used. It is also possible to use a laminated structure of the above-mentioned material and the above-mentioned metal material.

[0116] The gate electrode layer 116 may have a single-layer structure or a stacked structure. As a layer of the gate electrode layer 116 in contact with the border layer 114, a metal oxide containing nitrogen, specifically are In-Ga-Zn-O films containing nitrogen, In-Sn-O films containing nitrogen, and In-Ga-O film, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen, Examples of usable materials include In-O films containing InN and metal nitride films (InN, SnN, etc.). The film has a work function of 5 eV (electron volts) or more, preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, it shifts the threshold voltage of a transistor to the positive side. Thus, a so-called normally-off switching element can be realized.

[0117] The gate electrode layer 116 is formed by a method such as a plasma CVD method, a sputtering method, an MOCVD method, or an ALD method. It can be formed by a thermal CVD method or the like.

[0118] After forming the gate insulating layer 114 and / or the gate electrode layer 116, a heat treatment is performed. The heat treatment may be performed after the formation of the first oxide layer 104 and the oxide semiconductor layer 106. The treatment can be carried out under the same conditions as those for the treatment.

[0119] In this manner, the transistor 200 of this embodiment can be formed.

[0120] Note that after the gate electrode layer 116 is formed, an insulating layer may be formed over the gate electrode layer 116 . The insulating layer may be made of aluminum oxide, magnesium oxide, silicon oxide, or oxynitride. Silicon, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, indium oxide tritium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide The insulating layer may be a laminated film of the above materials. The insulating layer is formed by sputtering, CVD, MBE, ALD, or PLD. It can be formed by

[0121] For example, a material having low oxygen permeability (low oxygen permeability) may be used as an insulating layer on the gate electrode layer 116. As the material of the layer having low oxygen permeability, Examples of the nitride include aluminum oxide, silicon nitride, and silicon oxynitride. An insulating layer having low oxygen permeability is provided on the gate electrode layer 116 to cover the gate insulating layer 114. By this, oxygen released from the base insulating layer 102 and the like by the subsequent heat treatment can be prevented from Therefore, the oxygen can be efficiently supplied to the oxide stack 110. Cut.

[0122] Alternatively, the oxide layer 110 may be an insulating layer on the gate electrode layer 116 and may serve as an oxygen source for the oxide stack 110. A laminated structure of a layer containing possible oxygen (containing excess oxygen) and a layer with low oxygen permeability. may be formed.

[0123] After the insulating layer is formed over the gate electrode layer 116, heat treatment may be performed. The heat treatment is performed under the same conditions as those of the heat treatment after the formation of the oxide layer 104 and the oxide semiconductor layer 106 in the heat treatment of Example 1. can be done.

[0124] As described above, the transistor described in this embodiment has a gate electrode that overlaps with the side surface and the top surface. The semiconductor device has a plurality of channel forming regions each having a gate electrode layer. In addition, the electric field of the gate electrode layer is applied from the side, so the threshold voltage can be controlled. The above-mentioned configuration can be satisfactorily performed and the S value can be improved. By providing a plurality of channel forming regions, the effective channel width can be increased. Therefore, the on-state current of the transistor can be increased.

[0125] In addition, the transistor described in this embodiment includes an oxide semiconductor layer which forms a channel and Between the oxide semiconductor layer and the insulating layer overlapping it, at least one of the metal elements constituting the oxide semiconductor layer is The oxide semiconductor layer and the insulating layer include an oxide layer containing at least one metal element as a constituent element. In the case where the oxide semiconductor layer and the insulating layer are in contact with each other, trap states may be formed at the interface between the oxide semiconductor layer and the insulating layer. By adopting the above-mentioned structure having an oxide layer between the semiconductor layer and the insulating layer, The formation of a trap level can be suppressed. Therefore, the deterioration of the electrical characteristics of the transistor can be prevented. It can be suppressed.

[0126] <Modification 1 of the semiconductor device> FIG. 5 shows a modification of the transistor 200 shown in FIG. 1, which is partially different in configuration. FIG. 5(A) is a plan view of the transistor 210, and FIG. 5(B) is a diagram showing the V2-W2 of FIG. 5(A). 5(C) is a cross-sectional view taken along the line X2-Y2 of FIG. 5(A).

[0127] In the transistor 210 shown in FIG. 5, the second oxide layer 108 is , the oxide semiconductor layer 106 exposed from the source electrode layer 112a and the drain electrode layer 112b The source electrode layer 112a and the drain electrode layer 112b are provided in contact with each other. Therefore, in the transistor 210, the source electrode layer 112a and the drain electrode layer 11 2b is a side surface of the first oxide layer 104, a part of the upper surface and a side surface of the oxide semiconductor layer 106. the source electrode layer 112a, the drain electrode layer 112b, and the oxide semiconductor layer An n-type region is formed in the region where the first In the first oxide layer 104 and the second oxide layer 108, the source electrode layer 112a and the drain electrode layer 112b are It may also be formed in a region in contact with the inner electrode layer 112b.

[0128] In addition, the first oxide layer 104 is formed in the same mass as the oxide semiconductor layer 106 during etching. That is, in the transistor 210, the first oxide The oxide semiconductor layer 104 and the oxide semiconductor layer 106 have the same planar shape and a first cross-sectional shape. The upper end of the oxide layer 104 and the lower end of the oxide semiconductor layer 106 are aligned.

[0129] In the transistor 210, the second oxide layer 108 and the gate insulating layer 114 are The gate electrode layer 116 is used as a mask to perform etching in a self-aligned manner. In the transistor 210, the second oxide layer 108 and the gate insulating layer 114 are It has the same planar shape as the pole layer 116 .

[0130] In this specification, the expressions "same" or "match" mean exactly the same or match. The term "similar" does not necessarily mean that the product is identical to the product, and includes "approximately identical" or "approximately identical." For example, This includes the degree of correspondence in the shape obtained by etching with a mask of the same material.

[0131] The rest of the configuration of the transistor 210 is similar to that of the transistor 200, so a detailed description thereof will not be given. The explanation will be omitted.

[0132] As shown in FIG. 5B, in the transistor 210, the first oxide layer 104 is By patterning using the same mask as the semiconductor layer 106, one of the channel formation regions and the adjacent In the region between the first and second oxide layers 108 and the first insulating layer 1, With this configuration, the second oxide layer 10 is in contact with the second oxide layer 10 in this region. In comparison with the transistor 200 having a configuration in which the first oxide layer 104 is in contact with the first oxide layer 104, The gate electrode layer 116 provided in the region is disposed closer to the lower end (first The interface between the oxide layer 104 and the semiconductor layer 105 can be brought closer to the interface between the oxide layer 104 and the semiconductor layer 105 .

[0133] Therefore, in the transistor 210, the region to which an electric field is applied by the gate electrode layer 116 is This allows for better control of the threshold voltage and improved S value. It can be a gistar.

[0134] Note that when the oxide semiconductor layer 106 and the first oxide layer 104 are etched, By over-etching the oxide layer 104, a part of the base insulating layer 102 (island-shaped oxide The region exposed from the first oxide layer 104 and the semiconductor layer 106 is etched to reduce the thickness. This reduces the thickness of one of the channel formation regions and the adjacent channel formation region. A gate electrode layer 116 is formed in the region between the first and second gate electrodes 116 and 116 in the thickness direction of the channel forming region. It is possible to bring the oxide layer 104 closer to the lower end of the first oxide layer 104 (the interface with the first oxide layer 104).

[0135] In addition, the second oxide layer 108 is processed using the gate electrode layer 116 as a mask. The outward diffusion of indium contained in the oxide layer 108 can be suppressed. The out-diffusion of ZnO is a factor that causes fluctuations in the electrical characteristics of transistors and can cause problems in the deposition chamber during the process. In order to prevent contamination of the inside of the gate electrode layer 116, the second oxide layer 108 is processed using the gate electrode layer 116 as a mask. The work is effective.

[0136] Note that the first oxide layer 104 is processed using the same mask as that used for processing the oxide semiconductor layer 106. The second oxide layer 108 can be processed by using the gate electrode layer 116 as a mask. Therefore, compared to the manufacturing process of the transistor 200, the number of masks required for the transistor can be increased. This is preferable because the transistor 210 can be fabricated in this way.

[0137] <Modification 2 of Semiconductor Device> FIG. 6 shows a modification of the transistor 200 shown in FIG. 1, which has a partially different configuration. FIG. 6(A) is a plan view of the transistor 220, and FIG. 6(B) is a diagram showing the V3-W3 of FIG. 6(A). 6(C) is a cross-sectional view taken along the line X3-Y3 of FIG. 6(A).

[0138] The transistor 220 shown in FIG. 6 includes a first oxide layer 104, The oxide semiconductor layer 106 and the second oxide layer 108 are etched using the same mask. That is, in the transistor 220, the first oxide layer 104 and the oxide semiconductor layer The first oxide layer 106 and the second oxide layer 108 have the same planar shape and are substantially the same in cross section as the first oxide layer 106 and the second oxide layer 108. The upper end of the oxide semiconductor layer 104 is aligned with the lower end of the oxide semiconductor layer 106. The upper end of the second oxide layer 108 is flush with the lower end of the second oxide layer 108 .

[0139] Therefore, in the transistor 220, the source electrode layer 112a and the drain electrode layer 112b The side surface of the first oxide layer 104, the side surface of the oxide semiconductor layer 106, and the side surface of the second oxide layer 104 are It is provided in contact with a portion of the top surface and side surface of 08.

[0140] The rest of the configuration of the transistor 220 is similar to that of the transistor 200, so a detailed description thereof will not be given. The explanation will be omitted.

[0141] As shown in FIG. 6B, in the transistor 220, the first oxide layer 104, the oxide The semiconductor layer 106 and the second oxide layer 108 are patterned with the same mask. A gate insulating film is formed in a region between one of the gate-forming regions and one of the adjacent channel-forming regions. The layer 114 and the base insulating layer 102 are in contact with each other. The gate electrode layer 116 provided in the region further than the gate electrode 210 is formed in the channel forming region. It is possible to approach the lower end (interface with the first oxide layer 104) in the film thickness direction.

[0142] Therefore, in the transistor 220, the region to which an electric field is applied by the gate electrode layer 116 is This allows for better control of the threshold voltage and allows for the production of transistors with improved S values. It can be a star.

[0143] In addition, similarly to the transistor 210, the first oxide stack 110 is etched. By over-etching the oxide layer 104, a part of the base insulating layer 102 (the island-shaped second (regions exposed from the oxide layer 108, the oxide semiconductor layer 106, and the first oxide layer 104) The thickness of the film may be reduced by etching. The gate electrode layer 116 provided in the region between the adjacent channel formation regions is further It is possible to approach the lower end (interface with the first oxide layer 104) of the channel forming region in the thickness direction. Cut.

[0144] The transistor 220 is made of an oxide semiconductor that forms a channel in the channel width direction. The second oxide layer 108 is in contact with the gate insulating layer 114. In the case where a material having a high M content and insulating properties is used, the second oxide layer 108 As a result, the thickness of the gate insulating layer increases, and an electric field is applied to the channel formation region from the side. This can prevent the deterioration of the device.

[0145] Note that in the transistor 220, the first oxide layer 104, the oxide semiconductor layer 106, and The first oxide layer 106 and the second oxide layer 108 can be patterned using the same mask. , compared to the manufacturing process of the transistor 200, the number of masks required to manufacture the transistor 2 can be increased. 20 can be produced, which is preferred.

[0146] <Modification 3 of the semiconductor device> FIG. 7 shows a modification of the transistor 200 shown in FIG. 1, the configuration of which is partially different. FIG. 7(A) is a plan view of the transistor 230, and FIG. 7(B) is a diagram showing the V4-W4 region of FIG. 7(A). 7(C) is a cross-sectional view taken along line X4-Y4 of FIG. 7(A).

[0147] The transistor 230 shown in FIG. 7 is formed under the first oxide layer 104 via the base insulating layer 102. The gate electrode layer 103 overlaps with the oxide semiconductor layer 106. The transistor 230 can function as a so-called back gate electrode. In this embodiment, the base insulating layer 102 also functions as a gate insulating layer.

[0148] The gate electrode layer 116 of the transistor 230 is connected to the source electrode layer 112a and the drain electrode layer 112b. The gate electrode layer 112b is disposed so as not to overlap with the gate electrode layer 112b. Reduce the parasitic capacitance between the drain electrode layer 112b and the source electrode layer 112a. It is possible.

[0149] The rest of the configuration of the transistor 230 is similar to that of the transistor 200, so a detailed description thereof will not be given. The explanation will be omitted.

[0150] The transistor 230 has a gate electrode below the oxide semiconductor layer 106. By providing the gate electrode layer 103, an electric field is unlikely to be applied to the gate electrode layer 116 alone. The electric field is effectively applied to the bottom end (interface with the first oxide layer 104) of the channel formation region in the thickness direction. Therefore, the oxide semiconductor layer 1 included in the transistor 230 can be applied. The channel formation region of 06 can be applied with an electric field in the lateral and vertical directions. Therefore, the threshold voltage can be well controlled and the S value can be improved.

[0151] The method and material for forming the gate electrode layer 103 are the same as those for forming the gate electrode layer 116. The fee can be taken into consideration.

[0152] The base insulating layer 102 functioning as a gate insulating layer may have a stacked structure. In the edge layer 102, the area where the first oxide layer 104 is to be formed is treated with C to make the surface flat. It is preferable to perform planarization treatment by the MP method or the like.

[0153] In FIG. 7, the above-mentioned transistor 200 is provided with a gate electrode functioning as a back gate electrode. Although a configuration in which the polar layer 103 is added is shown, the embodiment of the present invention is not limited to this. A gate electrode layer that functions as a back gate electrode is added to the transistor 210 or the transistor 220. It is also possible to add

[0154] The gate electrode layer 116 included in the transistor 230 is connected to the source electrode layer 112a and and / or a region overlapping with the drain electrode layer 112b. 200, the gate electrode layer 116 of the transistor 210 or the transistor 220 is connected to a source The electrode layer 112a and the drain electrode layer 112b may not overlap with each other.

[0155] The transistors shown in the above-described modifications 1 to 3 have side and top electrodes similar to the transistor 200. By providing a plurality of channel formation regions in which gate electrode layers are provided so as to overlap with the surface, An electric field of the gate electrode layer is applied not only from the upper surface direction of the panel formation region but also from the side direction. Furthermore, the transistors described in Modifications 1 to 3 each have an oxide semiconductor layer and a second It is therefore possible to effectively apply an electric field to the region near the interface with the oxide layer of 1. The threshold voltage of the transistor having this configuration can be controlled well, and the S value Furthermore, by having a plurality of channel formation regions having the above structure, This allows the effective channel width to be increased, thereby increasing the on-state current of the transistor. It can be done.

[0156] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0157] (Embodiment 2) In this embodiment, an example of an oxide semiconductor layer which can be used for the transistor in Embodiment 1 will be described. I will explain it below.

[0158] <Crystallineness of oxide semiconductor layer> The oxide semiconductor layer used in the transistor may include, for example, a non-single crystal. Examples of crystals include CAAC (C Axis Aligned Crystal), Examples of the crystals include crystals and microcrystals.

[0159] The oxide semiconductor may include, for example, a CAAC. , CAAC-OS(C Axis Aligned Crystalline Oxy It is called the "De Semiconductor."

[0160] CAAC-OS can be used, for example, in a transmission electron microscope (TEM). The crystals were confirmed in the image observed by a lectron microscope. The crystal parts in the CAAC-OS may be, for example, The size of the CAAC-OS is often within a cube with sides of 100 nm. In EM images, the boundaries between crystalline regions may not be clearly visible. CAAC-OS is a TEM image showing grain boundaries. In some cases, it may not be possible to clearly confirm the grain boundaries. For example, the CAAC-OS does not have clear grain boundaries. In addition, the CAAC-OS does not have clear grain boundaries, for example. Therefore, the defect density is unlikely to increase. Since there are no clear grain boundaries, the decrease in electron mobility is small.

[0161] For example, the CAAC-OS has a plurality of crystal parts, and the c-axes of the crystal parts are oriented in a symmetrical manner. The vectors may be aligned along the normal vector of the resulting surface or parallel to the normal vector of the surface. In addition, CAAC-OS can be obtained by, for example, X-ray diffraction (XRD). n) When the out-of-plane analysis was performed using the device, the 2θ value indicating the orientation was 3 A peak may appear around 1°. The peak around 31° 2θ is InGaZnO4 If the crystal is of this type, it indicates that it is oriented in the (009) plane. For example, a peak may appear near 2θ of 36°. The peak near 2θ of 36° is Z If it is a nGa2O4 crystal, it indicates that it is oriented in the (222) plane. Preferably, a peak appears at 2θ of about 31° and no peak appears at 2θ of about 36°. stomach.

[0162] In addition, in the CAAC-OS, for example, the orientations of the a-axis and b-axis are different between different crystal parts. For example, CAAC-OS with InGaZnO4 crystals may not be uniform. If we use an XRD device, we can use the in-plane method, in which X-rays are incident from a direction perpendicular to the c-axis. When analyzing by 2θ, a peak may appear near 56°. The peak indicates the (110) plane of the InGaZnO4 crystal. Here, 2θ is about 56°. The sample is fixed and analyzed by rotating it around the normal vector of the surface (φ axis) (φ scan). In the case of a single-crystal oxide semiconductor in which the a-axis and b-axis are aligned, six symmetries are formed. In the case of CAAC-OS, no clear peak appears.

[0163] Thus, the CAAC-OS has, for example, a c-axis oriented structure, and the a-axis and / or the b-axis oriented structure. may not be aligned.

[0164] In addition, for example, CAAC-OS shows bright spots in the electron diffraction pattern. In particular, when using electron beams with a beam diameter of 10 nm or less, or 5 nm or less, The electron beam diffraction pattern obtained using this method is called a microelectron beam diffraction pattern.

[0165] FIG. 8(A) shows an example of an electron microbeam diffraction pattern of a sample having a CAAC-OS. In this example, the sample was cut in a direction perpendicular to the CAAC-OS surface to obtain a thickness of about 40 nm. In addition, the electron beam with a beam diameter of 1 nmφ is used to cut the sample. The electron diffraction pattern of CAAC-OS is shown in Fig. 8(A). It can be seen that spots are observed.

[0166] The crystal part included in the CAAC-OS has a c-axis that is a normal vector of the surface on which the CAAC-OS is formed. The direction is parallel to the vector or surface normal vector and perpendicular to the ab plane. When viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in a triangular or hexagonal shape. Atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. In this specification, the a-axis and the b-axis may be oriented in different directions. When described, the range includes 80° to 100°, preferably 85° to 95°. In addition, when simply describing it as parallel, it is -10° or more and 10° or less, preferably The range from -5° to 5° is also included.

[0167] The c-axis of the crystalline part in the CAAC-OS is aligned along the normal vector of the CAAC-OS surface. The CAAC-OS shape (surface shape) is aligned parallel to the normal vector of the surface. Depending on the cross-sectional shape of the forming surface or the cross-sectional shape of the surface, they may face in different directions. In addition, the crystallization process such as heat treatment was performed when the film was formed or after it was formed. Therefore, the c-axis of the crystal is aligned along the surface where the CAAC-OS is formed. The vectors are aligned parallel to the normal vector of the surface or the surface normal vector.

[0168] For example, the CAAC-OS can be formed by reducing the impurity concentration. Here, the impurities are the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon have a higher molecular weight than the metal elements that make up oxide semiconductors. Therefore, when the element removes oxygen from the oxide semiconductor, the oxide It can disrupt the atomic arrangement of semiconductors and reduce their crystallinity. Heavy metals, argon, carbon dioxide, etc. have large atomic (or molecular) radii, so they are easily oxidized. This can disrupt the atomic arrangement of the oxide semiconductor and reduce the crystallinity of the oxide semiconductor. The AAC-OS is an oxide semiconductor with a low impurity concentration. Impurities may act as a carrier generation source.

[0169] In the CAAC-OS, the distribution of the crystal parts may not be uniform. In the process of forming the -OS, when crystal growth is performed from the surface side of the oxide semiconductor, The proportion of crystalline parts may be higher near the surface than near the surface. When impurities are mixed into the OS, the crystalline part becomes amorphous or may become microcrystalline.

[0170] In addition, the CAAC-OS can be formed by, for example, reducing the density of defect states. In an oxide semiconductor, for example, oxygen vacancies are defect states. They can act as a site for charge transport or as a carrier source by capturing hydrogen. In order to form a C-OS, it is important to prevent oxygen vacancies from occurring in the oxide semiconductor. Therefore, the CAAC-OS is an oxide semiconductor with a low density of defect states. CAAC-OS is an oxide semiconductor with few oxygen vacancies.

[0171] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or real A highly pure intrinsic oxide semiconductor is a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. Since there are few carrier generation sources, it may be possible to reduce the carrier density. The threshold voltage of a transistor including an oxide semiconductor in a channel formation region is In some cases, the electrical characteristics are less likely to be normally on. A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor has a low density of defect states; The density of trap states may also be reduced. The transistors used in the present invention have little fluctuation in electrical characteristics and are therefore highly reliable. Note that it takes a certain amount of time for the charge trapped in the trap level of the oxide semiconductor to disappear. The charge may remain in the trap state for a long time and behave as if it were a fixed charge. A transistor that uses a high-density oxide semiconductor for the channel formation region has unstable electrical characteristics. This may be the case.

[0172] In addition, a transistor using a CAAC-OS that is highly intrinsic or substantially highly intrinsic The electrical characteristics of this material change little when exposed to visible or ultraviolet light.

[0173] The CAAC-OS can be formed, for example, by a sputtering method using a DC power source. can.

[0174] The oxide semiconductor may have, for example, polycrystals. This is called a polycrystalline oxide semiconductor. The polycrystalline oxide semiconductor includes a plurality of crystal grains.

[0175] In the polycrystalline oxide semiconductor, for example, crystal grains can be confirmed in the observation image by TEM. In a TEM image, for example, crystal grains contained in a polycrystalline oxide semiconductor are 2nm to 300nm, 3nm to 100nm, or 5nm to 50nm In addition, polycrystalline oxide semiconductors are often characterized by the following characteristics when observed by TEM: In some cases, the boundaries between crystal grains can be confirmed. In addition, the polycrystalline oxide semiconductor is, for example, In some cases, grain boundaries can be identified in TEM images.

[0176] The polycrystalline oxide semiconductor has, for example, a plurality of crystal grains, and the crystal grains have different orientations. In addition, the polycrystalline oxide semiconductor may be measured by, for example, an XRD apparatus. When performing out-of-plane analysis, single or multiple peaks may appear. For example, in polycrystalline In-Ga-Zn-O, the 2θ value indicating the orientation is at a peak near 31°. In some cases, multiple peaks may appear, indicating multiple orientations. The body may be observed as a spot in, for example, an electron diffraction pattern.

[0177] For example, a polycrystalline oxide semiconductor has high crystallinity and therefore high electron mobility. Therefore, a transistor in which a polycrystalline oxide semiconductor is used for a channel formation region has a high However, in the case of polycrystalline oxide semiconductors, impurities may segregate at grain boundaries. In addition, the grain boundaries of a polycrystalline oxide semiconductor become defect states. Since the field can become a carrier generation source and a trap state, the polycrystalline oxide semiconductor is used as a channel. The transistors used in the channel formation region are transistors using CAAC-OS in the channel formation region. Compared to transistors, the electrical characteristics vary greatly, making them less reliable. .

[0178] The polycrystalline oxide semiconductor can be formed by heat treatment at high temperature or laser light treatment. can.

[0179] The oxide semiconductor may have, for example, microcrystals. This is called a microcrystalline oxide semiconductor.

[0180] In the microcrystalline oxide semiconductor, for example, crystals can be clearly seen in the TEM observation image. The crystal parts contained in the microcrystalline oxide semiconductor may have a size of, for example, 1 nm or more. In particular, the size of the particles is often less than 00 nm, or between 1 nm and 10 nm. Microcrystals with a size between 1 nm and 10 nm are called nanocrystals (nc). The oxide semiconductor with nanocrystals is called nc-OS (nanocrystalline O xide Semiconductor). nc-OS is also known as, for example, TEM In the observation image, the boundary between the amorphous part and the crystalline part, and the boundary between the crystalline part and the crystalline part can be clearly confirmed. In addition, in the nc-OS, for example, clear grain boundaries are not observed in the TEM images. Since the nc-OS does not have any clear impurity segregation. Since it does not have grain boundaries, the defect density is unlikely to increase. For example, since there are no clear grain boundaries, the decrease in electron mobility is small.

[0181] For example, the nc-OS can be used in a microscopic area (e.g., an area of ​​1 nm to 10 nm). The atomic arrangement may have periodicity. In addition, the nc-OS may have, for example, crystalline parts and crystalline parts. There is no regularity between the atoms, so there is no periodicity in the atomic arrangement macroscopically, or in long-range Therefore, nc-OS may be non-ordered depending on the analytical method, e.g. In some cases, it may be difficult to distinguish nc-OS from amorphous oxide semiconductors. The analysis is performed by the out-of-plane method using X-rays with a beam diameter larger than the crystal part. In some cases, the peak indicating the orientation may not be detected. The electron beam diameter is larger than that of the conventional method (for example, 20 nmφ or more, or 50 nmφ or more). In the electron diffraction pattern of nc-O, a halo pattern may be observed. S is, for example, the beam diameter that is the same as or smaller than the crystal part (for example, 10 nmφ or less, In the ultrafine electron diffraction pattern using an electron beam of 5 nm diameter or less, spots were observed. In addition, the electron micro diffraction pattern of the nc-OS may show a circular pattern. In some cases, bright regions are observed. In addition, the electron micro diffraction pattern of nc-OS is For example, multiple spots may be observed within the region.

[0182] FIG. 8(B) shows an example of an electron microbeam diffraction pattern of a sample having an nc-OS. The sample was cut in a direction perpendicular to the surface on which the nc-OS was formed, and the thickness was about 40 nm. In this experiment, an electron beam with a diameter of 1 nm was aimed perpendicular to the cut surface of the sample. As shown in Fig. 8(B), the electron micro diffraction pattern of nc-OS is A bright area is observed, and multiple spots are observed within that area. It can be seen that.

[0183] nc-OS may have periodic atomic arrangement in a small area, so it is an amorphous oxide. However, the nc-OS has a lower defect level density than the crystalline semiconductor. Since there is no regularity between the layers, the density of defect states is higher than that of the CAAC-OS.

[0184] Therefore, the nc-OS may have a higher carrier density than the CAAC-OS. Oxide semiconductors with high carrier density can have high electron mobility. A transistor using an OS for a channel formation region can have high field-effect mobility. In addition, the nc-OS has a higher defect density than the CAAC-OS, and therefore the trap Therefore, in the case of a transistor using nc-OS for the channel formation region, The electrical characteristics of the transistors using CAAC-OS in the channel formation region are However, the nc-OS has a large variation in the transistors, which may result in unreliable transistors. It can be formed even if it contains a relatively large amount of impurities, so it has a smaller shape than CAAC-OS. This makes it easier to configure, and it may be suitable for some applications. For example, The nc-OS may be formed by a deposition method such as a sputtering method using an AC source. The sputtering method using a power supply is capable of depositing films with high uniformity on large substrates. A semiconductor device having a transistor in which the nc-OS is used for a channel formation region can be manufactured with high productivity. It can be made.

[0185] The oxide semiconductor may have, for example, an amorphous portion. An amorphous oxide semiconductor is, for example, a semiconductor in which the atomic arrangement is disordered. Alternatively, the amorphous oxide semiconductor may be formed of an amorphous material such as quartz. It has a structure in which no regularity is observed in the atomic arrangement.

[0186] In the case of an amorphous oxide semiconductor, for example, no crystal parts can be confirmed in a TEM image. There are cases where this is the case.

[0187] Amorphous oxide semiconductors are analyzed by the out-of-plane method using an XRD device. In addition, when the amorphous oxide semiconductor is used, for example, a peak indicating the orientation may not be detected. For example, a halo pattern may be observed in the electron diffraction pattern. For example, in the case of semiconductors, no spots can be observed in the ultrafine electron diffraction pattern, and halos Patterns may be observed.

[0188] The amorphous oxide semiconductor is formed by, for example, containing a high concentration of impurities such as hydrogen. Therefore, the amorphous oxide semiconductor may be, for example, It is an oxide semiconductor containing ZnO at a concentration of 1.0 to 2.0.

[0189] When an oxide semiconductor contains a high concentration of impurities, defect levels such as oxygen vacancies are generated in the oxide semiconductor. Therefore, an amorphous oxide semiconductor with a high impurity concentration has a defect state density In addition, amorphous oxide semiconductors have low crystallinity and are therefore different from CAAC-OS and nc-OS. The defect level density is relatively high.

[0190] Therefore, the amorphous oxide semiconductor may have a higher carrier density than the nc-OS. Therefore, a transistor in which an amorphous oxide semiconductor is used for a channel formation region has the following problems: Normally-on electrical characteristics may occur. Therefore, normally-on electrical characteristics are required. In some cases, an amorphous oxide semiconductor can be suitably used for a transistor in which a defect is eliminated. Since the density of recessed states is high, the density of trap states may also be high. Transistors that use semiconductors in the channel formation region include CAAC-OS and nc-OS. Compared to the transistors used in the channel formation region, the electrical characteristics of the transistors are more variable and less reliable. However, amorphous oxide semiconductors contain a relatively large amount of impurities. Since it can be formed by a film formation method that would normally be difficult, it is easy to form and can be used for various purposes. For example, a spin coating method, a sol-gel method, Dipping method, spray method, screen printing method, contact printing method, inkjet printing method Amorphous oxide semiconductors are formed by film formation methods such as roll coating and mist CVD. Therefore, a transistor including an amorphous oxide semiconductor in a channel formation region may be provided. Such a semiconductor device can be manufactured with high productivity.

[0191] Note that the oxide semiconductor may be a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or a non-crystalline oxide semiconductor. The mixed film may be a film having two or more kinds of amorphous oxide semiconductors. Oxide semiconductor region, microcrystalline oxide semiconductor region, polycrystalline oxide semiconductor region, CAAC In addition, the mixed film may have two or more regions, for example, , an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, The CAAC-OS region may have a laminated structure of two or more of these regions.

[0192] The oxide semiconductor may have, for example, a single crystal. The oxide semiconductor is called a single crystal oxide semiconductor.

[0193] For example, a single crystal oxide semiconductor has a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. The transistors used in the channel formation region rarely have normally-on electrical characteristics. In addition, since the density of defect states in a single crystal oxide semiconductor is low, the density of trap states is also low. Therefore, in a transistor using a single crystal oxide semiconductor for a channel formation region, In some cases, such a transistor has small fluctuations in electrical characteristics and can be highly reliable.

[0194] For example, the oxide semiconductor has a high density when it has few defects. For example, the density increases when the concentration of impurities such as hydrogen is low. It may be denser than AAC-OS. For example, CAAC-OS is a microcrystalline acid. In addition, polycrystalline oxide semiconductors may have a higher density than microcrystalline oxide semiconductors. In some cases, the density of a microcrystalline oxide semiconductor is higher than that of an amorphous oxide semiconductor. In some cases, the SiO 2 semiconductor may have a higher density than a porous oxide semiconductor.

[0195] Note that although the crystallinity of the oxide semiconductor layer has been described in detail here, In the device, a first oxide layer is provided in contact with an upper layer or a lower layer of the oxide semiconductor layer, and The second oxide layer is an oxide layer having the same main component as the oxide semiconductor layer. Similar to the conductor layer, the CAAC may be polycrystalline, microcrystalline, amorphous or single crystalline; A mixed film having two or more of these crystal states may also be used.

[0196] <<CAAC-OS film formation method>> The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0197] A flat sputtering particle has a circular equivalent diameter of 3 nm or more on a plane parallel to the ab plane. 0 nm or less, and the thickness (length in the direction perpendicular to the ab plane) is 0.7 nm or more and less than 1 nm. In addition, the flat sputtering particles have a surface parallel to the ab plane that is an equilateral triangle or hexagon. Here, the equivalent circle diameter of a face refers to the diameter of a perfect circle that is equal to the area of ​​the face.

[0198] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0199] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is suppressed. Specifically, the substrate temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or higher. The film is formed at a temperature of 500℃ or less. By increasing the substrate temperature during film formation, a flat sputtering When the sputtering particles reach the substrate, migration occurs on the substrate, and the sputtering particles The flat surface of the sputtering particle is attached to the substrate. At this time, the sputtering particle is positively charged, The sputtering particles adhere to the substrate while repelling each other, so the sputtering particles are unevenly distributed. A CAAC-OS film having a uniform thickness can be formed without uneven overlapping.

[0200] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be reduced. In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of 80° C. or less, preferably −100° C. or less, is used.

[0201] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0202] Alternatively, the CAAC-OS film is formed by the following method.

[0203] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. 00℃ or less, preferably 150℃ to 450℃, and the oxygen ratio in the deposition gas is 30 % or more, preferably 100% by volume.

[0204] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. In the case of a heat treatment in an inert atmosphere, the heat treatment is first performed in an oxidizing atmosphere. By the heat treatment in air, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In that case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be performed at 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The deposition may be performed under reduced pressure of 1 Pa or less. Under reduced pressure, the impurity concentration of the first oxide semiconductor film is It can be reduced in a shorter time.

[0205] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with nanometers or more, it can be easily crystallized by heat treatment.

[0206] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more and 50 nm or more. The second oxide semiconductor film is formed to a thickness of 1 nm or less by sputtering. Specifically, the substrate temperature is set to 100° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower. The oxygen ratio in the deposition gas is set to 30% by volume or more, preferably 100% by volume. do.

[0207] Next, heat treatment is performed to form a second oxide semiconductor film from the first CAAC-OS film by solid phase growth. The heat treatment temperature was 350° C. The temperature is set to 450° C. or higher and 740° C. or lower, preferably 450° C. or higher and 650° C. or lower. The heat treatment is performed for 1 minute or more and 24 hours or less, preferably 6 minutes or more and 4 hours or less. The heat treatment may be performed in an active atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the treatment. The oxygen deficiency can be reduced by heat treatment in a 10 The pressure may be reduced to 00 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced in a shorter time. do.

[0208] In this manner, a CAAC-OS film having a total thickness of 10 nm or more can be formed. The CAAC-OS film can be suitably used as an oxide semiconductor layer in an oxide stack. It is possible.

[0209] Next, for example, the substrate is not heated, so that the surface to be formed is kept at a low temperature (for example, less than 130° C. Oxidation at temperatures below 100℃, below 70℃, or at room temperature (20℃ to 25℃) A method for forming the film will now be described.

[0210] When the surface to be formed is at a low temperature, the sputtered particles rain down irregularly on the surface to be formed. For example, because migration does not occur, the area includes areas where other sputtered particles have already accumulated. That is, the oxide film obtained by deposition has a uniform thickness, for example. The oxide film obtained in this way is not uniform, and the crystal orientation may be disordered. In order to maintain the crystallinity of the carbon particles to a certain extent, the carbon nanotube has crystalline parts (nanocrystals).

[0211] In addition, for example, when the pressure during film formation is high, the flying sputtered particles may be mixed with other gases such as argon. The frequency of collisions with particles (atoms, molecules, ions, radicals, etc.) increases. Sputtered particles are The crystal structure may be destroyed by collisions with other particles during flight (resputtering). For example, sputtered particles can maintain their flat shape by colliding with other particles. In some cases, the material cannot be broken down into individual atoms, and is fragmented (e.g., into individual atoms). Atoms separated from the particles are deposited on the surface to form an amorphous oxide film. There are cases.

[0212] In addition, the sputtering method uses a liquid instead of a target having a polycrystalline oxide. In the case of a method of forming a film by gasifying a solid such as a target, In this case, the atoms fly apart and deposit on the surface, forming an amorphous oxide film. In addition, for example, in the laser ablation method, the target emits The ejected atoms, molecules, ions, radicals, clusters, etc. fly and deposit on the surface to be treated. In some cases, an amorphous oxide film may be formed.

[0213] In a stacked structure of an oxide layer and an oxide semiconductor layer included in a transistor of one embodiment of the present invention, The first oxide layer, the oxide semiconductor layer, and the second oxide layer each include any one of the above-mentioned A crystalline oxide layer or an oxide semiconductor layer may be used. For the oxide semiconductor layer, a CAAC-OS film is preferably used.

[0214] In addition, when the oxide semiconductor layer is a CAAC-OS film, The second oxide layer is formed by growing crystals using the crystals of the oxide semiconductor layer as seed crystals. Therefore, if the first oxide layer and the second oxide layer are formed in the same manner, Even if the second oxide layer is formed using the same material and manufacturing method, it is possible to form the second oxide layer with a larger thickness than the first oxide layer. In some cases, a film with high crystallinity can be obtained. The crystallinity may differ between the contacting region and the non-contacting region.

[0215] As described above, the configurations, methods, etc. described in this embodiment mode may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0216] (Embodiment 3) As an example of a semiconductor device according to one embodiment of the present invention, a circuit diagram of a NOR circuit which is a logic circuit is shown in FIG. An example is shown in Figure 9(A), and Figure 9(B) is a circuit diagram of a NAND type circuit.

[0217] In the NOR circuit shown in FIG. 9A, a p-channel transistor 801 and 802 are semiconductor materials other than oxide semiconductors (e.g., silicon) in the channel formation region. The transistor is an n-channel transistor, such as a transistor 80. 3 and 804 are the transistors described in Embodiment 1 including an oxide stack including an oxide semiconductor. A transistor having a similar structure is used.

[0218] Transistors made of semiconductor materials such as silicon can operate at high speeds. A transistor using a semiconductor is capable of holding charge for a long period of time due to its characteristics.

[0219] In order to miniaturize the logic circuit, n-channel transistors 803 and 8 04 is stacked on p-channel transistors 801 and 802. For example, it is preferable to form the transistors 801 and 802 using a single crystal silicon substrate. Transistors 803 and 804 are formed on the transistors 801 and 802 via an insulating layer. It is possible to achieve this.

[0220] In the NOR circuit shown in FIG. 9A, the transistors 803 and 804 are The transistor 230 has a similar configuration to the transistor 230, and controls the potential of the second gate electrode. For example, by setting the threshold voltage of the transistors 803 and 804 to GND, , and further, the transistor can be a normally-off transistor.

[0221] In the NAND circuit shown in FIG. 9B, the transistor is a p-channel transistor. The transistors 811 and 814 have a channel formation region formed of a semiconductor material other than an oxide semiconductor (for example, The transistor is an n-channel transistor. The oxide stacks 812 and 813 include oxide semiconductors. A transistor having a structure similar to that of the MOS transistor is used.

[0222] In the NAND circuit illustrated in FIG. 9B, the transistors 812 and 813 are The transistor 230 has a similar structure to the transistor 230, and the potential of the second gate electrode is controlled. For example, by setting the input terminal to GND, the threshold voltage of the transistors 812 and 813 becomes more positive. Furthermore, it can be a normally-off transistor.

[0223] In addition, similar to the NOR circuit shown in FIG. 9(A), in order to reduce the size of the logic circuit, The transistors 812 and 813 are p-channel transistors. It is preferable that the second transistor 813 is stacked on the transistors 811 and 814 .

[0224] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using transistors with extremely small capacitance, power consumption can be significantly reduced. .

[0225] In addition, stacking semiconductor elements using different semiconductor materials allows for miniaturization and high integration. A semiconductor device having stable and high electrical characteristics and a method for manufacturing the semiconductor device A method can be provided.

[0226] In addition, by using the structure of the transistor described in Embodiment 1, the reliability and stability of the semiconductor device can be improved. It is possible to provide NOR type circuits and NAND type circuits that exhibit consistent characteristics.

[0227] In this embodiment, a NOR circuit using the transistor described in Embodiment 1 and an NOR Although an example of an AND-type circuit is shown, the present invention is not limited to this and may be used to form an AND-type circuit, an OR circuit, etc. It is also possible.

[0228] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0229] (Embodiment 4) In this embodiment mode, the transistor described in Embodiment 1 is used, and the transistor is used in a case where power is not supplied. However, it is possible to retain memory contents and there is no limit to the number of times it can be written to. An example of the above will be described with reference to the drawings.

[0230] FIG. 10A is a circuit diagram showing the semiconductor device of the present embodiment.

[0231] The transistor 260 in FIG. 10A is made of a semiconductor material other than an oxide semiconductor (for example, This allows the use of transistors using silicon (e.g., silicon nitride), making high-speed operation easy. The transistor 262 includes an oxide stack including an oxide semiconductor. A transistor having a structure similar to that of a conventional transistor can be applied, and its characteristics allow it to operate for a long time. This allows charge retention between the electrodes.

[0232] It should be noted that the above transistors are all n-channel transistors. However, the transistor used in the semiconductor device described in this embodiment is a p-channel transistor. A transistor may also be used.

[0233] In FIG. 10A, the first wiring (1st Line) and the source of the transistor 260 The second wiring (2nd Lin) is electrically connected to either the drain electrode layer or the drain electrode layer. e) and the other of the source electrode layer or the drain electrode layer of the transistor 260 are electrically connected In addition, the third wiring (3rd Line) and the source electrode of the transistor 262 The fourth line is electrically connected to either the drain electrode layer or the drain electrode layer. and the gate electrode layer of the transistor 262 are electrically connected to each other. A gate electrode layer of the transistor 260 and a source electrode layer or a drain electrode layer of the transistor 262 The other of the electrodes is electrically connected to one of the electrodes of the capacitance element 264 and is a fifth wiring (5th ne) is electrically connected to the other electrode of the capacitor 264.

[0234] In the semiconductor device shown in FIG. 10A, the potential of the gate electrode layer of the transistor 260 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0235] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 262 is turned on by applying a potential to the transistor 262. The potential of the third wiring is applied to the gate electrode layer of the transistor 260 and the capacitor 264. That is, a predetermined charge is applied to the gate electrode layer of the transistor 260. (Write). Here, the charges that give two different potential levels (hereafter, low-level charges) Then, the fourth wiring The potential of the transistor 262 is set to a potential at which the transistor 262 is turned off. By setting the transistor 260 in the ON state, the charge applied to the gate electrode layer of the transistor 260 is held. (retain).

[0236] Since the off-state current of the transistor 262 is extremely small, the gate electrode layer of the transistor 260 The charge is retained for a long time.

[0237] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 260 Depending on the amount of charge held in the electrode layer, the second wiring has a different potential. If the transistor 260 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 260. The apparent threshold voltage V for a given charge th_H The gate of transistor 260 The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 260 is turned "on". The term "potential of the fifth wiring" refers to the potential of the fifth wiring required to achieve the "state". The potential of V th_H and V th_L By setting the potential V0 between the For example, in writing, the charge applied to the gate electrode layer of the If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) Then When a low level charge is applied, transistor 260 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 260 is "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0238] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 260 is in the "off state" regardless of th_H Alternatively, the potential of the fifth wiring may be lower than that of the fifth wiring. The potential at which the transistor 260 is in the "on" state, i.e., V th_L Higher potential should be applied to the fifth wire.

[0239] FIG. 10B shows an example of a structure of a different memory device. FIG. 10(C) is a conceptual diagram showing an example of a semiconductor device. The semiconductor device shown in FIG. 10(B) will be described first, followed by the semiconductor device shown in FIG. 10(C). The location will be explained below.

[0240] In the semiconductor device shown in FIG. 10B, the bit line BL and the source voltage of the transistor 262 The word line WL is electrically connected to one of the electrode layer and the drain electrode layer of the transistor 2. 62 is electrically connected to the gate electrode layer of the transistor 262. The other of the drain electrode layers and a first terminal of the capacitance element 254 are electrically connected.

[0241] The transistor 262 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 262 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long period of time. It is possible to retain it.

[0242] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. The case where the above is performed will be explained.

[0243] First, the potential of the word line WL is set to a potential at which the transistor 262 is turned on. The transistor 262 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal of the transistor 2 By setting the potential at which the transistor 262 is turned off, the capacitance The potential of the first terminal of the quantum element 254 is held (held).

[0244] Since the off-state current of the transistor 262 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitive element) can be held for a long period of time.

[0245] Next, the reading of information will be described. When the transistor 262 is turned on, The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0246] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is In this case, the potential of the first terminal of the capacitance element 254 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is held (=(CB × VB0+C×V0) / (CB+C)).

[0247] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0248] As described above, in the semiconductor device illustrated in FIG. 10B, the off-state current of the transistor 262 is extremely low. Due to its small size, the charge stored in the capacitance element 254 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to reduce the power consumption to an extremely low level, the power consumption can be reduced sufficiently. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. be.

[0249] Next, the semiconductor device shown in FIG.

[0250] The semiconductor device shown in FIG. 10C has a memory cell shown in FIG. 10B as a memory circuit thereon. The memory cell array 251a and the memory cell array 251b each having a plurality of memory cells 250 are provided. At the bottom, the memory cell array 251 (memory cell array 251a and memory cell array 25 1b) has a peripheral circuit 253 required for operating the memory device. The memory cell array 251 is electrically connected to the memory cell array 251 .

[0251] By using the configuration shown in FIG. 10C, the peripheral circuit 253 is connected to the memory cell array 251. (Memory cell array 251a and memory cell array 251b) Therefore, the semiconductor device can be made smaller.

[0252] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 262. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. Alternatively, organic semiconductor materials may be used. The transistor can operate at a sufficiently high speed. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require high speed operation. be.

[0253] In the semiconductor device shown in FIG. 10C, two memory cell arrays 251 (memory cell In the illustrated embodiment, a stacked memory cell array 251a and a stacked memory cell array 251b are used. The number of memory cell arrays to be stacked is not limited to this. The configuration may be such that:

[0254] The transistor 262 is a transistor in which an oxide semiconductor is used for a channel formation region. By using this function, it is possible to retain the memory contents for a long period of time. Semiconductor memory that does not require a refresh operation or that requires a very infrequent refresh operation Since it is possible to use the memory device as a storage device, power consumption can be reduced sufficiently.

[0255] In addition, the semiconductor device shown in this embodiment may be provided with the oxide film serving as the channel region shown in the first embodiment. By applying a transistor in which the oxide semiconductor layer is moved away from the surface of the oxide stack, A semiconductor device that is highly reliable and exhibits stable electrical characteristics can be provided.

[0256] (Embodiment 5) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, An example of application to an electronic device such as a child book will be described with reference to FIGS.

[0257] FIG. 11 shows a block diagram of an electronic device. The electronic device shown in FIG. A digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply Circuit 905, application processor 906, flash memory 910, display A controller 911, a memory circuit 912, a display 913, a touch sensor 919, The display 913 is a display. The image display device is configured with an application section 914, a source driver 915, and a gate driver 916. The application processor 906 is a CPU 907, a DSP 908, and an interface (IF Generally, the memory circuit 912 is composed of an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment for this portion, High speed writing and reading, long-term memory retention, and low power consumption Therefore, it is possible to provide a highly reliable electronic device.

[0258] FIG. 12 shows a display memory circuit 950 using the semiconductor device described in the previous embodiment. The memory circuit 950 shown in FIG. The memory controller 951 is also configured with a switch 954, a switch 955, and a memory controller 951. The memory circuit receives image data (input image data) input from a signal line, a memory 952, and The data (stored image data) stored in the memory 953 is read and controlled by the disk drive 955. Displayed by a signal from a spray controller 956 and a display controller 956 A display 957 for displaying the image is connected.

[0259] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then The image is sent to a display 957 via a switch 955 and a display controller 956. , will be displayed.

[0260] If there is no change in the input image data A, the stored image data A is usually 30Hz or more and 60Hz or less. The display controller 952 outputs the signal to the display device 953 via the switch 955 at a period of about 100 ms. Read from 56.

[0261] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This readout is followed by the next new image data being stored in the memory. This continues until the data is stored in the memory 952.

[0262] In this way, the memory 952 and the memory 953 alternately write image data and receive image data. The display 957 is displayed by reading out the data from the memory 9 The memory 52 and the memory 953 are not limited to being separate memories, but may be one memory divided and used. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, information can be written and read at high speeds and memory can be retained for long periods of time. Moreover, the power consumption can be sufficiently reduced. A highly reliable semiconductor device that is less susceptible to such influences can be obtained.

[0263] FIG. 13 shows a block diagram of an electronic book. FIG. 13 shows a battery 1001, a power supply circuit 1002, , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard A code 1006, a memory circuit 1007, a touch panel 1008, a display 1009, The display controller 1010 is configured as a display controller.

[0264] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The memory circuit 1007 has a function of temporarily storing the contents of a book. For example, when the user uses the highlight function, the memory circuit 1007 stores the The highlight function is a function that allows users to highlight the parts of an e-book that they have read. When you are reading, you can mark a specific part by, for example, changing the color of the display or underlining. Marking by drawing lines, making letters thicker, or changing the font of letters to differentiate them from the surroundings The memory circuit 1007 is used for short-term information storage and long-term information storage. The data held in the memory circuit 1007 is copied to the flash memory 1004. Even in such a case, the semiconductor device described in the above embodiment may be adopted. This allows information to be written and read at high speed, and to be stored for a long period of time. In addition, the power consumption can be sufficiently reduced. Therefore, a highly reliable semiconductor device that is not easily affected can be obtained.

[0265] FIG. 14 shows a specific example of an electronic device. FIG. 14(A) and FIG. 14(B) show a foldable tab. FIG. 14(A) shows the tablet terminal in an open state. 9630, display unit 9631a, display unit 9631b, display mode changeover switch 9034 , power switch 9035, power saving mode switch 9036, fastener 9033, operation The switch 9038 is a switch for controlling the operation of the power supply 9036.

[0266] The semiconductor device described in the above embodiment can be used for the display portion 9631a and the display portion 9631b. This makes it possible to make a highly reliable tablet-type terminal. The memory device shown in the embodiment may be applied to the semiconductor device of this embodiment.

[0267] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638, data can be input. In 1a, as an example, half of the area has a display function only, and the other half The display unit 96 has a touch panel function, but is not limited to this. The entire surface of 31a is made to display keyboard buttons to make it a touch panel, and the display part 9631b is displayed It can be used as a screen.

[0268] In addition, in the display unit 9631b, as in the display unit 9631a, The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard button can be displayed on the display portion 9631b.

[0269] In addition, the touch panel area 9632a and the touch panel area 9632b can be touched simultaneously. You can also input the character.

[0270] A display mode changeover switch 9034 is used to change the display orientation, such as portrait or landscape. You can choose between black and white and color display. The 9036 is a tablet-type device that detects external light during use using a built-in light sensor. The tablet device has a light sensor, which can adjust the display brightness to suit the amount of light. In addition to the sensor, other detection devices such as gyro, acceleration sensor, etc. that detect the inclination are also included. It may be built-in.

[0271] FIG. 14A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. For example, one display panel may have a higher resolution than the other. It is also possible to use the following.

[0272] FIG. 14B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 96 33, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636 In addition, in FIG. 14B, a battery 9635 is used as an example of the charge and discharge control circuit 9634. , a configuration having a DC-DC converter 9636 is shown.

[0273] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the durability can be improved. This makes it possible to provide a tablet terminal that is highly durable and reliable even for long-term use.

[0274] In addition, the tablet terminals shown in Figs. 14(A) and 14(B) can be used in various Functions that display information (still images, videos, text images, etc.), calendars, dates or times A function to display the information on the display, and a function to operate the information displayed on the display by touch input or editing. It has touch input function, function to control processing by various software (programs), etc. It is possible.

[0275] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0276] 100 Substrates 102 Undercoat insulation layer 103 Gate electrode layer 104 First oxide layer 106 Oxide semiconductor layer 106a Channel formation region 106b Channel formation region 106c Channel formation region 108 Second oxide layer 110 Oxide stack 112a Source electrode layer 112b Drain electrode layer 114 Gate Insulation Layer 116 Gate electrode layer 200 Transistors 210 Transistor 220 Transistor 230 Transistor 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b Memory Cell Array 253 Peripheral Circuits 254 Capacitive element 260 Transistors 262 Transistor 264 Capacitive element 801 Transistors 802 Transistor 803 Transistor 804 Transistor 811 Transistor 812 Transistor 813 Transistor 814 Transistor 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 Keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller 9033 Fastener 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9630 Case 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / discharge control circuit 9635 Battery 9636 DC-DC Converter 9638 Operation key 9639 Button

Claims

[Claim 1] an oxide semiconductor layer including at least first and second channel formation regions; a first oxide layer provided in contact with a lower surface of the oxide semiconductor layer; a second oxide layer provided in contact with an upper surface of the oxide semiconductor layer; a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer; a gate electrode layer provided over the oxide semiconductor layer and overlapping side surfaces and an upper surface of the first and second channel formation regions; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode layer.

Images