Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device having a trench gate structure in which unit cells with a FinFET structure are arranged, the silicon carbide semiconductor device being capable of improving breakdown voltage, and a method of manufacturing a silicon carbide semiconductor device.SOLUTION: A first p+-type region 31 faces the bottom face of a gate trench 6, is provided at a distance from a p-type base region 3, and linearly extends in a first direction X. The first p+-type regions 31 adjacent to each other extend directly below a p++-type contact region 5 between the gate trenches 6 adjacent to each other and are connected. A second p+-type region 32 is provided between the p-type base region 3 and the first p+-type region 31 at a portion between the gate trenches 6 adjacent to each other. The first and second p+-type regions 31, 32 are not provided directly below an n+-type source region 4. The width w21 of a portion of the first p+-type region 31 directly below the gate trench 6 in the second direction Y is equal to or less than the width w1 of the gate trench 6 in the second direction Y, and is wider than a Fin width w11.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices and methods of manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] The following Non-Patent Document 1 and the following Patent Document 1 describe a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) having a trench gate structure in which a unit cell (functional unit of an element) having a FinFET structure is arranged. The following Patent Documents 2 and 3 describe a trench gate structure in which a p-type region for alleviating an electric field is arranged at the bottom of a gate trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6631632 [Patent Document 2] Patent Publication No. 2022-010335 [Patent Document 3] Patent Publication No. 2021-012934 [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned Non-Patent Document 1 and Patent Document 1, the fin width (the width between adjacent gate trenches) is narrow, which causes a problem that the electric field strength at the bottom of the gate trench becomes large when the device is off, and the electric field is concentrated in the gate insulating film at the bottom of the gate trench, resulting in a low breakdown voltage.

[0006] An object of the present disclosure is to provide a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged, and capable of improving the breakdown voltage, and a method for manufacturing the silicon carbide semiconductor device. [Means for solving the problem]

[0007] A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A gate trench penetrates the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region.

[0008] A first high concentration region of a second conductivity type is provided at a position facing the bottom surface of the gate trench. The first high concentration region has a higher impurity concentration than the second semiconductor region. A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first high concentration region. A second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces over the entire area of ​​the second semiconductor region between the adjacent gate trenches. The width of the first high concentration region is equal to or smaller than the width of the gate trench and is wider than the width between the adjacent gate trenches. Effect of the Invention

[0009] ADVANTAGEOUS EFFECT OF THE DISCLOSURE According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present disclosure, it is possible to provide a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged, and to thereby achieve an effect of improving the breakdown voltage. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device in accordance with a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. [Figure 4] FIG. 11 is a cross-sectional view showing a structure of a semi-silicon carbide conductor device according to a second embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a structure of a silicon semicarbide conductor device according to a third embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a structure of a silicon semicarbide conductor device according to a third embodiment. [Figure 7] 11A to 11C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to a third embodiment. [Figure 8] 11A to 11C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to a third embodiment. [Figure 9] 11A to 11C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to a third embodiment. [Figure 10] 11A to 11C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to a third embodiment. [Figure 11] FIG. 13 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 12] FIG. 13 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 14] FIG. 13 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing a structure of a semi-silicon carbide conductor device according to a fifth embodiment. [Figure 16] 1 is a cross-sectional view showing a structure in the vicinity of a gate trench in Comparative Example 1. FIG. [Figure 17] 11 is a cross-sectional view showing a structure in the vicinity of a gate trench in Comparative Example 2. FIG. [Figure 18] 13 is a characteristic diagram showing the results of a simulation of the relationship between the TBP width W_TBP and the trench width W_Trench in Comparative Examples 1 and 2. FIG. [Figure 19] 13 is a characteristic diagram showing the results of a simulation of the relationship between the TBP width W_TBP and the trench width W_Trench in Comparative Examples 1 and 2. FIG. [Figure 20] 13 is a characteristic diagram showing the results of a simulation of the relationship between the TBP width W_TBP and the trench width W_Trench in Comparative Examples 1 and 2. FIG. [Figure 21] 13 is a characteristic diagram showing the results of a simulation of the relationship between the TBP width W_TBP and the trench width W_Trench in Comparative Examples 1 and 2. FIG. [Figure 22] 1 is a plan view showing a layout of a silicon carbide semiconductor device of a reference example as viewed from the front surface side of a semiconductor substrate. FIG. [Figure 23] 23 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 22. [Figure 24] 23 is a cross-sectional view showing a cross-sectional structure taken along line BB-BB' in FIG. 22. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] <Overview of the embodiment of the present disclosure> (1) A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A gate trench penetrates the fourth semiconductor region, the third semiconductor region and the second semiconductor region to reach the first semiconductor region.

[0012] A first high concentration region of a second conductivity type is provided at a position facing the bottom surface of the gate trench. The first high concentration region has a higher impurity concentration than the second semiconductor region. A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first high concentration region. A second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces over the entire area of ​​the second semiconductor region between the adjacent gate trenches. The width of the first high concentration region is equal to or smaller than the width of the gate trench and is wider than the width between the adjacent gate trenches.

[0013] According to the above disclosure, the gate insulating film at the bottom of the gate trench is protected by the first high concentration region, and the electric field applied to the gate insulating film at the bottom of the gate trench is alleviated, so that the breakdown voltage can be improved. In addition, by making the width of the first high concentration region equal to or smaller than the width of the gate trench, an increase in on-resistance due to JFET resistance can be suppressed.

[0014] (2) In the silicon carbide semiconductor device according to the present disclosure described above in (1), a width of the first heavily doped region may be 75% or more of a width of the gate trench.

[0015] According to the above disclosure, the electric field applied to the gate insulating film at the bottom surface of the gate trench can be made 3 MV / cm or less.

[0016] (3) In the silicon carbide semiconductor device according to the present disclosure described above in (1) or (2), the first heavily doped region may have a depth equal to or greater than a width between adjacent gate trenches.

[0017] According to the above disclosure, it is possible to obtain the effect of the double gate structure (reduction of the on-resistance) and also to secure a predetermined breakdown voltage to obtain a predetermined withstand voltage.

[0018] (4) In the silicon carbide semiconductor device according to any one of (1) to (3) above, the first highly doped region may have a depth of 0.8 μm or more.

[0019] According to the above disclosure, it is possible to obtain the effect of the double gate structure, and at the same time, it is possible to ensure a predetermined breakdown voltage and obtain a predetermined withstand voltage.

[0020] (5) In the silicon carbide semiconductor device according to any one of (1) to (4) described above, the gate trench may extend linearly in a first direction parallel to the first main surface of the semiconductor substrate, and the third semiconductor region and the fourth semiconductor region may be alternately and repeatedly disposed in the first direction between the gate trenches adjacent to each other.

[0021] According to the above disclosure, the width between adjacent gate trenches can be narrowed to a predetermined width to form a double gate structure.

[0022] (6) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (5), a second high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region is selectively provided in contact with the second semiconductor region at a position facing the fourth semiconductor region in the depth direction between the gate trenches adjacent to each other. The first high concentration region may be electrically connected to the second semiconductor region via the second high concentration region.

[0023] According to the above disclosure, by electrically connecting the first high concentration region to the second semiconductor region via the second high concentration region, the width of the first high concentration region can be made equal to or smaller than the width of the gate trench.

[0024] (7) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (6), the first high concentration regions adjacent to each other in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction are partially connected to each other at a position facing the second high concentration region in the depth direction. The second high concentration region may be in contact with the first high concentration region in the depth direction.

[0025] According to the above disclosure, the width of the first high concentration region, except for the portion connected to the adjacent first high concentration region, can be made equal to or smaller than the width of the gate trench.

[0026] (8) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (6), the second high concentration region may reach a position deeper toward the second electrode than a bottom surface of the gate trench, and may be adjacent to the first high concentration region in a second direction that is parallel to the first main surface of the semiconductor body and perpendicular to the first direction.

[0027] According to the above disclosure, the width of the first high concentration region can be made equal to or smaller than the width of the gate trench as a whole.

[0028] (9) A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region.

[0029] The gate trench penetrates the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region. A first high concentration region of a second conductivity type is provided at a position facing a bottom surface of the gate trench. The first high concentration region has a higher impurity concentration than the second semiconductor region. A second high concentration region of a second conductivity type is selectively provided between the adjacent gate trenches in contact with the second semiconductor region. The second high concentration region has a higher impurity concentration than the second semiconductor region. A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, the first high concentration region, and the second high concentration region.

[0030] A second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces throughout the entire area of ​​the second semiconductor region between the adjacent gate trenches. The gate trenches extend linearly in a first direction parallel to the first main surface of the semiconductor substrate. The third semiconductor region and the fourth semiconductor region are repeatedly arranged alternately in the first direction between the adjacent gate trenches. The second high concentration region is provided at a position facing the fourth semiconductor region in the depth direction. The first high concentration region is electrically connected to the second semiconductor region via the second high concentration region.

[0031] According to the above disclosure, the gate insulating film at the bottom of the gate trench is protected by the first high concentration region, and the electric field applied to the gate insulating film at the bottom of the gate trench is alleviated, so that the breakdown voltage can be improved. In addition, by electrically connecting the first high concentration region to the second semiconductor region via the second high concentration region, the width of the first high concentration region can be made equal to or smaller than the width of the gate trench. By making the width of the first high concentration region equal to or smaller than the width of the gate trench, an increase in on-resistance due to JFET resistance can be suppressed.

[0032] (10) Furthermore, in the silicon carbide semiconductor device according to this disclosure, in any one of (1) to (5) described above, the first high concentration region may extend toward the first electrode along a sidewall of the gate trench at a position facing the fourth semiconductor region in the depth direction and contact the second semiconductor region.

[0033] According to the above disclosure, the first high concentration region can be directly connected to the second semiconductor region. By not providing the second high concentration region, the spreading resistance of carriers is reduced.

[0034] (11) A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A gate trench penetrates the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region. A first high concentration region of a second conductivity type is selectively provided at a position facing a bottom surface of the gate trench. The first high concentration region has a higher impurity concentration than the second semiconductor region.

[0035] A gate electrode is provided inside the gate trench via a gate insulating film. The first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first high concentration region. The second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces in the entire area of ​​the second semiconductor region between the adjacent gate trenches. The gate trench extends linearly in a first direction parallel to the first main surface of the semiconductor substrate. The third semiconductor region and the fourth semiconductor region are alternately and repeatedly arranged in the first direction between the adjacent gate trenches. The first high concentration region extends toward the first electrode along the sidewall of the gate trench at a position facing the fourth semiconductor region in the depth direction and contacts the second semiconductor region.

[0036] According to the above disclosure, the first high concentration region can be directly connected to the second semiconductor region. By not providing the second high concentration region, the spreading resistance of carriers is reduced.

[0037] (12) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in any one of (6) to (11) described above, the first high concentration region does not have to be provided at a position facing the third semiconductor region in the depth direction.

[0038] According to the above disclosure, an increase in JFET resistance can be suppressed.

[0039] (13) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in any one of (6) to (9) described above, the second high concentration region may not be provided at a position facing the third semiconductor region in the depth direction.

[0040] According to the above disclosure, an increase in JFET resistance can be suppressed.

[0041] (14) Furthermore, the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), (9) or (11), may further comprise a fifth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region, the fifth semiconductor region being provided between the second semiconductor region and the first semiconductor region, in contact with the second semiconductor region and the first semiconductor region, and terminating on the second electrode side at the same depth position as the first high concentration region.

[0042] According to the above disclosure, the spreading resistance of carriers can be reduced.

[0043] (15) A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A gate trench penetrates the fourth semiconductor region, the third semiconductor region and the second semiconductor region to reach the first semiconductor region.

[0044] A gate insulating film is provided along the inner wall of the gate trench. A gate electrode is provided on the gate insulating film inside the gate trench. A first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, and the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces over the entire area of ​​the second semiconductor region between the adjacent gate trenches. The thickness of the gate insulating film at the bottom surface of the gate trench is thicker than the thickness of the gate insulating film on the sidewall of the gate trench and is thicker than the width between the adjacent gate trenches.

[0045] According to the above disclosure, since the breakdown voltage of the gate insulating film is increased, the gate insulating film at the bottom of the gate trench can be protected without providing the first and second high concentration regions, and the breakdown voltage can be improved. By not providing the first and second high concentration regions, the spreading resistance of carriers is reduced.

[0046] (16) Furthermore, the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (15), may further include a fifth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region, the fifth semiconductor region being provided between the second semiconductor region and the first semiconductor region, in contact with the second semiconductor region and the first semiconductor region, and reaching a side of the second electrode beyond a bottom surface of the gate trench.

[0047] According to the above disclosure, the spreading resistance of carriers can be reduced.

[0048] (17) A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present disclosure is the method for manufacturing a silicon carbide semiconductor device according to (1) or (9) above, as follows: A first step of forming the semiconductor base by sequentially stacking a first conductivity type silicon carbide layer to become the first semiconductor region and a second conductivity type silicon carbide layer to become the second semiconductor region is performed. A second step of selectively forming the third semiconductor region in a surface region of the second conductivity type silicon carbide layer is performed. A third step of selectively forming the fourth semiconductor region in the surface region of the second conductivity type silicon carbide layer is performed. A fourth step of forming the gate trench that penetrates the second conductivity type silicon carbide layer in a depth direction to expose the fourth semiconductor region, the third semiconductor region, and the second semiconductor region on a sidewall, reaches the first conductivity type silicon carbide layer, and exposes the first semiconductor region on a bottom surface. A fifth step is performed in which a second conductivity type impurity is ion-implanted into the bottom surface of the gate trench from a direction perpendicular to the first main surface of the semiconductor substrate to form the first high concentration region in a surface region of the first conductivity type silicon carbide layer exposed at the bottom surface of the gate trench. After the fifth step, a sixth step is performed in which a gate electrode is formed inside the gate trench via a gate insulating film.

[0049] According to the above disclosure, the first high concentration region having the same width as the gate trench can be formed in a self-aligned manner.

[0050] (18) A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present disclosure is the method for manufacturing a silicon carbide semiconductor device according to (11) above, as follows: A first step of forming the semiconductor base by sequentially stacking a first conductivity type silicon carbide layer to become the first semiconductor region and a second conductivity type silicon carbide layer to become the second semiconductor region is performed. A second step of selectively forming the third semiconductor region in a surface region of the second conductivity type silicon carbide layer is performed. A third step of selectively forming the fourth semiconductor region in the surface region of the second conductivity type silicon carbide layer is performed. A fourth step of forming the gate trench that penetrates the second conductivity type silicon carbide layer in a depth direction to expose the fourth semiconductor region, the third semiconductor region, and the second semiconductor region on a sidewall, reaches the first conductivity type silicon carbide layer, and exposes the first semiconductor region on a bottom surface. A fifth step is performed in which a second conductivity type impurity is ion-implanted into an inner wall of the gate trench from a direction oblique to the first main surface of the semiconductor substrate to form the first high concentration region in a surface region of the first conductivity type silicon carbide layer exposed on the inner wall of the gate trench. After the fifth step, a sixth step is performed in which a gate electrode is formed inside the gate trench via a gate insulating film.

[0051] According to the above disclosure, the first high concentration region can be locally connected to the second semiconductor region, and the process of forming the second high concentration region can be omitted, thereby improving the throughput of the manufacturing process.

[0052] <Foundational knowledge of this disclosure> First, the structure of a silicon carbide semiconductor device of a reference example will be described. Fig. 22 is a plan view showing a layout of the silicon carbide semiconductor device of the reference example as viewed from the front surface side of the semiconductor substrate. + type source region 104 and p ++22. The layout (hatched portion) of the contact region 105 is shown. Figures 23 and 24 are cross-sectional views showing cross-sectional structures taken along the cutting lines AA-AA' and BB-BB' in Figure 22, respectively. A silicon carbide semiconductor device 110 of a reference example shown in Figures 22 to 24 is a vertical SiC-MOSFET with a trench gate structure having a MOS gate 109 constituting a unit cell (functional unit of an element) 110a of a FinFET structure on the front surface (main surface on the p-type epitaxial layer 123 side) of a semiconductor substrate (semiconductor chip) 120 made of SiC.

[0053] The semiconductor substrate 120 is made of SiC. + On the starting substrate 121 - The epitaxial layers 122, 123 which become the n-type drift region 102 and the p-type base region 103 are epitaxially grown in this order. + The starting substrate 121 is n + The trench gate structure includes a p-type base region 103, an n-type drain region 101, and a + type source region 104, p ++ The semiconductor substrate 120 includes a first contact region 105 and a MOS gate 109. The MOS gate 109 includes a gate trench 106, a gate insulating film 107 and a gate electrode 108. The gate trenches 106 have a predetermined width w101 and extend linearly in a first direction X parallel to the front surface of the semiconductor substrate 120, and are arranged in a stripe pattern.

[0054] One unit cell 110a is formed in the portion between the centers of adjacent gate trenches 106. The width (Fin width) w111 between adjacent gate trenches 106 is set narrow so that one channel (n-type inversion layer) is formed in almost the entire p-type base region 103 between adjacent gate trenches 106. This one channel formed between adjacent gate trenches 106 contacts different MOS gates 109 on both side surfaces in a second direction Y that is parallel to the front surface of the semiconductor substrate 120 and perpendicular to the first direction X. The gate trench 106 penetrates the p-type epitaxial layer 123 from the front surface of the semiconductor substrate 120 in the depth direction Z to form an n-type inversion layer. -Type epitaxial layer 122(n - The junction ends within the drift region 102).

[0055] A gate electrode 108 is provided inside the gate trench 106 via a gate insulating film 107. + type source region 104 and p ++ The portion excluding the p-type contact region 105 is the p-type base region 103. + type source region 104 and p ++ The n-type contact regions 105 are selectively provided between the front surface of the semiconductor substrate 120 and the p-type base region 103, in contact with the p-type base region 103. + type source region 104 and p ++ The mold contact regions 105 are alternately and repeatedly provided adjacent to each other in the first direction X between the gate trenches 106 adjacent to each other.

[0056] n - The p-type drift region 102, the p-type base region 103 and the n + type source region 104, p ++ The contact region 105 contacts the gate insulating film 107 on the side walls of the gate trenches 106 located on both sides in the second direction Y. - The n-type drift region 102 surrounds the bottom surface of the gate trench 106 and contacts the gate insulating film 107 at the bottom surface of the gate trench 106. The interlayer insulating film 111 is provided on the entire front surface of the semiconductor substrate 120 and covers the gate electrode 108. The contact electrode 112 is provided on the front surface of the semiconductor substrate 120 inside the contact hole 111a of the interlayer insulating film 111. + type source region 104 and p ++ The semiconductor device is in ohmic contact with the contact region 105 .

[0057] The front surface electrode 113 is provided on the interlayer insulating film 111 and the contact electrode 112 so as to be embedded in the contact hole 111a of the interlayer insulating film 111. The front surface electrode 113 is connected to the n-type semiconductor layer 111 via the contact electrode 112. + type source region 104 and p ++ The front surface electrode 113 and the contact electrode 112 function as a source electrode. A rear surface electrode 114 is provided on the entire rear surface of the semiconductor substrate 120. The rear surface electrode 114 is an n-type contact region 105. + Type drain region 101(n + The back electrode 114 is in contact with and electrically connected to the starting mold substrate 121. The back electrode 114 functions as a drain electrode.

[0058] In the silicon carbide semiconductor device 110 of the reference example described above, the non-patent document 1 described above, and the patent document 1 described above, the Fin width w111 is narrow, so that the electric field strength at the bottom surface of the gate trench 106 is large during off-state. This causes a problem that the electric field is concentrated in the gate insulating film 107 at the bottom surface of the gate trench 106, lowering the breakdown voltage. Therefore, a problem to be solved in the present embodiment is how to improve the breakdown voltage in a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged.

[0059] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted.

[0060] (Details of the first embodiment) A silicon carbide semiconductor device according to a first embodiment for solving the above-mentioned problems will be described below. Fig. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate. + Type source region 4 and p ++ 1 shows a layout (hatched portion) of the contact region 5. Figures 2 and 3 are cross-sectional views showing cross-sectional structures taken along the cutting lines A-A' and B-B' in Figure 1, respectively. A silicon carbide semiconductor device 10 according to a first embodiment shown in Figures 1 to 3 is a vertical SiC-MOSFET with a trench gate structure having a MOS gate 9 constituting a unit cell (functional unit of an element) 10a of a FinFET structure on the front surface side of a semiconductor substrate (semiconductor chip) 20 made of silicon carbide (SiC).

[0061] The semiconductor substrate 20 is made of SiC. + On the front surface of the starting substrate 21, - The semiconductor substrate 20 is formed by epitaxially growing epitaxial layers (a first conductivity type silicon carbide layer and a second conductivity type silicon carbide layer) 22, 23, which become the p-type drift region (first semiconductor region) 2 and the p-type base region (second semiconductor region) 3, in this order. The semiconductor substrate 20 has a first main surface on the p-type epitaxial layer 23 side as the front surface, and an n-type + The second main surface (n + The back side of the starting substrate 21 is referred to as the back side. + The starting substrate 21 is n + The trench gate structure is a p-type base region 3, an n-type drain region 1, and + Type source region (third semiconductor region) 4, p ++ The gate electrode 9 is made up of a gate trench 6, a gate insulating film 7, and a gate electrode 8 (see FIGS. 2 and 3).

[0062] The FinFET structure is a so-called double-gate structure in which the width (Fin width) w11 between adjacent gate trenches 6 is narrowed to a predetermined width, and one channel (n-type inversion layer) formed in substantially the entire region of the p-type base region 3 between the gate trenches 6 is sandwiched from both side surfaces by MOS gates 9. By adopting the FinFET structure, the electric field in the direction parallel to the front surface of the semiconductor substrate 20 is reduced, so that carrier scattering is less, the carrier mobility is improved, and the channel resistance is lowered, thereby reducing the on-resistance. The gate trench 6 penetrates the p-type epitaxial layer 23 from the front surface of the semiconductor substrate 20 in the depth direction Z and reaches a first p + type region 31 to be described later. The cross-sectional shape of the gate trench 6 may be substantially rectangular or may be tapered (substantially trapezoidal) with the width decreasing toward the bottom surface.

[0063] The gate trenches 6 extend linearly in a first direction X (longitudinal direction) parallel to the front surface of the semiconductor substrate 20 and are arranged in a plurality of stripes. One unit cell 10a is formed in the portion between the centers of adjacent gate trenches 6. A plurality of unit cells 10a having the same structure are arranged adjacent to each other in a second direction Y (short side direction of the gate trench 6) parallel to the front surface of the semiconductor substrate 20 and orthogonal to the first direction X. The width w1 of the gate trench 6 in the second direction Y is uniform over the entire first direction X. The Fin width w11 is uniform over the entire first direction X. The Fin width w11 is narrower than the width w1 of the gate trench 6 in the second direction Y (w11 < w1), about 200 nm or less, for example, about 100 nm.

[0064] Inside the gate trench 6, a gate insulating film 7 is provided along the inner walls (side walls and bottom surface) of the gate trench 6, and a gate electrode 8 is provided on the gate insulating film 7 so as to fill the gate trench 6. Among the p-type epitaxial layer 23, the portion excluding the n + type source region 4 and the p ++ type contact region 5 formed by ion implantation in the p-type epitaxial layer 23 is the p-type base region 3. The n + type source region 4 and the p ++The n-type contact regions 5 are selectively provided between the front surface of the semiconductor substrate 20 and the p-type base region 3, in contact with the p-type base region 3. + Type source region 4 and p ++ The mold contact region 5 is in ohmic contact with a contact electrode 12 (described later) on the front surface of the semiconductor substrate 20 .

[0065] n + Type source region 4 and p ++ The n-type contact regions 5 are alternately and repeatedly provided adjacent to each other in the first direction X between the adjacent gate trenches 6. + The p-type source regions 4 of the unit cells 10a adjacent to each other in the second direction Y face each other with the MOS gate 9 therebetween. ++ The p-type contact regions 5 face each other in the second direction Y with the MOS gate 9 therebetween. ++ The contact region 5 is formed in a depth direction Z from the front surface of the semiconductor substrate 20 to an n-type + It may terminate at approximately the same depth as the n-type source region 4, or + n type source region 4 + They may reach a deep position on the side of the type drain region 1 (the back surface side of the semiconductor substrate 20). "Approximately the same depth" means that they are the same depth within a range including tolerances due to variations in the manufacturing process.

[0066] n + Type source region 4, p ++ The p-type contact region 5, the p-type base region 3, and an n-type current diffusion region 33 (described later) contact the gate insulating film 7 at the side walls of the gate trenches 6 located on both sides in the second direction Y. - Between the n-type drift region 2 and the bottom surface of the gate trench 6, + The first and second p + The n-type regions (first and second high concentration regions) 31 and 32 and the n-type current diffusion region (fifth semiconductor region) 33 are selectively provided. - Of the n-type epitaxial layer 22, -The first and second p-type epitaxial layers 22 are formed by ion implantation. + The portion excluding the n-type regions 31 and 32 and the n-type current diffusion region 33 is - type drift region 2.

[0067] 1st, 2p + The n-type regions 31 and 32 have a function of depleting when the SiC-MOSFET is turned off (or depleting the n-type current diffusion region 33, or both), thereby reducing the electric field applied to the gate insulating film 7. + The p-type region 31 is provided at a position facing the bottom surface of the gate trench 6, separated from the p-type base region 3, and extends in the first direction X with a predetermined width w21 and a length substantially equal to the longitudinal length of the gate trench 6. + The first p-type region 31 contacts the gate insulating film 7 at the bottom of the gate trench 6. + The p-type regions 31 are disposed between adjacent gate trenches 6. ++ They extend and are connected directly below the mold contact region 5. "Approximately the same length" means that they are the same length within a range including tolerances due to variations in the manufacturing process.

[0068] 1st p. + The type region 31 is n + The first p-type source region 4 is not provided directly below the first p-type source region 4. + The n-type region 31 is located closer to the bottom surface of the gate trench 6 than the n-type region 31. + At a deep position on the side of the p-type drain region 1, the bottom surface of the gate trench 6 and the p-type drain region 1 ++ The first p-type contact regions 5 are disposed opposite to each other and are arranged in a ladder shape (grid shape) when viewed from the front surface side of the semiconductor body 20. + The mold region 31 has an upper surface (n + The second p + The first p-type region 32 contacts the gate insulating film 7 at the bottom of the gate trench 6. + The mold region 31 has a lower surface (n + n - The mold is in contact with the drift region 2.

[0069] First p + The width w21 in the second direction Y of the portion directly below the gate trench 6 in the p-type region 31 (on the n-type drain region 1 side) is equal to or less than the width w1 in the second direction Y of the gate trench 6 and wider than the Fin width w11 (w11 < w21 ≤ w1). Also, the first p + The width w21 in the second direction Y of the portion directly below the gate trench 6 in the p-type region 31 is preferably, for example, 75% or more of the width w1 in the second direction Y of the gate trench 6 (that is, w1 × 0.75 ≤ w21 ≤ w1). Thereby, the electric field applied to the gate insulating film 7 on the bottom surface of the gate trench 6 can be made 3 MV / cm or less (see FIG. 21). + By making the width w21 in the second direction Y of the portion directly below the gate trench 6 in the p-type region 31 equal to or less than the width w1 in the second direction Y of the gate trench 6, an increase in the on-resistance due to the JFET (Junction FET) resistance can be suppressed. The JFET resistance is the diffusion resistance of the JFET portion (that is, the n-type current diffusion region 33) surrounded by the first and second p

[0070] First p + type regions 31, 32 and the gate trench 6. The first p + By making the width w21 in the second direction Y of the portion directly below the gate trench 6 in the p-type region 31 wider than the Fin width w11, when a large current (short-circuit current) exceeding the rated current flows between the drain and source of the SiC-MOSFET during a load short circuit or an arm short circuit, the first p + type region 31 becomes a resistance component, improving the short-circuit withstand capacity. + The depth d1 of the p-type region 31 is preferably equal to or greater than the Fin width w11 (w11 ≤ d1). The first p

[0071] First p + The depth d1 of the p-type region 31 is preferably equal to or greater than the Fin width w11 (w11 ≤ d1). The first p + The depth d1 of the p-type region 31 is the length in the depth direction Z from the bottom surface of the gate trench 6 (the first p + upper surface of the p-type region 31) to the first p + lower surface of the p-type region 31 and corresponds to the thickness of the p-type region 31. The first p + The depth d1 of the p-type region 31 is the length in the depth direction Z from the bottom surface of the gate trench 6 (the upper surface of the p-type region 31) to the lower surface of the p-type region 31 and corresponds to the thickness of the p-type region 31. The first p +The narrower the width w21 in the second direction Y of the portion of the mold region 31 directly under the gate trench 6, the lower the breakdown voltage BVdss. + It is necessary to increase the depth d1 of the mold region 31 (see FIG. 18). + The depth d1 of the mold region 31 is preferably, for example, about 0.8 μm or more.

[0072] 2nd p. + The p-type region 32 is disposed between the p-type base region 3 and the first p-type region 4 between the adjacent gate trenches 6. + A p-type base region 3 and a first p-type region 31 are disposed between the p-type base region 3 and the first p-type region 32. + The second p + The first p + The second p-type region 31 is electrically connected to the p-type base region 3. + The mold region 32 contacts the gate insulating film 7 at the side walls of both gate trenches 6 located on both sides in the second direction Y. + The type region 32 is n + The second p + The n-type region 32 is located closer to the bottom surface of the gate trench 6 than the n-type region 32. + At a shallow position on the side of the p ++ The gate trenches 6 are provided directly below the mold contact region 5 and are interspersed in the first direction X between adjacent gate trenches 6.

[0073] The n-type current diffusion region 33 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. By providing the n-type current diffusion region 33, n-type current is diffused from a channel formed in the p-type base region 3 between the adjacent gate trenches 6 when the SiC-MOSFET is turned on. - Since the electron current is easily diffused to the n-type drift region 2, the on-resistance can be reduced. The n-type current diffusion region 33 is in contact with the p-type base region 3 on the upper surface and in contact with the n-type drift region 2 on the lower surface. -The n-type current diffusion region 33 is in contact with the first and second p-type drift regions 2 on the side surfaces in the first direction X. + The first p-type region 31 and the second p-type region 32 are in contact with the gate insulating film 7 on the side wall of the gate trench 6 on the side surface in the second direction Y. + It is in contact with the mold region 31 .

[0074] The n-type current spreading region 33 is + The n-type current diffusion regions 33 are provided directly below the n-type source regions 4 and are interspersed between adjacent gate trenches 6 in the first direction X. + The first p + The n-type current diffusion region 33 terminates at approximately the same depth as the n-type region 31. That is, the n-type current diffusion region 33 is located at a position closer to the n-type region 31 than the bottom surface of the gate trench 6. + At a deep position on the side of the first p-type drain region 1, + The n-type current diffusion region 33 and the second p-type region 34 are arranged in a matrix shape surrounded by the n-type region 31. + The mold regions 32 are alternately and repeatedly disposed adjacent to each other in the first direction X between the gate trenches 6 adjacent to each other.

[0075] The n-type current diffusion region 33 may not be provided. In this case, instead of the n-type current diffusion region 33, - The p-type drift region 2 reaches the p-type base region 3 to form a JFET section. The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate 20 and covers the gate electrode 8. A contact hole 11a of the interlayer insulating film 11 is provided with an n + Type source region 4 and p ++ The mold contact region 5 is exposed. A contact electrode 12 is embedded inside the contact hole 11a on the front surface of the semiconductor substrate 20. The contact hole 11a may have a substantially rectangular cross-sectional shape, or may have a tapered cross-sectional shape that narrows toward the front surface of the semiconductor substrate 20.

[0076] The contact electrode 12 is + Type source region 4 and p ++The front electrode 13 is in ohmic contact with the n-type contact region 5. The front electrode 13 is provided on the interlayer insulating film 11 and the contact electrode 12 so as to be embedded in the contact hole 11a of the interlayer insulating film 11. The front electrode 13 is + Type source region 4 and p ++ The front surface electrode 13 and the contact electrode 12 function as a source electrode (first electrode). A rear surface electrode 14 is provided on the entire rear surface of the semiconductor substrate 20. The rear surface electrode 14 is an n-type contact region 5. + Type drain region 1(n + The back electrode 14 is in contact with and electrically connected to the starting mold substrate 21. The back electrode 14 functions as a drain electrode (second electrode).

[0077] The operation of the silicon carbide semiconductor device 10 (SiC-MOSFET) according to the embodiment will be described. When a positive voltage is applied to the drain electrode (rear electrode 14) with respect to the source electrode (front electrode 13 and contact electrode 12) (drain-source is forward biased), p ++ the p-type contact region 5, the p-type base region 3 and the first and second p-type + The n-type regions 31 and 32 and the n-type current diffusion regions 33 and - Type drift region 2 and n + The pn junction between the first p-type drain region 1 and the second p-type drain region 2 is reverse biased. In this state, if the voltage applied to the gate electrode 8 is less than the gate threshold voltage, the SiC-MOSFET maintains the off state. + Since the gate insulating film 7 on the bottom surface of the gate trench 6 is protected by the type region 31, the electric field applied to the gate insulating film 7 is reduced. - The breakdown voltage can be improved as compared to the reference structure surrounded by the type drift region 102 (FIGS. 22 to 24).

[0078] On the other hand, when a gate voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 with the drain-source being forward biased, one channel (n-type inversion layer) is formed in contact with different MOS gates 9 (gate insulating films 7 on the sidewalls of the gate trenches 6) on both sides in the second direction Y over almost the entire area in the first direction X of the p-type base region 3 between adjacent gate trenches 6. + Type drain region 1 to n - The n-type drift region 2, the JFET section (n-type current diffusion region 33) and the channel are passed through + A drift current (main current) flows toward the type source region 4, turning the SiC-MOSFET on. When the SiC-MOSFET is on, the adverse effect of the electric field generated by the flow of the main current in the second direction Y is reduced by the FinFET structure, so there is less carrier scattering and the carrier mobility is improved. This lowers the channel resistance and reduces the on-resistance.

[0079] A method for manufacturing silicon carbide semiconductor device 10 according to the first embodiment will be described. + n-type drain region 1 + Starting substrate (n + On the front surface of the mold starting wafer 21, n - n type drift region 2 - The n-type epitaxial layer 22 is epitaxially grown (deposited). - The n-type epitaxial layer 22 is - The epitaxial layer 22 is epitaxially grown to a thickness less than the predetermined thickness.

[0080] Next, p-type impurities (second conductivity type impurities) are ion-implanted to form n - In the surface region of the n-type epitaxial layer 22, - When viewed from the front surface side of the epitaxial layer 22, the first p + In addition, an n-type region 31 is formed in the active region by ion implantation of n-type impurities. - The first p type epitaxial layer 22 has a surface region +The lower part of the n-type current diffusion region 33 is formed at approximately the same depth as the first p-type region 31. + The mold regions 31 are arranged in a matrix shape surrounded by the periphery.

[0081] The active region is a region through which a main current (drift current) flows when the SiC MOSFET is on, and multiple unit cells 10a of the SiC MOSFET are arranged adjacent to each other. The active region is surrounded by an edge termination region (not shown). The edge termination region is a region that relieves the electric field on the front surface side of the semiconductor substrate 20 to maintain a breakdown voltage, and has a predetermined breakdown voltage structure arranged therein. The breakdown voltage is the limit voltage at which the semiconductor device does not malfunction or break down.

[0082] Then, n - The n-type epitaxial layer 22 is epitaxially grown to - The epitaxial layer 22 is then thickened to a predetermined thickness after completion of the product. Next, p-type impurities are ion-implanted to form n-type epitaxial layers in the active regions. - The second p-type epitaxial layer 22 is formed in the thickened portion. + The n-type region 32 is selectively formed in the active region by ion implantation of n-type impurities. - An upper portion of an n-type current spreading region 33 is formed over the entire thickened portion of the n-type epitaxial layer 22 .

[0083] 2nd p. + The mold region 32 is a first p-type region in the depth direction Z in a portion between adjacent gate trenches 6. + The second p + The mold region 32 is a first p-type region in the depth direction Z in a portion between adjacent gate trenches 6. + The n-type current diffusion region 33 may extend in a stripe shape in the second direction Y so as to face the n-type region 31 and to be perpendicular to the formation region of the gate trench 6. The upper part of the n-type current diffusion region 33 is formed at a position facing the lower part of the n-type current diffusion region 33 in the depth direction Z.

[0084] For example, the second p +When the n-type regions 32 extend in a stripe shape in the second direction Y, the upper portions of the n-type current diffusion regions 33 are adjacent to each other. + The second p is formed between the mold regions 32 and arranged in stripes extending in the second direction Y. + The n-type region 32 and the n-type current diffusion region 33 are also formed in the region where the gate trench 6 is to be formed, but the portions formed in the region where the gate trench 6 is to be formed are removed when the gate trench 6 is subsequently formed.

[0085] 2nd p. + The upper portions of the n-type region 32 and the n-type current diffusion region 33 are - The first p-type epitaxial layer 22 is formed to a depth penetrating the thickened portion of the epitaxial layer 22. + The n-type region 31 and the lower portion of the n-type current spreading region 33 are connected to each other. - The first and second p-type epitaxial layers 22 + The n-type regions 31 and 32 and the n-type current diffusion region 33 + The part on the mold starting substrate 21 side is n - This becomes type drift region 2.

[0086] Next, n - A p-type epitaxial layer 23 that will become the p-type base region 3 is epitaxially grown on the p-type epitaxial layer 22. The p-type epitaxial layer 23 is a second p + The n-type region 32 and the n-type current diffusion region 33 are in contact with each other. + A semiconductor base (semiconductor wafer) 20 is produced (manufactured) by laminating epitaxial layers 22, 23 in order on the front surface of a mold starting substrate 21 (first step).

[0087] Next, n is implanted into the surface region of the p-type epitaxial layer 23 by ion implantation. + Type source region 4 and p ++ The n-type contact region 5 is selectively formed in the p-type epitaxial layer 23 (steps 2 and 3). + Type source region 4 and p ++ n-type contact region 5 -The portion on the p-type epitaxial layer 22 side becomes the p-type base region 3. By ion implantation into the p-type base region 3, the p-type impurity concentration profile that contributes to the gate threshold voltage may be adjusted.

[0088] Next, a heat treatment is performed to activate all the implanted impurities. + Type source region 4, p ++ A first p-type contact region 5 and a first p-type base region 3 are formed through the p-type contact region 5 and the p-type base region 3. + A gate trench 6 is formed so as to reach the gate region 31 (fourth step). + Type source region 4, p ++ The p-type contact region 5, the p-type base region 3, the second p + The n-type region 32 and the n-type current spreading region 33 are exposed, and a first p + The mold area 31 is exposed.

[0089] Next, a gate electrode 8 is embedded in the gate trench 6 via a gate insulating film 7 by a general method to form a MOS gate 9 (sixth step). Next, an interlayer insulating film 11, a contact electrode 12, a front surface electrode 13, and a back surface electrode 14 are formed by a general method. Thereafter, the semiconductor wafer (semiconductor substrate 20) is diced (cut) into individual chips to complete the silicon carbide semiconductor device 10 shown in FIGS. 1 to 3.

[0090] In the method for manufacturing silicon carbide semiconductor device 10 according to the first embodiment described above, + The portion of the n-type region 31 directly below the gate trench 6 may be formed by ion-implanting p-type impurities into the bottom surface of the gate trench 6 from a direction perpendicular to the front surface of the semiconductor substrate 20 after the gate trench 6 is formed and before the gate electrode 8 is formed (fifth step). In this case, the n-type impurity exposed at the bottom surface of the gate trench 6 is - The first p-type epitaxial layer 22 has a width w21 substantially equal to the width w1 of the gate trench 6 in the second direction Y. + The mold region 31 is formed in a self-aligned manner. + In the mold region 31, adjacent first p+ The portion connecting the mold regions 31 to each other is, for example, the second p + It may be formed at the same time as the mold region 32 .

[0091] As described above, according to the embodiment, there is provided a silicon carbide semiconductor device having a double gate structure in which one channel is formed over the entire area in the first direction in almost the entire p-type base region between adjacent gate trenches, and a first p-type transistor fixed to the potential of the source electrode is provided at a position facing the bottom surface of the gate trench. + A mold region is provided. + The mold region protects the gate insulating film at the bottom of the gate trench and reduces the electric field applied to the gate insulating film at the bottom of the gate trench, thereby improving the breakdown voltage.

[0092] (Details of the second embodiment) A silicon carbide semiconductor device according to a second embodiment for solving the above-mentioned problems will be described below. Fig. 4 is a cross-sectional view showing a structure of a semi-silicon carbide semiconductor device according to the second embodiment. n of a silicon carbide semiconductor device 40 according to the second embodiment + Type source region 4, p ++ The layout of the contact region 5 and the MOS gate 9 viewed from the front surface side of the semiconductor substrate 20 is the same as that of the first embodiment (see FIG. 1). Figure 4 shows a cross-sectional structure taken along the line B-B' in Figure 1. In a silicon carbide semiconductor device 40 according to the second embodiment, the cross-sectional structure taken along the line A-A' in Figure 1 is the same as that in Figure 2, except that the reference numerals 31, 33, and w21 are replaced by 41, 43, and w22.

[0093] Silicon carbide semiconductor device 40 according to the second embodiment has p ++ In the portion directly under the contact region 5, the first and second p-type contacts for electric field relaxation are provided near the bottom surface of the gate trench 6. + The arrangement of the mold regions 41 and 42 is different from that of the silicon carbide semiconductor device 10 according to the first embodiment (see FIG. 3). +The p-type region 41 is provided at a position facing the bottom surface of the gate trench 6, separated from the p-type base region 3, and extends in the first direction X with a predetermined width w22 and a length substantially equal to the longitudinal length of the gate trench 6. + The upper surface of the n-type region 41 is in contact with the gate insulating film 7 at the bottom of the gate trench 6, and the lower surface of the n-type region 41 is in contact with the gate insulating film 7 at the bottom of the gate trench 6. - The mold is in contact with the drift region 2.

[0094] 1st p. + The type region 41 is disposed between adjacent gate trenches 6 (i.e., p ++ Type contact region 5 and n + The first p + The n-type region 41 is located closer to the bottom surface of the gate trench 6 than the n-type region 41. + The first p-type trenches 6 are located deep on the drain region 1 side and face only the bottom surface of the gate trench 6, and are arranged in a stripe shape when viewed from the front surface side of the semiconductor substrate 20. + The width w22 of the mold region 41 in the second direction Y is equal to or smaller than the width w1 of the gate trench 6 in the second direction Y and is wider than the fin width w11 (w11 <w22≦w1)。

[0095] 2nd p. + The n-type region 42 is disposed between the p-type base region 3 and the n-type region 42 between the adjacent gate trenches 6. - The second p-type drift region 2 is disposed between the first p-type base region 3 and the second p-type drift region 2. + The type region 42 is p ++ The n-type contact region 5 is provided only directly below the n-type contact region 5. + The second p + The mold regions 42 are interspersed between adjacent gate trenches 6 in the first direction X, similarly to the first embodiment. + The mold region 42 contacts the gate insulating film 7 at the side walls of both gate trenches 6 located on both sides in the second direction Y.

[0096] 2nd p. + The n-type region 42 is located closer to the bottom surface of the gate trench 6 than the n-type region 42. +The first p + The second p + Type region 42 and n - Between the first p-type drift region 2 is an n-type current diffusion region 43. + The mold regions 41 do not need to be arranged in a ladder shape when viewed from the front surface side of the semiconductor substrate 20. + The first p + The second p-type region 41 is electrically connected to the p-type base region 3. + The n-type current diffusion region 43 is located directly below the type region 42, and the n-type current diffusion region 43 extends in the first direction X by a length substantially equal to the length of the gate trench 6 in the longitudinal direction.

[0097] The n-type current diffusion region 43 extends in the first direction X with a length substantially equal to the longitudinal length of the gate trench 6, thereby reducing the spreading resistance of carriers in the first direction X. + The p-type source region 4 is in contact with the p-type base region 3 directly below the p-type source region 4. ++ The second p + The n-type current diffusion region 43 is in contact with the second p-type region 42. + The n-type current diffusion region 43 surrounds the side surface and the bottom surface of the n-type region 42 in the first direction X. The side surface of the n-type current diffusion region 43 in the second direction Y is in contact with the gate insulating film 7 on the side wall of the gate trench 6 and the first p-type current diffusion region 42. + The bottom surface of the n-type current diffusion region 43 is in contact with the n-type region 41. - The mold is in contact with the drift region 2.

[0098] The method for manufacturing silicon carbide semiconductor device 40 according to the second embodiment includes forming a first p + The layout of the type region 41 and the second p for electric field relaxation near the bottom surface of the gate trench 6 + The depth of the type region 42 is different from that of the silicon carbide semiconductor device 10 according to the first embodiment. + On the front surface of the starting mold substrate 21, n -The n-type epitaxial layer 22 is used as the n-type epitaxial layer after the product (silicon carbide semiconductor device 40) is completed. - The epitaxial layer 22 is epitaxially grown to a thickness less than the predetermined thickness.

[0099] Next, p-type impurity ions are implanted to form n - In the surface region of the n-type epitaxial layer 22, - When viewed from the front surface side of the epitaxial layer 22, the first p + In addition, an n-type region 41 is formed in the active region by ion implantation of n-type impurities. - The first p type epitaxial layer 22 has a surface region + The lower portion of the n-type current diffusion region 43 is formed at approximately the same depth as the n-type region 41. The lower portion of the n-type current diffusion region 43 is formed at approximately the same depth as the first p-type region 41. + The mold regions 41 are disposed in the entire area between the mold regions 41, and are formed in a stripe shape extending in the first direction X.

[0100] Next, as in the first embodiment, - The n-type epitaxial layer 22 is then grown to a predetermined thickness after completion of the product. - The second p type epitaxial layer 22 is formed in the thickened portion. + The second p + A mold region 42 is formed. + The mold region 42 is terminated at a position deeper than the bottom surface of the gate trench 6 to be formed in a later process. + The mold region 42 is the first p + The first and second p portions are arranged in the second direction Y and terminate at a position deeper than the upper surface of the mold region 41. + The mold regions 41 and 42 are connected to each other.

[0101] Thus, the second page + By terminating the mold region 42 at a position deeper than the bottom surface of the gate trench 6, the first and second p + The type regions 41 and 42 are maintained in a state of being connected to each other in the second direction Y. -The n-type epitaxial layer 22 is formed in the entire area of ​​the thickened portion in the depth direction Z. - The upper portion of the n-type current spreading region 43 is formed to a depth penetrating the thickened portion of the n-type epitaxial layer 22. As a result, the upper and lower portions of the n-type current spreading region 43 are connected in the depth direction Z.

[0102] 1st p. + The n-type region 41 may be formed by ion-implanting p-type impurities into the bottom surface of the gate trench 6 from a direction perpendicular to the front surface of the semiconductor substrate 20 after the gate trench 6 is formed and before the gate electrode 8 is formed (step 5). - The first p-type epitaxial layer 22 has a width w22 substantially equal to the width w1 of the gate trench 6 in the second direction Y. + The mold region 41 is formed in a self-aligned manner.

[0103] n - The first and second p-type epitaxial layers 22 + The n-type regions 41 and 42 and the n-type current diffusion region 43 + The part on the mold starting substrate 21 side is n - This becomes p-type drift region 2. Thereafter, similarly to the first embodiment, the steps following epitaxial growth of p-type epitaxial layer 23 are performed in order to complete silicon carbide semiconductor device 40 shown in FIG.

[0104] As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, according to the second embodiment, the n-type current diffusion region extends in the first direction with a length substantially equal to the longitudinal length of the gate trench, thereby reducing the carrier spreading resistance in the first direction, and therefore the on-resistance can be further reduced. Furthermore, according to the second embodiment, the n-type current diffusion region extends in the first direction with a length substantially equal to the longitudinal length of the gate trench, thereby reducing the carrier spreading resistance in the first direction, and therefore the on-resistance can be further reduced. + Type region and 2nd p + Therefore, the first p + Type region and 2nd p + There is no need to consider the accuracy of alignment with the mold region, and the manufacturing process is simplified.

[0105] (Details of the Third Embodiment) A silicon carbide semiconductor device according to a third embodiment for solving the above problems will be described below. FIGS. 5 and 6 are cross-sectional views showing a structure of a silicon carbide semiconductor device according to the third embodiment. n of a silicon carbide semiconductor device 50 according to the third embodiment + Type source region 4, p ++ The layout of the contact region 5 and the MOS gate 9 viewed from the front surface side of the semiconductor substrate 20 is the same as that of the first embodiment (see FIG. 1). Figures 5 and 6 show cross-sectional structures taken along lines A-A' and B-B' in FIG. 1, respectively.

[0106] 7 to 10 are cross-sectional views showing a state during the manufacture of the silicon carbide semiconductor device according to the third embodiment. In (a) of FIG. + FIG. 6(a) shows the cross-sectional structure of FIG. 6 (where the p-type source region 4 is disposed), and FIG. ++ 7 to 10 show a cross section of the first p + In order to clarify the method of forming the mold region 51, the structure in the vicinity of one gate trench 6 is shown on a scale different from that in FIGS.

[0107] Silicon carbide semiconductor device 50 according to the third embodiment differs from silicon carbide semiconductor device 10 according to the first embodiment (see FIG. 3) in the following two points. The first difference is that a first p + The mold regions 51 are arranged in a second direction Y. ++ The second difference is that the first p-type contact region 5 is provided only between the first p-type contact region 5 and the second p-type contact region 6 for electric field relaxation near the bottom of the gate trench 6. + The type region 51 is ++ In the third embodiment, the second p-type contact region 5 is directly connected to the p-type base region 3 and is disposed in the vicinity of the bottom surface of the gate trench 6 for electric field relaxation. + No mold area (corresponding to reference numeral 32 in FIG. 3) is provided.

[0108] Specifically, page 1 +The mold region 51 is provided at a position facing the bottom surface of the gate trench 6 and is oriented p ++ Opposed only to the p-type contact region 5 ++ The first contact regions 5 are arranged at substantially the same width and intervals as the first contact regions 5. + The mold region 51 has a shape similar to that of the first embodiment. + The first p-type source region 4 does not face the second p-type source region 4. The term "approximately the same width" and "approximately the same interval" means that the width and interval are the same within a range including a tolerance due to variations in the manufacturing process. + The upper surface of the n-type region 51 is in contact with the gate insulating film 7 at the bottom of the gate trench 6, and the lower surface of the n-type region 51 is in contact with the gate insulating film 7 at the bottom of the gate trench 6. - The mold is in contact with the drift region 2.

[0109] 1st p. + The width w23 of the mold region 51 in the second direction Y is greater than the width w1 of the gate trench 6 in the second direction Y. + The first p-type region 51 extends along the sidewall (one sidewall or both sidewalls) of the gate trench 6 to the p-type base region 3, contacts the gate insulating film 7 on the sidewall of the gate trench 6, and is directly connected to the p-type base region 3. + The type region 51 is p ++ The p-type base region 3 and the n-type contact region 5 are disposed directly below the p-type base region 3 and - The first p + The n-type region 51 is the same as in the first embodiment. + It is not provided directly under the type source region 4 .

[0110] p-type base region 3 and n - Between the first p-type drift region 2 + The portion other than the p-type region 51 is an n-type current diffusion region 53. - Between the first p-type drift region 2 + The n-type region 51 and the n-type current diffusion region 53 are alternately arranged in the first direction X and surround the inner wall of the gate trench 6. The n-type current diffusion region 53 is connected to the p-type base region 3 and the n-type - Type drift region 2 and first p +That is, when viewed from the front surface side of the semiconductor substrate 20, the first p + The n-type regions 51 are arranged in a matrix, and the n-type current diffusion regions 53 are first p + They are arranged in a lattice shape surrounding the periphery of the mold area 51 .

[0111] The method for manufacturing the silicon carbide semiconductor device 50 according to the third embodiment differs from the method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment in the following two points. The first difference is that the n-type ... - By ion-implanting p-type impurities into the p-type epitaxial layer 22 (hereinafter referred to as oblique ion implantation), a first p-type impurity for electric field relaxation near the bottom surface of the gate trench 6 is formed. + The second difference is that the second p-type region 51 is locally connected to the p-type base region 3. + The difference is that the step of forming a mold region (corresponding to reference numeral 32 in FIG. 3) is not carried out.

[0112] Specifically, first, as in the first embodiment, as shown in FIG. - By epitaxially growing the n-type epitaxial layer 22 and forming the n-type current diffusion region 53, an n-type - An n-type current diffusion region 53 is formed over the entire surface region of the p-type epitaxial layer 22. Next, similarly to the first embodiment, the steps from epitaxial growth of the p-type epitaxial layer 23 to the formation of the gate insulating film 7 are performed in order. + Type source region 4, p ++ The type contact region 5, the p-type base region 3 and the n-type current diffusion region 53 are exposed, and these regions are covered with the gate insulating film 7 on the inner wall of the gate trench 6.

[0113] Next, as shown in FIG. 8, while leaving the oxide film mask 71, for example, used in forming the gate trench 6, a first p +A resist mask 72 is formed having an opening in a portion corresponding to a region for forming the mold region 51. The entire surface of the gate insulating film 7 on the inner wall of the gate trench 6 is exposed through the opening 71a of the oxide film mask 71. ++ The contact region 5 is exposed while being covered with the oxide film mask 71, and adjacent p ++ The gate trench 6 between the mold contact regions 5 is exposed while being covered with the gate insulating film 7 .

[0114] The resist mask 72 is formed by aligning the oxide film mask 71 with the n + n-type source region 4 and adjacent to each other in the second direction Y + The resist mask 72 and the oxide film mask 71 are formed along the inner wall of the gate trench 6 between the source regions 4 and cover the gate insulating film 7. Therefore, the opening 70a of the mask 70 consisting of the resist mask 72 and the oxide film mask 71 contains p ++ The gate insulating film 7 on the inner wall of the gate trench 6 between the contact regions 5 is exposed. The portion exposed in the opening 70a of the mask 70 is the first p + This portion corresponds to the formation area of ​​the mold area 51 .

[0115] Next, using the resist mask 72 and the oxide film mask 71 as a mask 70, dry etching 73 such as reactive ion etching (RIE) is performed. This dry etching 73 removes the gate insulating film 7 on the bottom surface of the gate trench 6 in the portion exposed to the opening 70a of the mask 70. In addition, by performing the dry etching 73 for a relatively long time, it is possible to remove the portion of the gate insulating film 7 on the sidewall of the gate trench 6 that covers the n-type current diffusion region 53 in the portion exposed to the opening 70a of the mask 70 (see FIG. 9). Then, the resist mask 72 is removed.

[0116] 9, using the oxide film mask 71 and the gate insulating film 7 as a mask, oblique ion implantation 74 of p-type impurities is performed on the bottom surface and one sidewall of the gate trench 6. As a result, a first p-type impurity is implanted into the surface region of the inner wall of the gate trench 6 from the bottom surface of the gate trench 6 to one sidewall of the gate trench 6 at a depth penetrating the n-type current diffusion region 53 in the depth direction. + The mold region 51 is formed. + The type region 51 is p ++ The gate trench 6 extends from the bottom surface of the gate trench 6 along one sidewall directly below the contact region 5 to the p-type base region 3, and its upper end contacts the p-type base region 3 (fifth step).

[0117] 10, using the oxide film mask 71 and the gate insulating film 7 as a mask, oblique ion implantation 75 of p-type impurities is performed on the bottom surface and the other sidewall of the gate trench 6. As a result, a first p-type impurity is implanted into the surface region of the inner wall of the gate trench 6 from the bottom surface of the gate trench 6 to the other sidewall of the gate trench 6 to a depth penetrating the n-type current diffusion region 53 in the depth direction. + The mold region 51 is formed. + The type region 51 is p ++ The gate trench 6 extends from the bottom surface of the gate trench 6 directly below the contact region 5 along both side walls to the p-type base region 3, and its upper end contacts the p-type base region 3 (fifth step).

[0118] The first p is formed only on one side wall or the other side wall of the gate trench 6. + Alternatively, the p-type region 51 and the p-type base region 3 may be locally connected. In this case, one of the oblique ion implantations 74 and 75 may be omitted. + The mold regions 51 may be connected to each other. - The first p-type epitaxial layer 22 + The n-type region 51 and the n-type current spreading region 53 + The part on the mold starting substrate 21 side is n -This becomes the type drift region 2. Next, the gate insulating film 7 is formed again to make up for the missing portion of the gate insulating film 7 (that is, the portion removed by dry etching 73).

[0119] As a result, the entire inner wall of the gate trench 6 is covered with the gate insulating film 7. + The portion in contact with the n-type region 51 may be thicker than the portion in contact with the n-type current diffusion region 53. After removing all the gate insulating film 7 remaining on the sidewall of the gate trench 6, the gate insulating film 7 is formed again to form the first p + Gate insulating film 7 may be formed to have a substantially uniform thickness both in a portion in contact with n-type region 51 and in a portion in contact with n-type current diffusion region 53. Thereafter, oxide film mask 71 is removed, and then, as in the first embodiment, the steps following the formation of gate electrode 8 are performed in order to complete silicon carbide semiconductor device 50 shown in FIGS.

[0120] As described above, according to the third embodiment, it is possible to obtain the same effects as those of the first and second embodiments. Also, according to the third embodiment, the second p + Since the step of forming the mold region can be omitted, the number of steps can be reduced.

[0121] (Details of the fourth embodiment) Another example of the method for manufacturing the silicon carbide semiconductor device 50 according to the third embodiment will be described below as a method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment that solves the above-mentioned problems. FIGS. 11 to 14 are cross-sectional views showing a state during the manufacturing process of the silicon carbide semiconductor device according to the fourth embodiment. In FIGS. 11 to 14, (a) shows the cross-sectional structure (n) of FIG. + FIG. 6(a) shows the cross-sectional structure of FIG. 6 (where the p-type source region 4 is disposed), and FIG. ++ 11 to 14 show a cross section in which the first p + In order to clarify the method of forming the mold region 51, the structure in the vicinity of one gate trench 6 is shown on a scale different from that in FIGS.

[0122] The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment differs from the method for manufacturing a silicon carbide semiconductor device according to the third embodiment (see FIGS. 7 to 10) in that a polysilicon (poly-Si) layer 81 is used as a mask instead of the resist mask 72 (see FIG. 8) to form a first p + Specifically, as shown in FIG. 11, similarly to the third embodiment, - The steps from epitaxial growth of the type epitaxial layer 22 to the formation of the gate insulating film 7 are performed in order. Next, the oxide film mask 71 (see FIG. 7) used in forming the gate trench 6 is removed, and then a polysilicon layer 81 is deposited on the front surface of the semiconductor substrate 20 so as to completely fill the gate trench 6.

[0123] Next, as shown in FIG. 12, a first p + A resist mask 82 is formed with an opening only in a portion corresponding to a region for forming the mold region 51. The polysilicon layer 81 is deposited on the front surface of the semiconductor substrate 20 so as to completely fill the gate trench 6, and the surface of the polysilicon layer 81 is a flat surface that is approximately parallel to the front surface of the semiconductor substrate 20. This makes it possible to form the resist mask 82 flat and of a uniform thickness on the polysilicon layer 81. In the openings 82a of the resist mask 82, p ++ The gate trench 6 between the mold contact regions 5 is exposed while being covered with the polysilicon layer 81 and the gate insulating film 7 .

[0124] Next, dry etching 83 such as RIE is performed using the resist mask 82. This dry etching 83 removes the polysilicon layer 81 and the gate insulating film 7 on the bottom surface of the gate trench 6 in the portion exposed to the opening 82a of the resist mask 82. In addition, by performing the dry etching 83 for a relatively long time, the portion of the gate insulating film 7 on the sidewall of the gate trench 6 that covers the n-type current diffusion region 53 can be removed in the portion exposed to the opening 82a of the resist mask 82. As a result, the first p +An opening 81a is formed that exposes a portion corresponding to the formation region of the mold region 51 (see FIG. 13). Then, the resist mask 82 is removed.

[0125] 13, using the polysilicon layer 81 and the gate insulating film 7 as a mask, oblique ion implantation 84 of p-type impurities is performed on the bottom surface and one sidewall of the gate trench 6. As a result, a first p-type impurity is implanted into the surface region of the inner wall of the gate trench 6 from the bottom surface of the gate trench 6 to one sidewall of the gate trench 6 at a depth penetrating the n-type current diffusion region 53 in the depth direction. + The mold region 51 is formed. + The type region 51 is p ++ The gate trench 6 extends from the bottom surface of the gate trench 6 along one sidewall directly below the contact region 5 to the p-type base region 3, and its upper end contacts the p-type base region 3 (fifth step).

[0126] 14, using the polysilicon layer 81 and the gate insulating film 7 as a mask, oblique ion implantation 85 of p-type impurities is performed on the bottom surface and the other sidewall of the gate trench 6. As a result, a first p-type impurity is implanted into the surface region of the inner wall of the gate trench 6 from the bottom surface of the gate trench 6 to the other sidewall of the gate trench 6 at a depth penetrating the n-type current diffusion region 53 in the depth direction Z. + The mold region 51 is formed. + The type region 51 is p ++ The gate trench 6 extends from the bottom surface of the gate trench 6 directly below the contact region 5 along both side walls to the p-type base region 3, and its upper end contacts the p-type base region 3 (fifth step).

[0127] As in the third embodiment, either one of the oblique ion implantations 84 and 85 may be omitted, or the first p +The mold regions 51 may be connected to each other. Next, the gate insulating film 7 is formed again in the same manner as in the third embodiment. Next, the polysilicon layer 81 is deposited again to completely fill the gate trench 6. Next, the polysilicon layer 81 is etched back to leave only the portion of the polysilicon layer 81 that will become the gate electrode 8 inside the gate trench 6. Thereafter, similarly to the third embodiment, the steps following the formation of the interlayer insulating film 11 are performed in order to complete the silicon carbide semiconductor device 50 shown in FIGS. 5 and 6 .

[0128] As described above, according to the fourth embodiment, it is possible to obtain the same effects as those of the first to third embodiments. Also, according to the fourth embodiment, the first p for alleviating the electric field at the bottom of the gate trench is formed by using the polysilicon layer that becomes the gate electrode 8 as a mask. + A mold region can be formed.

[0129] (Details of the fifth embodiment) A silicon carbide semiconductor device according to a fifth embodiment for solving the above problems will be described below. Fig. 15 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the fifth embodiment. n of a silicon carbide semiconductor device 60 according to the fifth embodiment + Type source region 4, p ++ The layout of the contact region 5 and the MOS gate 9 as viewed from the front surface side of the semiconductor substrate 20 is obtained by changing the reference numeral 7 in FIG. 1 to 67 (67b). FIG. 15 shows a cross-sectional structure taken along the line A-A' in FIG. 1. In the silicon carbide semiconductor device 60 according to the fifth embodiment, the cross-sectional structure taken along the line B-B' in FIG. 1 corresponds to the n-type contact region 5 in FIG. 15. + The source region 4 is p ++ The contact region 5 is replaced by a contact region 6 (see FIG. 3).

[0130] The silicon carbide semiconductor device 60 according to the fifth embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment (see FIGS. 2 and 3) in the following two points. The first difference is that, of the gate insulating film 67 provided along the inner wall (bottom and sidewall) of the gate trench 6, the thickness t1 of a portion 67a along the bottom surface of the gate trench 6 (hereinafter referred to as the gate insulating film on the bottom surface of the gate trench 6) is made thicker than the thickness t2 of a portion 67b along the sidewall of the gate trench 6 (hereinafter referred to as the gate insulating film on the sidewall of the gate trench 6). The second difference is that the first and second p + The p-type base region 3 and the n-type region 4 are not provided. - The point is that the entire area between the n-type drift region 2 is made into an n-type current diffusion region 63 .

[0131] In the fifth embodiment, the thickness t1 of the gate insulating film 67a at the bottom of the gate trench 6 is thicker than the fin width w11 (t1>w11). By increasing the thickness t1 of the gate insulating film 67a at the bottom of the gate trench 6, the dielectric breakdown voltage of the gate insulating film 67 becomes higher (the electric field strength at the bottom of the gate trench 6 becomes smaller). For this reason, the first and second p + Even if a mold region is not provided, the gate insulating film 67a on the bottom surface of the gate trench 6 can be protected. + By not providing a type region, n - Since the electron current is easily diffused to the type drift region 2 and the spreading resistance of the carriers is reduced, the on-resistance can be reduced.

[0132] The thickness t2 of the gate insulating film 67b on the sidewall of the gate trench 6 is the same as that of the gate insulating film 7 in the first embodiment (see FIGS. 2 and 3). - The upper surface of the n-type drift region 2 is in contact with the p-type base region 3, and the lower surface of the n-type drift region 2 is in contact with the p-type base region 3. -The n-type current diffusion region 63 contacts the n-type drift region 2. The n-type current diffusion region 63 extends in the first direction X between adjacent gate trenches 6 with a length substantially equal to the longitudinal length of the gate trench 6. The side surface of the n-type current diffusion region 63 in the second direction Y contacts the gate insulating film 67b on the side wall of the gate trench 6. The n-type current diffusion region 63 surrounds the bottom surface of the gate trench 6 and contacts the gate insulating film 67a at the bottom surface of the gate trench 6.

[0133] The method for manufacturing the silicon carbide semiconductor device 60 according to the fifth embodiment differs from the method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment in the following two points. The first difference is that the gate insulating film 67 (67a, 67b) is formed so that the thickness t1 at the bottom surface of the gate trench 6 is greater than the thickness t2 at the sidewalls thereof. The second difference is that the first and second p + The step of forming the n-type region is not performed, and the n - 13. The point is that an n-type current diffusion region 63 is formed over the entire surface region of the n-type epitaxial layer 22.

[0134] As described above, according to the fifth embodiment, the gate insulating film on the bottom surface of the gate trench is thickened to a predetermined thickness, so that the first and second p layers for electric field relaxation are formed near the bottom surface of the gate trench. + Even if no mold region is provided, the same effects as those of the first to fourth embodiments can be obtained. Also, according to the fifth embodiment, the first and second p regions for alleviating the electric field near the bottom surface of the gate trench are provided. + Since the step of forming the mold region can be omitted, the number of steps can be reduced.

[0135] (Verification example) Regarding silicon carbide semiconductor device 10 according to the first embodiment (see FIG. 2), + The relationship between the width w21 in the second direction Y of the portion of the mold region 31 directly under the gate trench 6 and the width w1 in the second direction Y of the gate trench 6 was examined. +The electrical characteristics obtained by the portion of the gate trench 6 of the type region 31 are similar to those of the p type region directly below the gate trench of a normal SiC-MOSFET not having a FinFET structure. + The electrical characteristics are the same as those obtained by the mold region. For this reason, the conventional SiC-MOSFET (hereinafter, referred to as Comparative Examples 1 and 2) is used for verification. Figures 16 and 17 are cross-sectional views showing the structures near the gate trenches of Comparative Examples 1 and 2, respectively.

[0136] 18 to 21 are characteristic diagrams showing the results of simulating the relationship between the TBP width W_TBP and the trench width W_Trench in Comparative Examples 1 and 2. The trench width W_Trench is the width of the gate trench 206 in the second direction Y (short side direction). The TBP width W_TBP is the width of the first p + 18 to 21 is the width in the second direction Y of the mold region 231. The horizontal axis in FIGS. 18 to 21 is the ratio of the TBP width W_TBP to the trench width W_Trench (=W_TBP / W_Trench). The vertical axis in FIGS. 18 to 21 is the breakdown voltage BVdss [V], the gate threshold voltage Vth [V], and the on-resistance RonA [mΩ·cm 2 ] and electric field strength [MV / cm].

[0137] Comparative Examples 1 and 2 shown in Figures 16 and 17 have a comparatively wide width w211 between adjacent gate trenches 206, and have a normal unit cell that is not a FinFET structure. Figures 16 and 17 respectively show a half structure (a portion from the center of the gate trench 206 in the second direction Y to the center between adjacent gate trenches 206) of the unit cell (a portion between the centers of adjacent gate trenches 206) of Comparative Examples 1 and 2. Comparative Examples 1 and 2 differ from the silicon carbide semiconductor device 10 according to the first embodiment in that the width w211 between adjacent gate trenches 206 is comparatively wide, and the first and second p + Specifically, the semiconductor substrate 220 has an n-type region 231 and a n-type region 232. + n-type drain region + On a starting substrate (not shown),- The epitaxial layers which become the p-type drift region 202 and the p-type base region 203 are epitaxially grown in this order.

[0138] The semiconductor substrate 220 has a front surface (a main surface on the p-type epitaxial layer side that becomes the p-type base region 203) on which the p-type base region 203 and n + Type source region 204, p ++ A trench gate structure is provided, which is composed of a contact region 205, a gate trench 206, a gate insulating film 207, and a gate electrode 208. + The p-type source region 204 and ++ The n-type contact region 205 is a diffusion region formed by ion implantation in a surface region of the front surface of the semiconductor substrate 220 (a surface region of the p-type epitaxial layer that becomes the p-type base region 203). + The p-type source region 204 and ++ The contact region 205 is selectively provided between the front surface of the semiconductor substrate 220 and the p-type base region 203 in contact with the p-type base region 203 .

[0139] n + The p-type source region 204 and ++ The p-type contact region 205 is in ohmic contact with a source electrode (not shown) on the front surface of the semiconductor body 220. + The p-type source region 204 extends along the sidewall of the gate trench 206 in the first direction X by a length substantially equal to the longitudinal length of the gate trench 206. + The source region 204 is in contact with the gate insulating film 207 on the sidewall of the gate trench 206. + The source region 204 is adjacent to the ++ The mold contact region 205 is provided approximately in the center between the adjacent gate trenches 206 and spaced apart from the gate trenches 206 .

[0140] The gate trench 206 extends in a stripe shape in the first direction X, as in the first embodiment. The gate trench 206 extends from the front surface of the semiconductor substrate 220 to the n-th layer in the depth direction Z. + A first p-type source region 204 and a first p-type base region 203 are formed through the p-type source region 204 and the p-type base region 203. + The first and second p-type regions 231 are formed in the gate trench 206. A gate electrode 208 is provided inside the gate trench 206 via a gate insulating film 207. The gate electrode 208 is electrically insulated from the source electrode by an interlayer insulating film 211. + The n-type regions 231 and 232 and the n-type current diffusion region 233 are - n-type drift region 202 - The p-type epitaxial layer is a diffusion region formed by ion implantation into the p-type base region 203 and the n-type - Between the n-type drift region 202 and the bottom surface of the gate trench 206, + The gate insulating film is selectively provided at a deep position on the drain region side.

[0141] 1st p. + The p-type region 231 is provided away from the p-type base region 203 and is located at a position facing the bottom surface of the gate trench 206 and at approximately the center between adjacent gate trenches 206 (i.e., ++ The first p regions 204 and 205 extend in the first direction X at a length substantially equal to the longitudinal length of the gate trench 6. + The mold regions 231 are partially connected to each other at a portion not shown. + The mold region 231 contacts the gate insulating film 207 at the bottom surface of the gate trench 206. ++ The first p-type contact region 205 + The mold region 231 is provided away from the gate trench 206. + The width of the mold region 231 in the second direction Y (TBP width W_TBP) is approximately the same as the trench width W_Trench.

[0142] 2nd p. +The second p-type region 232 is provided between adjacent gate trenches 206, away from the gate trenches 206, and in contact with the p-type base region 203. + The type region 232 is p ++ The first p-type contact region 205 + The second p-type region 231 and the p-type base region 203 extend in the first direction X with a length substantially equal to the longitudinal length of the gate trench 6. + The mold region 232 + The n-type region 231 and the p-type base region 203 are electrically connected to each other. The n-type current diffusion region 233 is in contact with the p-type base region 203 on the upper surface and in contact with the n-type current diffusion region 233 on the lower surface. - The first and second p + The n-type current diffusion region 233 contacts the gate insulating film 207 on the side wall of the gate trench 206. The n-type current diffusion region 233 is formed in multiple stages, divided into an upper portion 233a and a lower portion 233b.

[0143] Comparative Example 1, No. 1p + The depth of the mold region 231 is p ++ The thickness of the first p-type contact region 205 and the thickness of the gate trench 206 are the same as those of the first p-type contact region 205 and the thickness of the gate trench 206. + Only the depth d201 of the mold region 231 is deepened. + The depth d201 of the mold region 231 is the depth from the bottom surface of the gate trench 206 (the first p + The upper surface of the mold region 231) to the first p + The length in the depth direction Z to the bottom surface of the mold region 231, and the length of the first p + This corresponds to the thickness of the mold region 231. In the comparative examples 1 and 2, the first p + The conditions are the same except for the depth d201 of the mold region 231. The trench width W_Trench is set to 0.8 μm.

[0144] 18 to 21 show simulation results of the breakdown voltage BVdss, gate threshold voltage Vth, on-resistance RonA, and electric field strength characteristics versus the ratio of the TBP width W_TBP to the trench width W_Trench when the TBP width W_TBP is changed in various ways for these comparative examples 1 and 2. FIGS. 18 to 21 show approximation curves 241 to 244 of each characteristic based on a plurality of simulation results for comparative example 1. FIGS. 18 to 21 show one simulation result 251 to 254 for comparative example 2, respectively, and the inventors have confirmed that the approximation curves of each characteristic of comparative example 2, including the simulation results 251 to 254, are also approximation curves that transition approximately parallel to the approximation curves 241 to 244 of comparative example 1.

[0145] 18, it was confirmed that the breakdown voltage BVdss increases as the TBP width W_TBP increases. + It was confirmed that the breakdown voltage BVdss increases as the depth d201 of the type region 231 increases. By increasing the breakdown voltage BVdss, the breakdown voltage can be improved. From the results shown in FIGS. 19 and 20, the gate threshold voltage Vth and the on-resistance RonA are determined by the TBP width W_TBP and the first p + It was confirmed that the TBP width W_TBP is almost independent of the depth d201 of the mold region 231. Therefore, even when the width w211 (Fin width) between adjacent gate trenches 206 is narrowed to obtain the effect of the FinFET structure, the TBP width W_TBP contributes to the breakdown voltage and does not adversely affect the effect of the FinFET structure (reduction of on-resistance).

[0146] From the results shown in FIG. 21, it was confirmed that the wider the TBP width W_TBP, the smaller the electric field strength at the bottom of the gate trench 206. In order to set the electric field strength at the bottom of the gate trench 206 to, for example, about 3MV / cm or less at which dielectric breakdown of the gate insulating film 207 in SiC does not occur, it is preferable to set the TBP width W_TBP to about 75% or more and 100% or less of the trench width W_Trench. By reducing the electric field strength at the bottom of the gate trench 206, the breakdown voltage can be improved. Even if the TBP width W_TBP is within the above range, the narrower the TBP width W_TBP, the lower the breakdown voltage BVdss (see FIG. 18), and therefore the breakdown voltage decreases. In addition, when obtaining the effect of the FinFET structure, the electric field strength at the bottom of the gate trench 206 increases, and the breakdown voltage decreases.

[0147] Therefore, the first p + By appropriately deepening the depth d201 of the type region 231 and increasing the breakdown voltage BVdss (see FIG. 18), a predetermined breakdown voltage can be ensured. Specifically, in the case where the effect of the FinFET structure is obtained by making the width w211 between the adjacent gate trenches 206 a Fin width narrower than the trench width W_Trench, the first p + The inventors have confirmed that it is preferable to set the depth d201 of the type region 231 to be equal to or greater than the fin width and approximately 0.8 μm or greater. This ensures that the breakdown voltage BVdss is, for example, 1200 V or greater (see FIG. 18), making avalanche breakdown less likely to occur, and thus ensuring a predetermined breakdown voltage.

[0148] Although not shown, silicon carbide semiconductor devices 40, 50 according to the second and third embodiments have similar characteristics to those in FIGS.

[0149] The present disclosure is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, in each of the first to fourth embodiments, the thickness of the gate insulating film on the bottom surface of the gate trench may be made thicker than the thickness of the gate insulating film on the side wall of the gate trench, as in the fifth embodiment. + Instead of forming the n-type source region by ion implantation, + The type source region is n + In this case, the n-type epitaxial layer may be formed. + n type source region + The surface of the epitaxial layer is the front surface of the semiconductor substrate. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0150] INDUSTRIAL APPLICABILITY As described above, a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of symbols]

[0151] 1n + Type drain region 2n - Mold Drift Region 3 p-type base region 4n + Type Source Area 5 p ++ Mold Contact Area 6 Gate trench 7,67,67a,67b Gate insulating film 8. Gate electrode 9. MOS Gate 10,40,50,60 Silicon carbide semiconductor device 10a Unit cell 11 Interlayer insulating film 11a Contact hole in interlayer insulating film 12 Contact electrode 13 Front electrode 14 Back electrode 20 Semiconductor substrate 21 n + Starting substrate 22n - Type epitaxial layer 23 p-type epitaxial layer 31, 32, 41, 42, 51 p for electric field relaxation + type area 33, 43, 53, 63 n-type current diffusion region 70,71,72,81,82 Masks for ion implantation and etching 70a, 71a, 72a, 81a, 82a Mask openings 73,83 Dry Etching 74,75,84,85 Oblique ion implantation t1,t2 Gate insulating film thickness w1 Width of trench in second direction w11 Fin width w21,w22,w23 P for electric field relaxation + Width in the second direction Y of the portion of the mold region directly under the gate trench d1 p for electric field relaxation + Depth of the part of the mold region directly below the gate trench X: a first direction parallel to the front surface of the semiconductor body Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. a first semiconductor region of a first conductivity type provided within a semiconductor substrate made of silicon carbide; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and having a higher impurity concentration than the second semiconductor region; a gate trench passing through the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region; a first high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the first high concentration region being provided at a position facing a bottom surface of the gate trench; a gate electrode provided inside the gate trench via a gate insulating film; a first electrode electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first high concentration region; A second electrode provided on a second main surface of the semiconductor substrate; Equipped with a double-gate structure in which one channel is formed in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other, the channel being sandwiched between the gate trenches from both side surfaces; a width of the first high concentration region is equal to or smaller than a width of the gate trench and is wider than a width between adjacent gate trenches, the width being longer than a width between adjacent gate trenches.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein a width of the first high concentration region is equal to or greater than 75% of a width of the gate trench.

3. 2 . The silicon carbide semiconductor device according to claim 1 , wherein a depth of said first high concentration region is equal to or greater than a width between adjacent said gate trenches.

4. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the first heavily doped region has a depth of 0.8 μm or more.

5. The gate trench extends linearly in a first direction parallel to the first main surface of the semiconductor substrate, 2 . The silicon carbide semiconductor device according to claim 1 , wherein the third semiconductor region and the fourth semiconductor region are repeatedly arranged alternately in the first direction between the gate trenches adjacent to each other.

6. a second high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the second high concentration region being selectively provided in contact with the second semiconductor region at a position facing the fourth semiconductor region in a depth direction between the gate trenches adjacent to each other, 6. The silicon carbide semiconductor device according to claim 5, wherein the first high concentration region is electrically connected to the second semiconductor region via the second high concentration region.

7. the first high concentration regions adjacent to each other in a second direction parallel to the first main surface of the semiconductor body and perpendicular to the first direction are partially connected to each other at positions facing the second high concentration regions in a depth direction, The silicon carbide semiconductor device according to claim 6 , wherein the second high concentration region is in contact with the first high concentration region in a depth direction.

8. 7. The silicon carbide semiconductor device according to claim 6, wherein the second high concentration region reaches a position deeper on the second electrode side than a bottom surface of the gate trench, and contacts the first high concentration region in a second direction that is parallel to the first main surface of the semiconductor base and perpendicular to the first direction.

9. a first semiconductor region of a first conductivity type provided within a semiconductor substrate made of silicon carbide; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and having a higher impurity concentration than the second semiconductor region; a gate trench passing through the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region; a first high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the first high concentration region being provided at a position facing a bottom surface of the gate trench; a second high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the second high concentration region being selectively provided between the gate trenches adjacent to each other and in contact with the second semiconductor region; a gate electrode provided inside the gate trench via a gate insulating film; a first electrode electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, the first high concentration region, and the second high concentration region; A second electrode provided on a second main surface of the semiconductor substrate; Equipped with a double-gate structure in which one channel is formed in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other, the channel being sandwiched between the gate trenches from both side surfaces; The gate trench extends linearly in a first direction parallel to the first main surface of the semiconductor substrate, the third semiconductor region and the fourth semiconductor region are alternately and repeatedly arranged in the first direction between the gate trenches adjacent to each other, the second high concentration region is provided at a position facing the fourth semiconductor region in a depth direction, 23. A silicon carbide semiconductor device, comprising: a first heavily doped region electrically connected to a second semiconductor region via the second heavily doped region.

10. 2. The silicon carbide semiconductor device according to claim 1 , wherein the first high concentration region extends toward the first electrode along a sidewall of the gate trench at a position facing the fourth semiconductor region in a depth direction and contacts the second semiconductor region.

11. a first semiconductor region of a first conductivity type provided within a semiconductor substrate made of silicon carbide; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and having a higher impurity concentration than the second semiconductor region; a gate trench passing through the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region; a first high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the first high concentration region being selectively provided at a position facing a bottom surface of the gate trench; a gate electrode provided inside the gate trench via a gate insulating film; a first electrode electrically connected to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first high concentration region; A second electrode provided on a second main surface of the semiconductor substrate; Equipped with a double-gate structure in which one channel is formed in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other, the channel being sandwiched between the gate trenches from both side surfaces; The gate trench extends linearly in a first direction parallel to the first main surface of the semiconductor substrate, the third semiconductor region and the fourth semiconductor region are alternately and repeatedly arranged in the first direction between the gate trenches adjacent to each other, the first high concentration region extends toward the first electrode along a sidewall of the gate trench at a position facing the fourth semiconductor region in a depth direction and contacts the second semiconductor region.

12. 12. The silicon carbide semiconductor device according to claim 6, wherein the first high concentration region is not provided at a position facing the third semiconductor region in a depth direction.

13. 10. The silicon carbide semiconductor device according to claim 6, wherein the second high concentration region is not provided at a position facing the third semiconductor region in a depth direction.

14. 12. The silicon carbide semiconductor device according to claim 1, further comprising a fifth semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region, the fifth semiconductor region being provided between the second semiconductor region and the first semiconductor region, in contact with the second semiconductor region and the first semiconductor region, and terminating on the second electrode side at the same depth position as the first high concentration region.

15. a first semiconductor region of a first conductivity type provided within a semiconductor substrate made of silicon carbide; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and having a higher impurity concentration than the second semiconductor region; a gate trench passing through the fourth semiconductor region, the third semiconductor region, and the second semiconductor region to reach the first semiconductor region; a gate insulating film provided along an inner wall of the gate trench; a gate electrode provided on the gate insulating film inside the gate trench; a first electrode electrically connected to the fourth semiconductor region, the third semiconductor region, and the second semiconductor region; A second electrode provided on a second main surface of the semiconductor substrate; Equipped with a double-gate structure in which one channel is formed in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other, the channel being sandwiched between the gate trenches from both side surfaces; a thickness of the gate insulating film at a bottom surface of the gate trench is thicker than a thickness of the gate insulating film at a side wall of the gate trench and is thicker than a width between adjacent gate trenches.

16. 16. The silicon carbide semiconductor device according to claim 15, further comprising a fifth semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region, the fifth semiconductor region being provided between the second semiconductor region and the first semiconductor region, in contact with the second semiconductor region and the first semiconductor region, and reaching a side of the second electrode beyond a bottom surface of the gate trench.

17. 10. A method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising the steps of: a first step of forming the semiconductor substrate by sequentially stacking a first conductivity type silicon carbide layer that is to become the first semiconductor region and a second conductivity type silicon carbide layer that is to become the second semiconductor region; A second step of selectively forming the third semiconductor region on a surface region of the second conductivity type silicon carbide layer; a third step of selectively forming the fourth semiconductor region in a surface region of the second conductivity type silicon carbide layer; a fourth step of forming the gate trench penetrating the second conductivity type silicon carbide layer in a depth direction to expose the fourth semiconductor region, the third semiconductor region, and the second semiconductor region on a side wall and reaching the first conductivity type silicon carbide layer to expose the first semiconductor region on a bottom surface; a fifth step of ion-implanting a second conductivity type impurity into a bottom surface of the gate trench from a direction perpendicular to the first main surface of the semiconductor substrate to form the first high concentration region in a surface region of the first conductivity type silicon carbide layer exposed at the bottom surface of the gate trench; a sixth step of forming the gate electrode inside the gate trench via the gate insulating film after the fifth step; A method for manufacturing a silicon carbide semiconductor device comprising the steps of:

18. 12. A method for manufacturing a silicon carbide semiconductor device according to claim 11, comprising: a first step of forming the semiconductor substrate by sequentially stacking a first conductivity type silicon carbide layer that is to become the first semiconductor region and a second conductivity type silicon carbide layer that is to become the second semiconductor region; A second step of selectively forming the third semiconductor region on a surface region of the second conductivity type silicon carbide layer; a third step of selectively forming the fourth semiconductor region on a surface region of the second conductivity type silicon carbide layer; a fourth step of forming the gate trench penetrating the second conductivity type silicon carbide layer in a depth direction to expose the fourth semiconductor region, the third semiconductor region, and the second semiconductor region on a side wall and reaching the first conductivity type silicon carbide layer to expose the first semiconductor region on a bottom surface; a fifth step of ion-implanting a second conductivity type impurity into an inner wall of the gate trench from a direction oblique to the first main surface of the semiconductor substrate to form the first high concentration region in a surface region of the first conductivity type silicon carbide layer exposed on the inner wall of the gate trench; a sixth step of forming the gate electrode inside the gate trench via the gate insulating film after the fifth step; A method for manufacturing a silicon carbide semiconductor device comprising the steps of:

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