Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device having a trench gate structure in which unit cells with a FinFET structure are arranged, the silicon carbide semiconductor device being capable of reducing on-resistance.SOLUTION: A drift layer 2 has an SJ structure with a parallel pn layer 43 including an n-type column region 41 and a p-type column region 42. A first p+-type region 31 for electric field relaxation is provided so as to face the bottom face of the gate trench 6. The width Wn1 of the n-type column region 41 in a short direction is wider than the width w21 of a portion of the first p+-type region 31 directly below the gate trench 6 in the second direction Y. The width Wp1 of the p-type column region 42 in a short direction is narrower than the width w21 of a portion of the first p+-type region 31 directly below the gate trench 6 in the second direction Y and wider than a Fin width w11 described later. The p-type column region 42 is arranged directly below the gate trench 6 at an interval of one gate trench of the gate trenches 6 adjacent to each other in the second direction Y, and is adjacent to the first p+-type region 31 in a depth direction Z.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] This disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] The following Non-Patent Document 1 and the following Patent Document 1 describe a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) having a trench gate structure in which a unit cell (functional unit of an element) having a FinFET structure is arranged. The following Patent Documents 2 and 3 describe that the on-resistance is reduced by forming at least a part of the drift layer into a super junction (SJ) structure in which n-type regions and p-type regions are alternately and repeatedly arranged. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6631632 [Patent Document 2] JP 2020-096086 A [Patent Document 3] JP 2019-016775 A [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned Non-Patent Document 1 and Patent Document 1, the drift resistance, which is another resistance component of the on-resistance, becomes dominant as the withstand voltage increases, and the on-resistance is difficult to reduce even if the fin width (the width between adjacent gate trenches) is narrowed. Non-Patent Document 1 discloses that this problem becomes prominent at withstand voltages of 1 kV or higher (especially 3.3 kV class).

[0006] An object of the present disclosure is to provide a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged, the silicon carbide semiconductor device being capable of reducing the on-resistance. [Means for solving the problem]

[0007] A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A parallel pn layer in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged is provided inside a semiconductor substrate made of silicon carbide. A first semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the parallel pn layer. A second semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A gate trench penetrates the third semiconductor region, the second semiconductor region, and the first semiconductor region in a depth direction.

[0008] Between the first semiconductor region and the parallel pn layer, a first high concentration region of a second conductivity type is selectively provided in contact with the parallel pn layer at a position facing the bottom surface of the gate trench. The first high concentration region has a higher impurity concentration than the first semiconductor region. A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the third semiconductor region, the second semiconductor region, the first semiconductor region, and the first high concentration region. A second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces over the entire area of ​​the first semiconductor region between the gate trenches adjacent to each other. The width of the first conductivity type region is wider than the width of the first high concentration region. The width of the second conductivity type region is narrower than the width of the first high concentration region and wider than the width between the gate trenches adjacent to each other. Effect of the Invention

[0009] ADVANTAGEOUS EFFECTS OF THE DISCLOSURE The silicon carbide semiconductor device according to the present disclosure is a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged, and has an effect of reducing the on-resistance. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device in accordance with a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. [Figure 4] FIG. 11 is a cross-sectional view showing a structure of a semi-silicon carbide conductor device according to a second embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a structure of a semi-silicon carbide conductor device according to a second embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a structure of a semi-silicon carbide conductor device according to a second embodiment. [Figure 7] FIG. 11 is a cross-sectional view showing a structure of a silicon semicarbide conductor device according to a third embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a structure of a silicon semicarbide conductor device according to a third embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a structure of a silicon semicarbide conductor device according to a third embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a structure of a comparative example. [Figure 11] FIG. 13 is a characteristic diagram showing the results of verifying the on-resistance characteristics of the comparative example. [Figure 12] 1 is a plan view showing a layout of a silicon carbide semiconductor device of a reference example as viewed from the front surface side of a semiconductor substrate. FIG. [Figure 13] 13 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 12. [Figure 14] 13 is a cross-sectional view showing a cross-sectional structure taken along line BB-BB' in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] <Overview of the embodiment of the present disclosure> (1) A silicon carbide semiconductor device according to one aspect of the present disclosure is as follows. A parallel p-n layer in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged is provided inside a semiconductor substrate made of silicon carbide. A first semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the parallel p-n layer. A second semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A gate trench penetrates the third semiconductor region, the second semiconductor region, and the first semiconductor region in a depth direction.

[0012] Between the first semiconductor region and the parallel pn layer, a first high concentration region of a second conductivity type is selectively provided in contact with the parallel pn layer at a position facing the bottom surface of the gate trench. The first high concentration region has a higher impurity concentration than the first semiconductor region. A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the third semiconductor region, the second semiconductor region, the first semiconductor region, and the first high concentration region. A second electrode is provided on the second main surface of the semiconductor substrate. A double gate structure is formed in which one channel is formed between the gate trenches from both side surfaces over the entire area of ​​the first semiconductor region between the gate trenches adjacent to each other. The width of the first conductivity type region is wider than the width of the first high concentration region. The width of the second conductivity type region is narrower than the width of the first high concentration region and wider than the width between the gate trenches adjacent to each other.

[0013] According to the above disclosure, the spreading resistance of carriers in the second direction is reduced, so that the JFET resistance can be reduced, and therefore the on-resistance can be reduced.

[0014] (2) In the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), the gate trenches extend linearly in a first direction parallel to the first main surface of the semiconductor substrate, and are arranged in a plurality of stripes adjacent to each other in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction. The first conductivity type regions and the second conductivity type regions may be arranged alternately and repeatedly in the second direction, and extend linearly in the first direction.

[0015] According to the above disclosure, the second conductivity type region reduces the spreading resistance of carriers in the second direction, thereby reducing the JFET resistance.

[0016] (3) Furthermore, in the silicon carbide semiconductor device according to this disclosure as described above in (2), the second conductivity type region may face bottom surfaces of the gate trenches in every other one of a plurality of the gate trenches adjacent to each other in the second direction.

[0017] According to the above disclosure, it is possible to prevent the current path from being blocked due to misalignment in the second direction of the second conductivity type region formed by ion implantation.

[0018] (4) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), the gate trenches extend linearly in a first direction parallel to the first main surface of the semiconductor substrate, and are arranged in a plurality of stripes adjacent to each other in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction. The first conductivity type regions and the second conductivity type regions may be arranged alternately and repeatedly in the first direction, and extend linearly in the second direction.

[0019] According to the above disclosure, the forward voltage of the body diode is reduced and the body diode is less likely to operate, so that the parasitic BJT operation can be suppressed.

[0020] (5) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (4), the second semiconductor regions and the third semiconductor regions are repeatedly arranged alternately in the first direction. The first high concentration regions facing each bottom surface of the gate trenches adjacent to each other are partially connected at a position facing the third semiconductor region in the depth direction. The second conductivity type region may extend linearly in the second direction adjacent to a connection portion between the first high concentration regions in the depth direction.

[0021] According to the above disclosure, it is possible to prevent the current path from being blocked due to misalignment in the second direction of the second conductivity type region formed by ion implantation.

[0022] (6) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (4), the second semiconductor regions and the third semiconductor regions are repeatedly arranged alternately in the first direction. The first high concentration regions facing each bottom surface of the gate trenches adjacent to each other are partially connected at a position facing the second semiconductor region in the depth direction. The second conductivity type region may extend linearly in the second direction adjacent to a connection portion between the first high concentration regions in the depth direction.

[0023] According to the above disclosure, it is possible to prevent the current path from being blocked due to misalignment in the second direction of the second conductivity type region formed by ion implantation.

[0024] (7) In the silicon carbide semiconductor device according to any one of (1) to (6) above, the parallel pn layer may have a thickness of 2 μm or more.

[0025] According to the above disclosure, the effect of reducing the on-resistance can be further obtained.

[0026] (8) In the silicon carbide semiconductor device according to any one of (1) to (7) above, the parallel pn layer may have a thickness four or more times the thickness of the first highly doped region.

[0027] According to the above disclosure, the effect of reducing the on-resistance can be further obtained.

[0028] (9) In addition, the silicon carbide semiconductor device according to the present disclosure may be any one of (1) to (8) above, further comprising a fourth semiconductor region of a first conductivity type provided between the first semiconductor region and the parallel pn layer in contact with the first semiconductor region and the first high concentration region, the fourth semiconductor region having an impurity concentration equal to or higher than the impurity concentration of the first conductivity type region. The fourth semiconductor region may terminate on the second electrode side at the same depth as the first high concentration region.

[0029] According to the above disclosure, the spreading resistance of carriers can be reduced.

[0030] (10) In addition, in the silicon carbide semiconductor device according to any one of (1) to (9) above, the first high concentration regions facing each other at bottom surfaces of the gate trenches adjacent to each other may be partially connected between the gate trenches adjacent to each other. A second high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region may be selectively provided between the first semiconductor region and a connection portion between the first semiconductor region and the connection portion between the gate trenches adjacent to each other, in contact with the first semiconductor region and the connection portion.

[0031] According to the above disclosure, by electrically connecting the first high concentration region to the first semiconductor region via the second high concentration region, the width of the first high concentration region can be made partially equal to or smaller than the width of the gate trench. By making the width of the first high concentration region equal to or smaller than the width of the gate trench, an increase in on-resistance due to JFET resistance can be suppressed.

[0032] <Foundational knowledge of this disclosure> First, the structure of a silicon carbide semiconductor device of the reference example will be described. Fig. 12 is a plan view showing a layout of the silicon carbide semiconductor device of the reference example as viewed from the front surface side of the semiconductor substrate. + type source region 104 and p ++ 12. The layout (hatched portion) of the contact region 105 is shown. Figures 13 and 14 are cross-sectional views showing cross-sectional structures taken along the cutting lines AA-AA' and BB-BB' in Figure 12, respectively. A silicon carbide semiconductor device 110 of a reference example shown in Figures 12 to 14 is a vertical SiC-MOSFET with a trench gate structure having a MOS gate 109 constituting a unit cell (functional unit of an element) 110a of a FinFET structure on the front surface (main surface on the p-type epitaxial layer 123 side) of a semiconductor substrate (semiconductor chip) 120 made of SiC.

[0033] The semiconductor substrate 120 is made of SiC. + On the starting substrate 121- The epitaxial layers 122, 123 which become the n-type drift region 102 and the p-type base region 103 are epitaxially grown in this order. + The starting substrate 121 is n + The trench gate structure includes a p-type base region 103, an n-type drain region 101, and a + type source region 104, p ++ The semiconductor substrate 120 includes a first contact region 105 and a MOS gate 109. The MOS gate 109 includes a gate trench 106, a gate insulating film 107 and a gate electrode 108. The gate trenches 106 have a predetermined width w101 and extend linearly in a first direction X parallel to the front surface of the semiconductor substrate 120, and are arranged in a stripe pattern.

[0034] One unit cell 110a is formed in the portion between the centers of adjacent gate trenches 106. The width (Fin width) w111 between adjacent gate trenches 106 is set narrow so that one channel (n-type inversion layer) is formed in almost the entire p-type base region 103 between adjacent gate trenches 106. This one channel formed between adjacent gate trenches 106 contacts different MOS gates 109 on both side surfaces in a second direction Y that is parallel to the front surface of the semiconductor substrate 120 and perpendicular to the first direction X. The gate trench 106 penetrates the p-type epitaxial layer 123 from the front surface of the semiconductor substrate 120 in the depth direction Z to form an n-type inversion layer. - Type epitaxial layer 122(n - The junction ends within the drift region 102).

[0035] A gate electrode 108 is provided inside the gate trench 106 via a gate insulating film 107. + type source region 104 and p ++ The portion excluding the p-type contact region 105 is the p-type base region 103. + type source region 104 and p ++The n-type contact regions 105 are selectively provided between the front surface of the semiconductor substrate 120 and the p-type base region 103, in contact with the p-type base region 103. + type source region 104 and p ++ The mold contact regions 105 are alternately and repeatedly provided adjacent to each other in the first direction X between the gate trenches 106 adjacent to each other.

[0036] n - The p-type drift region 102, the p-type base region 103 and the n + type source region 104, p ++ The contact region 105 contacts the gate insulating film 107 on the side walls of the gate trenches 106 located on both sides in the second direction Y. - The n-type drift region 102 surrounds the bottom surface of the gate trench 106 and contacts the gate insulating film 107 at the bottom surface of the gate trench 106. The interlayer insulating film 111 is provided on the entire front surface of the semiconductor substrate 120 and covers the gate electrode 108. The contact electrode 112 is provided on the front surface of the semiconductor substrate 120 inside the contact hole 111a of the interlayer insulating film 111. + type source region 104 and p ++ The semiconductor device is in ohmic contact with the contact region 105 .

[0037] The front surface electrode 113 is provided on the interlayer insulating film 111 and the contact electrode 112 so as to be embedded in the contact hole 111a of the interlayer insulating film 111. The front surface electrode 113 is connected to the n-type semiconductor layer 111 via the contact electrode 112. + type source region 104 and p ++ The front surface electrode 113 and the contact electrode 112 function as a source electrode. A rear surface electrode 114 is provided on the entire rear surface of the semiconductor substrate 120. The rear surface electrode 114 is an n-type contact region 105. + Type drain region 101(n + The back electrode 114 is in contact with and electrically connected to the starting mold substrate 121. The back electrode 114 functions as a drain electrode.

[0038] In the silicon carbide semiconductor device 110 of the above-mentioned reference example, the above-mentioned Non-Patent Document 1, and the above-mentioned Patent Document 1, the channel resistance is reduced by the FinFET structure, and the on-resistance is reduced. However, the higher the breakdown voltage class, the greater the drift resistance (n - In this embodiment, the resistance component due to the fin width w111 is dominant, and therefore the on-resistance is difficult to reduce even if the fin width w111 is narrowed. Therefore, a problem to be solved in this embodiment is how to reduce the on-resistance in a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged.

[0039] Preferred embodiments of the silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted.

[0040] (Details of the first embodiment) A silicon carbide semiconductor device according to a first embodiment for solving the above-mentioned problems will be described below. Fig. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate. + Type source region 4 and p ++ 2 shows the layout (hatched portion) of the mold contact region 5. Figures 2 and 3 are cross-sectional views showing cross-sectional structures taken along lines AA' and BB' in Figure 1, respectively.

[0041] The silicon carbide semiconductor device 10 according to the first embodiment shown in FIGS. 1 to 3 has a trench gate structure with a MOS gate 9 constituting a unit cell (functional unit of an element) 10a of a FinFET structure on the front surface side of a semiconductor substrate (semiconductor chip) 20 made of silicon carbide (SiC), and is a vertical MOSFET with a super junction (SJ) structure in which a drift layer (drift region) 2 is a parallel pn layer 43.

[0042] The semiconductor substrate 20 is made of SiC. + The epitaxial layers 22 and 23 that will become the drift layer 2 and the p-type base region (first semiconductor region) 3 are epitaxially grown in this order on the front surface of a starting substrate 21. The semiconductor substrate 20 has a first main surface on the side of the p-type epitaxial layer 23 as the front surface, and an n-type + The second main surface (n + The back side of the starting substrate 21 is referred to as the back side. + The starting substrate 21 is n + The gate electrode is a gate-type drain region 1.

[0043] The drift layer 2 is made up of a p-type base region 3 and an n + Between the n-type drain region 1 + The drift layer 2 is in contact with the n-type drain region 1. + The portion on the type source region 4 side (the front surface side of the semiconductor substrate 20) is a parallel pn layer 43. The parallel pn layer 43 is formed by alternately and repeatedly arranging n-type regions (hereinafter referred to as n-type column regions (first conductivity type regions)) 41 and p-type regions (hereinafter referred to as p-type column regions (second conductivity type regions)) 42 adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 20.

[0044] The n-type column regions 41 and the p-type column regions 42 are arranged in stripes extending in straight lines perpendicular to the direction in which the n-type column regions 41 and the p-type column regions 42 are adjacent to each other when viewed from the front surface side of the semiconductor substrate 20. The n-type column regions 41 and the p-type column regions 42 are arranged in stripes extending in straight lines perpendicular to the direction in which the n-type column regions 41 and the p-type column regions 42 are adjacent to each other when viewed from the front surface side of the semiconductor substrate 20. + The n-type drain region 1 extends linearly on the back surface of the semiconductor substrate 20. +The semiconductor layer 1 is in contact with the drain region 1 .

[0045] In the first embodiment, the short side direction of the n-type column region 41 and the p-type column region 42 is the same as the short side direction (second direction Y) of the gate trench 6 described later. The long side direction of the n-type column region 41 and the p-type column region 42 when viewed from the front surface side of the semiconductor substrate 20 is the same as the long side direction (first direction X) of the gate trench 6. The n-type column region 41 and the p-type column region 42 face different gate trenches 6 in the depth direction Z.

[0046] The parallel pn layer 43 and n + The portion between the n-type drain region 1 may be an n-type buffer region (an n-type region that does not have an SJ structure) 2a. The impurity concentration of the n-type buffer region 2a is equal to or lower than the impurity concentration of the n-type column region 41. When the n-type buffer region 2a is provided, the n-type column region 41 and the p-type column region 42 are n + The end of the n-type drain region 1 is in contact with the n-type buffer region 2a. + The semiconductor layer 1 is in contact with the drain region 1 .

[0047] The thickness Lsj of the parallel pn layer 43 is determined by the thickness of the p-type column region 42. When the n-type buffer region 2a is provided, the p-type column region 42 is thicker than the n-type column region 41. + In this case, the n-type drain region 1 may be formed between the adjacent p-type column regions 42. + An n-type buffer region 2a extends from the p-type drain region 1. The portions of the n-type buffer region 2a between the adjacent p-type column regions 42 function as a parallel pn layer 43.

[0048] By setting the thickness Lsj of the parallel pn layer 43 to about 2 μm or more, the effect of the parallel pn layer 43 can be obtained (see FIG. 9). + It is preferable that the depth d1 of the mold region 31 is four times or more. + The depth d1 of the type region 31 is the length in the depth direction Z from the bottom surface of the gate trench 6 to the parallel pn layer 43, and is the first p+ This corresponds to the thickness of the mold region 31, and is, for example, about 0.5 μm.

[0049] The widths (widths in the short direction) Wn1, Wp1 of the n-type column region 41 and the p-type column region 42 are approximately uniform in the depth direction Z. The impurity concentrations of the n-type column region 41 and the p-type column region 42 are, for example, approximately uniform in the depth direction Z. Charge balance is generally maintained between the adjacent n-type column region 41 and the p-type column region 42. The drift resistance (resistance component due to the drift layer 2) can be adjusted by the impurity concentration of the n-type column region 41.

[0050] The width and impurity concentration being substantially uniform means that the width and impurity concentration are the same within the range including the tolerance due to process variations. The charge balance is an index showing the degree of balance between the charge amount expressed by the product of the carrier concentration (concentration of activated impurities) of the n-type column region 41 and the width Wn1 in the short side direction, and the charge amount expressed by the product of the carrier concentration of the p-type column region 42 and the width Wp1 in the short side direction.

[0051] The width Wn1 of the n-type column region 41 in the short direction (here, the second direction Y) is + The area directly below the gate trench 6 in the type region 31 (n + The width Wp1 of the p-type column region 42 in the short side direction (here, the second direction Y) is wider than the width w21 of the p-type column region 42 in the second direction Y (Wn1>w21). + It is narrower than the width w21 in the second direction Y of the portion of the mold region 31 directly below the gate trench 6, and is wider than a fin width w11 described later (w21>Wp1>w11).

[0052] By setting the widths Wn1, Wp1 in the short side direction of the n-type column region 41 and the p-type column region 42 to the above conditions, the p-type column region 42 is arranged directly below the gate trenches 6 (i.e., facing the bottom surface of the gate trench 6) for every other one of the multiple gate trenches 6 arranged at a predetermined pitch in the second direction Y. The n-type column region 41 is arranged directly below the remaining gate trenches 6 except for the gate trenches 6 facing the p-type column region 42 in the depth direction Z. The spreading resistance of carriers is reduced compared to the case where the p-type column regions 42 are arranged directly below all of the gate trenches 6.

[0053] Furthermore, by setting the widths Wn1, Wp1 of the n-type column region 41 and the p-type column region 42 in the short-side direction under the above conditions, it is possible to prevent the current path (the connection point between the n-type current diffusion region 33 and the n-type column region 41) from being blocked due to misalignment (misalignment) in the second direction Y of the p-type column region 42 formed by implanting p-type impurity ions into the n-type epitaxial layer 22, as described below. + Alternatively, the width may be narrowed only at the end on the side of the source region 4 to ensure a current path.

[0054] The closer the length of the p-type column region 42 in the depth direction Z is to the thickness of the drift layer 2, the lower the on-resistance is. However, the longer the length of the p-type column region 42 in the depth direction Z is, the more stages of the parallel pn layer 43 formed by the multi-stage epitaxial method are formed, and therefore the higher the manufacturing cost becomes. + It is the distance (depth) in the depth direction Z from the boundary with the n-type region 31 to the boundary with the n-type buffer region 2a.

[0055] The multistage epitaxial method is a method in which the n-type epitaxial layer 22 is divided into multiple stages (multiple times) and epitaxially grown in multiple stages, and each time, a p-type region that becomes the p-type column region 42 is selectively formed adjacent to the p-type region in the depth direction Z by ion implantation of p-type impurities so that an n-type region that becomes the n-type column region 41 remains in each of the n-type epitaxial layers 22 epitaxially grown in multiple stages.

[0056] Also, by forming the drift layer 2 into an SJ structure with parallel pn layers 43, the impurity concentration of the n-type column region 41, which serves as the current path for the main current (drift current) of the SiC-MOSFET, can be increased compared to the case where the drift layer is an n-type drift region 102 that is not in an SJ structure as in the reference structure (see FIGS. 12 to 14). The higher the impurity concentration of the n-type column region 41, the lower the drift resistance can be reduced, and the on-resistance is reduced. - 型ドリフト領域102とする場合と比べて、SiC-MOSFETの主電流(ドリフト電流)の電流経路となるn型カラム領域41の不純物濃度を高くすることができる。n型カラム領域41の不純物濃度を高くするほど、ドリフト抵抗を低減することができ、オン抵抗が低減される。

[0057] The trench gate structure is composed of a p-type base region 3, an n + type source region (second semiconductor region) 4, a p ++ type contact region (third semiconductor region) 5, and a MOS gate 9. The MOS gate 9 is composed of a gate trench 6, a gate insulating film 7, and a gate electrode 8. The gate trench 6 penetrates the p-type epitaxial layer 23 from the front surface of the semiconductor substrate 20 in the depth direction Z and reaches the first p + type region 31 described later. The cross-sectional shape of the gate trench 6 is, for example, substantially rectangular.

[0058] The gate trench 6 extends linearly in a first direction X parallel to the front surface of the semiconductor substrate 20, and a plurality of gate trenches 6 are arranged in a second direction Y parallel to the front surface of the semiconductor substrate 20 and orthogonal to the first direction X. That is, the gate trenches 6 are arranged in a stripe shape extending in the first direction X as viewed from the front surface side of the semiconductor substrate 20. The width w1 of the gate trench 6 in the second direction Y is uniform over the entire first direction X.

[0059] The width (hereinafter referred to as the Fin width) w11 between adjacent gate trenches 6 is uniform over the entire first direction X. The Fin width w11 is narrower than the width w1 of the gate trench 6 in the second direction Y (w11 < w1) and is about 200 nm or less, for example, about 100 nm. One unit cell 10a of the FinFET structure is formed in the portion between the centers of adjacent gate trenches 6.

[0060] A plurality of unit cells 10a having the same structure are arranged adjacent to each other in the second direction Y (the short side direction of the gate trench 6). The FinFET structure is a so-called double gate structure in which the width (Fin width) w11 between adjacent gate trenches 6 is narrowed by a predetermined width, and one channel (n-type inversion layer) formed in almost the entire area of ​​the p-type base region 3 between the gate trenches 6 is sandwiched between MOS gates 9 from both side surfaces.

[0061] By narrowing the fin width w11 to form a FinFET structure, the electric field in the direction parallel to the front surface of the semiconductor substrate 20 is reduced near the bottom surface of the gate trench 6. This reduces carrier scattering near the bottom surface of the gate trench 6, improving carrier mobility, lowering channel resistance, and reducing on-resistance. A gate electrode 8 is provided inside the gate trench 6 with a gate insulating film 7 interposed therebetween.

[0062] n + Type source region 4 and p ++ The n-type contact regions 5 are selectively provided between the front surface of the semiconductor substrate 20 and the p-type base region 3 in contact with the p-type base region 3, and are in ohmic contact with a contact electrode 12 (described later) on the front surface of the semiconductor substrate 20. + Type source region 4 and p ++ The contact regions 5 are alternately and repeatedly provided adjacent to each other in the first direction X between the gate trenches 6 adjacent to each other.

[0063] The n unit cells 10a adjacent to each other in the second direction Y + The p-type source regions 4 of the unit cells 10a adjacent to each other in the second direction Y face each other with the MOS gate 9 therebetween. ++ The p-type contact regions 5 face each other across the MOS gate 9 in the second direction Y. + Type source region 4 and p ++ The portion excluding the contact region 5 is the p-type base region 3 .

[0064] n +Type source region 4, p ++ The contact region 5, the p-type base region 3, and the n-type current diffusion region 33 contact the gate insulating film 7 at the side walls of the gate trenches 6 located on both sides in the second direction Y. + Type regions (first and second high concentration regions) 31 and 32 and an n-type current diffusion region (fourth semiconductor region) 33 are selectively provided.

[0065] In the n-type epitaxial layer 22, first and second p-type epitaxial layers are formed in the n-type epitaxial layer 22 by ion implantation. + The portion excluding the n-type regions 31 and 32 and the n-type current diffusion region 33 constitutes the drift layer 2. + The n-type regions 31 and 32 have the function of reducing the electric field applied to the gate insulating film 7 by being depleted (or by depleting the n-type current diffusion region 33, or both) when the SiC-MOSFET is turned off.

[0066] 1st p. + The first p-type region 31 is provided at a position facing the bottom surface of the gate trench 6 and separated from the p-type base region 3. + The mold region 31 has a predetermined width w21 and extends in the first direction X by a length substantially equal to the longitudinal length of the gate trench 6. + A width w21 in the second direction Y of a portion of the mold region 31 directly below the gate trench 6 is equal to or smaller than the width w1 in the second direction Y of the gate trench 6 and is wider than the fin width w11.

[0067] The first p + The type regions 31 are p ++ The first contact region 5 extends directly below the first contact region 5 and is partially connected thereto. + The type region 31 is n + The first p-type source region 4 is not provided directly below the first p-type source region 4. + The type region 31 is connected to the bottom surface of the gate trench 6 and the p ++ The electrodes are provided opposite the mold contact region 5 and are arranged in a ladder shape (grid shape) when viewed from the front surface side of the semiconductor substrate 20.

[0068] 1st p. + The mold region 31 has an upper surface (n + The second p + The first p-type region 32 contacts the gate insulating film 7 at the bottom of the gate trench 6. + The portions of the mold region 31 directly below the gate trenches 6 are + The first p-type column region 41 and the second p-type column region 42 are in contact with different column regions of the parallel pn layer 43 at the first p-type drain region 1 side. + Type region 31 p ++ The portion directly below the n-type contact region 5 contacts the n-type column region 41 in the depth direction Z.

[0069] 1st p. + Type region 31 p ++ The width in the first direction X of the portion directly under the contact region 5 is, for example, p ++ The width w31 of the first contact region 5 in the first direction X is approximately the same as the width w31 of the first contact region 5 in the first direction X. + Type region 31 p ++ The interval at which the portions directly under the contact regions 5 are arranged in the first direction X is, for example, p ++ It is approximately the same as the interval w32 between the mold contact regions 5. Approximately the same length, approximately the same width, and approximately the same interval respectively mean that the length, width, and interval are the same within a range including the allowable error due to the variation in the manufacturing process.

[0070] 2nd p. + The p-type region 32 is disposed between the p-type base region 3 and the first p-type region 4 between the adjacent gate trenches 6. + Mold area 31 (1st p + The p-type base region 3 and the first p-type region 4 are connected to each other (the connection portion between the portions of the p-type region 31 directly below the gate trench 6). + The second p + The mold region 32 contacts the gate insulating film 7 at the side walls of both gate trenches 6 located on both sides in the second direction Y. + The first p + The p-type region 31 is electrically connected to the p-type base region 3 .

[0071] 2nd p. + The type region 32 is p ++ The second p + The type region 32 is n + The second p + The width of the mold region 32 in the first direction X is, for example, p ++ The width w31 of the second p-type contact region 5 in the first direction X is approximately the same as the width w31 of the second p-type contact region 5 in the first direction X. + The interval between the mold regions 32 is, for example, p ++ This is approximately the same as the interval w32 between the mold contact regions 5.

[0072] The n-type current diffusion region 33 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. By providing the n-type current diffusion region 33, electron current is easily diffused from a channel formed in the p-type base region 3 between the adjacent gate trenches 6 to the n-type column region 41 when the SiC-MOSFET is on, so that the on-resistance can be reduced.

[0073] The n-type current diffusion region 33 is in contact with the p-type base region 3 at its upper surface and in contact with the n-type column region 41 at its lower surface. The n-type current diffusion region 33 is not in contact with the p-type column region 42. The n-type current diffusion region 33 is in contact with the first and second p-type regions 41 and 42 at its side surfaces in the first direction X. + The first p-type region 31 and the second p-type region 32 are in contact with the gate insulating film 7 on the side wall of the gate trench 6 on the side surface in the second direction Y. + The n-type current diffusion region 33 is in contact with the n-type region 31. + The second source region 4 is provided only directly below the second source region 4 .

[0074] The n-type current spreading region 33 is + The first p + The n-type region 31 terminates at a depth substantially equal to that of the n-type region 31. + A first p +The n-type current diffusion region 33 is arranged in a matrix shape surrounded by the n-type region 31. The n-type current diffusion region 33 and the second p-type current diffusion region 34 are disposed between the gate trenches 6 adjacent to each other. + The mold regions 32 are alternately and repeatedly disposed adjacent to each other in the first direction X. "Approximately the same depth" means that the depth is the same within a range including tolerances due to variations in the manufacturing process.

[0075] The impurity concentration of the n-type current diffusion region 33 is equal to or higher than the impurity concentration of the n-type column region 41, and is preferably higher than the impurity concentration of the n-type column region 41. Specifically, the impurity concentration of the n-type column region 41 is 1.0×10 16 / cm 3 Above 1.0×10 17 / cm 3 The impurity concentration of the n-type current diffusion region 33 is about 3.0×10 16 / cm 3 Above 1.0×10 18 / cm 3 Preferably, the impurity concentration of the n-type current diffusion region 33 is about 5.0×10 16 / cm 3 Above 5.0×10 17 / cm 3 It is good to have the following.

[0076] The n-type current diffusion region 33 may not be provided. In this case, instead of the n-type current diffusion region 33, the n-type column region 41 reaches the p-type base region 3 and is arranged in the first direction X. + The first p-type region 31 and the second p-type region 32 are in contact with the gate insulating film 7 on the side wall of the gate trench 6 in the second direction Y. + It is in contact with the mold region 31 .

[0077] The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate 20 and covers the gate electrode 8. In the contact hole 11a of the interlayer insulating film 11, + Type source region 4 and p ++The mold contact region 5 is exposed. The contact hole 11a may have a substantially rectangular cross-sectional shape, or may have a tapered (trapezoidal) cross-sectional shape that narrows toward the front surface side of the semiconductor substrate 20.

[0078] A contact electrode 12 is embedded in the contact hole 11a on the front surface of the semiconductor substrate 20. The contact electrode 12 has an n + Type source region 4 and p ++ The front electrode 13 is in ohmic contact with the contact region 5. The front electrode 13 is provided on the interlayer insulating film 11 and the contact electrode 12 so as to be embedded in the contact hole 11a of the interlayer insulating film 11.

[0079] The front electrode 13 is connected to the n-type contact electrode 12 via the contact electrode 12. + Type source region 4 and p ++ The front surface electrode 13 and the contact electrode 12 function as a source electrode (first electrode). A rear surface electrode 14 is provided on the entire rear surface of the semiconductor substrate 20. The rear surface electrode 14 is an n-type contact region 5. + Type drain region 1(n + The back electrode 14 is in contact with and electrically connected to the mold starting substrate 21. The back electrode 14 functions as a drain electrode (second electrode).

[0080] The operation of the silicon carbide semiconductor device 10 (SiC-MOSFET) according to the embodiment will be described. When a positive voltage is applied to the drain electrode (rear electrode 14) with respect to the source electrode (front electrode 13 and contact electrode 12) (drain-source is forward biased), p ++ the p-type contact region 5, the p-type base region 3 and the first and second p-type + The n-type regions 31 and 32, the n-type current diffusion region 33, the n-type column region 41 and the n + A pn junction (main junction) between the gate electrode 8 and the type drain region 1 is reverse biased. In this state, if the voltage applied to the gate electrode 8 is less than the gate threshold voltage, no main current flows, and the SiC-MOSFET remains in the off state.

[0081] 1st p. + Since the gate insulating film 7 on the bottom surface of the gate trench 6 is protected by the type region 31, the electric field applied to the gate insulating film 7 is relaxed when the SiC-MOSFET is off. In addition, a predetermined withstand voltage is ensured by a depletion layer spreading from the main junction when the SiC-MOSFET is off. In addition, when the SiC-MOSFET is off, the pn junction between the p-type column region 42 and the n-type column region 41 is reverse biased, a depletion layer spreads from the pn junction, and the withstand voltage is borne by the parallel pn layer 43. This ensures a predetermined withstand voltage that exceeds the withstand voltage that can be realized by the impurity concentration (n-type column region 41) of the drift layer 2.

[0082] On the other hand, when a gate voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 with the drain-source being forward biased, one channel (n-type inversion layer) is formed in contact with different MOS gates 9 (gate insulating films 7 on the sidewalls of the gate trenches 6) on both sides in the second direction Y over almost the entire area in the first direction X of the p-type base region 3 between adjacent gate trenches 6. + The n-type drain region 1 passes through the n-type column region 41, the n-type current diffusion region 33, and the channel. + A main current (drift current) flows toward the type source region 4, and the SiC MOSFET turns on.

[0083] When the SiC-MOSFET is on, the adverse effect of the electric field generated by the flow of the main current in the second direction Y is reduced by the FinFET structure, so that there is less scattering of carriers, the mobility of carriers is improved, the channel resistance is lowered, and the on-resistance is reduced. In addition, by forming the drift layer 2 into an SJ structure using the parallel pn layer 43, the impurity concentration of the n-type column region 41, which is the current path of the main current, can be increased to reduce the drift resistance. In addition, the p-type column region 42 reduces the spreading resistance of carriers in the second direction Y, and the JFET (Junction FET) resistance is reduced. This further reduces the on-resistance.

[0084] A method for manufacturing silicon carbide semiconductor device 10 according to the first embodiment will be described. + n-type drain region 1 + Starting substrate (n + A drift layer 2 including a parallel pn layer 43 is formed on the front surface of a starting wafer 21. At this time, for example, a multistage epitaxial method is used to divide the n-type epitaxial layer 22 that will become the drift layer 2 into a plurality of stages, and p-type impurities are ion-implanted into each stage of epitaxial growth, thereby selectively forming p-type regions that will become p-type column regions 42 in each n-type epitaxial layer.

[0085] The portions of the n-type epitaxial layer 22 that are not implanted with ions and remain n-type between the adjacent p-type column regions 42 become n-type column regions 41. + The portion between the starting substrate 21 and the n-type buffer region 2a may be left as n-type without ion implantation. In this case, the n-type buffer region 2a is formed with the same impurity concentration as the impurity concentration of the n-type column region 41 (the impurity concentration of the n-type epitaxial layer 22).

[0086] The n-type column region 41 may be formed by ion implantation of n-type impurities. In this case, for example, instead of the n-type epitaxial layer 22, a non-doped epitaxial layer or an n-type epitaxial layer having the same impurity concentration as the n-type buffer region 2a is epitaxially grown in multiple stages. Ion implantation of n-type impurities may be performed on the portion of the non-doped epitaxial layer that will become the n-type buffer region 2a. This makes it possible to form an n-type buffer region 2a with a lower impurity concentration than the n-type column region 41.

[0087] Next, the n-type epitaxial layer 22 is epitaxially grown to increase the thickness of the n-type epitaxial layer 22. Next, a first p-type impurity is ion-implanted into the thickened portion of the n-type epitaxial layer 22 to a depth penetrating the thickened portion of the n-type epitaxial layer 22. +A first p-type region 31 is selectively formed, and a lower portion of an n-type current diffusion region 33 is formed by ion implantation of n-type impurities. + The type regions 31 are arranged in a lattice pattern extending linearly in the first and second directions X and Y, respectively, when viewed from the front surface side of the n-type epitaxial layer 22.

[0088] 1st p. + The n-type region 31 is in contact with different column regions of the parallel pn layer 43 in the depth direction Z at a portion extending linearly in the first direction X, and in contact with all column regions of the parallel pn layer 43 in the depth direction Z at a portion extending linearly in the second direction Y. + The n-type epitaxial layer 22 is arranged in a matrix shape surrounded by the n-type region 31 and contacts the n-type column region 41 in the depth direction Z. Instead of increasing the thickness of the n-type epitaxial layer 22, a first p + A doped type region 31 and a lower portion of an n-type current spreading region 33 may be formed.

[0089] Next, the n-type epitaxial layer 22 is further epitaxially grown to a predetermined thickness after the product (silicon carbide semiconductor device 10) is completed. Next, a second p-type impurity is ion-implanted into the thickened portion of the n-type epitaxial layer 22 to a depth penetrating the thickened portion of the n-type epitaxial layer 22. + A second p-type region 32 is selectively formed, and an upper portion of the n-type current diffusion region 33 is formed by ion implantation of n-type impurities. + The mold regions 32 are arranged in stripes extending in the second direction Y, for example.

[0090] The upper portion of the n-type current diffusion region 33 is adjacent to the second p + The second p is formed between the mold regions 32 and arranged in stripes extending in the second direction Y. + The n-type region 32 and the n-type current diffusion region 33 are also formed in the region where the gate trench 6 is to be formed, but the portions formed in the region where the gate trench 6 is to be formed are removed when the gate trench 6 is formed. + The mold region 32 is a first p +The upper portion of the n-type current spreading region 33 is connected to the lower portion of the n-type current spreading region 33 in the depth direction Z.

[0091] Next, a p-type epitaxial layer 23 that will become the p-type base region 3 is epitaxially grown on the n-type epitaxial layer 22. The p-type epitaxial layer 23 is a second p + The n-type region 32 and the n-type current diffusion region 33 are in contact with each other. + A semiconductor substrate (semiconductor wafer) 20 is fabricated (manufactured) by laminating epitaxial layers 22, 23 in order on the front surface of a mold starting substrate 21.

[0092] Next, n is implanted into the surface region of the p-type epitaxial layer 23 by ion implantation. + Type source region 4 and p ++ The p-type contact region 5 is selectively formed on the p-type epitaxial layer 23. + Type source region 4 and p ++ A portion closer to the n-type epitaxial layer 22 than the contact region 5 becomes the p-type base region 3. By ion implantation into the p-type base region 3, a p-type impurity concentration profile that contributes to the gate threshold voltage may be adjusted.

[0093] Next, a heat treatment is performed to activate all the implanted impurities. + Type source region 4, p ++ A first p-type contact region 5 and a first p-type base region 3 are formed through the p-type contact region 5 and the p-type base region 3. + A gate trench 6 is formed so as to reach the type region 31. The side wall of the gate trench 6 is provided with n + Type source region 4, p ++ The p-type contact region 5, the p-type base region 3, the second p + The n-type region 32 and the n-type current spreading region 33 are exposed, and a first p + The mold area 31 is exposed.

[0094] Next, a gate electrode 8 is embedded in the gate trench 6 via a gate insulating film 7 by a general method to form a MOS gate 9. Next, an interlayer insulating film 11, a contact electrode 12, a front surface electrode 13, and a back surface electrode 14 are formed by a general method. Thereafter, the semiconductor wafer (semiconductor substrate 20) is diced (cut) into individual chips to complete the silicon carbide semiconductor device 10 shown in FIGS. 1 to 3.

[0095] As described above, according to the embodiment, a cell with a FinFET structure is provided, the drift layer (drift region) has an SJ structure in which a parallel pn layer is made up of n-type column regions and p-type column regions, and the n-type column regions and p-type column regions are arranged in stripes extending parallel to the longitudinal direction (first direction) of the trench. In addition, the width of the n-type column regions in the short direction is 1p + The width of the p-type column region in the second direction is set to be wider than the width of the p-type column region directly under the gate trench. + The width is narrower than the width in the second direction of the portion of the mold region directly below the gate trench and wider than the Fin width.

[0096] The FinFET structure reduces carrier scattering and improves carrier mobility, lowering channel resistance and reducing on-resistance. By using an SJ structure for the drift layer, the impurity concentration of the n-type column region, which is the current path of the main current, is increased to reduce drift resistance, and the p-type column region reduces the carrier spreading resistance in the second direction, thereby reducing JFET resistance. In addition, by setting the widths of the n-type column region and the p-type column region in the short direction to the above conditions, p-type column regions are placed directly under the gate trenches adjacent to each other in the second direction. This further reduces the carrier spreading resistance in the second direction, thereby further reducing JFET resistance.

[0097] In a vertical MOSFET, the JFET resistance and drift resistance account for the majority of the on-resistance. According to the embodiment, as described above, among the multiple resistance components of the on-resistance, the resistance components other than the drift resistance (JFET resistance) can be reduced, so that the on-resistance can be reduced even in a high withstand voltage class where the drift resistance is dominant. The high withstand voltage class is, for example, a withstand voltage class of 1 kV or more (particularly, a withstand voltage class of 3.3 kV). Also, according to the embodiment, by setting each width in the short direction of the n-type column region and the p-type column region to the above conditions, it is possible to prevent the current path from being blocked due to misalignment in the second direction of the p-type column region, and therefore it is possible to prevent the JFET resistance from becoming high.

[0098] (Details of the second embodiment) A silicon carbide semiconductor device according to a second embodiment for solving the above-mentioned problems will be described below. FIGS. 4 to 6 are cross-sectional views showing a structure of a semi-silicon carbide semiconductor device according to the second embodiment. n of a silicon carbide semiconductor device 50 according to the second embodiment + Type source region 4, p ++ The layout of the n-type contact region 5 and the MOS gate 9 viewed from the front surface side of the semiconductor substrate 20 is the same as that of the first embodiment (see FIG. 1). Figures 4 to 6 show cross-sectional structures along the cutting lines A-A', B-B', and C-C' in FIG. 1, respectively. In FIG. 5, the boundary between the n-type column region 51 and the n-type buffer region 2a is shown by a dashed line.

[0099] The silicon carbide semiconductor device 50 according to the second embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment (see FIGS. 2 and 3) in that the longitudinal direction of the n-type column region 51 and the p-type column region 52 of the parallel pn layer 53 is perpendicular to the longitudinal direction (first direction X) of the gate trench 6. + Immediately below the first p-type source region 4, + The n-type column region 51 is in contact with the n-type region 31 and the n-type current diffusion region 33 and extends linearly in the second direction Y. The width Wn2 of the n-type column region 51 in the short side direction (first direction X) is + Type region 31 p ++It is wider than the width w22 in the first direction X of the portion directly under the mold contact region 5 (Wn2>w22).

[0100] The p-type column region 52 is ++ Directly below the first contact region 5, + The p-type column region 52 extends linearly in the second direction Y while contacting only the n-type region 31. The p-type column region 52 does not contact the n-type current diffusion region 33. The width Wp2 of the p-type column region 52 in the short side direction (first direction X) is + Type region 31 p ++ The width Wp2 in the first direction X is narrower than the width w41 of the portion directly under the p-type contact region 5 and is wider than the Fin width w11 (w22>Wp2>w11). ++ By extending linearly in the second direction Y directly below the p-type contact region 5, it is possible to prevent the current path (the connection point between the n-type current diffusion region 33 and the n-type column region 41) from being blocked due to misalignment of the p-type column region 52 in the second direction Y.

[0101] The widths Wn2, Wp2 in the short side directions of the n-type column region 51 and the p-type column region 52 are approximately uniform in the depth direction Z. The impurity concentrations of the n-type column region 51 and the p-type column region 52 are, for example, approximately uniform in the depth direction Z. A charge balance is generally maintained between the adjacent n-type column region 51 and the p-type column region 52. The drift resistance can be adjusted by the impurity concentration of the n-type column region 51.

[0102] Since the n-type column region 51 and the p-type column region 52 are perpendicular to the gate trench 6, the current paths of the body diodes (BD) formed in each of the unit cells 10a adjacent to each other in the second direction Y are linearly connected in the second direction Y by the n-type column region 51. This makes it possible to reduce the forward voltage Vf of the body diode of the unit cell 10a, and since the body diode is less likely to operate, the operation of a parasitic bipolar junction transistor (BJT) can be suppressed.

[0103] The body diode is a p ++ the p-type contact region 5, the p-type base region 3 and the first and second p-type + The n-type regions 31 and 32, the n-type current diffusion region 33, the n-type column region 51 and the n + A parasitic BJT is a parasitic diode formed by the pn junction (main junction) of the n-type drain region 1. + The n-type source region 4 serves as an emitter or collector, and the n-type current diffusion region 33, the n-type column region 51 and the n + The p-type drain region 1 serves as a collector or emitter, and the p-type base region 3 and the first and second p-type + The transistor has a parasitic npn bipolar junction transistor base formed by the type regions 31 and 32.

[0104] The method for manufacturing silicon carbide semiconductor device 50 according to the second embodiment may be the same as the method for manufacturing silicon carbide semiconductor device 10 according to the first embodiment, except that n-type column regions 51 and p-type column regions 52 of parallel pn layer 53 are arranged as described above.

[0105] As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained even when the n-type column regions and p-type column regions of the parallel pn layer are arranged in stripes perpendicular to the gate trench as viewed from the front surface side of the semiconductor substrate.

[0106] (Details of the Third Embodiment) A silicon carbide semiconductor device according to a third embodiment for solving the above problems will be described below. FIGS. 7 to 9 are cross-sectional views showing a structure of a silicon carbide semiconductor device according to the third embodiment. n of silicon carbide semiconductor device 60 according to the third embodiment + Type source region 4, p ++ The layout of the n-type contact region 5 and the MOS gate 9 viewed from the front surface side of the semiconductor substrate 20 is the same as that of the first embodiment (see FIG. 1). Figures 7 to 9 show cross-sectional structures along the cutting lines A-A', B-B', and C-C' in FIG. 1, respectively. In FIG. 7, the boundary between the n-type column region 61 and the n-type buffer region 2a is shown by a dashed line.

[0107] Silicon carbide semiconductor device 60 according to the third embodiment differs from silicon carbide semiconductor device 50 according to the second embodiment (see FIGS. 4 to 6) in that p ++ The third embodiment is characterized in that an n-type column region 61 of a parallel pn layer 63 is disposed directly below the n-type contact region 5. ++ An n-type current diffusion region 73 and an n-type column region 61 of the parallel pn layer 63 are disposed directly below the n-type contact region 5. + Immediately below the source region 4, the first and second p + The p-type regions 71 and 72 and the p-type column region 62 of the parallel pn layer 63 are arranged.

[0108] 1st, 2p + The first p-type regions 71 and 72 and the n-type current diffusion region 73 are selectively provided between the p-type base region 3 and the parallel pn layer 63. + The n-type region 71 is located closer to the bottom surface of the gate trench 6 than the n-type region 71. + The first p-type drain region 1 is provided at a position facing the bottom surface of the gate trench 6 and spaced apart from the p-type base region 3. + The mold region 71 has a predetermined width w41 and extends in the first direction X by a length substantially equal to the longitudinal length of the gate trench 6. + A width w41 in the second direction Y of a portion of the mold region 71 directly below the gate trench 6 is equal to or smaller than the width w1 of the gate trench 6 in the second direction Y and is wider than the fin width w11.

[0109] Next to each other, page 1 + The portions of the gate trench 6 in the type region 71 are + The first p-type source region 4 is connected to the first p-type source region 4. + The type region 71 is p ++ The first p-type contact region 5 is not provided directly below the first p-type contact region 5. + The n-type region 71 is adjacent to the bottom surface of the gate trench 6 in the depth direction Z. + The first p-type source region 4 is disposed opposite the first p-type source region 4 and is arranged in a ladder shape when viewed from the front surface side of the semiconductor substrate 20. + The mold region 71 has a second p +It is in contact with the gate insulating film 7 on the bottom surface of the gate trench 6 and the type region 72.

[0110] First p + The part directly below the n-type source region 4 of the type region 71 is in contact with the p-type column region 62 on the bottom surface. First p + The width w42 in the first direction X of the part directly below the n-type source region 4 of the type region 71 is, for example, narrower than the interval w32 between the p-type contact regions 5 adjacent to each other in the first direction X (w42 < w32). First p + The n of the first p-type region 71 + The width w42 in the first direction X of the part directly below the n-type source region 4 of the type region 71 is, for example, narrower than the interval w32 between the p-type contact regions 5 adjacent to each other in the first direction X (w42 < w32). First p ++ The width w42 in the first direction X of the part directly below the n-type source region 4 of the type region 71 is, for example, narrower than the interval w32 between the p-type contact regions 5 adjacent to each other in the first direction X (w42 < w32). First p + The n of the first p-type region 71 + The interval w43 at which the part directly below the n-type source region 4 of the type region 71 is arranged in the first direction X is, for example, wider than the width w31 in the first direction X of the p-type contact region 5 (w43 > w31). ++ The interval w43 at which the part directly below the n-type source region 4 of the type region 71 is arranged in the first direction X is, for example, wider than the width w31 in the first direction X of the p-type contact region 5 (w43 > w31).

[0111] Second p + The type region 72 is provided in contact with the p-type base region 3 and the first p-type region 71 between the adjacent gate trenches 6. + The type region 72 is provided in contact with the p-type base region 3 and the first p-type region 71 between the adjacent gate trenches 6. + That is, the second p-type region 72 is provided only directly below the n-type source region 4 and is scattered in the first direction X. + The second p-type region 72 is provided only directly below the n-type source region 4 and is scattered in the first direction X. + The second p-type region 72 is provided only directly below the n-type source region 4 and is scattered in the first direction X. + The second p-type region 72 is not provided directly below the p-type contact region 5. ++ The second p-type region 72 is not provided directly below the p-type contact region 5. + The second p-type region 72 is arranged in the first direction X with substantially the same width and substantially the same interval as the part directly below the n-type source region 4 of the first p-type region 71. + The n of the first p-type region 71 + The second p-type region 72 is arranged in the first direction X with substantially the same width and substantially the same interval as the part directly below the n-type source region 4 of the first p-type region 71.

[0112] The n-type current diffusion region 73 is provided directly below the p-type contact region 5 and terminates directly below the n-type source region 4 adjacent to the p-type contact region 5. First, second p ++ The n-type current diffusion region 73 is provided directly below the p-type contact region 5 and terminates directly below the n-type source region 4 adjacent to the p-type contact region 5. First, second p ++ The part directly below the p-type contact region 5 and the n of the first and second p-type regions 71, 72 and the n-type current diffusion region 73 + The n-type current diffusion region 73 is provided directly below the p-type contact region 5 and terminates directly below the n-type source region 4 adjacent to the p-type contact region 5. First, second p + The part directly below the p-type contact region 5 and the n of the first and second p-type regions 71, 72 and the n-type current diffusion region 73 ++ The part directly below the p-type contact region 5 and the n of the first and second p-type regions 71, 72 and the n-type current diffusion region 73+ The configuration other than the arrangement of the portion immediately below the source region 4 is the same as that of the first and second p + The n-type regions 31 and 32 and the n-type current spreading region 33 are similar.

[0113] The n-type column region 61 is ++ Directly below the first contact region 5, + The p-type column region 62 extends linearly in the second direction Y while contacting the n-type region 71 and the n-type current diffusion region 73. + Immediately below the first p-type source region 4, + The p-type column region 62 is in contact only with the n-type region 71 and extends linearly in the second direction Y. The p-type column region 62 is not in contact with the n-type current diffusion region 73.

[0114] The width Wn3 of the n-type column region 61 in the short side direction (first direction X) is + Type region 71 n + The width Wp3 of the p-type column region 62 in the short side direction (first direction X) is wider than the width w42 in the first direction X of the portion directly under the p-type source region 4 (Wn3>w42). + Type region 71 n + It is narrower than the width w42 in the first direction X of the portion directly under the type source region 4 and is wider than the Fin width w11 (w42>Wp3>w11).

[0115] The widths Wn3, Wp3 in the short side direction of the n-type column region 61 and the p-type column region 62 are approximately uniform in the depth direction Z. The impurity concentrations of the n-type column region 61 and the p-type column region 62 are, for example, approximately uniform in the depth direction Z. A charge balance is generally maintained between the adjacent n-type column region 61 and the p-type column region 62. The drift resistance can be adjusted by the impurity concentration of the n-type column region 61.

[0116] In addition, the p-type column region 62 is +By extending linearly in the second direction Y directly below the p-type source region 4, it is possible to prevent the current path (the connection point between the n-type current diffusion region 73 and the n-type column region 61) from being blocked due to misalignment of the p-type column region 62 in the second direction Y. In addition, the effect obtained by the n-type column region 61 and the p-type column region 62 intersecting the gate trench 6 at right angles is the same as that in the second embodiment (suppression of parasitic BJT operation).

[0117] The method for manufacturing the silicon carbide semiconductor device 60 according to the third embodiment is the same as the method for manufacturing the silicon carbide semiconductor device 50 according to the second embodiment, except that the arrangement of the n-type column region 61 and the p-type column region 62 of the parallel pn layer 63 and the first and second p + The arrangement of the n-type regions 71 and 72 and the n-type current diffusion region 73 may be set as described above.

[0118] As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained even when the n-type column region and the p-type column region of the parallel pn layer are arranged in stripes perpendicular to the gate trench as viewed from the front surface side of the semiconductor substrate. + Even when the second embodiment is disposed directly under the source region, the same effect as that of the second embodiment can be obtained.

[0119] (Verification example) The relationship between the thickness Lsj and the on-resistance RonA of the parallel pn layer 43 of the silicon carbide semiconductor device 10 (see FIGS. 2 and 3) according to the first embodiment was examined. The electrical characteristics of the parallel pn layer are the same regardless of the presence or absence of a FinFET structure. For this reason, the electrical characteristics of the parallel pn layer were examined using a normal SiC-MOSFET (hereinafter referred to as a comparative example) that does not have a FinFET structure. FIG. 10 is a cross-sectional view showing the structure of the comparative example. FIG. 11 is a characteristics diagram showing the results of examining the on-resistance characteristics of the comparative example. The horizontal axis of FIG. 11 is the thickness T_SJ [μm] of the parallel pn layer 243 of the comparative example, and the vertical axis is the on-resistance RonA [mΩ·cm] of the comparative example. 2 ].

[0120] 10 is a vertical MOSFET with an SJ structure in which drift layer 202 is a parallel pn layer 243, the width between adjacent gate trenches 206 is relatively wide, and the MOSFET has a normal unit cell that is not a FinFET structure. Comparative example 210 differs from silicon carbide semiconductor device 10 according to the first embodiment in that the width between adjacent gate trenches 206 is relatively wide, and the first and second p + Specifically, the semiconductor substrate 220 has an n-type region 231 and a n-type region 232. + The n-type drain region 201 + The epitaxial layers 222, 223 which become the drift layer 202 and the p-type base region 203 are epitaxially grown in this order on a starting substrate 221.

[0121] The drift layer 202 is made up of a p-type base region 203 and an n + Between the n-type drain region 201 + The n-type drain region 201 is in contact with the drift layer 202. + The portion on the side of the n-type source region 204 is a parallel pn layer 243. As in the first embodiment, the parallel pn layer 243 is formed by alternately and repeatedly arranging n-type column regions 241 and p-type column regions 242 adjacent to each other in the second direction Y. As in the first embodiment, the n-type column regions 241 and the p-type column regions 242 extend in a stripe shape in the first direction X. + The portion between the p-type drain region 201 and the n-type buffer region 202a is an n-type buffer region 202a. The thickness T_SJ of the parallel pn layer 243 is determined by the length of the p-type column region 242 in the depth direction Z.

[0122] The parallel pn layer 243 was formed inside the n-type epitaxial layer 222 by a multi-stage epitaxial method. The n-type epitaxial layer 222 was formed by epitaxially growing n-type layers 250-259 in multiple stages. The p-type regions that become the p-type column region 242 are formed adjacent to each of the n-type layers 250-257 in the depth direction Z. The portion of the n-type layer 250 excluding the p-type column region 242 becomes the n-type buffer region 202a. The n-type layer (1 stlayer~7 th The portions of n-type layer 250, excluding p-type column region 242, of n-type layer 251 to 257 become n-type column region 241. The thickness of n-type layer 250 corresponds to the thickness of n-type buffer region 202a and is thicker than the thickness of n-type layer 251. N-type layers 251 to 259 have the same thickness.

[0123] The semiconductor substrate 220 has a front surface (main surface on the p-type epitaxial layer 223 side) on which a p-type base region 203 and a n-type + Type source region 204, p ++ A trench gate structure is provided, which is composed of a contact region 205, a gate trench 206, a gate insulating film 207, and a gate electrode 208. + The p-type source region 204 and ++ The n-type contact region 205 is a diffusion region formed by ion implantation in the surface region of the front surface of the semiconductor substrate 220 (the surface region of the p-type epitaxial layer 223). + The p-type source region 204 and ++ The contact region 205 is selectively provided between the front surface of the semiconductor substrate 220 and the p-type base region 203 in contact with the p-type base region 203 .

[0124] n + The p-type source region 204 and ++ The p-type contact region 205 is in ohmic contact with the source electrode 213 on the front surface of the semiconductor body 220. + The p-type source region 204 extends along the sidewall of the gate trench 206 in the first direction X by a length substantially equal to the longitudinal length of the gate trench 206. + The source region 204 is in contact with the gate insulating film 207 on the sidewall of the gate trench 206. + The source region 204 is adjacent to the ++ The mold contact region 205 is provided approximately in the center between the adjacent gate trenches 206 and spaced apart from the gate trenches 206 .

[0125] The gate trench 206 extends in a stripe shape in the first direction X, as in the first embodiment. The gate trench 206 extends from the front surface of the semiconductor substrate 220 to the n-th layer in the depth direction Z. + A first p-type source region 204 and a first p-type base region 203 are formed through the p-type source region 204 and the p-type base region 203. + The gate trench 206 is provided with a gate insulating film 207 therebetween. The gate electrode 208 is electrically insulated from the source electrode 213 by an interlayer insulating film 211. The drain electrode 214 is provided on the back surface of the semiconductor substrate 220 and has an n-type doped region 231. + The first and second p-type drain regions 201 are electrically connected to the first and second p-type drain regions 201. + The n-type regions 231 and 232 and the n-type current diffusion region 233 are formed in the upper layer (n + The n-type layers 258 and 259 are diffusion regions formed by ion implantation into the n-type layers 258 and 259 on the side of the p-type source region 204, and are selectively provided between the p-type base region 203 and the drift layer 202, respectively.

[0126] 1st p. + The n-type region 231 is located closer to the bottom of the gate trench 206 than the n-type region 231. + The first p-type drain region is provided at a deep position away from the p-type base region 203. + The mold region 231 is located at a position facing the bottom surface of the gate trench 206 and at approximately the center (p ++ The first p regions 204 and 205 extend in the first direction X at a length substantially equal to the longitudinal length of the gate trench 6. + The mold regions 231 are partially connected to each other at a portion not shown. + The first p region 231 is in contact with the gate insulating film 207 at the bottom of the gate trench 206. + The n-type region 231 is in contact with the n-type column region 241 at its lower surface. ++ The first p-type contact region 205 + The mold region 231 is provided away from the gate trench 206. ++The first p-type contact region 205 + The lower surface of the type region 231 contacts the p-type column region 242 .

[0127] 2nd p. + The second p-type region 232 is provided between adjacent gate trenches 206, away from the gate trenches 206, and in contact with the p-type base region 203. + The type region 232 is p ++ The first p-type contact region 205 + The second p-type region 231 and the p-type base region 203 are in contact with these regions and extend in the first direction X with a length substantially equal to the longitudinal length of the gate trench 6. + The mold region 232 + The n-type region 231 and the p-type base region 203 are electrically connected to each other. The n-type current diffusion region 233 is in contact with the p-type base region 203 at its upper surface and in contact with the n-type column region 241 at its lower surface. + The n-type current diffusion region 233 contacts the gate insulating film 207 on the side wall of the gate trench 206. The n-type current diffusion region 233 is formed in multiple stages, divided into an upper portion 233a and a lower portion 233b.

[0128] 11 shows the results of actual measurement (actual measurement) of the on-resistance RonA of this comparative example 210 with variously changing the thickness T_SJ of the parallel pn layer 243, and the on-resistance RonA (sim) versus the thickness T_SJ of the parallel pn layer 243 simulated based on the actual measurement results. The thickness T_SJ of the parallel pn layer 243 corresponds to the thickness Lsj of the parallel pn layer 43 of the silicon carbide semiconductor device 10 (see FIGS. 2 and 3) according to the first embodiment. FIG. 11 shows a sample of the comparative example 210 operated at room temperature (RT: Room Temperature, about 25° C.) and a sample of the comparative example 210 operated in a temperature environment of 175° C.

[0129] From the results shown in FIG. 11, it was confirmed that the effect of reducing the on-resistance RonA can be obtained by setting the thickness T_SJ of the parallel pn layer 243 to 2 μm or more and increasing the thickness T_SJ of the parallel pn layer 243. +The depth D201 of the type region 231 is set to 0.5 μn. Therefore, the thickness T_SJ of the parallel pn layer 243 is set to + It is preferable that the thickness Lsj of the parallel pn layer 43 in the silicon carbide semiconductor device 10 (see FIGS. 2 and 3) according to the first embodiment is 2 μm or more, and the thickness Lsj of the first pn layer 43 is 2 μm or more. + It has been confirmed that it is preferable to set the depth d1 of the mold region 31 to four times or more.

[0130] Although not shown, parallel pn layers 53, 63 of silicon carbide semiconductor devices 50, 60 according to the second and third embodiments have characteristics similar to those in FIG.

[0131] The present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, + Instead of forming the n-type source region by ion implantation, + The type source region is n + In this case, the n-type epitaxial layer may be formed. + n type source region + The surface of the epitaxial layer is the front surface of the semiconductor substrate. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0132] INDUSTRIAL APPLICABILITY As described above, silicon carbide semiconductor devices according to the present disclosure are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of symbols]

[0133] 1n + Type drain region 2. Drift layer 2a n-type buffer region 3 p-type base region 4n + Type Source Area 5 p ++Mold Contact Area 6 Gate trench 7 Gate insulating film 8. Gate electrode 9. MOS Gate 10,50,60 Silicon carbide semiconductor device 10a Unit cell 11 Interlayer insulating film 11a Contact hole in interlayer insulating film 12 Contact electrode 13 Front electrode 14 Back electrode 20 Semiconductor substrate 21 n + Starting substrate 22 n-type epitaxial layer 23 p-type epitaxial layer 31,32,71,72 p for electric field relaxation + type area 33,73 n-type current diffusion region 41, 51, 61 n-type column region 42,52,62 p-type column region 43,53,63 parallel pn layer Lsj Parallel pn layer thickness w1 Width of trench in second direction w11 Fin width w21,w22,w41,w42 P for electric field relaxation + Mold area width w31 p ++ Width of the mold contact region in the first direction w32 adjacent p in the first direction ++ Spacing between mold contact areas w43 P for electric field relaxation + The spacing at which the mold regions are placed d1 p for electric field relaxation + Depth of the part of the mold region directly below the gate trench X: a first direction parallel to the front surface of the semiconductor body Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. a parallel pn layer in which first conductivity type regions and second conductivity type regions are alternately arranged in a repeated manner, the parallel pn layer being provided inside a semiconductor substrate made of silicon carbide; a first semiconductor region of a second conductivity type provided between a first main surface of the semiconductor substrate and the parallel pn layer; a second semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region and having a higher impurity concentration than the first semiconductor region; a gate trench penetrating the third semiconductor region, the second semiconductor region, and the first semiconductor region in a depth direction; a first high concentration region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region, the first high concentration region being selectively provided in contact with the parallel pn layer at a position facing a bottom surface of the gate trench between the first semiconductor region and the parallel pn layer; a gate electrode provided inside the gate trench via a gate insulating film; a first electrode electrically connected to the third semiconductor region, the second semiconductor region, the first semiconductor region, and the first high concentration region; A second electrode provided on a second main surface of the semiconductor substrate; Equipped with a double-gate structure in which one channel is formed in the entire area of ​​the first semiconductor region between the gate trenches adjacent to each other, the channel being sandwiched between the gate trenches from both side surfaces; The width of the first conductivity type region is wider than the width of the first high concentration region, a width of the second conductivity type region is narrower than a width of the first high concentration region and is wider than a width between adjacent ones of the gate trenches.

2. the gate trenches extend linearly in a first direction parallel to the first main surface of the semiconductor body, and are arranged in a stripe shape adjacent to each other in a second direction parallel to the first main surface of the semiconductor body and perpendicular to the first direction; 2 . The silicon carbide semiconductor device according to claim 1 , wherein the first conductivity type regions and the second conductivity type regions are repeatedly arranged alternately in the second direction and extend linearly in the first direction.

3. 3 . The silicon carbide semiconductor device according to claim 2 , wherein the second conductivity type region faces a bottom surface of the gate trench for every other one of the plurality of gate trenches adjacent to each other in the second direction.

4. the gate trenches extend linearly in a first direction parallel to the first main surface of the semiconductor body, and are arranged in a stripe shape adjacent to each other in a second direction parallel to the first main surface of the semiconductor body and perpendicular to the first direction; 2 . The silicon carbide semiconductor device according to claim 1 , wherein the first conductivity type regions and the second conductivity type regions are repeatedly arranged alternately in the first direction and extend linearly in the second direction.

5. The second semiconductor regions and the third semiconductor regions are alternately and repeatedly arranged in the first direction, the first high concentration regions facing the bottom surfaces of the gate trenches adjacent to each other are partially connected to each other at a position facing the third semiconductor region in a depth direction, 5 . The silicon carbide semiconductor device according to claim 4 , wherein the second conductivity type region extends linearly in the second direction adjacent to a connection portion between the first high concentration regions in the depth direction.

6. The second semiconductor regions and the third semiconductor regions are alternately and repeatedly arranged in the first direction, the first high concentration regions facing the bottom surfaces of the gate trenches adjacent to each other are partially connected to each other at a position facing the second semiconductor region in a depth direction, 5 . The silicon carbide semiconductor device according to claim 4 , wherein the second conductivity type region extends linearly in the second direction adjacent to a connection portion between the first high concentration regions in the depth direction.

7. The silicon carbide semiconductor device according to claim 1 , wherein the parallel pn layer has a thickness of 2 μm or more.

8. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the parallel pn layer has a thickness equal to or greater than four times a thickness of the first highly doped region.

9. a fourth semiconductor region of a first conductivity type provided between the first semiconductor region and the parallel pn layer in contact with the first semiconductor region and the first high concentration region and having an impurity concentration equal to or higher than an impurity concentration of the first conductivity type region; 2 . The silicon carbide semiconductor device according to claim 1 , wherein the fourth semiconductor region terminates on the second electrode side at the same depth position as the first high concentration region.

10. the first high concentration regions facing the bottom surfaces of the gate trenches adjacent to each other are partially connected between the gate trenches adjacent to each other, 2. The silicon carbide semiconductor device according to claim 1, further comprising: a second high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, selectively provided in contact with the first semiconductor region and a connection portion between the first semiconductor region and a connection portion between the first high concentration regions between the gate trenches adjacent to each other, the second high concentration region being in contact with the first semiconductor region and the connection portion.

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