Super junction semiconductor device

Abstract

To provide a super junction semiconductor device capable of suppressing charge balance deviations in an edge termination region.SOLUTION: It has a parallel pn layer 51 with alternating repetition of first and second conductive type regions 52 and 53 in an active region and a termination region 30, and a third semiconductor region 32 of the second conductive type that constitutes a voltage-resistant structure in the termination region 30, and the second conductive type region 53 has a plurality of second conductive small regions stacked on top of each other, among the plurality of second conductive type small regions, the second conductive type small region 53a, which is the most on the first main surface side of the semiconductor substrate, also serves as the third semiconductor region 32.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This disclosure relates to superjunction semiconductor devices. [Background technology]

[0002] Patent Document 1 describes a silicon carbide semiconductor device having a drift layer including a superjunction structure (SJ structure) in which three-layer parallel pn layers are stacked in sequence, where the parallel pn layers have the same structure in the active region, edge termination region, and intermediate region connecting the two. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-089916 Summary of the Invention [Problem to be solved by the invention]

[0004] However, a conventional silicon carbide semiconductor device with an SJ structure has a problem in that a charge balance shift occurs in the edge termination region.

[0005] An object of the present disclosure is to provide a super-junction semiconductor device capable of suppressing deviation in charge balance in an edge termination region. [Means for solving the problem]

[0006] A super-junction semiconductor device according to one aspect of the disclosure is as follows. An active region is provided in a semiconductor substrate made of silicon carbide. A termination region is provided in the semiconductor substrate, surrounding the periphery of the active region. A first semiconductor layer of a second conductivity type is provided in a first main surface of the semiconductor substrate. In the active region and the termination region, a parallel pn layer is provided inside the semiconductor substrate, in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate. In the active region, a first semiconductor region of a first conductivity type is selectively provided in a surface layer of the first semiconductor layer on the opposite side to the semiconductor substrate side. A trench is provided that penetrates the first semiconductor region and the first semiconductor layer to reach the semiconductor substrate. A gate electrode is provided inside the trench via a gate insulating film. A first electrode is provided on the first main surface of the semiconductor substrate, electrically connected to the first semiconductor region. A second electrode is provided on a second main surface of the semiconductor substrate. A third semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the parallel pn layer in the termination region, surrounding the periphery of the active region and electrically connected to the first electrode to form a voltage withstanding structure. The second conductivity type region is formed by stacking a plurality of second conductivity type small regions, and the second conductivity type small region closest to the first main surface of the semiconductor substrate among the plurality of second conductivity type small regions also serves as the third semiconductor region. Effect of the Invention

[0007] The super-junction semiconductor device according to the present disclosure has the advantage that it is possible to suppress deviations in the charge balance of the edge termination region. [Brief description of the drawings]

[0008] [Figure 1] 2 is a cross-sectional view showing a structure of an active region of the SJ-MOSFET according to the embodiment. [Diagram 2] 2 is a cross-sectional view showing a structure of an intermediate region and an edge termination region of the SJ-MOSFET according to the embodiment. FIG. [Diagram 3]FIG. 1 is a cross-sectional view showing a state during the manufacture of a parallel pn layer of an SJ-MOSFET according to an embodiment (part 1). [Figure 4] FIG. 2 is a cross-sectional view showing a state during the manufacture of the parallel pn layer of the SJ-MOSFET according to the embodiment (part 2). [Diagram 5] FIG. 3 is a cross-sectional view showing a state during the manufacture of the parallel pn layer of the SJ-MOSFET according to the embodiment (part 3). [Figure 6] FIG. 1 is a cross-sectional view showing details of the edge termination region of a conventional SJ-MOSFET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] <Overview of the embodiment of the present disclosure> (1) A super-junction semiconductor device according to one aspect of the disclosure is as follows. An active region is provided in a semiconductor substrate made of silicon carbide. A termination region is provided in the semiconductor substrate, surrounding the periphery of the active region. A first semiconductor layer of a second conductivity type is provided in a first main surface of the semiconductor substrate. A parallel pn layer is provided in the active region and the termination region, in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate. In the active region, a first semiconductor region of a first conductivity type is selectively provided in a surface layer of the first semiconductor layer on the opposite side to the semiconductor substrate side. A trench is provided that penetrates the first semiconductor region and the first semiconductor layer to reach the semiconductor substrate. A gate electrode is provided in the trench via a gate insulating film. A first electrode is provided in the first main surface of the semiconductor substrate, electrically connected to the first semiconductor region. A second electrode is provided in a second main surface of the semiconductor substrate. A third semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the parallel pn layer in the termination region, surrounding the periphery of the active region and electrically connected to the first electrode to form a voltage withstanding structure. The second conductivity type region is formed by stacking a plurality of second conductivity type small regions, and the second conductivity type small region closest to the first main surface of the semiconductor substrate among the plurality of second conductivity type small regions also serves as the third semiconductor region.

[0010] According to the above disclosure, the p-type region that is the uppermost part of the p-type region (second conductivity type region) of the parallel pn layer also serves as the p-type region (second conductivity type third semiconductor region) that constitutes the JTE structure, and the p-type region that is the uppermost part of the parallel pn layer functions as the JTE structure. Therefore, the p-type region of the parallel pn layer and the p-type region that constitutes the JTE structure do not overlap, and it is possible to suppress deviation of the charge balance in the edge termination region. Furthermore, it is no longer necessary to form the p-type region that constitutes the JTE structure, so the process of forming the semiconductor device can be simplified and the manufacturing cost can be reduced.

[0011] (2) Furthermore, the super-junction semiconductor device according to this disclosure, in the above-mentioned (1), may further include a second semiconductor region of a second conductivity type provided at the bottom of the trench, and the second semiconductor region and the third semiconductor region may have surfaces at the same depth on the second main surface side of the semiconductor substrate.

[0012] According to the above disclosure, the p-type region, the p-type region constituting the JTE structure and the p + The bottom of the mold region is a straight line. + The corners at the bottom of the mold region are eliminated, and electric field concentration at these corners can be suppressed.

[0013] (3) In the super-junction semiconductor device according to the present disclosure, in the above-mentioned (2), the second semiconductor region and the third semiconductor region may have the same thickness.

[0014] <Foundational knowledge of this disclosure> First, the problems of conventional super junction semiconductor devices will be described. Conventionally, semiconductor devices with a super junction (SJ) structure have been known in which the drift layer is a parallel pn layer formed by alternately and repeatedly arranging n-type regions and p-type regions adjacent to each other in a direction parallel to the main surface of the substrate. The n-type regions and p-type regions constituting the parallel pn layer extend in a stripe shape parallel to the main surface of the semiconductor substrate (semiconductor chip). The n-type regions and p-type regions constituting the parallel pn layer are provided substantially uniformly over substantially the entire semiconductor substrate, from the active region in the center of the semiconductor substrate (chip center) to the edge of the semiconductor substrate (chip edge).

[0015] The structure of a conventional silicon carbide semiconductor device with an SJ structure will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) as an example. Figure 6 is a cross-sectional view showing the details of the edge termination region of a conventional SJ-MOSFET.

[0016] 6 is a vertical MOSFET with an SJ structure that has a typical trench gate structure in the active region of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide, and has a drift layer 102 as a parallel pn layer 151. The semiconductor substrate 140 has a rectangular planar shape. The active region has a substantially rectangular planar shape, and is provided in the center of the semiconductor substrate 140 (chip center). The active region is surrounded by an edge termination region 130 with an intermediate region 120 interposed therebetween.

[0017] A gate wiring layer (not shown), such as a gate runner, is disposed in the intermediate region 120. The edge termination region 130 is a region between the intermediate region 120 and an end (chip end) of the semiconductor substrate 140. The edge termination region 130 includes a junction termination extension (JTE) structure 132 and an n + A type channel stop region (not shown) is disposed in the JTE structure 132. The JTE structure 132 surrounds the active region 110 via the intermediate region 120.

[0018] Parallel pn layer 151 is uniformly provided over substantially the entire semiconductor substrate 140 from the active region to edge termination region 130. Parallel pn layer 151 has an SJ structure in which n-type regions 152 and p-type regions 153 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of semiconductor substrate 140. N-type regions 152 and p-type regions 153 of parallel pn layer 151 extend in stripes in a second direction Y parallel to the front surface of semiconductor substrate 140 and perpendicular to first direction X.

[0019] The n-type region 152 and the p-type region 153 of the parallel pn layer 151 are connected to the JTE structure 132 and + Directly below the channel stopper region (n + The parallel pn layer 151 is disposed in substantially the entire edge termination region 130 on the n-type drain region 101 side. + The JTE structure 132 and the n-type channel stopper region are formed in the depth direction Z around the entire circumference of the channel stopper region. + adjacent to the type channel stopper region, the JTE structure 132 and the n + The upper surface of the semiconductor substrate 140 is reached between the first and second channel stopper regions.

[0020] A cross-sectional structure of a conventional SJ-MOSFET 150 will be described. The semiconductor substrate 140 is a n-type silicon carbide semiconductor. + The epitaxial layers 142 and 143 that become the drift layer 102 and the p-type base region 104 are laminated in this order on a starting substrate 141. The main surface of the semiconductor substrate 140 on the p-type epitaxial layer 143 side is the front surface, and the n + The n-type drain region 101 + The main surface on the mold starting substrate 141 side is referred to as the back surface. The epitaxial layer 142 is a portion that becomes the drift layer (drift region) 102, and includes a parallel pn layer 151.

[0021] The p-type epitaxial layer 143 in the edge termination region 130 is removed by etching, forming a step 131 on the front surface of the semiconductor substrate 140.- The epitaxial layer 142 is exposed. - The p-type epitaxial layer 142 includes a p-type region 133 constituting the JTE structure 132 and an n-type region 134. + and a mold channel stopper region are selectively provided.

[0022] The p-type region 133 of the JTE structure 132 is a p + The p-type regions 111 and 112 a are fixed to the potential of a source electrode (not shown) via the p-type base region 104 .

[0023] The n-type regions 152 and p-type regions 153 of the parallel pn layer 151 are equally spaced across substantially the entirety of the semiconductor substrate 140 from the active region to the edge termination region 130. The n-type regions 152 and p-type regions 153 of the parallel pn layer 151 are p + The p-type region 111 is disposed directly below the p-type region 133 in the edge termination region 130, and is disposed directly below the p-type region 133 in the depth direction Z. + Type regions 111 and p - It contacts the mold area 133 .

[0024] The carrier concentration (impurity concentration) and width (width in the first direction X) of each of the n-type region 152 and p-type region 153 of the parallel pn layer 151 are set so that charge balance is achieved between the adjacent n-type region 152 and p-type region 153 of the parallel pn layer 151.

[0025] The charge balance means that the amount of charge expressed by the product of the carrier concentration and width of n-type region 152 is approximately the same as the amount of charge expressed by the product of the carrier concentration and width of p-type region 153, within a range including tolerances due to process variations. A field oxide film 114 is provided on p-type region 133 of JTE structure 132 and semiconductor substrate 140.

[0026] In a conventional SJ-MOSFET 150, a JTE structure 132 is formed to provide a breakdown voltage for edge termination region 130. In edge termination region 130, p-type region 153 of pn layer 151 overlaps with p-type region 133 of JTE structure 132, and in the overlapping region (region S101 in FIG. 6), the impurity concentration is the sum of the impurity concentration of p-type region 153 of pn layer 151 and the impurity concentration of p-type region 133 of JTE structure 132. This poses a problem of a charge balance shift in edge termination region 130. Also, + Since the p-type region 111 is formed deeper than the p-type region 133 of the JTE structure 132, + A corner (S102 in FIG. 6) is formed at the bottom of mold region 111, and there is a problem in that the electric field is concentrated at this corner.

[0027] Preferred embodiments of the super-junction semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions marked with n or p respectively have electrons or holes as majority carriers. In addition, + and - marked with n or p respectively indicate a higher impurity concentration and a lower impurity concentration than layers and regions not marked with them. In the following description of the embodiments and the accompanying drawings, similar configurations are marked with the same reference numerals, and duplicated explanations will be omitted.

[0028] (Details of the embodiment) A super-junction semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. The structure of the super-junction semiconductor device according to the embodiment will be described using an SJ-MOSFET as an example. Fig. 1 is a cross-sectional view showing the structure of an active region of an SJ-MOSFET according to the embodiment. Fig. 2 is a cross-sectional view showing the structure of an intermediate region and an edge termination region of an SJ-MOSFET according to the embodiment.

[0029] Figure 1 shows one unit cell among multiple unit cells (components of an element) of the same structure arranged in an active region 10. Figure 2 shows the area from near the boundary between an intermediate region 20 and an edge termination region 30 to the end of a semiconductor substrate 40 (the chip end).

[0030] 1 and 2 is a vertical MOSFET with a trench gate structure (element structure) of an SJ structure that includes an active region 10, an intermediate region 20, and an edge termination region 30 in a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and has a drift layer (drift region) 2 as a parallel pn layer 51 extending from the active region 10 to the edge termination region 30. The active region 10 is a region through which a main current flows when the MOSFET is in an on-state, and is located in the center of the semiconductor substrate 40 (chip center).

[0031] 1, the active region 10 has a typical trench gate structure provided on the front surface side of a semiconductor substrate 40. The trench gate structure includes a p-type base region (a first semiconductor layer of a second conductivity type) 4, a n + A first conductive type source region (a first semiconductor region of a first conductivity type) 5, p ++ The semiconductor substrate 40 is made of silicon carbide. + The epitaxial layers 42 and 43 which will become the drift layer 2 and the p-type base region 4 are deposited in this order on the front surface of a starting substrate 41 .

[0032] The main surface of the semiconductor substrate 40 on the side of the p-type epitaxial layer 43 is the front surface, and + The main surface on the mold starting substrate 41 side is referred to as the back surface (second main surface). + The starting substrate 41 is n + The gate trench 7 penetrates the p-type epitaxial layer 43 from the front surface of the semiconductor substrate 40 in the depth direction Z to form an n-type - Extending into the epitaxial layer 42 .

[0033] The gate trench 7 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 (here, in the second direction Y). A gate electrode 9 is provided inside the gate trench 7 via a gate insulating film 8. The p-type base region 4, the n + Type source region 5 and p ++The p-type contact regions 6 are selectively provided between adjacent gate trenches 7. The p-type base region 4 is formed by the n-type epitaxial layer 43. + Type source region 5 and p ++ This is the portion excluding the mold contact region 6.

[0034] n + Type source region 5 and p ++ The p-type contact region 6 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 4 in contact with the p-type base region 4, and is exposed on the front surface of the semiconductor substrate 40. The exposure on the front surface of the semiconductor substrate 40 means that the p-type contact region 6 is in contact with the source electrode 15 in a contact hole of the interlayer insulating film 14. ++ The contact region 6 is an n + The source region 5 is disposed farther from the gate trench 7 than the source region 5 .

[0035] The parallel pn layer 51 is - The parallel pn layer 51 is provided at the above-mentioned predetermined position inside the type epitaxial layer 42. - Each time the n-type epitaxial layer 42 is epitaxially grown in multiple stages, - The n-type region (first conductivity type region) 52 and the p-type region (second conductivity type region) 53 are formed by selectively forming regions of the same conductivity type adjacent to each other by implanting ions into the n-type epitaxial layer 42 in the depth direction Z.

[0036] In the active region 10, between the p-type base region 4 and the parallel pn layer 51 (drift layer 2), an n-type current diffusion region 3 and a p + The n-type current diffusion region 3 and the p-type current diffusion region 4 are selectively provided. + The mold regions 11 and 12 are, for example, n - The n-type current diffusion region 3 and the p-type epitaxial layer 42 are diffusion regions formed by ion implantation. + The n-type regions 11 and 12 are located closer to the bottom surface of the gate trench 7 than the n-type regions 11 and 12. +The gate trench 7 is disposed at a deep position on the side of the type drain region 1 and extends linearly in the second direction Y in parallel with the gate trench 7 .

[0037] The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + The p-type regions 11 and 12 are in contact with the p-type base region 4 and the n-type region 52 of the parallel pn layer 51, and are located closer to the n-type region 52 than the bottom surface of the gate trench 7. + The n-type current diffusion region 3 is replaced by a n-type drain region 1. - A non-implanted portion of the type epitaxial layer 42 may be disposed.

[0038] p + The mold regions 11 and 12 have the function of reducing the electric field applied to the bottom surface of the gate trench 7. + The p-type regions 11 and 12 are in contact with different p-type regions 53 of the parallel pn layer 51 in the depth direction Z. + The p-type region (second semiconductor region of the second conductivity type) 11 is disposed apart from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The p-type region 12 is in contact with the p-type base region 4 between the adjacent gate trenches 7 and has a p + It is provided apart from the mold region 11 and the gate trench 7 .

[0039] The interlayer insulating film 14 is provided on the entire first main surface side of the semiconductor substrate 40 so as to cover the gate electrode 9 embedded in the trench 7. The source electrode (first electrode) 15 is connected to the n-type semiconductor substrate 40 via a contact hole opened in the interlayer insulating film 14. + Type source region 5 and p ++ The source electrode 15 is in contact with the gate electrode 9 through the interlayer insulating film 14. + A drain electrode (second electrode) 16 is provided on the entire back surface of the starting mold substrate 41.

[0040] 2, the edge termination region 30 is a region between the intermediate region 20 and the end of the semiconductor substrate 40, and surrounds the periphery of the active region 10 via the intermediate region 20. The intermediate region 20 is adjacent to the active region 10 and surrounds the periphery of the active region 10. The intermediate region 20 and the edge termination region 30 have an SJ structure with the drift layer 2 as a parallel pn layer 51.

[0041] The edge termination region 30 has a function of maintaining a breakdown voltage by mitigating the electric field on the front surface (first main surface) side of the semiconductor substrate 40 of the drift layer 2 in the active region 10 and the intermediate region 20. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the element does not malfunction or break down. The edge termination region 30 has a breakdown voltage structure including a junction termination extension (JTE) structure 32 composed of a p-type region (third semiconductor region of the second conductivity type) 33 and an n-type region (third semiconductor region of the second conductivity type) 34. + A type channel stopper region (not shown) is disposed in the JTE structure 32. The JTE structure 32 surrounds the active region 10 via the intermediate region 20.

[0042] The p-type epitaxial layer 43 in the edge termination region 30 is removed by etching, and a step 31 is formed on the front surface of the semiconductor substrate 40. The front surface of the semiconductor substrate 40 is more n-type on the edge termination region 30 side than on the active region 10 side, with the step 31 as a boundary. + The front surface of the semiconductor substrate 40 in the edge termination region 30 is recessed toward the n-type drain region 1. The front surface of the semiconductor substrate 40 in the edge termination region 30 is exposed by removing the p-type epitaxial layer 43. - 4 is an exposed surface of the type epitaxial layer 42.

[0043] JTE structure 32 is a structure in which p-type regions 33 are concentrically arranged adjacent to and surrounding active region 10 via intermediate region 20. JTE structure 32 reduces electric field concentration outside intermediate region 20, making it possible to prevent element destruction due to application of a voltage less than a predetermined voltage (the breakdown voltage of edge termination region 30).

[0044] The parallel pn layer 51 has an SJ structure in which n-type regions 52 and p-type regions 53 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 52 and p-type regions 53 of the parallel pn layer 51 extend in a striped pattern to the vicinity of the ends of the intermediate region 20 and the edge termination region 30 in a second direction Y that is parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X.

[0045] The n-type region 52 and the p-type region 53 of the parallel pn layer 51 are aligned in the depth direction Z from the p + The p-type region 53 of the parallel pn layer 51 is in contact with the p-type region 11. + The potential is fixed to the potential of the source electrode 15 (see FIG. 1) via the mold region 12a.

[0046] In the edge termination region 30, the parallel p-n layer 51 is disposed outside the outer end (periphery) of the JTE structure 32 in the first direction X, such that at least one p-type region 53 is disposed outside the outer end (outer periphery) of the JTE structure 32 in the first direction X.

[0047] By arranging the p-type region 53 of the parallel p-n layer 51 outward from the outer end of the JTE structure 32 in the first direction X, it is possible to suppress electric field concentration at the outer end of the JTE structure 32 when the MOSFET is off. The outer end of the JTE structure 32 is the outer end of the p-type region 33 of the JTE structure 32. The parallel p-n layer 51 may be arranged in the first direction X within a range of, for example, about 10 μm or less from the outer end of the JTE structure 32.

[0048] The range in which the parallel p-n layers 51 are arranged is set within the above-mentioned range from the outer end of the JTE structure 32 in the first direction X, and the number of floating p-type regions 53 arranged in the edge termination region 30 is reduced. This makes it possible to reduce the amount of accumulated charge of minority carriers (holes) that accumulate in the edge termination region 30 due to MOSFET switching or the like and remain without being discharged to the outside. For this reason, it is preferable to reduce the number of p-type regions 53 arranged outside the outer end of the JTE structure 32 in the first direction X.

[0049] In edge termination region 30, n-type region 52 and p-type region 53 of parallel pn layer 51 contact JTE structure 32 in depth direction Z. + The potential is fixed to the potential of the source electrode 15 (see FIG. 1) via the mold region 12a.

[0050] In the intermediate region 20, a p-type base region 4 and a p-type junction region 5 are formed on the front surface side of the semiconductor substrate 40 from the active region 10. + p corresponding to the lower part of the mold region 12 + Type region 12a and p + p corresponding to the upper part of the mold region 12 + The mold region 12b extends. + The lower part of the mold region 12 is p + Type 12 p + The part is the same height as the mold region 11, and p + The upper part of the mold region 12 is p + Type 12 p + This is the portion on the source electrode 15 side from the mold region 11 .

[0051] In the intermediate region 20 and the edge termination region 30, an insulating layer in which a field oxide film 35 and an interlayer insulating film (not shown) are laminated in this order is provided on the front surface of the semiconductor substrate 40. In the intermediate region 20, a polysilicon (poly-Si) layer (not shown) and a metal wiring layer (not shown) are laminated in this order on the field oxide film 35, the polysilicon (poly-Si) layer (not shown) serving as a gate runner that electrically connects the gate electrode 9 and the gate pad (not shown).

[0052] On the front surface of the semiconductor substrate 40, - A p-type region 33 constituting the JTE structure 32 is selectively provided inside the p-type epitaxial layer 42, and an n-type region 34 is provided outside the p-type region 33 away from the JTE structure 32. + The p-type region 33 constituting the JTE structure 32 is p-type in the direction parallel to the front surface of the semiconductor substrate 40. + The p-type region 33 constituting the JTE structure 32 is in contact with the p-type region 12a. +The potential is fixed to the potential of the source electrode 15 via the type region 12a.

[0053] As described above, the p-type region 53 and the p-type region 33 according to the embodiment are n - Each time the n-type epitaxial layer 42 is epitaxially grown, - The p-type epitaxial layer 42 is formed by implanting ions in the depth direction Z. In the embodiment, the p-type region 53a which is the uppermost part of the p-type region 53 (the second conductivity type small region closest to the first main surface side of the semiconductor substrate) also serves as the p-type region 33 which constitutes the JTE structure 32, and the p-type region 53a functions as the JTE structure 32.

[0054] As a result, p-type region 53 and p-type region 33 constituting JTE structure 32 do not overlap, the impurity concentration of region S1 does not change from that of p-type region 53, and charge balance deviation can be suppressed in edge termination region 30. Furthermore, there is no need to form p-type region 33 constituting JTE structure 32, which simplifies the process of forming the semiconductor device and reduces manufacturing costs.

[0055] The p-type region 53a is + Since the p-type region 53a, the p-type region 33 and the p-type region 12a constituting the JTE structure 32 are located at the same depth as the p-type region 12a in the region S2, + The bottom of the mold region 12a is in a straight line. + Since there are no corners at the bottom of the mold region 12a, electric field concentration at these corners can be suppressed.

[0056] Next, a method for manufacturing the SJ-MOSFET 50 according to the embodiment will be described. FIGS. 3 to 5 are cross-sectional views showing the parallel pn layers of the SJ-MOSFET according to the embodiment in the process of being manufactured. + n-type drain region 1 + The drift layer 2 including the parallel pn layer 51 is formed on the front surface of the starting substrate (semiconductor wafer) 41. For example, a multi-stage epitaxial method is used to form the n-type pn layer 51 that will become the drift layer 2. -Each time the n-type epitaxial layer 42 is epitaxially grown in multiple stages (for example, 9 stages), - In the epitaxial layer 42, regions to become n-type region 52 and p-type region 53 are selectively formed by ion implantation so that the regions of the same conductivity type are adjacent to each other in the depth direction Z.

[0057] At this time, p-type impurities are implanted into the stages other than the topmost stage of the multi-stage structure (for example, stages 1 to 8 in the case of nine stages) using ion implantation mask 38 having openings in portions corresponding to p-type region 53 as shown in Fig. 3. On the other hand, p-type impurities are implanted into the topmost stage of the multi-stage structure (for example, stage 9 in the case of nine stages) using ion implantation mask 38 having openings in portions corresponding to p-type region 33 of JTE region 32 as shown in Fig. 4. As a result, p-type region 53a, which is the topmost portion of p-type region 53, can be formed to function as p-type region 33 that constitutes JTE structure 32.

[0058] Next, in the active region 10, the n-type current diffusion region 3 and the p + In the intermediate region 20 and the edge termination region 30, as shown in FIG. + A mask 38 for ion implantation having openings in the areas corresponding to the p-type regions 12a and 12b is used to implant p-type impurities. + The depth of the n-type regions 12a and 12b is formed to the same depth as the p-type region 53a. + The mold area 12 is divided into two sections, a lower section and an upper section. - The p-type epitaxial layer 42 is formed by epitaxial growth. + Type region 11 is p + It may be formed simultaneously with the mold region 12a.

[0059] Next, n - On the n-type epitaxial layer 42, a p-type epitaxial layer 43 which becomes the p-type base region 4 is epitaxially grown. +A semiconductor substrate (semiconductor wafer) 40 is produced in which epitaxial layers 42 and 43 are stacked in order on a p-type starting substrate 41, and a parallel pn layer 51 is included in epitaxial layer 42. Next, a portion of p-type epitaxial layer 43 on the edge termination region 30 side is removed by etching to form a step 31 on the front surface of semiconductor substrate 40 that is lower on the edge termination region 30 side than on the active region 10 side. At this time, in edge termination region 30, p + The p-type region 53a is then removed by etching up to the portion corresponding to the p-type region 12b. + The p-type epitaxial layer 43 is exposed on the front surfaces of the active region 10 and intermediate region 20. The p-type epitaxial layer 43 is exposed on the front surfaces of the edge termination region 30. The p-type epitaxial layer 43 is exposed on the front surfaces of the active region 10 and intermediate region 20.

[0060] Next, n + Type source region 5, p ++ Type contact region 6 and n + The n-type channel stopper regions are selectively formed. + Type source region 5 and p ++ The portion excluding the contact region 6 becomes the p-type base region 4 .

[0061] Next, a heat treatment (hereinafter, referred to as activation annealing) is performed to activate the impurities ion-implanted into the epitaxial layers 42 and 43. Next, the n-type GaN- ... + The p-type source region 5 and the p-type base region 4 are penetrated into the n-type current diffusion region 3. + A gate trench 7 is formed facing the mold region 11. Next, a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. Next, the polysilicon layer deposited on the front surface of the semiconductor substrate 40 so as to fill the inside of the gate trench 7 is etched back, leaving a portion that will become the gate electrode 9 inside the gate trench 7.

[0062] A field oxide film 35 is formed on the front surface of the semiconductor substrate 40 in the intermediate region 20 and the edge termination region 30. A polysilicon layer (not shown) that will become a gate runner is formed on the field oxide film 35 in the intermediate region 20. This polysilicon layer may be formed from a part of the polysilicon layer deposited on the front surface of the semiconductor substrate 40 when the gate electrode 9 is formed. Next, an interlayer insulating film (not shown) is formed over the entire front surface of the semiconductor substrate 40. Next, surface electrodes (source electrode 15, gate pad, metal wiring layer (not shown), and drain electrode 16) are formed on both sides of the semiconductor substrate 40 by a general method.

[0063] Next, the front surface of the semiconductor substrate 40, except for a part of the source electrode 15 (a part that will become a source pad), the gate pad, and the metal wiring layer, is covered and protected with a passivation film (not shown). Thereafter, the semiconductor wafer (semiconductor substrate 40) is diced (cut) into individual chips, thereby completing the SJ-MOSFET 50 shown in FIGS. 1 and 2.

[0064] As described above, according to the embodiment, the p-type region that is the uppermost part of the p-type region of the parallel pn layer also serves as the p-type region that constitutes the JTE structure, and the p-type region that is the uppermost part of the parallel pn layer functions as the JTE structure. Therefore, the p-type region of the parallel pn layer and the p-type region that constitutes the JTE structure do not overlap, and it is possible to suppress deviation of the charge balance in the edge termination region. Furthermore, it is no longer necessary to form the p-type region that constitutes the JTE structure, so the process of forming the semiconductor device can be simplified and the manufacturing cost can be reduced.

[0065] The present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, in the above-described embodiments, + The impurity concentration of a normal n-type drift region that does not have an SJ structure with the starting substrate may be higher than the impurity concentration of the n-type region of the parallel pn layer. The present disclosure also applies when the conductivity types (n-type, p-type) are reversed. [Industrial Applicability]

[0066] INDUSTRIAL APPLICABILITY As described above, the super junction semiconductor device according to the present disclosure is useful for power semiconductor devices with an SJ structure used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0067] 1n + Type drain region 2. Drift layer 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6 p ++ Mold Contact Area 7 Gate trench 8 Gate insulating film 9 Gate electrode 10 Active area 11,12,13 p + type area 14 Interlayer insulating film 15 Source electrode 16 Drain electrode 20 Intermediate area 30 Edge Termination Area 31 Step on the front surface of a semiconductor substrate 32 JTE structure 33 p-type region of JTE structure 35 Field oxide 40 Semiconductor Substrate 41 n + Starting substrate 42n - Type epitaxial layer 43 p-type epitaxial layer 50 SJ-MOSFET 51 parallel pn layer 52 n-type region of parallel pn layer 53 p-type region of parallel pn layer X: Parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction) Z depth direction

Claims

1. an active region provided in a semiconductor substrate made of silicon carbide; a termination region provided in the semiconductor substrate and surrounding the active region; a first semiconductor layer of a second conductivity type provided on a first main surface of the semiconductor substrate; a parallel pn layer provided inside the semiconductor substrate in the active region and the termination region, the parallel pn layer including first conductivity type regions and second conductivity type regions alternately arranged in a first direction parallel to a first main surface of the semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the first semiconductor layer on an opposite side to the semiconductor substrate in the active region; a trench penetrating the first semiconductor region and the first semiconductor layer to reach the semiconductor substrate; a gate electrode provided inside the trench via a gate insulating film; a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the first semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate; a third semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the parallel pn layer in the termination region, surrounding the active region, and electrically connected to the first electrode to form a voltage withstanding structure; Equipped with The second conductivity type region is formed by stacking a plurality of second conductivity type sub-regions, and the second conductivity type sub-region closest to the first main surface of the semiconductor substrate among the plurality of second conductivity type sub-regions also serves as the third semiconductor region.

2. a second semiconductor region of a second conductivity type provided at a bottom of the trench; 2. The super-junction semiconductor device according to claim 1, wherein the second semiconductor region and the third semiconductor region are at the same depth on the second main surface side of the semiconductor substrate.

3. 3. The super-junction semiconductor device according to claim 2, wherein the second semiconductor region and the third semiconductor region have the same thickness.

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