Semiconductor structure and method of manufacturing semiconductor structure

Abstract

To disclose a semiconductor structure including interconnects manufactured by a modified Damascene method to reduce the use of a chemical-mechanical polishing (CMP) process, and a method of manufacturing a semiconductor structure.SOLUTION: A semiconductor structure 100 includes a conductive line 104 of an Nth metal layer 130, a first insulating layer 112, a dielectric layer 114, a second insulating layer 116, an interconnect base 122, and an interconnect body 124. The first insulating layer is on the conductive line and free from covering a portion of the conductive line. The dielectric layer is on the first insulating layer and free from covering the portion of the conductive line. The second insulating layer is on the dielectric layer and free from covering the portion of the conductive line. The interconnect base is laterally surrounded by the dielectric layer, the first insulating layer, and the second insulating layer. A top surface of the interconnect base and a top surface of the second insulating layer are coplanar.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] cross reference This application claims the benefit of previously filed U.S. Application No. 18 / 480,567, filed October 4, 2023, which is incorporated by reference in its entirety.

[0002] Technical Field The present disclosure relates to semiconductor structures, and more particularly to semiconductor structures including interconnects fabricated by a modified Damascene process to reduce the use of chemical mechanical polishing (CMP) processes. [Background technology]

[0003] The damascene process is a well-known semiconductor manufacturing process used to fabricate copper interconnects. The copper damascene process provides a solution for forming conductive traces coupled to vias without the need to etch the copper component. The dual damascene process allows for the formation of both conductive vias and conductive traces through a single copper deposition process. Generally, the damascene process requires a CMP process to planarize the surface of the copper layer. However, the CMP process is time consuming, can cause reliability issues, and the slurry employed to polish the metal is expensive. Therefore, there is a need for a more cost-effective and resource-saving method for forming interconnects and conductive lines. Summary of the Invention [Means for solving the problem]

[0004] One aspect of the present disclosure discloses a semiconductor structure. The semiconductor structure includes a conductive line of an Nth metal layer, a first insulating layer, a dielectric layer, a second insulating layer, an interconnect base, and an interconnect body, where N is an integer equal to or greater than 1. The first insulating layer is on the conductive line and does not cover a portion of the conductive line. The dielectric layer is on the first insulating layer and does not cover a portion of the conductive line and a portion of the first insulating layer. The second insulating layer is on the dielectric layer and does not cover a portion of the conductive line. The interconnect base is laterally surrounded by the dielectric layer, the first insulating layer, and the second insulating layer. A top surface of the interconnect base and a top surface of the second insulating layer are coplanar. The interconnect body is on the second insulating layer and in contact with a top surface of the interconnect base.

[0005] Another aspect of the present disclosure provides a method for fabricating a semiconductor structure, the method including receiving a wafer having conductive lines of an Nth metal layer at a surface thereof, where N is an integer equal to or greater than 1, forming a first insulating layer on a surface of the wafer that does not cover any portion of the conductive lines, forming a dielectric layer (e.g., using a low-k dielectric material) on the first insulating layer, forming a second insulating layer on the dielectric layer and the first insulating layer, the second insulating layer including at least a base region over a portion of the conductive lines, and forming an interconnect base in the base region. The operation of forming an interconnect base in the base region includes forming a photoresist layer on the second insulating layer, the base region of the second insulating layer is not covered by the photoresist layer, forming at least one conductive material on the photoresist layer, the second insulating layer, and the conductive line, the top surface of the conductive material on the conductive line is substantially flush with the top surface of the second insulating layer, and removing the photoresist layer by using a lift-off process to remove the conductive material on the second insulating layer to form the interconnect base. Furthermore, another photolithography process is applied, and a lift-off process is applied again to form the interconnect body and the conductive trace on different regions with or without the interconnect base. The result of the proposed improved damascene method is similar to the single damascene method. That is, the interconnect base and the conductive line on the interconnect base can be formed by two lift-offs, respectively. As a result, the number of CMP processes can be reduced. [Brief description of the drawings]

[0006] A more complete understanding of the present disclosure may be derived by reference to the detailed description and claims when considered in conjunction with the drawings, in which like reference numerals refer to like elements throughout. [Figure 1] FIG. 1 illustrates a semiconductor conductive via structure according to one embodiment of the present disclosure. [Figure 2A] 2A-2D are cross-sectional views illustrating a manufacturing process for forming input / output terminals of a CMOS transistor according to one embodiment of the present disclosure. [Figure 2B] 2A-2D are cross-sectional views illustrating a manufacturing process for forming input / output terminals of a CMOS transistor according to one embodiment of the present disclosure. [Figure 2C] 2A-2D are cross-sectional views illustrating a manufacturing process for forming input / output terminals of a CMOS transistor according to one embodiment of the present disclosure. [Figure 2D] 2A-2D are cross-sectional views illustrating a manufacturing process for forming input / output terminals of a CMOS transistor according to one embodiment of the present disclosure. [Diagram 3] 3 is a cross-sectional view illustrating interconnect-based fabrication of the semiconductor structure of FIG. [Figure 4A] 4A-4B are cross-sectional views illustrating a manufacturing process for an interconnect base according to one embodiment. [Figure 4B] 4A-4B are cross-sectional views illustrating a manufacturing process for an interconnect base according to one embodiment. [Diagram 5] FIG. 5 illustrates a cross-sectional view of a metal layer according to one embodiment of the present disclosure. [Figure 6] FIG. 6 illustrates a cross-sectional view of a metal layer according to another embodiment of the present disclosure. [Figure 7] FIG. 7 illustrates a cross-sectional view of a metal layer having an increased conductive area according to another embodiment of the present disclosure. [Figure 8] FIG. 8 illustrates a cross-sectional view of a metal layer having an increased conductive area according to another embodiment of the present disclosure. [Figure 9] FIG. 9 illustrates a cross-sectional view of a metal layer as a coaxial cable according to another embodiment of the present disclosure. [Figure 10] FIG. 10 shows a top view of a metal layer according to another embodiment of the present disclosure. [Figure 11] FIG. 11 illustrates a cross-sectional view of metal layers as a pair of waveguides according to another embodiment of the present disclosure. [Figure 12]FIG. 12 illustrates a top view of a metal layer as a coaxial cable with multiple conductive traces in the center, according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The following description is accompanied by drawings, which are incorporated in and constitute a part of the present specification, illustrating embodiments of the present disclosure, but the present disclosure is not limited to the embodiments. In addition, the following embodiments can be appropriately combined to complete another embodiment.

[0008] References to "one embodiment," "one embodiment," "exemplary embodiment," "other embodiment," "another embodiment," etc. indicate that the embodiment of the disclosure so described may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Further, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

[0009] In order to make the present disclosure fully understandable, detailed steps and structures are provided in the following description. Obviously, the implementation of the present disclosure is not limited to specific details known by those skilled in the art. In addition, known structures and steps are not described in detail so as not to unnecessarily limit the present disclosure. Below, the preferred embodiment of the present disclosure is described in detail. However, in addition to the detailed description, the present disclosure may be broadly implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, but is defined by the claims.

[0010] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and the semiconductor structure. The method for manufacturing the semiconductor structure includes an improved version of a damascene process that can form both conductive terminals in a substrate process (front-end, FEOL) and conductive lines in a wiring process (back-end, BEOL) by utilizing one or more lift-off processes, respectively, to reduce the use of CMP processes. Therefore, a large amount of resources and time required by CMP processes can be saved. Furthermore, the semiconductor structure provided by the embodiments of the present disclosure is suitable for high-frequency signal transmission and can even be applied to form a monolithic microwave integrated circuit (MMIC) or a 3D MMIC therein.

[0011] FIG. 1 illustrates a semiconductor structure 100 according to one embodiment of the present disclosure. The semiconductor structure 100 includes a wafer 102, a conductive line 104 formed on the wafer 102, an interlevel dielectric layer 110, an interconnect base 122 formed on the interlevel dielectric layer 110 and in contact with the conductive line 104, and a metal layer 130 including an interconnect body 124 formed on the interconnect base 122. In this embodiment, the conductive line 104 can be in an Nth metal layer, and the interconnect body 124 can be part of a conductive line in an (N+1)th metal layer (i.e., metal layer 130). In such a case, the interconnect 120 including the interconnect base 122 and the interconnect body 124 can provide a vertical electronic connection between the conductive lines in two different levels of metal layers. That is, interconnect 120 may provide additional electronic connections to conductive line 104 such that conductive line 104 may be coupled to other conductive traces or to external circuitry.

[0012] In the following description, the elements in the semiconductor structure 100 are introduced individually and separately. First, some possible manufacturing methods and structures of the conductive lines 104 are introduced, then some possible manufacturing methods and structures of the interconnect base 122 are presented. Finally, some possible manufacturing methods and structures of the metal layers 130, etc. are described.

[0013] In this embodiment, the conductive lines 104 may be input / output electrodes (i.e., including source, drain, and gate) of a FET (or other terminal of another type of transistor) formed in the wafer 102. In such a case, the conductive lines 104 are formed in a substrate at end of line (FEOL) process and may include copper, cobalt, ruthenium, aluminum, tungsten, other conductors, or combinations thereof. However, the disclosure is not limited in this respect. In some embodiments, the conductive lines 104 may be part of a metal layer fabricated in a back-end of line (BEOL) process.

[0014] In some embodiments, before forming the interlayer dielectric layer 110 and the interconnect base 122 on the conductive lines 104 and the wafer 102, if the surfaces of the conductive lines 104 and the wafer 102 are not flat and do not meet the requirements of photolithography depth of focus (DoF), a polishing process such as a CMP process may be performed to facilitate the formation of the interlayer dielectric layer 110 and the interconnect base 122. However, the present disclosure also proposes a method of forming the conductive lines 104 in a wafer 102 having a flat surface that can meet the requirements of DoF, in order to reduce the use of the CMP process and reduce the required cost and time.

[0015] In some embodiments, to reduce the use of CMP processes, if the uneven surfaces of the conductive lines 104 and the wafer 102 can be planarized by a spin-on-glass (SoG) process, the SoG process is preferred due to its low cost. However, if the unevenness of the surfaces of the conductive lines 104 and the wafer 102 exceeds the planarization capability of the SoG process, a lift-off process may be first considered to deposit a metal material (e.g., tungsten) on the wafer 102 under high temperature so that the conductive lines 104 and the wafer 102 can have flat surfaces as they are formed.

[0016] One embodiment of the present disclosure provides a manufacturing method M1 for input / output electrodes (formed under high temperature) of transistors by utilizing a lift-off process. FIGS. 2A-2D are cross-sectional views showing a manufacturing process for forming input / output electrodes of CMOS transistors by the method M1. In FIG. 2A, an NMOS transistor T1 and a PMOS transistor T2 are formed in a P-type substrate 10. The NMOS transistor T1 includes a P-well 11 formed in the substrate 10 and two N-type doped regions 14 (i.e., source / drain) formed in the P-well 11. The PMOS transistor T2 includes an N-well 12 formed in the substrate 10 and two P-type doped regions 15 (i.e., source / drain) formed in the N-well 12. As shown in FIG. 2A, the NMOS transistor T1 and the PMOS transistor T2 can be separated by a shallow trench isolation (STI) structure 13. In this embodiment, the method M1 is adopted to form the input / output electrodes (i.e., input / output plugs) of the transistors T1, T2. The method M1 includes steps S110 to S190 as follows.

[0017] S110: As shown in FIG. 2A, an interlevel dielectric layer 16 is formed on (over) the transistors T1 and T2 formed on a P-type substrate 10.

[0018] S120: As shown in FIG. 2B, a first silicate glass layer 18 is formed on the interlayer dielectric layer 16.

[0019] S130: Form a first silicon nitride (SiN) layer 19 only on the portions of the first silicate glass layer 18 disposed on the first terminals 17 of the transistors T1 and T2.

[0020] S140: A second silicate glass layer 20 is formed on the first silicate glass layer 18 and the first SiN layer 19.

[0021] S150: A second SiN layer 21 is formed on the second silicate glass layer 20.

[0022] S160: Form a first opening H1 in the second terminals 14 and 15 of the transistors T1 and T2.

[0023] S162: A layer of TiN (not shown) and a first layer 22 of electrode metal (including tungsten, cobalt or ruthenium) are deposited to fill the first opening H1.

[0024] S170: The exposed portions of the second silicate glass layer 20 are removed.

[0025] S180: As shown in FIG. 2C, a second opening H2 is formed in the first terminals of the transistors T1 and T2.

[0026] S182: As shown in FIG. 2C, a layer of TiN (not shown) and a second layer 23 of electrode metal (including tungsten, cobalt or ruthenium) are deposited to fill the second opening H2.

[0027] S190: The first SiN layer 19 and the second SiN layer 21 are removed.

[0028] The method M1 is outlined as follows. As shown in FIG. 2A, an interlayer dielectric layer 16 is formed on the transistors T1 and T2 (S120). After the interlayer dielectric layer 16 is formed, as shown in FIG. 2B, a first silicate glass layer 18, a first SiN layer 19 (S130), a second silicate glass layer 20 (S140), and a second SiN layer 21 (S150) are sequentially formed. Note that the first SiN layer 19 is formed only on the portion of the first silicate glass layer 18 that is disposed on the first terminals 17 of the transistors T1 and T2. In addition, in step S160, the second SiN layer 21 is patterned to form first openings H1 in the second terminals 14 and 15 of the transistors T1 and T2, respectively. In this embodiment, the second terminals 14 and 15 are located at a depth deeper than the depth at which the first terminal 17 is disposed. For example, the first terminal 17 may be the gates of transistors T1 and T2, and the second terminals 14 and 15 may be the sources / drains of transistors T1 and T2.

[0029] It should be noted that the interlevel dielectric layer 16, the first silicate glass layer 18, the first SiN layer 19, the second silicate glass layer 20, and the second SiN layer 21 may be formed by high temperature processes in the FEOL, and thus the lift-off method is described as "lift-off process for high temperature formed materials" in this disclosure.

[0030] Next, in step S162, as shown in FIG. 2C, a layer of TiN (2-10 nm, not shown) and a layer of electrode metal (including tungsten, cobalt or ruthenium) 22 can be deposited on the second SiN layer 21 to fill the first openings H1 on the second terminals 14 and 15 of the transistors T1 and T2, thereby forming input / output electrodes coupled to the second terminals 14 and 15 of the transistors T1 and T2. In some embodiments, the TiN layer can be a wetting layer for the tungsten deposition, and the TiN layer can have a thickness, for example, but not limited to, 2 nm to 10 nm.

[0031] After the input / output electrodes coupled to the second terminals 14 and 15 of the transistors T1 and T2 are formed, the exposed portions of the second silicate glass layer 20 can be removed by deep reactive ion etching (DRIE) in step S170. In such a case, the second SiN layer 21, TiN (not shown) and electrode metal layer 22 formed on the exposed second silicate glass layer 20 will also be removed. In some embodiments, the silicate glass layers 18 and 20 may preferably be phosphosilicate glass (PSG) layers. Alternatively, the silicate glass layers 18 and 20 may be borophosphosilicate glass (BPSG) layers.

[0032] Then, in step S180, lithography processes can be successively performed to etch a part of the first SiN layer 19, a part of the first silicate glass layer 18, and a part of the interlayer dielectric layer 16 formed on the first terminal 17, and form a second opening H2 on the first terminal 17. Next, in step S182, as shown in FIG. 2C, another layer of TiN (not shown) and a layer of electrode metal layer 23 (including tungsten, cobalt, ruthenium) are deposited to fill the second opening H2 on the first terminal 17. Finally, in step S190, the SiN layers 19 and 21 are removed by DRIE, and thus unnecessary parts of TiN (not shown) and the second electrode metal layer 23 can also be removed. As a result, as shown in FIG. 2D, the input / output electrodes of the transistors T1 and T2 can be formed such that their surfaces are substantially flush with the surfaces of the silicate glass layers 18 and 20. That is, method M1 allows for the formation of a flat surface in the FEOL by utilizing a lift-off process for materials formed at high temperatures, reducing the use of CMP processes. In some embodiments, the conductive lines 104 in FIG. 1 are input / output electrodes of a transistor, and method M1 can be employed to form the conductive lines 104 on a wafer 102 having a flat surface. However, the present disclosure is not limited thereto.

[0033] It should be noted that in another embodiment, the above-mentioned electrodes (i.e., tungsten plugs) can be filled. If the electrodes containing tungsten, cobalt, or ruthenium on the source and drain have a thickness that is greater than the thickness of the electrode on the gate by a thickness difference ΔT1, the electrodes on the gate, source, and drain can be filled simultaneously and initially with the same thickness (in some embodiments, a barrier layer of TiN may also be filled before depositing tungsten). Then, a first lift-off process for materials formed at high temperature can be performed to form the electrode on the gate. In such a case, a part of the electrode on the source and drain is also formed. Then, another photoresist layer (not shown) is applied to cover the gate and form an opening H1 on the source and drain. The remaining part of the electrode on the source and drain can then be embedded in the opening by a thickness equal to the thickness difference ΔT1 (in this embodiment, the barrier layer of TiN does not need to be filled before depositing the electrode, because the electrode is already present on the sidewall of the opening H1 on the source and drain). Finally, a second lift-off process for the material formed at high temperature can be performed successively to form the remaining part of the electrode on the source and drain. As a result, an electrode can be formed on the source and drain having a thickness that is greater than the thickness of the electrode on the gate by a thickness difference ΔT1. In some embodiments, such a process can be repeated r times (e.g., r is an integer greater than 1) to form electrodes having r different thicknesses. That is, preferably, the electrodes can be formed according to the order of their thickness, with the thinnest electrode formed first and the thickest electrode formed last, which can improve the efficiency of the manufacturing process by r times.

[0034] After the conductive lines 104 (e.g., tungsten plugs) are formed in the wafer 102, with the conductive lines 104 and the surface of the wafer 102 meeting the DoF requirements, the interconnects 120 including the interconnect base 122 and the interconnect body 124 (e.g., copper) as shown in Figures 1 and 3 can also be formed by another lift-off process, reducing the use of costly CMP processes.

[0035] In this embodiment, the interlevel dielectric layer 110 may be formed first before forming the interconnect body 124. The interlevel dielectric layer 110 includes a first insulating layer 112, a dielectric layer 114, and a second insulating layer 116. The insulating layer 112 is formed on the wafer 102, and the dielectric layer 114 is formed on the first insulating layer 112, but leaves at least a portion of the insulating layer 112 uncovered. The second insulating layer 116 is formed on the dielectric layer 114 and the first insulating layer 112, and the second insulating layer 116 may cover a sidewall of the dielectric layer 114.

[0036] In some embodiments, the first and second insulating layers 112 and 116 are made of silicon oxynitride (SiO x N Y ), and the dielectric layer 114 may comprise, for example, but not limited to, a low-k material having a dielectric constant lower than that of the first and second insulating layers 112 and 116. For example, silicon oxynitride has a dielectric constant greater than 3, and the dielectric constant of the dielectric layer 114 is less than 2.5. The dielectric layer 114 may comprise methylsilsesquioxane (MSQ), fluorocarbon silsesquioxane (FSQ), and / or other suitable materials. In some embodiments, the low-k dielectric material may be a low hardness material, so that the second insulating layer 116 may surround the dielectric layer 114 to provide structural support to the dielectric layer 114.

[0037] Hereinafter, an improved damascene method M2 for fabricating the interconnect base 122 according to one embodiment of the present disclosure will be introduced in detail. Figure 3 shows a cross-sectional view illustrating the fabrication of the interconnect base 122 by the method M2. The method M2 includes steps S210 to S240 as follows.

[0038] S210: The first insulating layer 112 is formed.

[0039] S220: Form a dielectric layer 114 on the first insulating layer 112, leaving at least a portion of the first insulating layer 112 uncovered.

[0040] S230: A second insulating layer 116 is formed on the dielectric layer 114 and the first insulating layer 112.

[0041] S240: An interconnect base 122 is formed on the first insulating layer 112 and the second insulating layer 116.

[0042] An overview of method M2 is as follows: In some embodiments, method M2 can be employed to fabricate semiconductor structure 100.

[0043] In step S210, a first insulating layer 112 is formed on the conductive line 104. In this embodiment, the first insulating layer 112 may be patterned by performing a lithography process to form an opening 113 so that at least a portion of the conductive line 104 is exposed.

[0044] Next, in step S220, a dielectric layer 114 is formed on the first insulating layer 112. In this embodiment, the dielectric layer 114 may be patterned by performing a lithography process to form an opening 115 so that at least a part of the first insulating layer 112 and at least a part of the conductive line 104 can be exposed. The opening 115 formed in the dielectric layer 114 covers the opening 113 previously formed in the first insulating layer 112 in a projected view. In some embodiments, the dielectric layer 114 may be thicker than the first insulating layer 112. For example, the thickness of the first insulating layer 112 may be 100 nm to 150 nm, and the thickness of the dielectric layer 114 may be 200 nm to 400 nm, but is not limited thereto.

[0045] In step S230, a second insulating layer 116 is formed on the dielectric layer 114 and the first insulating layer 112. In this embodiment, the second insulating layer 116 may be patterned by performing a lithography process to form an opening 117 so as to expose at least a portion of the conductive line 104 to be coupled to the interconnect base 122. The opening 117 is located in a base region 119 (e.g., the region surrounded by a dotted line in FIG. 4A) of the second insulating layer 116 on a portion of the conductive line 104. In some embodiments, the opening 113 formed in the first insulating layer 112 is entirely included in the opening 117. Also, as shown in FIG. 3, the second insulating layer 116 surrounds the dielectric layer 114 and covers the sidewalls of the dielectric layer 114, so that the second insulating layer 116 can provide structural support for the dielectric layer 114, thereby maintaining the structural stability of the semiconductor structure 100.

[0046] In some embodiments, the first insulating layer 112 and the second insulating layer 116 may include silicon oxynitride. In such cases, because the formation of silicon oxynitride may require deposition temperatures of, for example, up to about 350° C., the dielectric layer 114 may include a material that can withstand temperatures in excess of about 350° C. to ensure stability of the dielectric layer 114 during the formation of the second insulating layer 116.

[0047] In some embodiments, after the second insulating layer 116 is formed in step S230, the interconnect base 122 is formed in the base region 119 of the first insulating layer 112 and the second insulating layer 116 by filling the opening 117, as shown in FIG. 3. In this embodiment, the step S240 of forming the interconnect base 122 can be performed to reduce the use of a CMP process. According to one embodiment of the present disclosure, the step S240 may include sub-steps S241 to S245 (method M3) as follows. FIGS. 4A to 4B are cross-sectional views showing a manufacturing process of the interconnect base 122 according to the sub-steps S241 to S245.

[0048] S241: A photoresist layer PR1 is patterned on the second insulating layer 116, but leaving the first insulating layer 112 and the base region 119 of the second insulating layer 116 uncovered.

[0049] S242: A barrier layer 1221 is formed on the photoresist layer PR1 and in the base region 119.

[0050] S243: A copper-phosphorus alloy layer 1222 is formed on the barrier layer 1221.

[0051] S244: A copper layer 1223 is plated on the copper-phosphorus alloy layer 1222 to fill the base region 119.

[0052] S245: The photoresist layer PR1 is removed together with a part of the barrier layer 1221, a part of the copper-phosphorus alloy layer 1222, and a part of the copper layer 1223 that are laminated on the photoresist layer PR1.

[0053] The method M3 is outlined as follows. In step S241, as shown in FIG. 4A, a photoresist layer PR1 is provided on the second insulating layer 116 and patterned to form an opening PR1-1 that does not cover the base region 119. In this embodiment, the photoresist layer PR1 is patterned using the same mask as that used to pattern the second insulating layer 116. Therefore, the width of the opening PR1-1 shown in FIG. 4A is the same as the width of the opening 113 in the first insulating layer 112 and the width of the opening 117 in the second insulating layer 116 shown in FIG. 3. In such a case, the mask used to pattern the opening 113 in the insulating layers 112 and 116 can be reused to pattern the opening PR1-1 in the photoresist layer PR1, thereby reducing the manufacturing cost of a new mask.

[0054] After the opening PR1-1 of the photoresist layer PR1 is formed, at least one conductive material can be provided on the wafer including the photoresist layer PR1 to form the interconnect base 122. In this embodiment, the following three types of conductive materials are used. In step S242, as shown in FIG. 4B, a first conductive layer 1221 of a barrier material is formed on the photoresist layer PR1 and on the base region 119 (FIG. 3) of the first insulating layer 112 and the second insulating layer 116. In such a case, the barrier material 1221 contacts the side of the first insulating layer 112 and the side of the second insulating layer 116, and also contacts the conductive line 104. In this embodiment, the barrier material 1221 may include, but is not limited to, titanium nitride (TiN), for example.

[0055] In step S243, as shown in FIG. 4B, a second conductive copper-phosphorus alloy layer 1222 is formed on the barrier layer 1221. In this embodiment, the copper-phosphorus alloy layer 1222 can be regarded as a wettability layer for depositing copper in a subsequent step. In addition, the copper-phosphorus alloy layer 1222 is formed by performing an electroless plating process. Due to the good wettability of the copper-phosphorus alloy layer 1222, the copper-phosphorus alloy layer 1222 is formed as a good adhesion film covering the barrier layer 1221. In addition, a suitable additive in the plating solution, such as a deactivator (quencher) or inhibitor, may be adopted to prevent the barrier material 1221 and the copper-phosphorus alloy layer 1222 from adhering to the sidewall of the photoresist layer PR1.

[0056] After the copper-phosphorus alloy layer 1222 is formed, in step S244, a third conductive copper layer 1223 is plated on the copper-phosphorus alloy layer 1222 to fill the base region 119, as shown in Fig. 3. Then, in step S245, the photoresist layer PR1 and the barrier layer 1221, the copper-phosphorus alloy layer 1222, and the copper layer 1223 on the photoresist layer PR1 are removed. This allows the interconnect base 122 in the semiconductor structure 100 to be formed by such a lift-off operation, as shown in Fig. 3.

[0057] Therefore, by using the above improved damascene method M2 and properly controlling the thickness of the plating material, the number of CMP processes required can be significantly reduced. In some embodiments, the copper plating thickness may be controlled by AI learning and monitoring methods. As a result, the use of CMP processes can be reduced, thus saving the resources (e.g., water, slurry, electricity, manpower, conductive materials, etc.) required by the CMP process and the extra design of dummy loads. Therefore, both the cost and yield of the semiconductor structure can be optimized, which is in line with the spirit of ESG (Environment, Social, and Governance).

[0058] In some embodiments, the photoresist layer PR1 may be a negative photoresist to ensure that the unwanted portions of the barrier layer 1221, the copper-phosphorus alloy layer 1222, and the copper layer 1223 on the photoresist layer PR1 can be removed without damaging the desired portions of the barrier layer 1221, the copper-phosphorus alloy layer 1222, and the copper layer 1223 formed in the base region. Since the negative photoresist is insoluble in a photoresist developer after exposure, the openings in the photoresist layer PR1 can be undercut (not shown), which reduces the connection between the unwanted portions of the barrier layer 1221, the copper-phosphorus alloy layer 1222, the copper layer 1223, etc. on the photoresist layer PR1 and the desired portions of the copper layer 1223, etc. in the base region 119. This is because the undercut shape of the openings PR1-1 can suppress the copper layer 1223 from adhering to the sidewalls of the photoresist layer PR1 during the plating process.

[0059] Furthermore, in some embodiments, two photoresist layers may be employed to further reduce the connection between the unwanted and desired portions of the plated metal. For example, after the photoresist layer PR1 is provided and patterned to have an opening PR1-1, an additional photoresist layer may be provided and patterned to have an opening. This additional photoresist layer may include a negative photoresist material different from the material employed by the photoresist layer PR1. In such a case, after the additional photoresist layer is patterned, a photoresist developer for the photoresist layer PR1 may be applied to further etch the photoresist layer PR1 and widen the opening PR1-1. Since this additional photoresist is exclusively insoluble in the photoresist developer for the photoresist layer PR1, the width of the opening in the additional photoresist does not change. As a result, by applying two photoresist layers, a larger undercut structure of the lower layer can be formed, and the lift-off operation by the thicker layer of photoresist to form a thicker layer of copper can be further facilitated. In some embodiments, the copper layer 1223 may be replaced by a cobalt layer, a ruthenium layer, or an alloy layer including at least one of the metal materials mentioned above. A more detailed structure can be seen in FIG. 5, and the related description is provided below.

[0060] In this embodiment, the interconnect base 122 is formed in the semiconductor structure 100 to provide a vertical electronic connection between conductive lines in two different levels of metal layers. In such a case, the interconnect base 122 can be considered as a conductive via, and the interconnect body 124 can be a part of the conductive line in the metal layer 130. However, the present disclosure is not limited thereto. In some embodiments, the interconnect base 122 is not required for via coupling between conductive lines in different metal layers. Alternatively, the interconnect base 122 may also be applied to fabricate passive devices of 3D MMICs, which have several advantages. For example, compared to conventional MMICs that are usually formed on an interposer (e.g., PI) or PCB, the method and semiconductor structure provided by the embodiments of the present disclosure allow designers to fabricate 3D MMICs with better performance to obtain smaller form factors and higher precision (such as bandwidth and gain) and yield by utilizing semiconductor manufacturing processes to form the interconnect base 122.

[0061] Specifically, the method of forming the interconnect base 122 of the present disclosure is flexible and may be adopted to integrate the passive devices of multi-layer 3D MMIC. For example, the interconnect base 122 may be adopted as a part of a waveguide, a bandpass filter, a bandstop filter, a resonator with parasitic L and C in parallel or series, a π-type or T-type impedance matching filter. Moreover, by using an improved damascene method that can reduce the use of CMP processes, the embedded passive devices of these 3D MMICs can be formed at low cost. Moreover, since these embedded (passive devices) may be perpendicular to other planar devices in the semiconductor structure, most of the currents of the passive devices of the 3D MMICs formed in the interconnect base 122 will flow along the vertical direction, and thus the electromagnetic fields generated by these 3D MMICs can be perpendicular to the electromagnetic fields generated by the planar semiconductor devices, which can significantly reduce the mutual interference between circuits.

[0062] Moreover, compared to conventional copper vias, the interconnect base 122 employed to fabricate 3D MMICs may have a larger form factor. For example, the interconnect base 122 may have a diameter in the range of 1 μm to 500 μm and a thickness in the range of 10 μm to 400 μm, while a conventional copper via on the same wafer may have a diameter in the range of 10 nm to 100 nm and a thickness in the range of 10 nm to 1 μm.

[0063] After the interconnect base 122 is formed, the metal layer 130 and the dielectric layer 140 can be formed thereon as shown in FIG. 1. In this embodiment, the copper plating (including electroplating and electroless plating) process allows for accurate thickness control, for example, by AI learning and monitoring methods, so that the thickness of the copper layer 1223 can be controlled to be approximately the same as the depth of the base region 119. Therefore, the surface of the interconnect body 124 and the surface of the insulating layer 116 can be approximately flush, so that the dielectric layer 140 can be formed on the interconnect body 124, and the surface of the insulating layer 116 can be appropriately patterned.

[0064] After the dielectric layer 140 is patterned, the metal layer 130 may be formed. In this embodiment, the metal layer 130 includes an interconnect body 124 and conductive traces 132 and 134. The interconnect body 124 is disposed on the interconnect base 122, and the conductive traces 132 and 134 are disposed on the insulating layer 116. In some embodiments, the conductive traces 132 and 134 may be part of other conductive lines in the metal layer 130.

[0065] In this embodiment, the metal layer 130 can be formed by a method similar to the formation method (lift-off method) of the interconnect base 122 described above. That is, the metal layer 130 may be deposited to fill the opening of the dielectric layer 140 to form the desired lines and reduce the use of the CMP process, which simplifies the semiconductor manufacturing process and reduces resources (e.g., water, slurry, electricity, manpower, conductive materials, etc.), extra design of dummy loads, dish effect, reliability issues, time and cost. Therefore, in some embodiments of the present disclosure, the formation of both the interconnect base 122 and the interconnect body 124 is based on a modified damascene method that can reduce the use of the CMP process.

[0066] Furthermore, in some embodiments, the conductive traces 132, 134 and the interconnect body 124 can have various thicknesses, and can even exceed the thickness of the conductive traces formed by conventional methods. Although the CMP method can be limited by the degraded adhesion between the copper layer and the low-k dielectric material over time, the modified damascene method and lift-off process can be applied to plate a thicker copper layer, which can result in lower resistance of the conductive traces 132, 134 and the interconnect body 124. In some embodiments, such conductive traces 132 and 134 with thicker copper layers and lower resistance can be very useful for forming high power devices as well as the outer regions of the chip.

[0067] Additionally, in this embodiment, the thickness of the interconnect body 124 and the conductive traces 132 and 134 are the same, so that the interconnect body 124 and the conductive traces 132 and 134 can all be formed in one copper plating process and one lift-off process. However, in some other embodiments, the conductive traces 132, 134 and the interconnect body 124 in the metal layer 130 can have different thicknesses. For example, if the conductive trace 132 is employed for higher power transmission, the conductive trace 132 may have a thickness that is greater than the thickness of the general conductive trace 134 and the interconnect body 124 (the thicknesses of 124 and 134 are equal) by a thickness difference ΔT2, so that the conductive trace 132 can have a lower resistance, thereby increasing the power transmission efficiency. In such a case, a copper layer may be plated to form the conductive trace 134 (in some embodiments, a barrier layer and a copper-phosphorus alloy layer may also be plated with the copper layer) in the metal layer 130, the interconnect body 124, and the first portion of the conductive trace 132 with the same thickness. Then, a first lift-off process can be performed to form the conductive trace 134 and the interconnect body 124, and the first portion of the conductive trace 132 for higher power transmission. Then, another photoresist layer is provided to cover the conductive trace 134 and the interconnect body 124, while an opening is formed on the first portion of the conductive trace 132. Then, another copper layer can be plated in the opening of the photoresist (i.e., on the conductive trace 132) and on the photoresist layer with a thickness equal to the thickness difference ΔT2 (in some embodiments, a barrier layer and a copper-phosphorus alloy layer may also be plated together with the copper layer). Finally, a second lift-off process can be performed successively to form the second portion of the conductive trace 132. As a result, a conductive trace 132 for higher power transmission can be formed with a thickness that is greater than the thickness of the conductive trace 134 or the interconnect body 124 by the thickness difference ΔT2.

[0068] In some embodiments, such a process can be repeated multiple times to form conductive traces and / or interconnect bodies having multiple different thicknesses, i.e., if there are conductive traces and / or interconnect bodies having q (an integer greater than 1) different thicknesses, the conductive traces and / or interconnect bodies can be formed in order of their thickness, with the thinnest conductive traces and / or interconnect bodies formed first and the thickest conductive traces and / or interconnect bodies formed last, thereby increasing the efficiency of the manufacturing process by a factor of q.

[0069] Similarly, the interconnect bases 122 may also be formed with different thicknesses. For example, if there are interconnect bases 122 with p (an integer greater than 1) different thicknesses, the method given in the previous paragraph, including the metal plating process and the lift-off process, can be applied to form the interconnect bases from one with the smallest thickness to one with the largest thickness in p times.

[0070] In the following, some further embodiments of the present disclosure are presented to introduce other possible manufacturing methods and structures of the metal layer.

[0071] FIG. 5 is a cross-sectional view of a metal layer 230 according to one embodiment of the present disclosure. The metal layer 230 includes a conductive trace 232 disposed on the second insulating layer 216 and an interconnect body 224 disposed on the interconnect base 222. As shown in FIG. 5, the conductive trace 232 and the interconnect body 224 may be separated from each other by a dielectric layer 240. In some embodiments, similar to the dielectric layer 140, the dielectric layer 240 may include a material having a low-k constant. In this embodiment, the conductive trace 232 and the interconnect body 224 may be formed by a process similar to that employed to form the interconnect base 122 described above, and the process used to form the metal layer 230 is also similar to that employed to form the metal layer 130. For example, after the insulating layer 216 is formed, a photoresist layer may be patterned thereon, and then a barrier layer B1, a copper-phosphorus alloy P1, and a copper layer C1 may be sequentially formed thereon.

[0072] Thereafter, the unnecessary portions of the barrier layer B1, the copper-phosphorus alloy P1, and the copper layer C1 can be removed by a lift-off process together with the photoresist layer. In one embodiment of the present disclosure, instead of plating a large thickness of the copper layer C1 at once to fill the opening of the insulating layer 216, several plating processes are performed together with thickness measurement and monitoring by AI learning techniques to ensure that the unnecessary copper remaining on the photoresist layer can be removed together with the photoresist layer. As shown in FIG. 5, the copper layers C1, C2, and C3 may be formed by three plating processes respectively, and each of the copper layers C1, C2, and C3 may have a thickness of about one-third of the thickness of the dielectric layer 240. However, the present disclosure is not limited thereto. In some embodiments, the interconnect body 224 or the conductive trace 232 may include only one copper layer or other number of copper layers according to need. That is, in some embodiments, the opening of the insulating layer 216 may be filled by the barrier layer B1, the copper-phosphorus alloy P1, and the copper layer C1 without further plating the copper layers C2 and C3.

[0073] After the opening of the insulating layer 216 is filled (either by one copper layer C1 having a total thickness that can fill the opening of the insulating layer 216 at once, or by multiple copper layers such as C1, C2, and C3 successively (this is adopted in the following figures)), another copper-phosphorus alloy layer P2 and another barrier layer B2 are sequentially formed before forming the third insulating layer 250. In such a case, the copper-phosphorus alloy layers P1 and P2 are sandwiched between the copper layers C1, C2, and C3 and the barrier layers B1 and B2, and the copper layers C1, C2, C3 are trapped within the lower and upper layers of the barrier layers B1, B2. The copper-phosphorus alloy layer P2 on the copper layers C1, C2, C3 can protect the copper layers C1, C2, C3 from oxidation. In some embodiments, the copper layers C1, C2, and C3 may be replaced by a cobalt layer, a ruthenium layer, or an alloy layer including at least one of the above-mentioned metal materials. In some embodiments, when the fabrication process is not yet well developed, offline measurements may be performed every time after the copper layer C1, C2, or C3 is plated. In such a case, a layer of copper-phosphorus alloy may be formed on the copper layer C1, C2, C3 to protect it every time the copper layer C1, C2, C3 is plated. However, the present disclosure is not limited thereto.

[0074] Furthermore, in this embodiment, if the metal layer 230 is the top metal layer, a polyimide layer 260 may be further formed on the third insulating layer 250 to form a flat upper surface (in FIG. 5, the upper and lower structures for connecting to an external circuit are not shown). However, the present disclosure is not limited thereto.

[0075] In some embodiments, the conductive traces in the semiconductor structure may be used for high frequency signal transmission. In such embodiments, the skin effect may become significant, causing low signal transmission efficiency. In the present disclosure, to improve the signal transmission efficiency, a low-k dielectric may be formed on the conductive traces and / or the interconnect body to increase the total surface area of ​​the traces and the interconnect body, thereby increasing the signal transmission efficiency, as follows:

[0076] 6 is a cross-sectional view of the metal layer 330 according to one embodiment of the present disclosure. In some embodiments, the metal layer 330 may be employed to replace the metal layer 130. In some embodiments, as shown in FIG. 6, a dielectric layer 340 is formed on the second insulating layer 316 and the interconnect base 322. In this embodiment, the dielectric layer 340 is patterned to form a plurality of openings 341, 342, 343, and 344, with a dielectric 345 remaining between the openings 341 and 342 and a dielectric 346 remaining between the openings 343 and 344. In some embodiments, the dielectric layer 340 and the dielectrics 345 and 346 may include a dielectric material having a low dielectric constant (i.e., a low-k material).

[0077] 6, after the dielectric layer 340 is patterned, a barrier layer B1, a copper-phosphorus alloy layer P1, and a copper layer C1 can be formed in the openings 341, 342, 343, and 344 of the dielectric layer 340 by performing processes similar to those described above. Similarly, another copper layer C2 is plated on the copper layer C1.

[0078] Further, as shown in FIG. 6, another copper layer C3 is deposited on the copper layer C2 and the dielectrics 345 and 346. Then, a copper-phosphorus alloy layer P2 and a barrier layer B2 are sequentially formed on the copper layer C3, and the copper layers C1, C2 and C3 are confined in the barrier layers B1 and B2. This forms the conductive trace 332 and the interconnect body 324 of the metal layer 330. In this embodiment, the dielectric 345 is formed in the conductive trace 332, and the dielectric 346 is formed in the interconnect body 324, so that the surface area of ​​the conductive trace 332 and the surface area of ​​the interconnect body 324 are increased. As a result, the decrease in signal transmission efficiency caused by the skin effect can be reduced.

[0079] In some embodiments, a third insulating layer 350 is formed on the metal layer 330, as shown in Figure 6. Additionally, if the metal layer 330 is the top metal layer, i.e., no further metal layers are formed on top of the metal layer 330, a polyimide layer 360 may be formed on the third insulating layer 350 to obtain a flat top surface (top and bottom features for connecting to external circuitry are not shown in Figure 6).

[0080] 6, dielectrics 345 and 346 are formed from the bottom of metal layer 330. However, the disclosure is not limited in this respect. In some other embodiments, the dielectrics may be embedded within metal layer 330.

[0081] 7 is a cross-sectional view illustrating a metal layer 430 having an increased conductive surface area according to one embodiment of the present disclosure. As shown in FIG. 7, a dielectric layer 440 can be formed on the second insulating layer 416 and the interconnect base 422. In this embodiment, the dielectric layer 440 is patterned to form two openings on both the second insulating layer 416 for forming the conductive traces 432 of the left MMIC and the interconnect base 422 for forming the interconnect body 424 of the right MMIC.

[0082] In some embodiments, as shown in FIG. 7, a barrier layer B1, a copper-phosphorus alloy layer P1, and a copper layer C1 can be formed in the openings in the dielectric layer 440 to fabricate the conductive traces 432 and the interconnect body 424 by performing a process similar to that previously described.

[0083] Next, using a photolithography process, two dielectrics 445 and 446 are formed on the copper layer C1. Furthermore, the copper layer C2 is then plated on the copper layer C1 and the dielectrics 445 and 446. As a result, the dielectrics 445 and 446 are embedded within the copper layers C1 and C2 in the conductive trace 432 and the interconnect body 424.

[0084] 7, a copper-phosphorus alloy layer P2 and a barrier layer B2 can be formed on the copper layer C2, and a third insulating layer 450 can be formed on the metal layer 430. In addition, if the metal layer 430 is the top metal layer (i.e., no further metal layer is formed on the metal layer 430), a polyimide layer 460 (or the like) can be formed on the third insulating layer 450 to obtain a flat top surface. In some embodiments, the flat polyimide layer 460 can be used to form a coplanar waveguide (not shown) of a 3D MMIC thereon (top and bottom structures for connecting to external circuits are not shown in FIG. 7).

[0085] 7, conductive trace 432 and interconnect body 424 are embedded with either dielectric 445 or 446, respectively. However, this embodiment is not so limited. In some embodiments, more layers of copper metal can be formed as well as more dielectric can be embedded to further increase the surface area of ​​conductive trace 432 and interconnect body 424.

[0086] 8 illustrates a cross-sectional view of a metal layer 530 having an increased conductive surface area according to another embodiment of the present disclosure. As shown in FIG. 8, a dielectric layer 540 can be formed on the second insulating layer 516 and the interconnect base 522. In this embodiment, the dielectric layer 540 is patterned to form two openings on both the second insulating layer 516 for forming the conductive traces 532 of the left MMIC and the interconnect base 522 for forming the interconnect body 524 of the right MMIC.

[0087] At least one dielectric 545 is embedded in each of the conductive trace 532 and the interconnect body 524. In addition, by controlling the thickness of the copper deposit, a copper layer C2 can be formed on the copper layer C1 without covering the dielectric 545. In addition, the surface of the copper layer C2 and the surface of the dielectric 545 can be approximately flush with each other. In this case, a copper layer C3 can be formed on the copper layer C2 and the dielectric 545. Also, another barrier layer B2 and another copper-phosphorus alloy layer P2 can be formed on the copper layer C3. This allows the formation of a planar layer of a third insulating layer 550 and a polyimide layer 560, as shown in FIG. 8 (top and bottom structures for connecting to an external circuit are not shown in FIG. 8).

[0088] In the embodiments shown in Figures 7 and 8, a dielectric can be inserted (embedded) into the conductive lines (e.g., conductive traces 432, 532 and interconnect bodies 424, 524) to increase the surface area, making such conductive lines particularly suitable for high frequency applications. On the other hand, by properly designing the dimensions, both the circuits in Figures 7 and 8 can be applied to form filters such as low pass filters, band pass filters, high pass filters, and notch filters.

[0089] As described above, by increasing the surface area of ​​the transmission line, the efficiency of high frequency signal transmission can be improved. However, as the die size becomes smaller, the distance between the transmission lines becomes shorter, so interference between different high frequency signal transmissions, i.e., electromagnetic interference (EMI), can still be a problem.

[0090] FIG. 9 shows a cross-sectional view of a metal layer 630 as a coaxial cable according to another embodiment of the present disclosure. In this embodiment, the metal layer 630 includes conductive traces 632, 634, and 636 separated by a dielectric layer 640. The conductive trace 632 can be used to transmit high-frequency signals, while the conductive traces 634 and 636 can be coupled to ground. In such a case, the conductive traces 632, 634, and 636 can be used as a 3D waveguide. However, the present disclosure is not limited thereto. In some other embodiments, the conductive traces 632, 634, and 636 can also be used as a π-type or T-type impedance matching filter (top and bottom structures for connecting to external circuits and ground points are not shown in FIG. 9).

[0091] In some embodiments, the conductive traces 632, 634, and 636 may be formed by the process described and illustrated above. In such cases, each of the conductive traces 632, 634, and 636 may include a first barrier layer B1, a first copper-phosphorus alloy layer P1, at least one copper layer C1, a second barrier layer B2, and a second copper-phosphorus alloy layer P1. However, the present disclosure is not limited in this respect.

[0092] In some embodiments, conductive traces 634 and 636 may run parallel to conductive trace 632 to contain electromagnetic fields caused by high frequency signals carried by conductive trace 632.

[0093] In some embodiments, the conductive traces 632, 634, and 636 extend horizontally along the XY plane. However, the disclosure is not limited in this respect. In other embodiments, a similar electromagnetic shielding structure is employed when the conductive traces extend vertically along the Z direction.

[0094] FIG. 10 shows a top view of a metal layer 730 according to one embodiment of the present disclosure. In this embodiment, the metal layer 730 includes conductive traces 732 and 734 that extend upward along the direction Z. In such an embodiment, the conductive trace 734 that is coupled to ground surrounds the conductive trace 732 that is used to transmit high-frequency signals. As a result, the conductive trace 734 provides a complete shielding wall (such as a coaxial cable) to reduce EMI issues. However, the present disclosure is not limited thereto. In some other embodiments, the inner conductive trace 732 can be grounded, whereas the outer conductive trace 734 can be applied to transmit high-frequency signals, in which case the circuit can be applied as one of a π-type or T-type impedance matching filter (top and bottom structures for connecting to external circuits and ground points are not shown in FIG. 10).

[0095] Furthermore, in some embodiments, multiple conductive traces may be employed to carry the same high frequency signal in order to increase the surface area available for high frequency current to flow.

[0096] FIG. 11 shows a cross-sectional view of a metal layer 830 as a pair of waveguides according to another embodiment of the present disclosure. In this embodiment, the metal layer 830 includes conductive traces 832, 834, 836 and 838 extending along the XY plane. The conductive traces 832 and 834 are used to transmit the same high-frequency signal, and the conductive traces 836 and 838 are coupled to ground. In such an embodiment, the metal layer 830 can be employed as a pair of waveguides for transmitting high-frequency signals, and the total surface area through which high-frequency current flows can be increased, thereby improving the signal transmission efficiency. On the other hand, the metal layer 830 can also be used as a π-type or T-type impedance matching filter (top and bottom structures for connecting to external circuits and ground points are not shown in FIG. 11).

[0097] 12 illustrates a top view of metal layer 930 as a coaxial cable with multiple conductive traces in the center, according to one embodiment of the present disclosure. In this embodiment, metal layer 930 includes conductive traces 931, 932, 933, 934, and 936 that extend along the Z direction. Conductive traces 931, 932, 933, and 934 are used to carry the same high frequency signal, and conductive trace 936 is coupled to ground.

[0098] In such an embodiment, the conductive traces 931, 932, 933, and 934 are surrounded by the conductive trace 936, so that the EMI caused by the high frequency signal transmitted by the conductive traces 931, 932, 933, and 934 can be shielded. Therefore, in some embodiments, the conductive traces 931, 932, 933, and 934 can be applied as a coaxial cable between a pair of upper and lower circuits. Furthermore, as more conductive traces are employed to transmit the same high frequency signal, the total surface area through which the high frequency current flows can be further increased. Through proper design, this basic circuit can be applied as one of the pin connections of a semiconductor (e.g., Si) interposer (e.g., TSV), in which case the coupling between the pins can be reduced. On the other hand, the inner conductive traces 931, 932, 933 and 934 may be grounded, while the outer conductive trace 936 may be applied to transmit high frequency signals, in which case the circuit may be applied as one of a π-type or T-type impedance matching filter (top and bottom structures for connection to external circuits and ground points are not shown in FIG. 12).

[0099] In summary, the semiconductor structure and semiconductor manufacturing method provided by the embodiments of the present disclosure enable the formation of interconnects and conductive traces that reduce the use of copper CMP processes. Therefore, manufacturing time and costs can be reduced. In addition, the interconnects and / or conductive traces in the semiconductor structure can be employed to fabricate 3D MMICs that not only reduce the circuit area but also increase the circuit performance. Furthermore, the surface area of ​​the conductive traces and interconnects can be increased by embedding a dielectric in the conductive traces and interconnects. As a result, the transmission efficiency of high frequency signals can also be improved.

[0100] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims. For example, many of the processes discussed above can be performed in different methodologies or replaced by other processes, or combinations thereof.

[0101] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufacture, compositions, means, methods, and steps described herein. As one skilled in the art will readily appreciate from this disclosure, any currently existing or later developed processes, machines, manufacture, compositions, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized in accordance with the present disclosure. Accordingly, it is intended that the appended claims include within their scope such processes, machines, manufacture, compositions, means, methods, and steps. [Explanation of symbols]

[0102] 10 P type board 11 P-well 12 N-well 13 Shallow trench isolation structure 14 N-type doped region, second terminal 15 P-type doped region, second terminal 16 Interlayer Dielectric Layer 17 First Terminal 18 First silicate glass layer 19 First silicon nitride (SiN) layer 20 Second silicate glass layer 21 Second SiN layer 22, 23 Electrode metal (layer) 100 Semiconductor Structure 102 Wafer 104 Conductive Wire 110 Interlayer dielectric layer 112 First insulating layer 114 Dielectric layer 113 Opening 115 Opening 116 Second insulating layer 117 Opening 119 Base Area 120 Interconnect 122 Interconnect Base 1221 A first conductive layer of barrier material (barrier layer) 1222 Copper-phosphorus alloy layer 1223 Copper layer 124 Interconnect body 130 Metal layer 132, 134 Conductive traces 140 Dielectric layer 216 Second insulating layer 222 Interconnect Base 224 Interconnect body 230 Metal layer 232 Conductive Trace 240 Dielectric Layer 250 Third insulating layer 260 Polyimide layer 316 Second Insulation Layer 322 Interconnect Base 324 Interconnect body 330 Metal layer 332 Conductive Trace 340 Dielectric layer 341, 342, 343, 344 Openings 345, 346 Dielectrics 350 Third insulating layer 360 Polyimide layer 416 Second Insulation Layer 422 Interconnect Base 424 Interconnect body 430 Metal layer 432 Conductive Trace 440 Dielectric layer 445, 446 Dielectric 450 3rd insulating layer 460 Polyimide layer 516 Second Insulation Layer 522 Interconnect Base 524 Interconnect Body 530 Metal layer 532 Conductive Trace 540 Dielectric Layer 545 Dielectric 550 Third insulating layer 560 Polyimide layer 630 Metal layer 632, 634, 636 Conductive Traces 640 Dielectric layer 730 Metal layer 732, 734 Conductive Traces 830 Metal layer 832, 834, 836 and 838 Conductive Traces 930 Metal layer 931, 932, 933, 934, 936 Conductive Traces B1, B2 Barrier layers C1, C2, C3 copper layer H1 First opening H2 Second opening PR1 photoresist layer P1 Copper-phosphorus alloy layer P2 Copper-phosphorus alloy layer PR1-1 opening T1 NMOS transistor T2 PMOS transistor

Claims

1. 1. A semiconductor structure comprising: a conductive line in an Nth metal layer, where N is an integer greater than or equal to 1; a first insulating layer over the conductive line but not covering any portion of the conductive line; a first dielectric layer on the first insulating layer, the first dielectric layer not covering the portion of the conductive line and the portion of the first insulating layer; a second insulating layer on the first dielectric layer, the second insulating layer not covering the portion of the conductive line; an interconnect base laterally surrounded by the first dielectric layer, the first insulating layer, and the second insulating layer, wherein a top surface of the interconnect base and a top surface of the second insulating layer are coplanar; an interconnect body overlying the second insulating layer and contacting the top surface of the interconnect base; 1. A semiconductor structure comprising:

2. 2. The semiconductor structure of claim 1, wherein the first dielectric layer has a lower dielectric constant than the first insulating layer and the second insulating layer.

3. The interconnect base includes: a barrier layer in direct contact with the first insulating layer and the second insulating layer; a copper layer surrounded by the barrier layer; and A copper-phosphorus alloy layer sandwiched between the barrier layer and the copper layer.

10. The semiconductor structure of claim 1 comprising:

4. a first conductive trace on the second insulating layer; the interconnect body and the first conductive trace are part of a conductive line of an (N+1)th metal layer and are laterally separated by a second dielectric layer; The first conductive trace overlaps the first dielectric layer along a stacking direction of the semiconductor structure. The semiconductor structure of claim 1 .

5. The semiconductor structure of claim 4 further comprising a dielectric formed on the first conductive trace or the interconnect body.

6. 5. The semiconductor structure of claim 4, further comprising a second conductive trace adjacent to the first conductive trace, the first conductive trace configured to carry a high frequency signal, the second conductive trace coupled to ground, and the first conductive trace separated from the second conductive trace by a second dielectric layer.

7. 7. The semiconductor structure of claim 6, wherein the second conductive trace surrounds the first conductive trace.

8. 8. The semiconductor structure of claim 7, further comprising a third conductive trace configured to carry the high frequency signal with the first conductive trace, the second conductive trace surrounding the first conductive trace and the third conductive trace, and the first conductive trace separated from the third conductive trace by the second dielectric layer.

9. 7. The semiconductor structure of claim 6, further comprising a fourth conductive trace coupled to the ground, the first conductive trace being disposed between the second conductive trace and the fourth conductive trace, and the first conductive trace being separated from the fourth conductive trace by the second dielectric layer.

10. 10. The semiconductor structure of claim 9, further comprising a fifth conductive trace configured to carry the high frequency signal together with the first conductive trace, the first conductive trace and the fifth conductive trace being disposed between the second conductive trace and the fourth conductive trace.

11. The semiconductor structure of claim 4 , wherein the thickness of the interconnect body is different from the thickness of the first conductive trace.

12. a second dielectric layer configured to separate the interconnect body from the conductive traces on the second insulating layer, the interconnect body comprising: a first barrier layer in direct contact with a sidewall of the interconnect base and the second dielectric layer; at least one conductive layer surrounded by said barrier layer; a first copper-phosphorus alloy layer sandwiched between the first barrier layer and the at least one conductive layer; a second copper-phosphorus alloy layer formed on the at least one conductive layer; and a second barrier layer formed on the second copper-phosphorus alloy layer; 10. The semiconductor structure of claim 1 comprising:

13. 13. The semiconductor structure of claim 12, wherein the at least one conductive layer comprises at least one metallic material of copper, cobalt, and ruthenium.

14. 2. The semiconductor structure of claim 1, wherein a multi-layer 3D monolithic microwave integrated circuit (MMIC) is formed in said semiconductor structure, said multi-layer 3D MMIC including said interconnect base.

15. 10. The semiconductor structure of claim 1, wherein the interconnect base is part of a waveguide, a bandpass filter, a bandstop filter, a pi-type impedance matching filter, or a T-type impedance matching filter.

16. 1. A method for manufacturing a semiconductor structure, comprising the steps of: receiving a wafer having conductive lines of an Nth metal layer on a surface thereof, where N is greater than or equal to 1; forming a first insulating layer on a surface of the wafer, the first insulating layer not covering any portion of the conductive lines; forming a first dielectric layer on the first insulating layer; forming a second insulating layer on the first dielectric layer and the first insulating layer, the second insulating layer including at least a base region overlying but not covering the portion of the conductive line; forming an interconnect base in the base region, forming a photoresist layer over the second insulating layer, the base region of the second insulating layer not being covered by the photoresist layer; forming at least one conductive material over the photoresist layer, the second insulating layer, and the conductive lines, a top surface of the conductive material over the conductive lines being substantially coplanar with a top surface of the second insulating layer; removing the conductive material over the second insulating layer by removing the photoresist layer to form the interconnect base. and A method comprising:

17. 17. The method of claim 16, wherein the first dielectric layer has a lower dielectric constant than the first insulating layer and the second insulating layer.

18. The steps of forming at least one conductive material over the photoresist layer, the second insulating layer, and the conductive lines include: forming a barrier layer in the base region, the barrier layer contacting a side surface of the first insulating layer and a side surface of the second insulating layer; forming a copper-phosphorus alloy layer on the barrier layer; and plating a copper layer onto said copper-phosphorus alloy layer; 17. The method of claim 16, comprising:

19. The operation of plating the copper layer on the copper-phosphorus alloy layer comprises: forming the copper layer having a predetermined thickness using electroplating or electroless plating such that an upper surface of the second insulating layer and an upper surface of the interconnect base formed in the base region are coplanar; 20. The method of claim 18, comprising:

20. forming a first conductive trace on the second insulating layer; forming an interconnect body on the interconnect base and laterally surrounded by the first conductive trace; wherein the interconnect body and the first conductive trace are laterally spaced apart by a second dielectric layer; The first conductive trace overlaps the first dielectric layer along a stacking direction of the semiconductor structure.

17. The method of claim 16.

21. forming at least one dielectric on the first conductive trace; 21. The method of claim 20 further comprising:

22. forming an (N+1)th metal layer including conductive traces and interconnect bodies having q different thicknesses; q is an integer greater than 1; The conductive traces and interconnect bodies are formed by q metal plating processes and q different lift-off processes from the conductive trace or interconnect body having the smallest thickness to the conductive trace or interconnect body having the largest thickness.

21. The method of claim 20.

23. 17. The method of claim 16, wherein the semiconductor structure further comprises a plurality of interconnect bases having p different thicknesses, where p is an integer greater than 1, and the interconnect bases are formed by p metal plating processes from an interconnect base having a smallest thickness to an interconnect base having a largest thickness and p different lift-off processes.

24. The conductive lines include input / output electrodes of transistors formed in the wafer, and the method includes forming the input / output electrodes, the method comprising the steps of: forming an interlevel dielectric layer over transistors formed in a substrate of said wafer; forming a first silicate glass layer over the interlevel dielectric layer; forming a first silicon nitride (SiN) layer on a portion of the first silicate glass layer disposed at a first depth at a first terminal of the transistor; forming a second silicate glass layer on the first silicate glass layer and the first SiN layer; forming a second SiN layer on the second silicate glass layer; forming a first opening at a second terminal of the transistor at a second depth greater than the first depth; depositing a first layer of electrode metal to fill the first opening; removing exposed portions of the second silicate glass layer; forming a second opening in the first terminal of the transistor; depositing a second layer of electrode metal to fill the second opening; and removing the first SiN layer and the second SiN layer; wherein the electrode metal comprises tungsten, cobalt or ruthenium.

17. The method of claim 16.

25. 17. The method of claim 16, wherein the semiconductor structure further comprises a plurality of electrodes having r different thicknesses, r being an integer greater than 1, and the electrodes are formed by r metal plating processes from an electrode having a smallest thickness to an electrode having a largest thickness and r lift-off processes.

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