Power conversion device

Abstract

To equalize source inductance.SOLUTION: A power conversion device includes a plurality of semiconductor packages each including a power semiconductor element electrically connected between a high potential side terminal and a low potential side terminal, and layered wirings including a high potential side wiring connected to the high potential side terminals of the respective semiconductor packages and a low potential side wiring connected to the low potential side terminals of the respective semiconductor packages. Of the plurality of semiconductor packages, a first semiconductor package and a second semiconductor package adjacent to each other are arranged in such a way that the respective low potential side terminals are disposed between the respective high potential side terminals. The low potential side wiring has an integral connection terminal section where a connection with the low potential side terminal of the first semiconductor package and a connection with the low potential side terminal of the second semiconductor package are coupled.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] Power converters that convert DC power and AC power are used in various devices, and are required to be highly efficient, compact, and generate little heat. A plurality of semiconductor elements constituting the power converter are connected in parallel according to the magnitude of the required current. Patent Document 1 discloses a semiconductor unit comprising: a plurality of transistor chips each having a first main electrode on one side and a second main electrode on the other side, arranged in a plurality of parallel rows; a first conductor layer electrically connected to the first main electrodes of the transistor chips and having both corners of one side protruding along the extension direction of the rows of the transistor chips; a second conductor layer arranged between the both corners of the first conductor layer; and a wiring board arranged on the second main electrode side of the plurality of transistor chips, and having a wiring layer electrically connected to the second main electrodes of the plurality of transistor chips and the second conductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-047656 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the current flowing through multiple semiconductor elements varies, the amount of heat generated becomes uneven, and additional heat dissipation measures are required, which is undesirable. During switching, the variation in source inductance of each semiconductor element causes the variation in current. In the invention described in Patent Document 1, there is variation in source inductance. [Means for solving the problem]

[0005] A power conversion device according to a first aspect of the present invention comprises a plurality of semiconductor packages incorporating power semiconductor elements electrically connected between a high potential side terminal and a low potential side terminal, and stacked wiring including high potential side wiring connected to the high potential side terminal of each of the plurality of semiconductor packages and low potential side wiring connected to the low potential side terminal of each of the plurality of semiconductor packages, wherein adjacent first and second semiconductor packages among the plurality of semiconductor packages are arranged such that the low potential side terminals of each of the first and second semiconductor packages are sandwiched between the high potential side terminals of each of the first and second semiconductor packages, and the low potential side wiring has an integrated connection terminal portion to which a connection portion with the low potential side terminal of the first semiconductor package and a connection portion with the low potential side terminal of the second semiconductor package are connected. Effect of the Invention

[0006] According to the present invention, the source inductances can be equalized. [Brief description of the drawings]

[0007] [Figure 1] Plan view of the power converter [Diagram 2] Diagram showing the polarity of DC terminals on a semiconductor package [Diagram 3] A diagram showing the configuration of each layer of multilayer wiring [Figure 4] FIG. 1 shows an equivalent circuit of a power conversion device. [Diagram 5] FIG. 1 is a diagram showing a current flow in a power conversion device. [Figure 6] Detailed configuration diagram of semiconductor package [Figure 7] FIG. 1 shows the allocation of semiconductor packages in Modification 1. [Figure 8] Configuration diagram of a power conversion device in Modification 2 [Figure 9] Configuration diagram of a power conversion device in Modification 3 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] --First embodiment-- A first embodiment of a power conversion device according to the present invention will be described below with reference to Figs. 1 to 6.

[0009] FIG. 1 is a plan view of a power conversion device 1. The power conversion device 1 includes a stacked wiring 2 and a semiconductor package group 4. The stacked wiring 2 has a plurality of layers in the depth direction of the figure, in other words, in the thickness direction of the power conversion device 1. Specifically, the stacked wiring 2 has a four-layer configuration consisting of a first layer 21, a second layer 22, a third layer 23, and a fourth layer 24, and FIG. 1 shows only the first layer 21. The configuration of each layer of the stacked wiring 2 will be described later. The stacked wiring 2 includes a first region 2L, a second region 2C, and a third region 2R.

[0010] The semiconductor package group 4 is composed of a plurality of semiconductor packages 4c, specifically, an upper arm first package P1, an upper arm second package P2, an upper arm third package P3, an upper arm fourth package P4, a lower arm first package N1, a lower arm second package N2, a lower arm third package N3, and a lower arm fourth package N4. That is, the semiconductor package group 4 includes four semiconductor packages 4c constituting the upper arm and four semiconductor packages 4c constituting the lower arm. The same semiconductor packages 4c are connected only in the first layer 21 of the stacked wiring 2. Note that each of the semiconductor packages 4c has the same physical configuration, but is arranged in a different manner.

[0011] Each semiconductor package 4c includes two lined-up DC terminals, a high-potential side terminal 4P and a low-potential side terminal 4N, and three lined-up terminals, a high-potential side signal terminal, a low-potential side signal terminal, and a high-potential side terminal. Each semiconductor package 4c is arranged with the high-potential side terminal 4P and the low-potential side terminal 4N facing the side of the stacked wiring 2, i.e., toward the inside. Details will be described with reference to FIG. 2 below.

[0012] FIG. 2 is a diagram showing the polarity of the DC terminal of the semiconductor package 4c, and is a diagram in which the stacked wiring 2 is removed from FIG. 1. Focusing on the two packages at the top left, namely the upper arm first package P1 and the upper arm second package P2, a low potential side terminal 4N is arranged between the high potential side terminals 4P of these two semiconductor packages 4c. The upper arm third package P3 and the upper arm fourth package P4 shown at the bottom left of FIG. 2 also have a low potential side terminal 4N arranged between the high potential side terminals 4P of these two semiconductor packages 4c. The same is true for the lower arm first package N1 to the lower arm fourth package N4 shown on the right side of FIG. 2. That is, the semiconductor package group 4 is arranged such that each low potential side terminal 4N is sandwiched between the high potential side terminals 4P of two semiconductor packages 4c adjacent to each other.

[0013] 3 is a diagram showing the configuration of each layer of the laminated wiring 2. However, the first layer 21 and the third layer 23 have almost the same configuration, and the second layer 22 and the fourth layer 24 have the same configuration. In the laminated wiring 2 of this embodiment, the same potential is indicated by hatching. Vias V indicated by circles in FIG. 3 penetrate from the first layer 21 to the fourth layer 24, and electrically connect each layer. For example, the via V in the upper left of the figure is present in the region hatched with diagonal lines in all of the first layer 21 to the fourth layer 24, and makes the potential of the laminated wiring 2 in the laminated direction the same.

[0014] The laminated wiring 2 includes an upper high wiring UP which is the high potential side wiring in the upper arm, an upper low wiring UN which is the low potential side wiring in the upper arm, a lower high wiring LP which is the high potential side wiring in the lower arm, and a lower low wiring LN which is the low potential side wiring in the lower arm. In this embodiment, the upper high wiring UP is shown by diagonal hatching, the upper low wiring UN by lattice hatching, the lower high wiring LP by oblique lattice hatching, and the lower low wiring LN by mesh hatching. However, since the upper low wiring UN and the lower high wiring LP have the same potential, they may be shown by the same hatching.

[0015] The first layer 21 includes a first connection terminal portion 51, a second connection terminal portion 52, a third connection terminal portion 53, and a fourth connection terminal portion 54. Hereinafter, these are collectively referred to as a connection terminal portion 50. The connection terminal portion 50 is a portion where the connection portions of the low potential side terminals 4N of the two adjacent semiconductor packages 4c are integrally connected. Specifically, it is as follows. The first connection terminal portion 51 is connected to the low potential side terminals 4N of the upper arm first package P1 and the upper arm second package P2. The second connection terminal portion 52 is connected to the upper arm third package P3 and the upper arm fourth package P4. The third connection terminal portion 53 is connected to the lower arm first package N1 and the lower arm second package N2. The fourth connection terminal portion 54 is connected to the lower arm third package N3 and the lower arm fourth package N4.

[0016] Fig. 4 is a diagram showing an equivalent circuit of the power conversion device 1, and the corresponding parts of the inductance elements in the equivalent circuit are diagrammatically illustrated in the lower part of Fig. 4. P and N shown at the upper and lower ends of the equivalent circuit are connected to the high potential side terminal 4P and the low potential side terminal 4N of the capacitor connected to the power conversion device 1, for example.

[0017] Fig. 5 is a diagram showing the current flow in the power conversion device 1. Specifically, in Fig. 5, the upper part shows the current flow in the first layer 21 and the third layer 23 of the laminated wiring 2, the middle part shows the current flow in the second layer 22 and the fourth layer 24 of the laminated wiring 2, and the lower part shows the current flow in a cross section. However, the cross section shown in the lower part is a cross section at the position of the dashed line in the upper and middle parts. In the cross section, a "circled X" indicates that the current is flowing to the rear, and a "circled black circle" indicates that the current is flowing to the front.

[0018] For example, in the first region 2L, the current flows toward the rear in the first layer 21, toward the front in the second layer 22, toward the rear in the third layer 23, and toward the front in the fourth layer 24. That is, in the first region 2L, the current flows in the opposite direction for each layer. This tendency is also seen in the second region 2C and the third region 2R, and even in the same layer, the current flows in different directions for adjacent regions. In this way, the inductance is reduced because opposing currents flow through the laminated wiring 2.

[0019] The four dashed circles shown in FIG. 5 are junctions 60. The junctions 60 are the points where the currents flowing through the two connection terminals 50 having the same potential join together. The junctions 60 are provided in the approximate center of the two connection terminals 50. Specifically, the first junction 61 is the point where the currents flowing through the first connection terminal 51 and the second connection terminal 52 join together after moving from the first layer 21 to the second layer 22 and the fourth layer 24 through the via V. The second junction 62 is the point where the currents flowing through the third connection terminal 53 and the fourth connection terminal 54 join together after moving from the first layer 21 to the second layer 22 and the fourth layer 24 through the via V.

[0020] The first junction 61 is located at the approximate center of the first connection terminal projection 51a obtained by moving the first connection terminal 51 in the thickness direction and the second connection terminal projection 52a obtained by projecting the second connection terminal 52 in the thickness direction in the vertical direction in FIG. 5. Therefore, the distance from the first connection terminal 51 to the first junction 61 is approximately equal to the distance from the second connection terminal 52 to the first junction 61, and the inductance value is approximately the same even if the path is different. The second junction 62 is located at the approximate center of the third connection terminal projection 53a obtained by moving the third connection terminal 53 in the thickness direction and the fourth connection terminal projection 54a obtained by projecting the fourth connection terminal 54 in the thickness direction in the vertical direction in FIG. Therefore, the distance from the third connection terminal 53 to the second junction 62 is approximately equal to the distance from the fourth connection terminal 54 to the second junction 62, and the inductance value is approximately the same even if the path is different.

[0021] FIG. 6 is a detailed configuration diagram of the semiconductor package 4c. The hatching pattern in FIG. 6 is unrelated to the stacked wiring 2. When the mold 41 is removed from the semiconductor package 4c shown in FIG. 6(a), the state shown in FIG. 6(b) is obtained. In FIG. 6(b), a low-potential body 4NB having a low-potential side terminal 4N formed at its tip is shown. The DD cross section and the EE cross section in FIG. 6(b) will be described later. When the low-potential body 4NB is removed from the state shown in FIG. 6(b), the state shown in FIG. 6(c) is obtained. In FIG. 6(c), a bonding wire 44 extending from a power semiconductor element 43 and a high-potential body 4PB having a high-potential side terminal 4P formed at its tip are shown.

[0022] Figures 6(d) and 6(e) are a DD cross-sectional view and an EE cross-sectional view of Figure 6(b). Figures 6(d) and 6(e) show how the power semiconductor element 43 is connected to the low potential body 4NB and the high potential body 4PB via the solder 45. Note that the upper arm first package P1 and the upper arm third package P3 are used in the arrangement shown in Figure 6(a), and the upper arm second package P2 and the upper arm fourth package P4 are arranged upside down.

[0023] According to the above-described first embodiment, the following advantageous effects can be obtained. (1) The power conversion device 1 includes a plurality of semiconductor packages 4c each having a built-in power semiconductor element 43 electrically connected between a high potential side terminal 4P and a low potential side terminal 4N, and a stacked wiring 2 including upper high wiring UP and lower high wiring LP as high potential side wirings connected to the high potential side terminal 4P of each of the plurality of semiconductor packages 4c, and upper low wiring UN and lower low wiring LN as low potential side wirings connected to the low potential side terminal 4N of each of the plurality of semiconductor packages 4c. In the power conversion device 1, adjacent first and second semiconductor packages, for example, an upper arm first package P1 and an upper arm second package P2, are arranged such that each low potential side terminal 4N is sandwiched between the high potential side terminals 4P of each of the packages, and the upper low wiring UN and lower low wiring LN as low potential side wirings have an integrated connection terminal portion 50, for example, a first connection terminal portion 51, to which a connection portion with the low potential side terminal 4N of the first semiconductor package and a connection portion with the low potential side terminal 4N of the second semiconductor package are connected. Therefore, the source inductance in each of the power semiconductor elements 43 can be equalized.

[0024] (2) The power conversion device 1 configures an upper arm and a lower arm, and each of the upper arm and lower arm has N connection terminal portions 50 for 2N or 2N+1 (N is a natural number) semiconductor packages 4c. For example, the power conversion device 1 shown in FIG. 1 includes four semiconductor packages 4c in each of the upper arm and lower arm, and since 4 is 2x2, "N=2", and each of the upper arm and lower arm has two connection terminal portions 50.

[0025] (3) The junction 60 where currents flowing through two connection terminal portions 50 having the same potential join together is provided approximately in the center of the two connection terminal portions 50. For example, the first junction 61 where currents flowing through the first connection terminal portion 51 and the second connection terminal portion 52 having the same potential join together is provided approximately in the center of the first connection terminal portion 51 and the second connection terminal portion 52 in the longitudinal direction of the laminated wiring 2. Therefore, the source inductance in each power semiconductor element 43 can be made more equal.

[0026] (4) N connection terminal portions 50 are provided for 2N or 2N+1 semiconductor packages 4c, and the low-potential side terminals 4N of the semiconductor packages 4c located at both ends in the longitudinal direction are disposed on the inner side.

[0027] (5) The laminated wiring 2 has a first region 2L, a second region 2C, and a third region 2R. The second region 2C exists between the first region 2L and the third region 2R. The connection terminal portion 50 exists in the first region 2L and the third region 2R. In the first region 2L, the high potential side wiring of the upper arm and the low potential side wiring of the upper arm are laminated. In the second region 2C, the high potential side wiring of the upper arm and the low potential side wiring of the lower arm are laminated. In the third region 2R, the high potential side wiring of the lower arm and the low potential side wiring of the lower arm are laminated. Therefore, as shown in the lower part of FIG. 5, opposing currents flow in the laminated wiring 2, reducing the inductance.

[0028] (6) The upper arm first package P1 and the upper arm second package P2 arranged adjacent to each other have the same configuration and are connected upside down to the stacked wiring 2. This allows the number of types of components constituting the power conversion device 1 to be reduced.

[0029] (Variation 1) FIG. 7 is a diagram showing the shape of a semiconductor package 4c in the first modification. In the first embodiment, the positions of the high potential side terminal 4P and the low potential side terminal 4N in the thickness direction of the semiconductor package 4c were not specified. However, as shown in FIG. 7, the high potential side terminal 4P and the low potential side terminal 4N may be disposed at approximately the center in the thickness direction of the semiconductor package 4c. In other words, the distance T1 in the thickness direction from the end of the low potential body 4NB to the high potential side terminal 4P and the low potential side terminal 4N is equal to the distance T2 in the thickness direction from the end of the high potential body 4PB to the high potential side terminal 4P and the low potential side terminal 4N. In this case, the upper end and the lower end in the thickness direction are aligned regardless of the orientation of the semiconductor package 4c. Therefore, when the upper cooling path 8U and the lower cooling path 8D are disposed so as to sandwich the semiconductor package group 4 as shown in FIG. 7(b), it is possible to eliminate the gap between the cooling path and the semiconductor package 4c.

[0030] This modified example provides the following advantages. (7) The semiconductor package 4c has the high potential terminal 4P and the low potential terminal 4N at approximately the center in the thickness direction, which simplifies the cooling structure.

[0031] (Variation 2) The number of semiconductor packages 4c constituting each of the upper arm and the lower arm of the power conversion device 1 is not limited to four. Each of the upper arm and the lower arm may be composed of two or more semiconductor packages 4c, and there is no upper limit. When the number of semiconductor packages 4c constituting each of the upper arm and the lower arm is 2N and 2N+1, where N is a natural number, N connection terminal units 50 are provided. The case of an odd number will be described with reference to the drawings.

[0032] 8 is a configuration diagram of a power conversion device 1a in Modification 2. In the power conversion device 1a, each of the upper arm and the lower arm includes five semiconductor packages 4c. Since one connection terminal unit 50 is provided for two semiconductor packages 4c, the upper arm third package P3 and the lower arm third package N3 arranged in the center are not connected to the connection terminal unit 50.

[0033] (Variation 3) 9 is a configuration diagram of a power converter 1b in Modification 3. The difference between the power converter 1b and the power converter 1 is the arrangement of the upper arm third package P3 and the upper arm fourth package P4, and the stacked wiring 2 is also changed in accordance with this change in arrangement. Specifically, the upper arm third package P3 and the upper arm fourth package P4 have been moved downward in the figure relative to the power converter 1. This movement makes it possible to make the distance from the first connection terminal 51 to the first junction 61 and the distance from the second connection terminal 52 to the first junction 61 more equal.

[0034] (Variation 4) In the first embodiment described above, the multilayer wiring 2 has the first layer 21 to the fourth layer 24. However, the number of layers in the multilayer wiring 2 is not limited to four as long as it is an even number. Regardless of the number, each of the even-numbered layers has the same configuration, and each of the odd-numbered layers has the same configuration.

[0035] The above-mentioned embodiments and modifications may be combined with each other. Although various embodiments and modifications have been described above, the present invention is not limited to these. Other aspects that are conceivable within the scope of the technical idea of ​​the present invention are also included in the scope of the present invention. [Explanation of symbols]

[0036] 1: Power conversion device 2: Multilayer wiring 2C: 2nd area 2L: 1st area 2R: 3rd area 4: Semiconductor packages 4N: Low potential terminal 4NB: Low potential body 4P: High potential terminal 4PB: High potential body 4c: Semiconductor packages 21 :1st layer 22: 2nd layer 23:Third layer 24: 4th layer 50: Connection terminal 60: Junction 61: 1st confluence part 62:Second confluence LN: Bottom low wiring LP: Bottom high wiring UN: Upper and lower wiring UP: Upper wiring

Claims

1. A plurality of semiconductor packages each having a built-in power semiconductor element electrically connected between a high potential side terminal and a low potential side terminal; a stacked wiring including a high-potential side wiring connected to the high-potential side terminal of each of the plurality of semiconductor packages and a low-potential side wiring connected to the low-potential side terminal of each of the plurality of semiconductor packages, a first semiconductor package and a second semiconductor package adjacent to each other among the plurality of semiconductor packages are arranged such that the low potential side terminals of each of the first and second semiconductor packages are sandwiched between the high potential side terminals of each of the first and second semiconductor packages; A power conversion device, wherein the low potential side wiring has an integrated connection terminal portion to which a connection portion with the low potential side terminal of the first semiconductor package and a connection portion with the low potential side terminal of the second semiconductor package are connected.

2. The power conversion device according to claim 1, Configures an upper arm and a lower arm, A power conversion device, wherein each of the upper arm and the lower arm has N connection terminal portions for 2N or 2N+1 (N is a natural number) semiconductor packages.

3. The power conversion device according to claim 2, A power conversion device, wherein a junction where currents flowing through the two connection terminals having the same potential join together is provided approximately in the center of the two connection terminals.

4. The power conversion device according to claim 2, A power conversion device having N connection terminal portions for 2N or 2N+1 semiconductor packages, wherein the semiconductor packages located at the top and bottom in the vertical direction have the low potential side terminals arranged on the inside.

5. The power conversion device according to claim 1, the multilayer wiring has a first region, a second region, and a third region; the second region is between the first region and the third region, the connection terminal portion is present in the first region and the third region, In the first region, a high potential side wiring of an upper arm and the low potential side wiring of the upper arm are stacked, In the second region, the high potential side wiring of the upper arm and the low potential side wiring of the lower arm are laminated, In the third region, a high potential side wiring of a lower arm and the low potential side wiring of the lower arm are stacked.

6. The power conversion device according to claim 1, A power conversion device in which the first semiconductor package and the second semiconductor package have the same configuration and are connected to the stacked wiring in an inverted state.

7. The power conversion device according to claim 6, The semiconductor package is a power conversion device having the high potential side terminal and the low potential side terminal at approximately the center in the thickness direction.

Images